A universal fixed-length static instruction generation method based on UVM
Patent Information
- Application Number
- CN202610996144.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-06
- Publication Date
- 2026-10-13
AI Technical Summary
1、指令生成与仿真过程割裂，动态适配能力缺失：指令生成逻辑与仿真过程无任何关联，若需调整指令占比，新增指令场景，则需重新运行离线脚本生成汇编代码、编译指令文件、再启动仿真，迭代周期长，无法快速适配验证需求的动态变更
本方法基于UVM方法学，可移植性强，可重用度高，层次结构明显。使用脚本处理指令集规格文档，能够一键生成所需的指令库建模，而指令生成的逻辑内置在验证环境中，仅需修改环境的配置参数如：指令占比、地址范围等，在激励下发前完成生成，直接写入内置的内存模型，模拟真实处理器的指令存储和访存逻辑，同时生成过程中集成了合法性校验逻辑，过滤非法操作码、未定义格式的指令，减少无效仿真迭代。突破指令生成和验证环境完全解耦的局限，实现指令生成逻辑和验证环境的轻量级成，打通生成和异常定位流程，降低问题复现和迭代验证的成本。另外针对已知的动态场景，修改定制指令序列，弥补静态序列无法响应DUT状态的短板。摆脱静态固化地址映射的约束，支持内存模型多区域差异化的指令加载，按需生成并且写入指令序列，避免全量加载带来的内存浪费。
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Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and in particular to a method for generating general-purpose fixed-length static instructions based on UVM. Background Technology
[0002] In the functional verification process of processors (including microprocessors, microcontrollers, DSPs, etc.), the instruction generator is the core stimulus generation component. Its role is to generate instruction sequences that conform to the target instruction set architecture, driving the design under test (DUT) to execute various operations, thereby verifying the correctness of the DUT's core functions such as instruction decoding, arithmetic execution, memory access control, and exception handling. Currently, the mainstream basic instruction generation scheme in the industry is the static pre-compilation method. The core logic of this scheme is to completely decouple the instruction generation process from the simulation process. The generation, compilation, and storage of the instruction assembly file are completed through offline tools or scripts. After the simulation starts, the pre-generated instruction file is loaded into the DUT's memory according to a fixed address mapping relationship for instruction fetching and execution. This method has the following disadvantages: 1. The instruction generation and simulation process are disconnected, resulting in a lack of dynamic adaptation capabilities: The instruction generation logic is not related to the simulation process. If it is necessary to adjust the instruction ratio or add new instruction scenarios, it is necessary to rerun the offline script to generate assembly code, compile the instruction file, and then start the simulation again. The iteration cycle is long and it is impossible to quickly adapt to the dynamic changes in verification requirements.
[0003] 2. Fixed address mapping, poor adaptability and scalability: Static pre-compiled instruction files are usually bound to fixed memory address spaces and mapping rules. Simulation strictly loads according to the predetermined address, making it difficult to support the loading requirements of instructions with different memory regions.
[0004] 3. Lengthy debugging process, resulting in low efficiency in problem localization and reproduction: Since the instruction generation process is completely decoupled from the simulation process, when a DUT problem is found during simulation, the problem localization process is lengthy. It is necessary to simultaneously trace back multiple independent data such as offline generated instruction files, address mapping logs, simulation running logs, and DUT status logs to locate the specific instruction and context that caused the anomaly. If it is necessary to modify the instruction sequence to reproduce the problem or verify the repair effect, the entire process of "offline generation-compilation-loading-restarting simulation" needs to be re-executed, resulting in a long debugging cycle and significantly reducing verification efficiency. Summary of the Invention
[0005] To address the shortcomings of existing technologies, this invention provides a general fixed-length static instruction generation method based on UVM. This method, based on the UVM methodology, offers strong portability, high reusability, and a clear hierarchical structure. It overcomes the limitation of complete decoupling between instruction generation and verification environments, achieving lightweight integration of instruction generation logic and verification environment, streamlining the generation and anomaly localization processes, and reducing the cost of problem reproduction and iterative verification.
[0006] To achieve the above objectives, this invention provides a general fixed-length static instruction generation method based on UVM. (1) Read the target specification file of the instruction set under test, parse the instruction set information and convert it into a system internal data structure model that can be used in the instruction generation process; (2) In a UVM-based verification environment, configure static parameters related to instruction generation and dynamic parameters related to environment configuration; (3) The instruction generator in the verification environment dynamically generates an instruction sequence based on the generated internal data structure model of the system and the configured static and dynamic parameters, and directly writes the generated instructions into the built-in memory model that simulates the memory of a real processor in the verification environment to drive the execution of the DUT. (4) The DUT starts simulation, fetches instructions from the built-in memory model and executes them, and uses the functional check and monitoring components in the verification environment to verify and record the execution process and results.
[0007] Furthermore, step (1) specifically includes: (1.1) Read the target specification file of the instruction set under test, and convert the instruction set into an instruction set information table in a unified format. The table fields cover instruction attribute characteristics; (1.2) Write a script in Python to read and examine the instruction set information table, and parse the information in the instruction set information table into an internal data structure model of the system, including field classes corresponding to instruction attributes and instr classes corresponding to the instruction as a whole.
[0008] Furthermore, the inspection of the instruction set information table includes: a preprocessing inspection of the format and logical integrity of the instruction set information table.
[0009] Furthermore, the instruction set information table is an Excel spreadsheet, and the table fields include at least: instruction opcode, instruction type, number of operands and bit width, function description, and legal address range.
[0010] Furthermore, step (1) also includes: generating corresponding library files from the generated internal data structure model of the system. The generated library files include: a 32-bit compressed instruction library, a 32-bit integer instruction library, a 32-bit floating-point instruction library, a 32-bit multiply-accumulate instruction library, an instruction enumeration name library / type library / group library, and an instruction set function coverage library, for a total of 6 library files. The specific process of generating the corresponding library files from the generated internal system data structure model is as follows: Clear the instruction library, traverse the instruction set information table, and call the generate_instr_lib function to generate the instruction library file; clear the global definition file, and call the jinja2 rendering function render based on instr_define_svh_template to generate the instruction global definition file; clear the function coverage file, traverse the registered instruction list, and call the generate_single_cg_declare, generate_single_cg_new, and generate_single_cg_sample functions in sequence to generate the declaration, instantiation, and sampling logic of the function coverage group.
[0011] Furthermore, the static parameters include at least the number of general-purpose registers, memory modeling, and register address mapping; The dynamic parameters include at least the number of instructions, enable coverage collection, whether it is a bare program, and interrupt vector.
[0012] Furthermore, the dynamic generation of instruction sequences specifically involves: the instruction generator sequentially creating a static instruction list based on the generated internal data structure model of the system and the configured static and dynamic parameters; creating a static CSR register list that can be read and written; classifying memory access instructions into different groups; specifying the instruction flow template and its scaling factor required for the current simulation; and specifying the types and weights of instructions in the basic pool; and finally, applying all static and dynamic configurations to generate instruction queues.
[0013] Furthermore, the basic pool consists of multiply-accumulate instructions and integer instructions.
[0014] Furthermore, step (4) specifically involves: the DUT fetching instructions from the built-in memory model and performing simulation verification; and completing the recording of instruction registration status, dynamic configuration, logs of all generated instructions, the proportion of each type of instruction, and the loading log and coverage after the simulation ends.
[0015] This invention also provides a general-purpose fixed-length static instruction generator based on UVM, comprising: The instruction set parsing unit is used to read the target specification file of the instruction set under test, parse the instruction set information and transform it into a system internal data structure model that can be used in the instruction generation process. The configuration unit is used to receive and configure static parameters related to instruction generation and dynamic parameters related to environment configuration in the UVM-based verification environment. A dynamic generation engine unit is used by the instruction generator in the verification environment to dynamically generate instruction sequences based on the generated internal data structure model of the system and the configured static and dynamic parameters; The instruction loading unit is used to directly write the generated instructions into the built-in memory model that simulates the real processor memory in the verification environment, so as to drive the execution of the DUT.
[0016] The beneficial effects of this invention are: This method, based on the UVM methodology, boasts strong portability, high reusability, and a clear hierarchical structure. It uses scripts to process instruction set specification documents, enabling one-click generation of the required instruction library model. The instruction generation logic is built into the verification environment; only environment configuration parameters such as instruction ratio and address range need modification. Generation is completed before stimulus delivery and directly written to the built-in memory model, simulating the instruction storage and memory access logic of a real processor. Simultaneously, validity verification logic is integrated during generation to filter illegal opcodes and undefined format instructions, reducing unnecessary simulation iterations. It overcomes the limitation of complete decoupling between instruction generation and the verification environment, achieving lightweight integration of instruction generation logic and the verification environment, streamlining the generation and anomaly localization processes, and reducing the cost of problem reproduction and iterative verification. Furthermore, for known dynamic scenarios, customized instruction sequences are modified to compensate for the inability of static sequences to respond to DUT states. It breaks free from the constraints of static fixed address mapping, supporting instruction loading differentiated across multiple memory model regions, generating and writing instruction sequences on demand, avoiding memory waste caused by full loading. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the general fixed-length static instruction generation method based on UVM according to an embodiment of the present invention.
[0018] Figure 2 A schematic diagram of the integrated environment structure of the kungfu instruction generator in an embodiment of the present invention. Detailed Implementation
[0019] The present invention will be further explained and described below with reference to the accompanying drawings and embodiments.
[0020] The embodiments of this invention are described using a kungfu instruction generator as an example. Figure 1 A schematic flowchart of the general fixed-length static instruction generation method based on UVM according to an embodiment of the present invention is provided. Figure 2A schematic diagram of the integrated environment structure of the Kungfu instruction generator according to an embodiment of the invention is provided. The overall structure is divided into two core layers: a hardware simulation layer and a UVM verification layer. From top to bottom, these layers include test cases (uvm_test_top), dynamic configuration files for instruction generation (kungfu_instr_gen_config), the instruction generator (kungfu_program_code_gen), a bus agent (bus_slave_agent), a memory model (slave_mem), and a CPU reference model. The specific functions of each module are as follows: Hardware simulation layer: includes the testbench top-level environment, which integrates the DUT and bus interface bus_if internally, serving as the hardware carrier for instruction execution. It completes the interface handle transfer with the UVM verification layer through uvm config db.
[0021] The UVM verification layer consists of a configuration unit kungfu_instr_gen_config and an instruction generation unit kungfu_program_code_gen. It has built-in configuration parameters stream_ratio, an instruction generation interface gen_test_file, an instruction sequence storage instr_stream, and a functional coverage acquisition unit instr_cg. It can generate a ram.txt instruction file and output a kungfu_instr type instruction queue.
[0022] This invention provides a method for generating general fixed-length static instructions based on UVM, comprising the following steps: S101. Read the target specification file of the instruction set under test, parse the instruction set information and convert it into a system internal data structure model that can be used in the instruction generation process.
[0023] (1) Read the target specification file of the instruction set under test, and convert the instruction set into a unified format instruction set information table. The table fields cover instruction attribute characteristics.
[0024] The instruction set under test is converted into a standardized instruction set information table. All information of the target instruction set is organized into a standardized table file, which serves as the input source for subsequent scripts, ensuring the integrity and parsability of the instruction information. The instruction set table is constructed using Excel format, following a unified description standard. The table fields cover the core attributes of the instruction, specifically including: instruction opcode, instruction type, number and bit width of operands, function description, legal address range, etc.
[0025] (2) Write a script in Python to read and examine the instruction set information table, and parse the information in the instruction set information table into an internal data structure model of the system, including field class corresponding to instruction attributes and instr class corresponding to the instruction as a whole.
[0026] The Python script `instr_greb.py` reads and inspects the format and logical integrity of the instruction set table. It uses the `openpyxl` library to read the table file, parses the table information into declared `field` and `instr` classes in Python, and then proceeds by: first, clearing the instruction library; then, iterating through the table and calling the `generate_instr_lib` function to generate the instruction library file; clearing the global definition file; calling the `render` function of Jinja2 based on `instr_define_svh_template` to generate the instruction global definition file; clearing the feature coverage file; and finally, iterating through the list of registered instructions and calling `generate_single_cg_declare` and `generate_single_cg_n` sequentially. The `ew` and `generate_single_cg_sample` functions generate the declaration, instantiation, and sampling logic of the function coverage group. Then, copy the generated 32-bit compressed instruction library `kf32c_instr_lib.sv`, 32-bit integer instruction library `kf32i_instr_lib.sv`, 32-bit floating-point instruction library `kf32f_instr_lib.sv`, 32-bit multiply-accumulate instruction library `kf32m_instr_lib.sv`, instruction enumeration name library / type library / group library `kungfu_instr_define.svh`, and instruction set function coverage class library `kungfu_instr_cov_group.sv` to the DUT's test directory.
[0027] S102. In a UVM-based verification environment, configure static parameters related to instruction generation and dynamic parameters related to environment configuration.
[0028] Static parameters include at least the number of general-purpose registers, memory modeling, and register address mapping.
[0029] Dynamic parameters include at least the number of instructions, enable coverage collection, whether it is a bare program, and interrupt vectors.
[0030] S103. The instruction generator in the verification environment dynamically generates an instruction sequence based on the generated internal data structure model of the system and the configured static and dynamic parameters, and directly writes the generated instructions into the built-in memory model of the verification environment that simulates the memory of a real processor, so as to drive the execution of the DUT.
[0031] The process of dynamically generating instruction sequences is as follows: Instantiate and integrate `kungfu_program_code_gen` and `kungfu_instr_gen_config` into the DUT simulation verification environment. In the `build_phase` of the verification environment `uvm_test_top`, create instances of `kungfu_program_code_gen` and `kungfu_instr_gen_config` through the factory, and then integrate the latter through the `config` function. The database mechanism is set in the former; in the end_of_elaboration_phase of the verification environment uvm_test_top, the instruction generation parameters of kungfu_instr_gen_config are configured, such as: number of instructions, enable coverage collection, whether to use bare program, interrupt vector address, etc. After the configuration is completed, the static function create_instr_list in kungfu_instr is called to create a static instruction list, the static function create_csr_filter in kungfu_csr_instr is called to create a static CSR register list that can be read and written, the static function build_group in kungfu_lite_load_store_base_instr_stream is called to classify memory access instructions into different groups, and then the add_directed_instr_stream function of kungfu_program_code_gen is called to specify the instruction stream and scaling factor required for the current simulation, as well as the types and weights of instructions in the base pool. Finally, the gen_program function is called to apply all static and dynamic configurations to generate the instruction queue. In the `start_of_simulation_phase` of the verification environment, the `gen_test_file` function of `kungfu_program_code_gen` generates the file `test.txt`. The text file `test.txt`, containing the instruction sequence obtained from the instruction generator, contains instruction-encoded text that the processor can directly load. This text is loaded into the built-in memory model via a backdoor, simulating the instruction storage and fetch logic of a real processor, thereby driving the DUT execution. The `uvm_hdl_deposit` or `readmemh` command is then called to write this backdoor into the environment's memory after simulation startup.
[0032] The basic instruction pool consists of multiply-accumulate instructions and integer instructions, designed to ensure that the CPU executes correctly regardless of randomness. The remaining instruction types are implemented using different instruction stream templates, with specific constraints defined by the templates themselves.
[0033] S104. The DUT starts simulation, fetches instructions from the built-in memory model and executes them, and uses the functional check and monitoring components in the verification environment to verify and record the execution process and results.
[0034] After integrating the instruction generator, the DUT is activated to start the simulation, and the system prints the instruction registration status, dynamic configuration, logs of all generated instructions, and the proportion of each instruction category. After the simulation, the logs and coverage report are loaded. Developers can use the logs to trace the generation and loading chain of abnormal instructions and analyze and verify shortcomings using the coverage report, providing data support for subsequent DUT optimization and instruction set parameter optimization.
[0035] This invention also provides a UVM-based instruction generator, comprising: The instruction set parsing unit is used to read the target specification file of the instruction set under test, parse the instruction set information and transform it into a system internal data structure model that can be used in the instruction generation process.
[0036] The configuration unit is used to receive and configure static parameters related to instruction generation and dynamic parameters related to environment configuration in the UVM-based verification environment.
[0037] The dynamic generation engine unit is used by the instruction generator in the verification environment to dynamically generate instruction sequences based on the generated internal data structure model of the system and the configured static and dynamic parameters.
[0038] The instruction loading unit is used to directly write the generated instructions into the built-in memory model that simulates the real processor memory in the verification environment, so as to drive the execution of the DUT.
[0039] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A general fixed-length static instruction generation method based on UVM, characterized in that, Includes the following steps: (1) Read the target specification file of the instruction set under test, parse the instruction set information and convert it into a system internal data structure model that can be used in the instruction generation process; (2) In a UVM-based verification environment, configure static parameters related to instruction generation and dynamic parameters related to environment configuration; (3) The instruction generator in the verification environment dynamically generates an instruction sequence based on the generated internal data structure model of the system and the configured static and dynamic parameters, and directly writes the generated instructions into the built-in memory model that simulates the memory of a real processor in the verification environment to drive the execution of the DUT. (4) The DUT starts simulation, fetches instructions from the built-in memory model and executes them, and uses the functional check and monitoring components in the verification environment to verify and record the execution process and results.
2. The method for generating general fixed-length static instructions based on UVM according to claim 1, characterized in that, The specific steps (1) are as follows: (1.1) Read the target specification file of the instruction set under test, and convert the instruction set into an instruction set information table in a unified format. The table fields cover instruction attribute characteristics; (1.2) Write a script in Python to read and examine the instruction set information table, and parse the information in the instruction set information table into an internal data structure model of the system, including field classes corresponding to instruction attributes and instr classes corresponding to the instruction as a whole.
3. The method for generating general fixed-length static instructions based on UVM according to claim 2, characterized in that, The inspection of the instruction set information table includes: a preprocessing inspection of the format and logical integrity of the instruction set information table.
4. The method for generating general fixed-length static instructions based on UVM according to claim 2, characterized in that: The instruction set information table is an Excel spreadsheet, and the table fields include at least: instruction opcode, instruction type, number of operands and bit width, function description, and legal address range.
5. The method for generating general fixed-length static instructions based on UVM according to claim 2, characterized in that, The step (1) further includes: generating corresponding library files from the generated internal data structure model of the system. The generated library files include: 32-bit compressed instruction library, 32-bit integer instruction library, 32-bit floating-point instruction library, 32-bit multiply-accumulate instruction library, instruction enumeration name library / type library / group library and instruction set function coverage class library, a total of 6 library files; The specific process of generating the corresponding library files from the generated internal system data structure model is as follows: Clear the instruction library, traverse the instruction set information table, and call the generate_instr_lib function to generate the instruction library file; clear the global definition file, and call the jinja2 rendering function render based on instr_define_svh_template to generate the instruction global definition file; clear the function coverage file, traverse the registered instruction list, and call the generate_single_cg_declare, generate_single_cg_new, and generate_single_cg_sample functions in sequence to generate the declaration, instantiation, and sampling logic of the function coverage group.
6. The method for generating general fixed-length static instructions based on UVM according to claim 1, characterized in that: The static parameters include at least the number of general-purpose registers, memory modeling, and register address mapping; The dynamic parameters include at least the number of instructions, enable coverage collection, whether it is a bare program, and interrupt vector.
7. The method for generating general fixed-length static instructions based on UVM according to claim 1, characterized in that: The dynamic generation of instruction sequences specifically involves the instruction generator creating a static instruction list, a static CSR register list that can be read and written, and classifying memory access instructions into different groups based on the generated internal data structure model of the system and the configured static and dynamic parameters. It also specifies the instruction flow template and its scaling factor required for the current simulation, as well as the types and weights of instructions in the basic pool, and finally applies all static and dynamic configurations to generate instruction queues.
8. The method for generating general fixed-length static instructions based on UVM according to claim 7, characterized in that: The basic pool consists of multiply-accumulate instructions and integer instructions.
9. The method for generating general fixed-length static instructions based on UVM according to claim 1, characterized in that, The specific steps (4) are as follows: the DUT fetches instructions from the built-in memory model and performs simulation verification; and completes the recording of instruction registration status, dynamic configuration, log of all generated instructions, recording of the proportion of each type of instruction, and recording of loading log and coverage after the simulation ends.
10. A general-purpose fixed-length static instruction generator based on UVM, characterized in that, include: The instruction set parsing unit is used to read the target specification file of the instruction set under test, parse the instruction set information and transform it into a system internal data structure model that can be used in the instruction generation process. The configuration unit is used to receive and configure static parameters related to instruction generation and dynamic parameters related to environment configuration in the UVM-based verification environment. A dynamic generation engine unit is used by the instruction generator in the verification environment to dynamically generate instruction sequences based on the generated internal data structure model of the system and the configured static and dynamic parameters; The instruction loading unit is used to directly write the generated instructions into the built-in memory model that simulates the real processor memory in the verification environment, so as to drive the execution of the DUT.