Processor, zero-knowledge proof system, proof trajectory generation method and system on chip

Abstract

The application discloses a processor, a zero-knowledge proof system, a proof track generation method and a system on chip. The processor comprises: a track processing circuit configured to construct a track record or an operation log corresponding to a to-be-retired instruction, the track record or the operation log comprising a plurality of track fields or log fields; and a synchronous decoupling track circuit connected to the track processing circuit and configured to, after receiving the track record or the operation log sent by the track processing circuit, fill data in an unfinished track field or a log field in the plurality of track fields or log fields, and output the track record or the operation log for generating a proof track record when there is no unfinished track field or log field in the track record. The to-be-retired instruction is completed when the synchronous decoupling track circuit receives the track record. The processor can execute instructions in a user program with high performance, and provide complete, orderly and semantically consistent execution witness data for subsequent proof.

Description

Technical Field

[0001] This application relates to the field of proof technology, and in particular to a processor, a zero-knowledge proof system, a proof trajectory generation method, and a system-on-a-chip. Background Technology

[0002] The proof process is typically divided into two stages: the trajectory generation stage and the proof generation stage. In the trajectory generation stage, the target program is executed to generate the corresponding execution trajectory. In the proof generation stage, the proof is performed using this execution trajectory.

[0003] However, if the correct execution trajectory cannot be obtained during the trajectory generation phase, the proof in the proof generation phase cannot be supported. Taking the zKVM (Zero-Knowledge Virtual Machine) scenario as an example, problems such as incomplete execution trajectories, disordered order, or inconsistencies with the submission semantics are prone to occur during the trajectory generation phase. For example, if the asynchronous time consumption of memory read and write instruction execution, cache latency, old value reading, timestamp access, and execution trajectory output is not handled, the proof generation phase will be unable to verify whether the generated execution trajectory is correct. Summary of the Invention

[0004] To address the aforementioned issues, this application proposes a processor, a zero-knowledge proof system, a proof trajectory generation method, and an on-chip system, which enables the processor to execute instructions in the user program at high performance while providing complete, ordered, and semantically consistent execution witness data for subsequent proofs.

[0005] In a first aspect, this application provides a processor, comprising: a trajectory processing circuit, configured to construct a trajectory record or operation log corresponding to a retirement instruction, the trajectory record or operation log including multiple trajectory fields or log fields; and a synchronous decoupling trajectory circuit, connected to the trajectory processing circuit, configured to, upon receiving the trajectory record or operation log sent by the trajectory processing circuit, fill in incomplete trajectory fields or log fields among the multiple trajectory fields or log fields with data, and when the incomplete trajectory fields or log fields are not present in the trajectory record or operation log, output the trajectory record or operation log to generate a proof trajectory record; wherein the retirement instruction is completed when the synchronous decoupling trajectory circuit receives the trajectory record or operation log.

[0006] In some embodiments, the trajectory processing circuit is further configured to construct a trajectory record or operation log corresponding to the type of the retirement instruction, based on the type of the retirement instruction.

[0007] In some embodiments, the trajectory processing circuit is further configured to provide the synchronous decoupled trajectory circuit with the data required for the incomplete trajectory field or log field in the trajectory record or operation log, based on the trajectory record or operation log.

[0008] In some embodiments, the trajectory processing circuit includes: a processor core, the processor core including an instruction pipeline circuit, the instruction pipeline circuit being connected to the synchronous decoupled trajectory circuit, the instruction pipeline circuit being used to construct the trajectory record or operation log, and to send the trajectory record or operation log to the synchronous decoupled trajectory circuit when the retirement instruction meets preset retirement conditions.

[0009] In some embodiments, the preset retirement conditions include a first preset condition and a second preset condition; the trajectory processing circuit is further configured to send the trajectory record or operation log to the synchronous decoupled trajectory circuit when the retirement instruction satisfies both the first and second preset conditions, wherein the first preset condition is used to determine whether the retirement instruction has been successfully executed without triggering an exception, and the second preset condition is used to determine whether the address of the retirement instruction is located in the proof area.

[0010] In some embodiments, the processor core includes: a memory data cache circuit connected to the instruction pipeline circuit, configured to provide memory data to the synchronous decoupling trajectory circuit, so that the synchronous decoupling trajectory circuit fills the memory data into the corresponding incomplete trajectory field or log field in the trajectory record or operation log; and a memory timestamp cache circuit connected to the instruction pipeline circuit, configured to provide memory timestamps to the synchronous decoupling trajectory circuit, so that the synchronous decoupling trajectory circuit fills the memory timestamps into the corresponding incomplete trajectory field or log field in the trajectory record or operation log.

[0011] In some embodiments, the processor core includes: a general-purpose register circuit connected to the instruction pipeline circuit, configured to provide register service data to the synchronous decoupled trajectory circuit, so that the synchronous decoupled trajectory circuit fills the register service data into the corresponding incomplete trajectory field or log field in the trajectory record or operation log; the trajectory processing circuit further includes: a register timestamp circuit connected between the instruction pipeline circuit and the synchronous decoupled trajectory circuit, configured to provide a register timestamp to the synchronous decoupled trajectory circuit, so that the synchronous decoupled trajectory circuit fills the register timestamp into the corresponding incomplete trajectory field in the trajectory record.

[0012] In some embodiments, the processor is disposed on a system-on-a-chip, the system-on-a-chip includes a pre-compiled computation circuit, the pre-compiled computation circuit being connected between the instruction pipeline circuit and the synchronous decoupling trajectory circuit; the instruction pipeline circuit is further configured to, in cooperation with the pre-compiled computation circuit, construct the trajectory record or operation log corresponding to the instruction to be retired when the type of the instruction to be retired is a pre-compiled call instruction.

[0013] In some embodiments, the trajectory processing circuit is further configured to stop sending the trajectory record or operation log to the synchronous decoupled trajectory circuit when it receives a signal indicating to pause sending the trajectory record or operation log.

[0014] In some embodiments, the synchronous decoupling trajectory circuit is further configured to send a signal to the trajectory processing circuit indicating to suspend sending the trajectory record or operation log when the synchronous decoupling trajectory circuit is unable to output the trajectory record or operation log and / or is unable to receive the trajectory record or operation log.

[0015] In some embodiments, the synchronous decoupling trajectory circuit includes a storage area for storing a preset number of trajectory records or operation logs.

[0016] In some embodiments, the synchronous decoupling trajectory circuit is further configured to fill in the incomplete trajectory field or log field in the trajectory record or operation log in the synchronous decoupling trajectory circuit in the order of receiving the trajectory record or operation log.

[0017] In some embodiments, the synchronous decoupling trajectory circuit is further configured to output the trajectory records or operation logs in the synchronous decoupling trajectory circuit sequentially according to the receiving order of the trajectory records.

[0018] Secondly, this application provides a zero-knowledge proof system, comprising: a host computer for providing a program, input parameters, and configuration data, wherein the program includes at least one instruction; a system-on-a-chip including the processor described in the first aspect, for acquiring the program, the input parameters, and the configuration data, and generating a proof trajectory record corresponding to the at least one instruction; and a proof circuit for acquiring the proof trajectory record, and after generating proof data corresponding to the proof trajectory record, returning the proof data to the host computer.

[0019] In some embodiments, the host is further configured to write the program, the input parameters, and the configuration data into shared memory, and perform a cache refresh operation after the writing is completed.

[0020] In some embodiments, the host computer is further configured to send a trajectory generation start signal to the system-on-chip; The on-chip system is also used to, upon receiving the trajectory generation start signal, acquire the program, the input parameters, and the configuration data, and generate the proof trajectory record corresponding to the at least one instruction.

[0021] In some embodiments, the system-on-chip is further configured to send a trajectory generation end signal to the host after generating the proof trajectory record corresponding to the at least one instruction, so as to start the proof circuit through the host.

[0022] In some embodiments, the host is further configured to perform a memory barrier operation after receiving the trajectory generation end signal, and send a proof start signal to the proof circuit after performing the memory barrier operation to start the proof circuit.

[0023] In some embodiments, the proof circuit is further configured to write the proof data into shared memory after generating proof data corresponding to the proof trajectory record, and send a proof completion signal to the host.

[0024] Thirdly, this application provides a method for generating a proof trajectory, comprising: constructing a trajectory record or operation log corresponding to a retirement instruction, the trajectory record or operation log including multiple trajectory fields or log fields; sending the trajectory record or operation log to a synchronous decoupled trajectory queue, and filling in the incomplete trajectory fields or log fields among the multiple trajectory fields or log fields in the synchronous decoupled trajectory queue with data; when the incomplete trajectory fields or log fields do not exist in the trajectory record or operation log, outputting the trajectory record or operation log to generate a proof trajectory record; wherein the retirement instruction completes retirement when the synchronous decoupled trajectory queue receives the trajectory record or operation log.

[0025] In some embodiments, constructing a trajectory record corresponding to a retirement instruction includes: constructing a trajectory record or operation log corresponding to the type of the retirement instruction based on the type of the retirement instruction.

[0026] In some embodiments, constructing the trajectory record or operation log corresponding to the type of the retirement instruction includes: providing the synchronous decoupled trajectory queue with the data required for the incomplete trajectory field or log field in the trajectory record or operation log, based on the trajectory record or operation log.

[0027] In some embodiments, before sending the trajectory record or operation log to the synchronous decoupled trajectory queue, the method includes: sending the trajectory record or operation log to the synchronous decoupled trajectory queue when the retirement instruction meets the preset retirement conditions.

[0028] In some embodiments, the preset retirement conditions include a first preset condition and a second preset condition; the step of sending the trajectory record or operation log to the synchronous decoupled trajectory queue when the retirement instruction meets the preset retirement conditions includes: when the retirement instruction meets both the first and second preset conditions, sending the trajectory record or operation log to the synchronous decoupled trajectory queue, wherein the first preset condition is used to determine whether the retirement instruction has been successfully executed and has not triggered an exception, and the second preset condition is used to determine whether the address of the retirement instruction is located in the proof area.

[0029] In some embodiments, after sending the trajectory record or operation log to the synchronous decoupled trajectory queue when the retirement instruction meets preset retirement conditions, the method includes: providing memory data to the synchronous decoupled trajectory queue to fill the corresponding incomplete trajectory field or log field in the trajectory record or operation log through the synchronous decoupled trajectory queue; and providing a memory timestamp to the synchronous decoupled trajectory queue to fill the corresponding incomplete trajectory field or log field in the trajectory record or operation log through the synchronous decoupled trajectory queue.

[0030] In some embodiments, sending the trajectory record or operation log to the synchronous decoupled trajectory queue when the retirement instruction meets preset retirement conditions includes: providing register service data to the synchronous decoupled trajectory queue to fill the corresponding incomplete trajectory field or log field in the trajectory record or operation log through the synchronous decoupled trajectory queue; and providing a register timestamp to the synchronous decoupled trajectory queue to fill the corresponding incomplete trajectory field or log field in the trajectory record or operation log through the synchronous decoupled trajectory queue.

[0031] In some embodiments, when the type of the retirement instruction is a precompiled call instruction, a first trajectory record and a second trajectory record corresponding to the retirement instruction are constructed through a first trajectory construction path and a second trajectory construction path, respectively. After the first trajectory record and the second trajectory record are encapsulated into the trajectory record, they are sent to the synchronous decoupled trajectory queue.

[0032] In some embodiments, when the synchronous decoupled trajectory queue is unable to output the trajectory record or operation log, and / or is unable to receive the trajectory record or operation log, a signal indicating to suspend sending the trajectory record or operation log is sent.

[0033] In some embodiments, the synchronous decoupling trajectory queue includes a trajectory queue for storing a preset number of trajectory records or operation logs.

[0034] In some embodiments, filling the incomplete trajectory field or log field among the plurality of trajectory fields or log fields in the synchronous decoupled trajectory queue with data further includes: filling the incomplete trajectory field or log field in the trajectory record or operation log in the synchronous decoupled trajectory queue with data in sequence according to the receiving order of the trajectory record or operation log.

[0035] In some embodiments, the synchronous decoupled trajectory queue outputs the trajectory records or operation logs, including: sequentially outputting the trajectory records or operation logs in the synchronous decoupled trajectory queue according to the receiving order of the trajectory records or operation logs.

[0036] Fourthly, this application provides a system-on-a-chip including the processor described in the first aspect above, or for implementing the method described in the third aspect above.

[0037] The beneficial effects of this application are as follows: By setting up trajectory processing circuits and synchronous decoupling trajectory circuits in the processor, instruction execution and trajectory record generation are decoupled into two collaborative stages. This hardware-level task division fundamentally changes the performance bottleneck caused by waiting for complete trajectory data collection in traditional architectures. During instruction execution, the reading of data such as memory values ​​and timestamps often involves multi-cycle delays. If the instruction pipeline is required to wait for these slow data to return before constructing a complete trajectory record, it will inevitably cause severe pipeline congestion. This results in scarce hardware resources such as the processor core's out-of-order execution buffer, reorder buffer, and physical register file being occupied for a long time by instructions that have been executed but cannot be retired, significantly reducing the processor's instruction-level parallel throughput. The trajectory processing circuit constructs a preliminary trajectory record containing multiple fields when the instruction reaches the write-back stage, quickly capturing the ready execution information. The synchronous decoupled trajectory circuit receives this preliminary record and asynchronously fills in any incomplete fields. This asynchronous data processing mechanism ensures that the instruction execution process does not stall due to waiting for slow-returning memory write values, timestamp read values, or write values, fundamentally avoiding pipeline pauses and significantly shortening the overall latency from instruction execution to retirement. The synchronous decoupled trajectory circuit, as a dedicated hardware buffer and filling unit, undertakes the collection and encapsulation of latency-sensitive data without interfering with the continuous instruction fetching and decoding of the main instruction pipeline. This achieves deep parallelism between the execution unit and the trajectory generation unit, significantly improving the effective throughput of the processor core. Simultaneously, the instruction retirement condition is rigidly bound to the successful reception of trajectory records or operation logs by the synchronous decoupled trajectory circuit. This makes the instruction's update to the architecture state and the trajectory record's entry into the decoupled circuit an inseparable atomic event, avoiding the semantic inconsistency problem caused by the disconnect between hardware state updates and trajectory records. It also avoids verification failures and retries triggered by missing or out-of-order data in the backend proof system, further reducing overall computational waste. At the storage and data flow level, the prototype trajectory record is immediately transferred to the synchronous decoupled trajectory circuit after instruction retirement, allowing for the rapid release of temporary storage resources within the pipeline and alleviating bandwidth pressure on on-chip cache and storage subsystems. The synchronous decoupled trajectory circuit outputs a complete proof trajectory record once all fields are complete, optimizing the output efficiency of trajectory data and mitigating performance constraints caused by the storage wall. This solution ensures the efficiency and performance of proof trajectory record generation while maintaining high-performance processor execution of user programs, providing complete, ordered, and semantically consistent execution witness data for subsequent proofs, achieving end-to-end hardware performance enhancement from instruction execution and state tracking to proof verification. Attached Figure Description

[0038] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.

[0039] Figure 1 This is a schematic diagram of the processor structure in some embodiments of this application. Figure 1 ; Figure 2 This is a schematic diagram of the processor structure in some embodiments of this application. Figure 2 ; Figure 3 This is a schematic diagram of the processor structure in some embodiments of this application. Figure 3 ; Figure 4 This is a schematic diagram of the structure of a system-on-a-chip according to some embodiments of this application. Figure 1 ; Figure 5 This is a schematic diagram of the structure of a zero-knowledge proof system according to some embodiments of this application. Figure 1 ; Figure 6 This is a schematic diagram of the structure of a zero-knowledge proof system according to some embodiments of this application. Figure 2 ; Figure 7 This is a schematic diagram of the zero-knowledge proof process for some embodiments of this application. Figure 1 ; Figure 8 This is a schematic diagram of the zero-knowledge proof process for some embodiments of this application. Figure 2 ; Figure 9 This is a flowchart illustrating the proof trajectory generation method of some embodiments of this application; Figure 10 This is a schematic diagram of the structure of a system-on-a-chip according to some embodiments of this application. Figure 2 ; Figure 11 This is a schematic diagram of the structure of a system-on-a-chip according to some embodiments of this application. Figure 3 . Detailed Implementation

[0040] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be noted that the following embodiments are for illustrative purposes only and are not intended to limit the scope of the application. Similarly, the following embodiments are only some, not all, embodiments of the present application, and all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0041] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0042] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Additionally, the character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, "many" in this application means two or more. Moreover, the term "at least one" in this application means any combination of at least two of any one or more of a plurality of objects. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C. Furthermore, the terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0043] With the rapid development of blockchain scaling, privacy transactions, verifiable computation, decentralized computing, and off-chain execution scenarios, the computational scale of procedures to be proven continues to increase. The computational overhead of the proof generation process has become a key bottleneck for system throughput and response latency, and this bottleneck effect becomes increasingly significant with the increase in program size and input data volume. In this context, if the execution trajectory generation stage encounters problems such as incomplete execution trajectories, disordered sequences, or inconsistencies with the submission semantics, the proof system will be unable to construct valid cryptographic proofs, or the proofs will be judged as invalid during the verification stage. This leads to wasted computational resources, proof task retries, and in severe cases, may cause transaction rejection or state inconsistencies in upper-layer applications. Software-layer retry or serialization waiting mechanisms introduced to compensate for these defects will further exacerbate the system's throughput and latency bottlenecks.

[0044] Taking the zKVM scenario as an example, zero-knowledge proofs have been widely used in blockchain scaling, privacy protection, verifiable computing, decentralized computing, and off-chain execution scenarios, making the performance and reliability of the proof system a key part of the entire technology stack.

[0045] To this end, this application provides a processor, including a trajectory processing circuit for constructing a trajectory record or operation log corresponding to a retirement instruction, the trajectory record or operation log including multiple trajectory fields or log fields; and a synchronous decoupling trajectory circuit connected to the trajectory processing circuit, for filling in incomplete trajectory fields or log fields in the multiple trajectory fields or operation log after receiving the trajectory record or operation log sent by the trajectory processing circuit, and outputting the trajectory record or operation log to generate a proof trajectory record when no incomplete trajectory fields or log fields exist in the trajectory record or operation log; wherein the retirement instruction completes retirement when the synchronous decoupling trajectory circuit receives the trajectory record or operation log. This achieves high-performance execution of user programs by the processor while providing complete, ordered, and semantically consistent execution witness data for subsequent proof.

[0046] To enable those skilled in the art to better understand the technical solution of this application, the technical solution of this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0047] Please see Figure 1 , Figure 1 This is a schematic diagram of the processor structure in some embodiments of this application. Figure 1 The processor 100 includes: a trajectory processing circuit 110, used to construct a trajectory record or operation log corresponding to the retirement instruction, the trajectory record or operation log including multiple trajectory fields or log fields; and a synchronous decoupling trajectory circuit 120, connected to the trajectory processing circuit 110, used to fill in the incomplete trajectory fields or log fields among the multiple trajectory fields or log fields after receiving the trajectory record or operation log sent by the trajectory processing circuit 110, and output the trajectory record or operation log to generate a proof trajectory record when there are no incomplete trajectory fields or log fields in the trajectory record or operation log; wherein the retirement instruction is completed when the synchronous decoupling trajectory circuit 120 receives the trajectory record or operation log.

[0048] The processor 100 can be an integrated circuit chip used to execute a user program and generate a proof trace record corresponding to the user program. The user program includes at least one instruction. The proof trace record can be used for zero-knowledge proofs, as well as for proofs in other cryptographic or secure computing fields.

[0049] In one implementation, the processor 100 may be a CPU (Central Processing Unit), specifically implemented based on a reduced instruction set architecture. In a specific embodiment, the processor 100 may be a RISC-V (Reduced Instruction Set Computer-Five) based processor, configured to execute user programs and generate corresponding proof trace records, wherein the user program may be an executable program conforming to the RISC-V instruction set architecture.

[0050] The trajectory processing circuit 110 can be a circuit used to construct trajectory records or operation logs corresponding to the retirement instruction.

[0051] In one embodiment, the trajectory processing circuit 110 includes circuitry for providing data and circuitry for executing instructions.

[0052] The circuitry used to provide data is configured to store data required or generated during instruction execution, such as register files, instruction cache circuitry, and data cache circuitry.

[0053] The circuitry used to execute instructions is configured to execute instructions in the user program instruction-by-instruction. For example, an instruction pipeline circuit can be functionally divided into multiple working stages, each stage completing a sub-task in the instruction execution process. In one embodiment, the instruction pipeline circuit can be divided into an instruction fetch stage, a decode stage, an execution stage, a memory access stage, and a write-back stage.

[0054] The trajectory processing circuit 110 is configured to capture relevant information about an instruction from the circuitry for providing data and / or the circuitry for executing the instruction during the execution of a user program by the circuitry for executing the instruction, and to construct a trajectory record or operation log corresponding to the instruction. In one embodiment, when an instruction reaches the write-back stage, the instruction pipeline circuitry has completed the main execution operations for the instruction, and in this stage, a trajectory record or operation log corresponding to the instruction to be retired is constructed.

[0055] Among them, the pending retirement instruction can be an instruction that has been executed in the user program but has not yet retired. For example, the pending retirement instruction can be an instruction in the user program that has entered the write-back stage and is waiting for retirement.

[0056] Trajectory records or operation logs can be a data form of instruction execution evidence structure. Instruction execution evidence structure can be a data set automatically captured and constructed by the processor 100 or trajectory processing circuit 110 from the relevant data generated by the executed instruction, used to record and prove the instruction execution process and results. In different implementations or application scenarios, instruction execution evidence structure can be referred to as trajectory records, operation logs, execution traces, verification data packets, etc. That is to say, the trajectory processing circuit 110 can also be used to construct execution trajectories and verification data packets corresponding to the instruction to be retired. This application's use of trajectory records or operation logs for interpretation does not limit this application to constructing only trajectory records or operation logs corresponding to the instruction to be retired.

[0057] In one implementation, the trajectory record or operation log constructed by the trajectory processing circuit 110 includes multiple trajectory fields or log fields. Taking the trajectory field as an example, the trajectory field may include, but is not limited to, at least one of the following: valid, used to indicate whether the current trajectory data is valid; zk_clk or base_timestamp derived from zk_clk, used to record the position of the instruction in the global instruction clock sequence, or as a reference for the derived timestamp; pc, used to record the program counter address of the instruction; inst, used to record the opcode and operand encoding of the instruction; rs1Index, used to record the number (index) of source register 1; rs1Val, used to record the value of source register 1; rs1Tsp, used to record the pair of source register 1... The `rdOrMemIndex` field records the source register 2's index or the memory access address; `rs2OrMemVal` records the source register 2's value or the value read from the memory access address; `rs2OrMemTsp` records the old timestamp corresponding to the source register 2 or the memory access address; `rdOrMemIndex` records the destination register index or the address written to memory; `rdOrMemReadValue` records the old value of the destination register or the old value of the memory address; `rdOrMemWriteValue` records the destination register write-back value or the memory write value; and `rdOrMemTsp` records the old timestamp corresponding to the destination register or the memory address. When the instruction execution evidence structure is an operation log, its log fields are structurally and functionally similar to the trace fields, all used to record relevant information generated during instruction execution; these will not be repeated here.

[0058] The trajectory record or operation log constructed by the trajectory processing circuit 110 may include complete fields and complete field values, or it may include complete fields but not complete field values. For example, multiple trajectory fields or log fields in the trajectory record or operation log constructed by the trajectory processing circuit 110 may include completed trajectory fields or log fields and / or incomplete trajectory fields or log fields. Taking the above-mentioned instruction pipeline circuit as an example, when the instruction arrives at the write-back stage, the trajectory processing circuit 110 constructs a prototype of the trajectory record or operation log. In this trajectory record or operation log, the corresponding values ​​of multiple trajectory fields or log fields are all completed, partially completed, or not completed at all.

[0059] In one embodiment, the trajectory processing circuit 110 executes the instructions in the user program instruction by instruction. For example, the user program includes instructions A, B and C. The trajectory processing circuit 110 executes instructions A, B and C in sequence and constructs trajectory records or operation logs corresponding to instructions A, B and C respectively.

[0060] The synchronous decoupling trajectory circuit 120 can be a circuit for receiving trajectory records or operation logs for retirement instructions, wherein the retirement instruction is completed when it is received by the synchronous decoupling trajectory circuit 120.

[0061] In one embodiment, the synchronous decoupling trajectory circuit 120 includes storage space for accommodating trajectory records or operation logs. For example, the synchronous decoupling trajectory circuit 120 receives trajectory records or operation logs corresponding to a retirement instruction from the trajectory processing circuit 110, and the retirement instruction completes retirement upon receiving the trajectory records or operation logs. The trajectory records or operation logs are output by the synchronous decoupling trajectory circuit 120 as proof of the trajectory record.

[0062] As described above, the trajectory record or operation log constructed by the trajectory processing circuit 110 may include incomplete trajectory fields or log fields. For example, since the data sources required by ordinary operation instructions, load instructions or storage instructions when generating trajectory records or operation logs are different, and the reading and writing of memory values ​​and timestamp values ​​may have multi-cycle delays, the corresponding field values ​​in the trajectory record or operation log may be delayed when filled. That is, the trajectory record or operation log constructed by the trajectory processing circuit 110 may include complete fields but not complete field values.

[0063] Furthermore, the synchronous decoupling trajectory circuit 120 can receive trajectory records or operation logs containing complete fields but not complete field values ​​from the trajectory processing circuit 110. The synchronous decoupling trajectory circuit 120 can continue to fill in the field values ​​corresponding to the incomplete trajectory fields or log fields, and output them after filling to generate proof trajectory records. It should be noted that the synchronous decoupling trajectory circuit 120 waits for the retirement instruction to complete retirement when receiving trajectory records or operation logs containing complete fields but not complete field values. That is to say, while ensuring the number of retirement instructions per clock cycle, it continues to fill in the incomplete fields in the trajectory records or operation logs corresponding to the instruction after the instruction retires.

[0064] Taking the trajectory record constructed by the trajectory processing circuit 110 as an example, which does not include the memory write value, timestamp read value, and the field value corresponding to the timestamp write value, the trajectory processing circuit 110 sends the trajectory record to the synchronous decoupling trajectory circuit 120. After receiving the trajectory record, the synchronous decoupling trajectory circuit 120 can continue to process the memory write value, timestamp read value, and timestamp write value required for the trajectory record, and continue to send them to the synchronous decoupling trajectory circuit 120. The synchronous decoupling trajectory circuit 120 fills the memory write value, timestamp read value, and timestamp write value into the corresponding incomplete fields.

[0065] The asynchronously returned memory write values, timestamp read values, and timestamp write values ​​can be filled according to preset filling rules. For example, they can be filled by finding the corresponding trajectory record based on the preset identifier fields (pc and / or inst), by filling according to the field name of the incomplete field, or by blocking filling. The preset filling rules can be changed according to actual design requirements.

[0066] In one implementation, when there is no incomplete trajectory field or log field in the trajectory record or operation log, the synchronous decoupling trajectory circuit 120 outputs the trajectory record or operation log to generate a proof trajectory record. For example, when there is no incomplete field in the trajectory record received by the synchronous decoupling trajectory circuit 120, the trajectory record can be output as a proof trajectory record; or, when there is an incomplete field in the trajectory record received by the synchronous decoupling trajectory circuit 120, the field value asynchronously returned from the trajectory processing circuit 110 is received and filled into the corresponding field. When there is no incomplete trajectory field in the trajectory record, the trajectory record can be output as a proof trajectory record.

[0067] In one example, when the trajectory record in the synchronous decoupling trajectory circuit 120 meets the following conditions: valid, no exception has occurred or the exception trajectory record or operation log ends according to the exception handling rules, and it is a non-memory access instruction, there is no need to wait for the return of the field value related to the memory access, and the trajectory record can be output as a proof trajectory record.

[0068] In another example, when the trajectory record in the synchronous decoupling trajectory circuit 120 meets the following conditions: valid, no exception occurred, or the exception trajectory record or operation log ended according to the exception handling rules, and it is a memory access instruction, it is necessary to wait for the return of the field values ​​related to the memory access. After the values ​​are returned and filled, the trajectory record can be output as a proof trajectory record. For example, a dDone field can be constructed to record whether the memory data return is complete; a tReadDone field can be constructed to record the completion of the memory timestamp read operation; and a tWriteDone field can be constructed to record the completion of the memory timestamp write operation. When the above three constructed fields are valid, it indicates that the corresponding values ​​have been asynchronously returned / filled, and the trajectory record can be output as a proof trajectory record.

[0069] In the above scheme, a trajectory processing circuit 110 and a synchronous decoupling trajectory circuit 120 are set in the processor 100 to decouple instruction execution and the generation of proven trajectory records into two collaborative stages. This hardware-level task division fundamentally changes the performance bottleneck caused by waiting for complete collection of trajectory data in traditional architectures. During instruction execution, the reading of data such as memory values ​​and timestamps often has multi-cycle delays. If the instruction pipeline is required to wait for these slow data to return before constructing a complete trajectory record, it will inevitably cause serious pipeline blockage. This will cause scarce hardware resources such as the out-of-order execution buffer, reorder buffer, and physical register file of the processor core to be occupied for a long time by instructions that have been executed but cannot be retired, significantly reducing the processor's instruction-level parallel throughput. The trajectory processing circuit 110 constructs a preliminary trajectory record containing multiple fields when the instruction reaches the write-back stage, quickly capturing the ready execution information. The synchronous decoupling trajectory circuit 120 receives this preliminary record and asynchronously fills in the incomplete fields. This asynchronous data processing mechanism ensures that the instruction execution process does not stagnate due to waiting for slow-returning memory write values, timestamp read values, or write values, fundamentally avoiding pipeline stalls and significantly shortening the overall latency from instruction execution to retirement. The synchronous decoupling trajectory circuit 120, as a dedicated hardware buffer and filling unit, undertakes the collection and encapsulation of latency-sensitive data without interfering with the continuous instruction fetching and decoding of the main instruction pipeline. This achieves deep parallelism between the execution unit and the trajectory generation unit, greatly improving the effective throughput of the processor core. Simultaneously, the instruction retirement condition is rigidly bound to the successful reception of trajectory records or operation logs by the synchronous decoupled trajectory circuit 120. This makes the instruction's update of the architecture state and the trajectory record's entry into the decoupled circuit an inseparable atomic event, avoiding the semantic inconsistency problem caused by the disconnect between hardware state updates and trajectory records. It also avoids verification failures and retries triggered by missing or out-of-order data in the backend proof system, further reducing overall computational waste. At the storage and data flow level, the prototype trajectory record is immediately transferred to the synchronous decoupled trajectory circuit 120 after instruction retirement, allowing temporary storage resources within the pipeline to be released quickly, reducing bandwidth pressure on on-chip cache and storage subsystems. The synchronous decoupled trajectory circuit 120 outputs complete proof trajectory records after all fields are complete, optimizing the output efficiency of trajectory data and alleviating performance constraints caused by the storage wall. This solution ensures the efficiency and performance of proof trajectory record generation while the processor 100 executes user programs at high performance, providing complete, ordered, and semantically consistent execution witness data for subsequent proofs, achieving hardware performance enhancement across the entire chain from instruction execution and state tracking to proof verification.

[0070] In some embodiments, the trajectory processing circuit 110 is further configured to construct a trajectory record or operation log corresponding to the type of retirement instruction, based on the type of retirement instruction.

[0071] In one implementation, a trajectory record corresponding to the type of retirement instruction is constructed. For example, multiplexed fields are differentiated according to the instruction type to form a valid set of fields that matches the instruction type.

[0072] Taking the trajectory field in the above embodiment as an example, for ordinary operation instructions, the trajectory processing circuit 110 fills in: valid, zk_clk or base_timestamp, pc, inst, and rs1Index, rs1Val and rs1Tsp (the number, value and old timestamp of source register 1), and rs2OrMemIndex, rs2OrMemVal, rs2OrMemTsp (the number, value and old timestamp of source register 2), and rdOrMemIndex, rdOrMemReadValue, rdOrMemWriteValue, rdOrMemTsp (the number, old value, write-back value and old timestamp of the destination register).

[0073] Taking the trajectory field in the above embodiment as an example, for the load instruction, the trajectory processing circuit 110 fills in: valid, zk_clk or base_timestamp, pc, inst, and rs1Index, rs1Val and rs1Tsp (base address register number, value and old timestamp), and rs2OrMemIndex, rs2OrMemVal, rs2OrMemTsp (memory access address, memory read value and old timestamp), and rdOrMemIndex, rdOrMemReadValue, rdOrMemWriteValue, rdOrMemTsp (destination register number, old value, write-back value and old timestamp).

[0074] Taking the trajectory field in the above embodiment as an example, for the storage instruction, the trajectory processing circuit 110 fills in: valid, zk_clk or base_timestamp, pc, inst, and rs1Index, rs1Val and rs1Tsp (the number, value and old timestamp of the base address register), and rs2OrMemIndex, rs2OrMemVal, rs2OrMemTsp (the number, value and old timestamp of the source register 2), and rdOrMemIndex, rdOrMemReadValue, rdOrMemWriteValue, rdOrMemTsp (the address, old value, written value and old timestamp of the memory to be written).

[0075] In one implementation, a trajectory record corresponding to the type of retirement instruction is constructed. For example, a corresponding trajectory field is generated based on the instruction type and filled accordingly to form a valid field that matches the instruction type.

[0076] Taking the trajectory field in the above embodiment as an example, for the loading instruction, the field names are not reused. Instead, rs2OrMemIndex, rs2OrMemVal, and rs2OrMemTsp are replaced with memAddr, memReadVal, and memTsp. In this example, only the field names are changed, and the actual meaning represented by the fields is not changed.

[0077] Taking the trajectory field in the above embodiment as an example, for the storage instruction, the field name is not reused. Instead, rdOrMemIndex, rdOrMemReadValue, rdOrMemWriteValue, and rdOrMemTsp are replaced with memAddr, memOldVal, memNewVal, and memTsp. In this example, only the field name is changed, and the actual meaning represented by the field is not changed.

[0078] It should be noted that, depending on the command type, a number of fields corresponding to the command type can be generated. That is, the number of trajectory fields or log fields included in the trajectory record or operation log can vary for different commands. A first number of fields can also be preset. If a command requires a second number of fields, and the second number is less than the first number, the fields not needed by the command can be marked as invalid, and the trajectory record will be output normally after the required fields for the command are filled. Examples will not be provided here.

[0079] In the above scheme, corresponding trajectory records or operation logs are generated according to the type of retirement instruction, providing clear structured data, ensuring the completeness and correctness of the trajectory records in the final proof, and reserving sufficient compatibility space for future instruction set expansion.

[0080] In some embodiments, the trajectory processing circuit 110 is further configured to provide the synchronous decoupled trajectory circuit 120 with the data required for the incomplete trajectory field or log field in the trajectory record or operation log, based on the trajectory record or operation log.

[0081] In one implementation, when filling trajectory records or operation logs, the trajectory processing circuit 110 can send trajectory records or operation logs including complete fields but not complete field values ​​to the synchronous decoupling trajectory circuit 120, and continuously send field values ​​corresponding to incomplete trajectory fields or operation logs to the synchronous decoupling trajectory circuit 120. For example, for a load instruction, the read value of memory access and the old timestamp can be sent asynchronously to the synchronous decoupling trajectory circuit 120. As another example, for a store instruction, the old value of memory, the write value, and the old timestamp can be sent asynchronously to the synchronous decoupling trajectory circuit 120.

[0082] In the above scheme, the instruction context held by the trajectory processing circuit 110 is used to ensure accurate matching between asynchronous data and trajectory records or operation logs. While ensuring the integrity and correctness of the trajectory records, the scheme optimizes the division of responsibilities and timing convergence between modules.

[0083] Please see Figure 2 , Figure 2 This is a schematic diagram of the processor structure in some embodiments of this application. Figure 2 The trajectory processing circuit 110 includes a processor core 111, which includes an instruction pipeline circuit 1111 connected to a synchronous decoupled trajectory circuit 120. The instruction pipeline circuit 1111 is used to construct trajectory records or operation logs and send trajectory records or operation logs to the synchronous decoupled trajectory circuit 120 when the retirement instruction meets the preset retirement conditions.

[0084] In one implementation, processor 100 can be modified from a Rocket Chip RV32IM sequential single-issue core. Processor core 111 is also a Rocket Chip RV32IM sequential single-issue core. The instruction pipeline circuit 1111 in processor core 111 is configured to process instructions sequentially according to a five-stage pipeline: fetch, decode, execute, memory access, and write-back. When an instruction reaches the write-back stage, the instruction pipeline circuit 1111 constructs a trajectory record or operation log corresponding to that instruction. This processor 100 adopts a sequential single-issue architecture, where instructions arrive at the write-back stage strictly according to the program order, and the construction order of the trajectory record or operation log is consistent with the instruction execution order.

[0085] In one implementation, when a retirement instruction meets preset retirement conditions, a trajectory record or operation log is sent to the synchronous decoupling trajectory circuit 120. For example, when the retirement instruction and / or the trajectory record or operation log corresponding to the retirement instruction meets the preset retirement conditions, the instruction pipeline circuit 1111 sends the trajectory record or operation log to the synchronous decoupling trajectory circuit 120. In one example, the retirement instruction meeting the preset retirement conditions may mean that the retirement instruction meets the retirement semantics of a standard RISC-V five-stage pipeline, and the trajectory record or operation log corresponding to the retirement instruction meeting the preset retirement conditions may mean that fields in the trajectory record or operation log meet preset requirements, for example, the pc is located in a pre-configured user program address space.

[0086] In the above scheme, the instruction pipeline circuit 1111 sends trajectory records or operation logs to the synchronous decoupling trajectory circuit 120 when the instruction to be retired meets the preset retirement conditions. This ensures that the trajectory records or operation logs originate from real and valid instruction execution and have a complete initial structure, thus providing a reliable and compliant input basis for the subsequent asynchronous backfilling and proof trajectory record generation of the synchronous decoupling trajectory circuit 120. At the same time, this mechanism can automatically filter out invalid instructions such as replays and exceptions, avoiding the generation of useless trajectory records for them, saving the storage and bandwidth resources of the synchronous decoupling trajectory circuit 120, and ensuring that the final output proof trajectory records strictly correspond to the real and valid instruction execution history in the user program.

[0087] In some embodiments, the preset retirement conditions include a first preset condition and a second preset condition; the trajectory processing circuit 110 is further configured to send a trajectory record or operation log to the synchronous decoupling trajectory circuit 120 when the retirement instruction meets both the first and second preset conditions, wherein the first preset condition is used to determine whether the retirement instruction has been successfully executed and has not triggered an exception, and the second preset condition is used to determine whether the address of the retirement instruction is located in the proof area.

[0088] The first preset condition can be the continuation of the retirement semantics of the standard RISC-V five-stage pipeline, that is, whether the instruction to be retired is valid, whether a return has occurred, and whether an exception has occurred. If all of these conditions are met, then the instruction to be retired satisfies the first preset condition.

[0089] The trajectory processing circuit 110 can simultaneously determine whether the retirement instruction meets the first preset condition and the second preset condition, or it can use the second preset condition as a further determination of the first preset condition.

[0090] In one implementation, the second preset condition is used to determine whether the address of the instruction to be retired is located in the verification region. That is, verification is only required for the trajectory record or operation log corresponding to the instruction to be retired if the address of the instruction to be retired is located in the verification region. The verification region can be a pre-configured user program address space. For example, it can be determined whether the PC of the instruction to be retired is located in the pre-configured user program address space. If the PC is located in the pre-configured user program address space, the trajectory record or operation log is sent to the synchronous decoupling trajectory circuit 120. In one example, the verification region is [userMemBase, userMemBase + userMemSize), which can be configured by the HOST (host side / host machine), where userMemBase is the starting address and userMemSize is the address size. In addition, if the instruction to be retired does not meet the second preset condition, for example, if the pc is located in Boot ROM (Boot Read-Only Memory), MMIO (Memory-Mapped I / O), startup code or other non-proof areas, then the instruction to be retired can be retired according to the semantics of a normal processor, without sending trajectory records or operation logs to the synchronous decoupling trajectory circuit 120, and without generating proof trajectory records.

[0091] The above scheme is compatible with the retirement semantics of the standard RISC-V pipeline and precisely defines the generation range of the proof trajectory record, so that only instructions located within the proof area enter the generation path of the proof trajectory record, thereby avoiding the generation of useless trajectory records or operation logs for instructions that do not require proof, and saving the storage and bandwidth resources of the synchronous decoupling trajectory circuit 120.

[0092] Please see Figure 3 , Figure 3 This is a schematic diagram of the processor structure in some embodiments of this application. Figure 3 The processor core 111 includes: a memory data cache circuit 1112, connected to the instruction pipeline circuit 1111, for providing memory data to the synchronous decoupling trajectory circuit 120, so that the synchronous decoupling trajectory circuit 120 fills the memory data into the corresponding incomplete trajectory field or log field in the trajectory record or operation log; and a memory timestamp cache circuit 1113, connected to the instruction pipeline circuit 1111, for providing memory timestamps to the synchronous decoupling trajectory circuit 120, so that the synchronous decoupling trajectory circuit 120 fills the memory timestamps into the corresponding incomplete trajectory field or log field in the trajectory record or operation log.

[0093] In one embodiment, the memory data cache circuit 1112 is used to provide memory data to the synchronous decoupling trajectory circuit 120. For example, when the instruction type processed by the instruction pipeline circuit 1111 is a load instruction, the memory read value corresponding to the memory access address is provided to the instruction pipeline circuit 1111, so that the memory read value corresponding to the memory access address is provided to the synchronous decoupling trajectory circuit 120 through the instruction pipeline circuit 1111. As another example, when the instruction type processed by the instruction pipeline circuit 1111 is a store instruction, the old value corresponding to the memory write address is provided to the instruction pipeline circuit 1111, so that the old value corresponding to the memory write address is provided to the synchronous decoupling trajectory circuit 120 through the instruction pipeline circuit 1111.

[0094] In one embodiment, the memory data cache circuit 1112 is also used to receive memory data returned by the instruction pipeline circuit 1111. For example, when the instruction type processed by the instruction pipeline circuit 1111 is a store instruction, it receives the write value corresponding to the memory write address.

[0095] In one embodiment, the memory timestamp cache circuit 1113 provides memory timestamps to the synchronization decoupling trajectory circuit 120. For example, when the instruction type processed by the instruction pipeline circuit 1111 is a load instruction, it provides the old timestamp corresponding to the memory access address to the instruction pipeline circuit 1111, so that the memory read value corresponding to the memory access address is provided to the synchronization decoupling trajectory circuit 120 through the instruction pipeline circuit 1111. As another example, when the instruction type processed by the instruction pipeline circuit 1111 is a store instruction, it provides the old timestamp corresponding to the memory write address to the instruction pipeline circuit 1111, so that the old timestamp corresponding to the memory write address is provided to the synchronization decoupling trajectory circuit 120 through the instruction pipeline circuit 1111.

[0096] In one embodiment, the memory timestamp cache circuit 1113 is also used to receive the memory timestamp returned by the instruction pipeline circuit 1111. For example, when the instruction type processed by the instruction pipeline circuit 1111 is a store instruction, it receives the new timestamp corresponding to the memory write address, wherein the new timestamp corresponding to the memory write address represents the timestamp corresponding to the memory write event (storing the write value to the memory write address).

[0097] In one embodiment, the memory data cache circuit 1112 and the memory timestamp cache circuit 1113 are connected to the instruction pipeline circuit 1111 according to a preset connection method. Taking the instruction pipeline circuit 1111 as a five-stage pipeline circuit as an example, the memory data cache circuit 1112 and the memory access stage of the instruction pipeline circuit 1111 are connected via a handshake, and the memory timestamp cache circuit 1113 and the memory access stage of the instruction pipeline circuit 1111 are also connected via a handshake. Figure 3 As shown.

[0098] In one embodiment, memory data is cached in memory data caching circuit 1112 and / or stored by memory data caching circuit 1112 to the target storage device, and / or memory timestamp data is cached in memory timestamp caching circuit 1113 and / or stored by memory timestamp caching circuit 1113 to the target storage device, such as Figure 3 As shown. In one example, the target storage device is located outside the processor, and memory data and memory timestamps can be stored in different areas of the target storage device, which can be DRAM (Dynamic Random Access Memory).

[0099] In the above scheme, memory data is provided by memory data cache circuit 1112, and memory timestamp cache circuit 1113 is added to the processing core 111 to provide memory timestamp data, so as to maintain memory-related data while executing user programs, and provide clear and provable data for backend memory consistency proof.

[0100] Please continue reading. Figure 3 The processor core 111 includes a general-purpose register circuit 1114 connected to the instruction pipeline circuit 1111, used to provide register service data to the synchronous decoupling trajectory circuit 120, so that the synchronous decoupling trajectory circuit 120 fills the register service data into the corresponding incomplete trajectory field or log field in the trajectory record or operation log; the trajectory processing circuit 110 also includes a register timestamp circuit 112 connected between the instruction pipeline circuit 1111 and the synchronous decoupling trajectory circuit 120, used to provide register timestamps to the synchronous decoupling trajectory circuit 120, so that the synchronous decoupling trajectory circuit 120 fills the register timestamps into the corresponding incomplete trajectory field or log field in the trajectory record or operation log.

[0101] In one implementation, the general-purpose register circuit 1114 provides register service data to the synchronous decoupling trajectory circuit 120. For example, when the instruction processed by the instruction pipeline circuit 1111 is a normal arithmetic instruction, it provides the value of source register 1, the value of source register 2, and the old value of the destination register to the instruction pipeline circuit 1111, so that the instruction pipeline circuit 1111 provides the value of source register 1, the value of source register 2, and the old value of the destination register to the synchronous decoupling trajectory circuit 120. As another example, when the instruction processed by the instruction pipeline circuit 1111 is a load instruction, it provides the value of source register 1 and the old value of the destination register to the instruction pipeline circuit 1111, so that the instruction pipeline circuit 1111 provides the value of source register 1 and the old value of the destination register to the synchronous decoupling trajectory circuit 120. For example, when the instruction type processed by the instruction pipeline circuit 1111 is a store instruction, the values ​​of source register 1 and source register 2 are provided to the instruction pipeline circuit 1111 so that the values ​​of source register 1 and source register 2 are provided to the synchronous decoupling trajectory circuit 120 through the instruction pipeline circuit 1111.

[0102] In one embodiment, the general-purpose register circuit 1114 is also used to receive register data returned by the instruction pipeline circuit 1111. For example, when the instruction type processed by the instruction pipeline circuit 1111 is a normal arithmetic instruction, it receives the write-back value of the destination register. As another example, when the instruction type processed by the instruction pipeline circuit 1111 is a load instruction, it receives the write-back value of the destination register.

[0103] In one embodiment, the register timestamp circuit 112 provides register timestamps to the synchronous decoupling trajectory circuit 120. For example, when the instruction type processed by the instruction pipeline circuit 1111 is a normal arithmetic instruction, it provides the old timestamps of source register 1, source register 2, and destination register to the synchronous decoupling trajectory circuit 120. As another example, when the instruction type processed by the instruction pipeline circuit 1111 is a load instruction, it provides the old timestamps of source register 1 and destination register to the synchronous decoupling trajectory circuit 120. As yet another example, when the instruction type processed by the instruction pipeline circuit 1111 is a store instruction, it provides the old timestamps of source register 1 and source register 2 to the synchronous decoupling trajectory circuit 120.

[0104] In one implementation, the register timestamp circuit 112 is also used to receive the register timestamp returned by the instruction pipeline circuit 1111. For example, when the instruction type processed by the instruction pipeline circuit 1111 is a load instruction or a normal operation instruction, the new timestamp of the target register is received, wherein the new timestamp of the target register represents the timestamp corresponding to the register write-back event (storing a new value in the target register).

[0105] In the above scheme, the general-purpose register circuit 1114 provides register service data, and the register timestamp circuit 112 provides register timestamp data, so as to maintain the register-related data while executing the user program, avoid supplementing the fields required for proof through additional microinstructions, software scanning or multi-cycle register supplementary reading, and provide clear and provable data for back-end register consistency proof.

[0106] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of a system-on-a-chip (SoC) according to some embodiments of this application. A processor 100 is disposed in the SoC 10, which includes a pre-compilation arithmetic circuit 200 connected between an instruction pipeline circuit 1111 and a synchronous decoupling trajectory circuit 120. The instruction pipeline circuit 1111 is also used to, in conjunction with the pre-compilation arithmetic circuit 200, construct a trajectory record or operation log corresponding to the instruction to be retired when the type of the instruction to be retired is a pre-compiled call instruction.

[0107] The pre-compilation operation circuit 200 can be an integrated circuit used to process pre-compilation operations.

[0108] In one implementation, the pre-compilation operation circuit 200 may include a coprocessor. Specifically, the coprocessor is scheduled by the processor 100 and executes instructions from the processor 100. Using the processor core 111 as an example, which is based on Rocket Core, the coprocessor is connected to the instruction pipeline circuit 1111 via a RoCC (Rocket Custom Coprocessor) interface. It receives pre-compilation call instructions sent by the instruction pipeline circuit 1111 and performs pre-compilation operations related to these instructions. In one example, the coprocessor is connected to the write-back stage of the instruction pipeline circuit 1111. The pre-compilation operations include, but are not limited to, hash operations, large integer operations, elliptic curve operations, finite field operations, and signature verification. In another example, the pre-compilation call instructions may be pre-defined instructions in the user program, such as custom RoCC instructions.

[0109] In one implementation, the instruction pipeline circuit 1111 identifies the instruction to be retired and, when the instruction to be retired is a precompiled call instruction, sends the precompiled call instruction to the precompilation operation circuit 200. For example, the instruction pipeline circuit 1111 identifies the instruction type during the decoding stage, and after identifying it as a precompiled call instruction, sends the precompiled call instruction from the write-back stage to the precompilation operation circuit 200. In one example, the precompiled call instruction may include preset field information, such as a precompiled operation type field, used to identify the specific precompiled operation type (e.g., hash operation), the value of source register 1, the value of source register 2, and the old value of the destination register, etc.

[0110] If memory-related operations are involved, the pre-compilation operation circuit 200 can obtain relevant memory data or memory timestamps. In one embodiment, the pre-compilation operation circuit 200 is connected to the memory data cache circuit 1112 and the memory timestamp cache circuit 1113, and obtains the corresponding memory data or memory timestamps from the memory data cache circuit 1112 and the memory timestamp cache circuit 1113.

[0111] In one implementation, the instruction pipeline circuit 1111 and the pre-compilation operation circuit 200 collaboratively construct a trajectory record or operation log corresponding to the instruction to be retired. For example, when the type of the instruction to be retired is a pre-compiled call instruction, the instruction pipeline circuit 1111 constructs part of the trajectory record or operation log of the instruction to be retired, and the pre-compilation operation circuit 200 constructs another part of the trajectory record or operation log of the instruction to be retired. Furthermore, the pre-compilation operation circuit 200 can return the constructed trajectory record or operation log to the instruction pipeline circuit 1111, and the instruction pipeline circuit 1111 sends it to the synchronous decoupling trajectory circuit 120. In one example, the fields constructed by the instruction pipeline circuit 1111 may include valid, zk_clk or base_timestamp, pc, inst, rs1Index, rs1Val, rs1Tsp, rs2OrMemIndex, rs2OrMemVal, rs2OrMemTsp, rdOrMemIndex, rdOrMemReadValue, and rdOrMemTsp, and the fields constructed by the pre-compilation operation circuit 200 may include rdOrMemWriteValue.

[0112] It should be noted that the fields related to the precompile call instruction are not limited to the examples above. In another example, the precompile call instruction may also include: precompile_id, which identifies the type of precompile operation; input_digest and output_digest, which can be used to compress large inputs and large outputs, and can be selected to record complete data, summary data or address range pointing to a memory table according to the constraint format of the back-end proof circuit; and status, which is used to indicate the operation success, invalid input, exception or rollback status, etc.

[0113] In the above scheme, a pre-compilation operation circuit 200 is introduced to process pre-compilation call instructions in the user program, which greatly improves the execution efficiency of such heavy-load operations. Furthermore, the pre-compilation operation circuit 200 and the instruction pipeline circuit 1111 work together to construct the trajectory record or operation log of the instruction to be retired, realize the generation mechanism of the reuse trajectory record or operation log, and ensure the integrity and correctness of the fields in the trajectory record or operation log, thereby providing reliable and complete witness data for subsequent proof.

[0114] In some embodiments, the trajectory processing circuit 110 is further configured to stop sending trajectory records or operation logs to the synchronous decoupling trajectory circuit 120 when it receives a signal indicating to pause the transmission of trajectory records or operation logs.

[0115] The signal used to indicate the pause of sending trajectory records or operation logs can be triggered by the trajectory processing circuit 110 itself, or by another circuit part.

[0116] In one embodiment, the trajectory processing circuit 110 automatically triggers a signal indicating a pause in sending trajectory records or operation logs under preset conditions. For example, the preset conditions include, but are not limited to, at least one of the following: for a load instruction, the old value corresponding to the memory access address was not read; for a store instruction, the old value corresponding to the memory write address was not read.

[0117] In one embodiment, the trajectory processing circuit 110 receives a signal from another circuit section indicating to pause the transmission of trajectory records or operation logs, for example, the other circuit section is a synchronous decoupling trajectory circuit 120.

[0118] In one implementation, when the trajectory processing circuit 110 receives a signal indicating a pause in sending trajectory records or operation logs, it stops sending trajectory records or operation logs to the synchronous decoupling trajectory circuit 120. For example, the signal indicating a pause in sending trajectory records or operation logs is applied to the instruction pipeline circuit 1111, causing the instruction pipeline circuit 1111 to pause sending trajectory records or operation logs. In one example, when the instruction pipeline circuit 1111 receives a signal indicating a pause in sending trajectory records or operation logs, it freezes the execution phase, memory access phase, and write-back phase, and prevents the instruction fetch phase from continuing to send new instructions to the decoding phase.

[0119] In the above scheme, the transmission of trajectory records or operation logs is paused when fields in the trajectory records or operation logs are incomplete or when the synchronous decoupling trajectory circuit 120 cannot receive them. This ensures the integrity of the trajectory records or operation logs on one hand, and dynamically adjusts the transmission rhythm of the trajectory records or operation logs based on the pause signal from the synchronous decoupling trajectory circuit 120 on the other. Simultaneously, by pausing the pipeline circuit 1111, new instructions are prevented from entering, ensuring that instructions are not erroneously advanced and the architecture state is not illegally updated during backpressure, thus providing a safe timing boundary for the construction of trajectory records or operation logs and asynchronous backfilling.

[0120] Please continue reading. Figure 3 The synchronous decoupling trajectory circuit 120 is also used to send a signal to the trajectory processing circuit 110 to indicate that the transmission of trajectory records or operation logs should be suspended when the synchronous decoupling trajectory circuit 120 is unable to output trajectory records or operation logs and / or is unable to receive trajectory records or operation logs.

[0121] In one embodiment, the synchronous decoupling trajectory circuit 120 sends a signal to the trajectory processing circuit 110 instructing the pausing of trajectory recording. For example... Figure 3As shown, the synchronous decoupling trajectory circuit 120 includes a reverse voltage signal line 120a connected to the trajectory processing circuit 110. When the synchronous decoupling trajectory circuit 120 is unable to output trajectory records or operation logs, and / or is unable to receive trajectory records or operation logs, it sends a signal (reverse voltage signal) instructing the trajectory processing circuit 110 to pause the transmission of trajectory records or operation logs via the reverse voltage signal line 120a. In one example, the output of the synchronous decoupling trajectory circuit 120 is connected to a trajectory parsing circuit 130. The trajectory parsing circuit 130 includes, but is not limited to, receiving the trajectory records or operation logs output by the synchronous decoupling trajectory circuit 120, parsing the trajectory records or operation logs into a preset format (such as parsing them into proof trajectory records readable by subsequent proofs), and outputting the trajectory records or operation logs to a target storage area, such as a storage area accessible to the circuit that performs the proof. In response to the trajectory parsing circuit 130 being unable to receive trajectory records or operation logs, the synchronous decoupling trajectory circuit 120 receives a reverse voltage from the trajectory parsing circuit 130, and then outputs a reverse voltage signal to the trajectory processing circuit 110 through the reverse voltage signal line 120a. In another example, if the synchronous decoupling trajectory circuit 120 can no longer store the trajectory records or operation logs corresponding to the next instruction, the synchronous decoupling trajectory circuit 120 outputs a reverse voltage signal to the trajectory processing circuit 110 through the reverse voltage signal line 120a.

[0122] When the trajectory processing circuit 110 receives a signal indicating to pause the transmission of trajectory records or operation logs, it stops sending trajectory records or operation logs to the synchronous decoupling trajectory circuit 120, for example, by pausing the pipeline circuit 1111.

[0123] The above scheme effectively prevents data overflow and loss caused by the synchronous decoupling trajectory circuit 120's inability to receive or output data. By sending a signal to the trajectory processing circuit 110 to indicate the suspension of trajectory recording or operation log transmission, it ensures that the front-end instructions are not erroneously advanced and the architecture state is not illegally updated when the receiving end is abnormal, thus maintaining the timing security of the generation and transmission of the trajectory record.

[0124] In some embodiments, the synchronous decoupling trajectory circuit 120 includes a storage area for storing a preset number of trajectory records or operation logs.

[0125] Taking the synchronous decoupling trajectory circuit 120, which includes storage areas A1, A2, ..., An, as an example, storage areas A1, A2, ..., An are used to store trajectory records or operation logs corresponding to different instructions. For example, storage area A1 stores trajectory record or operation log B1, storage area A2 stores trajectory record or operation log B2, ..., storage area A3 stores trajectory record or operation log B3. The trajectory record or operation log B1, trajectory record or operation log B2, and trajectory record or operation log B3 are all different.

[0126] In the above scheme, a preset number of independent storage areas are set in the synchronous decoupling trajectory circuit 120, enabling the synchronous decoupling trajectory circuit 120 to simultaneously cache trajectory records or operation logs of multiple different instructions, providing multi-depth buffering for asynchronous backfilling. This design supports parallel data backfilling of multiple trajectory records, improving backfilling efficiency. At the same time, the elastic buffer formed can absorb the pressure of sudden front-end transmission, reduce the backpressure frequency on the instruction pipeline, and ensure the isolation and integrity of each instruction trajectory data.

[0127] In some embodiments, the synchronous decoupling trajectory circuit 120 is further configured to sequentially fill in the incomplete trajectory field or log field in the trajectory record or operation log in the synchronous decoupling trajectory circuit 120 according to the receiving order of the trajectory record or operation log.

[0128] In one implementation, the synchronous decoupling trajectory circuit 120 employs a blocking data filling method. Continuing with the example of storage areas A1, A2...An, and trajectory records or operation logs B1, B2, and B3 being received sequentially by the synchronous decoupling trajectory circuit 120, if trajectory record or operation log B1 contains incomplete trajectory fields or log fields, then these incomplete trajectory fields or log fields in trajectory record or operation log B1 are filled. In response to the absence of incomplete trajectory fields or log fields in trajectory record or operation log B1, it is determined whether trajectory record or operation log B2 contains incomplete trajectory fields or log fields. If so, these incomplete trajectory fields or log fields in trajectory record or operation log B2 are filled. This process is repeated to fill in incomplete trajectory fields or log fields in trajectory records or operation logs sequentially according to the receiving order.

[0129] In one implementation, the synchronous decoupling trajectory circuit 120 uses a preset identifier filling method. The preset identifier includes, but is not limited to, pc, inst, and zk_clk. Taking zk_clk as an example, zk_clk increments when the retirement instruction is completed; that is, it increments when the trajectory record or operation log is received by the synchronous decoupling trajectory circuit 120. Each trajectory record or operation log entering the synchronous decoupling trajectory circuit 120 includes a unique zk_clk field that monotonically increments according to the entry order. For field values ​​asynchronously returned from the trajectory processing circuit 110 to the synchronous decoupling trajectory circuit 120, the corresponding trajectory record or operation log can be found based on zk_clk, and the corresponding field can be filled.

[0130] In the above scheme, the synchronous decoupling trajectory circuit 120 can asynchronously backfill in incomplete trajectory fields or operation logs in an orderly and correct manner according to the received sequence of trajectory records or operation logs. This ensures that the fields of the final output trajectory records or operation logs are complete and in the correct order, providing reliable witness data for subsequent verification.

[0131] In some embodiments, the synchronous decoupling trajectory circuit 120 is further configured to output the trajectory records in the synchronous decoupling trajectory circuit 120 sequentially according to the receiving order of the trajectory records.

[0132] In one implementation, the synchronous decoupling trajectory circuit 120 adopts a blocking data filling method, strictly following the receiving order to fill in the unfinished fields of the trajectory records or operation logs B1 to Bn in the storage areas A1 to An one by one. Only after all the unfinished fields of the previous trajectory record are filled is it output and the filling of the next record continues, thereby realizing the sequential output according to the receiving order.

[0133] In one implementation, the synchronous decoupling trajectory circuit 120 uses a preset identifier filling method. Each trajectory record or operation log entering the synchronous decoupling trajectory circuit 120 includes a unique zk_clk field that monotonically increases in the order of entry. The synchronous decoupling trajectory circuit 120 fills the corresponding field of the corresponding trajectory record with asynchronously returned data according to zk_clk. In response to all incomplete fields of any trajectory record or operation log being filled, the synchronous decoupling trajectory circuit 120 outputs the trajectory records or operation logs sequentially in the monotonically increasing order of zk_clk.

[0134] In the above scheme, the synchronous decoupling trajectory circuit 120 outputs trajectory records sequentially according to the receiving order, ensuring that the output trajectory records or operation logs strictly follow the instruction execution order, which meets the strict requirements of subsequent proof on trajectory order, so that the back-end proof does not need to reorder the trajectory, reducing the complexity of data processing, and taking into account both the efficiency of internal asynchronous backfilling and the timing correctness of external data consumption.

[0135] Please see Figure 5-8 , Figure 5 This is a schematic diagram of the structure of a zero-knowledge proof system according to some embodiments of this application. Figure 1 , Figure 6 This is a schematic diagram of the structure of a zero-knowledge proof system according to some embodiments of this application. Figure 2 , Figure 7 This is a schematic diagram of the zero-knowledge proof process for some embodiments of this application. Figure 1 , Figure 8 This is a schematic diagram of the zero-knowledge proof process for some embodiments of this application. Figure 2 ,in, Figures 7-8 These are two examples of numerous zero-knowledge proof process embodiments in this application. The zero-knowledge proof system 500 includes: a host 510, used to provide a program, input parameters, and configuration data, wherein the program includes at least one instruction; an on-chip system 520, used to acquire the program, input parameters, and configuration data, and generate a proof trajectory record corresponding to at least one instruction; and a proof circuit 530, used to acquire the proof trajectory record, and after generating proof data corresponding to the proof trajectory record, return the proof data to the host.

[0136] The host 510 can be a control-side electronic device in the zero-knowledge proof system 500 responsible for controlling and managing the proof task. In one embodiment, the host 510 includes, but is not limited to, a host CPU, host DDR (Double Data Rate Synchronous Dynamic Random-Access Memory), an operating system, a ZKTrace application, a PCIe driver, a task scheduling module, and a shared memory management module.

[0137] The program can be a user program, that is, a program to be proven, which includes at least one instruction. In one implementation, the host 510 compiles the program into a preset format file, such as a RISC-V ELF format file.

[0138] Input parameters can be a collective term for program input data provided by the host that the program to be proven depends on when executing zero-knowledge proof. In one implementation, input parameters include, but are not limited to, common proof inputs and nondeterministic inputs.

[0139] Configuration data can be data used to initialize and manage the hardware resources of the zero-knowledge proof system. In one implementation, the configuration data includes configuring multiple regions. For example, the configuration data includes, but is not limited to: the base address and size of the user program area, the base address and size of the memory timestamp area, the base address and length of the proof trajectory record output area, and other system configuration parameters.

[0140] The system-on-a-chip 520 may include, but is not limited to, the processor 100 in the above embodiments, or the processor 100 and pre-compiled computing circuit 200 in the above embodiments.

[0141] In one implementation, the system-on-chip 520 is connected to a host 510 to obtain programs, input parameters, and configuration data from the host 510. Further, the system-on-chip 520 generates a proof trajectory record corresponding to at least one instruction. The proof trajectory record can be used for zero-knowledge proofs. The number of proof trajectory records can be equal to or less than the number of at least one instruction. For details on how to generate the proof trajectory records, please refer to the above embodiments; further details will not be repeated here.

[0142] The proof circuit 530 can be an integrated circuit in the zero-knowledge proof system 500 responsible for proving the proof trajectory record to generate proof data.

[0143] In one implementation, the proof circuit 530 includes, but is not limited to, a GPU (Graphics Processing Unit), an FPGA (Field-Programmable Gate Array), an ASIC (Application-Specific Integrated Circuit), or other programmable parallel computing devices.

[0144] In one implementation, the proof circuit 530 acquires proof trajectory records. For example, the proof circuit 530 is connected to the system-on-a-chip 520 to acquire proof trajectory records from the system-on-a-chip 520. Another example is that the proof circuit 530 reads proof trajectory records from a preset storage area, where the preset storage area can be the storage area of ​​a storage device in the host 510, i.e., the proof circuit 530 is connected to the host 510. Figure 5 As shown. The preset storage area can also be the storage area of ​​an independent storage device, where the on-chip system 520 outputs the proof trajectory record to the storage area after generating the proof trajectory record.

[0145] In one implementation, the proof circuit 530 generates proof data based on the proof trajectory record and returns the proof data to the host 510, such as... Figure 5As shown, the proof circuit 530 is connected to the host 510. The proof circuit 530 directly transmits the proof data to the host 510, or the proof circuit 530 outputs the proof data to a storage area in an independent storage device accessible to the host 510, so that the host 510 can read the proof data from that storage area. Furthermore, the proof circuit 530 can notify the host 510 via MSI-X (Extended Message Signaled Interrupts). When handling this interrupt, the host 510 can perform buffer refresh operations and memory cache invalidation operations to read the latest proof data.

[0146] In one embodiment, the proof circuit 530 performs a preset proof data generation operation to generate proof data. The preset proof data generation operation includes, but is not limited to, columnarizing, sorting, calculating permutation parameters, calculating search parameters, and calculating polynomial commitments on the proof trajectory record according to the constraints in the proof circuit 530.

[0147] In the above solution, the three-level collaborative architecture of host 510, system-on-chip 520 and proof circuit 530 realizes the efficient flow of the entire process of zero-knowledge proof task from issuance to generation. At the same time, the output proof trajectory record has completeness, order and semantic compliance, taking into account both execution efficiency and proof reliability, and provides feasible hardware support for the large-scale implementation of zero-knowledge proof.

[0148] In some embodiments, the host 510 is also configured to write the program, input parameters, and configuration data to shared memory, and perform a cache refresh operation after the writing is complete.

[0149] The shared memory can be a storage area accessible and writable by the host 510 and / or the system-on-chip 520 and / or the verification circuit 530. For example, the shared memory includes at least one of the following: a storage area within the host 510, a storage area within the system-on-chip 520, a storage area in the verification circuit 530, and an external storage device (such as DRAM).

[0150] In one example, the shared memory includes at least a separate input data area, a trajectory result collection area, and a proof data area. The input data area is used to store the program, input parameters, and configuration data provided by the host 510; the trajectory result collection area is used to store the proof trajectory records generated by the system-on-chip 520; and the proof data area is used to store the proof data generated by the proof circuit 530.

[0151] The trajectory result collection area can be further subdivided into multiple result collection areas. For example, it may include a result collection area for storing proof trajectory records, a result collection area for storing final state auxiliary trajectory records, and a result collection area for storing timestamp final state and result header information. The specific design can be based on the structure of the data related to the proof task that the System-on-Chip 520 can generate. The final state auxiliary trajectory records may include a memory final state data set and a register final state data set.

[0152] Furthermore, after the host 510 writes the program, input parameters, and configuration data to the shared memory, it performs a cache refresh operation to ensure that the latest data is written back to the shared memory from the host 510's cache. This ensures that the subsequent system-on-chip 520 accurately retrieves the program, input parameters, and configuration data from the shared memory. Additionally, after performing the cache refresh operation, a memory barrier operation can be performed to ensure that the program, input parameters, and configuration data are globally visible to the system-on-chip 520.

[0153] In the above solution, shared memory balances cross-device interaction efficiency and reliability, and in conjunction with the host 510 cache refresh mechanism, it prevents data from becoming outdated and is compatible with various certifications.

[0154] In some embodiments, the host 510 is further configured to send a trajectory generation start signal to the system on-chip 520; the system on-chip 520 is further configured to, upon receiving the trajectory generation start signal, acquire the program, input parameters and configuration data, and generate a proof trajectory record corresponding to at least one instruction.

[0155] In some implementations, after performing a preset operation (such as a cache refresh operation and / or a memory barrier operation), the host 510 sends a trace generation start signal to the system-on-chip 520, for example, by notifying the system-on-chip 520 to start via a PCIe doorbell or control register.

[0156] In some implementations, the system-on-chip 520 acquires the program, input parameters, and configuration data according to a preset reading method. For example, the read interface of the system-on-chip 520 is configured in a non-cached or strongly ordered mode to directly read the program, input parameters, and configuration data, bypassing obsolete caches. Furthermore, a proof trajectory record corresponding to at least one instruction is generated, as described in the above embodiments, and will not be repeated here.

[0157] In the above scheme, the host 510 triggers the transmission of the trajectory generation start signal only after performing a preset operation. The on-chip system 520 responds to the signal and starts data acquisition and proof trajectory record generation. This establishes a cross-device task triggering timing between the host 510 and the on-chip system 520. Furthermore, the host 510 sends the trajectory generation start signal only after performing the preset operation, which avoids the on-chip system 520 starting prematurely before the data is ready, thus preventing the reading of outdated data and ensuring the accuracy and completeness of the proof trajectory record generation.

[0158] In some embodiments, the system-on-chip 520 is further configured to send a trajectory generation end signal to the host 510 after generating a proof trajectory record corresponding to at least one instruction, so as to start the proof circuit 530 through the host 510.

[0159] In one implementation, after generating a proof trace record corresponding to at least one instruction, the on-chip system 520 generates an end signal via a PCIe MSI-X interrupt, completion register, or doorbell to notify the host 510 that a proof trace record corresponding to at least one instruction has been generated. Subsequently, the host 510 starts the proof circuit 530 to generate proof data based on the proof trace record.

[0160] In the above scheme, the closed-loop mechanism of the host 510 starting the proof circuit 530 is triggered by the end signal generated by the on-chip system 520, which further reduces the system idle waiting time and eliminates the computing power overhead of the host 510 polling the state. At the same time, the timing boundary from trajectory readiness to proof start is strictly locked by hardware signals to ensure that the data obtained by the proof circuit 530 is complete and valid.

[0161] In some embodiments, the host 510 is further configured to perform a memory barrier operation after receiving a trajectory generation end signal, and send a proof start signal to the proof circuit 530 after performing the memory barrier operation to start the proof circuit 530.

[0162] The memory barrier operation is used to ensure that the proof trajectory record is globally visible to the proof circuit 530.

[0163] In one implementation, the read interface of the proof circuit 530 is configured in an unbuffered or strongly ordered mode to directly read the complete proof trajectory record, for example, by reading the proof trajectory record from the trajectory result collection area.

[0164] In the above scheme, after receiving the trajectory generation end signal, the host 510 executes a memory barrier to ensure that the proof trajectory record output by the on-chip system 520 has been completely written to the shared memory, avoiding the risk of out-of-order transmission where the proof start signal is globally visible before the proof trajectory record. Furthermore, with the non-cached / strongly ordered read configuration of the proof circuit 530, there is no need to deploy a complex cross-device cache consistency protocol, which reduces the complexity of hardware implementation and avoids proof verification failure caused by incomplete or out-of-order trajectory data from the source, further improving the reliability of system operation and the success rate of tasks.

[0165] In some embodiments, the proof circuit 530 is further configured to write the proof data into shared memory after generating proof data corresponding to the proof trajectory record, and send a proof completion signal to the host 510.

[0166] As described in the above embodiments, the proof data can be written to the proof data area in shared memory. Then, after the proof data writing is complete, a proof completion signal is sent to the host 510, so that the host 510 can read the latest proof data.

[0167] In the above scheme, the task progress is precisely synchronized by hardware signals, avoiding host polling overhead and ensuring that the host can read the latest valid content only after the proof data is completely written to disk. Furthermore, the unified shared memory interface is compatible with various proof devices, further improving the closed loop of heterogeneous collaborative zero-knowledge proof tasks.

[0168] Please see Figure 9 , Figure 9 This is a flowchart illustrating a proof trajectory generation method according to some embodiments of this application. The method can be applied to processors, systems-on-a-chip (SoCs), electronic devices (such as computers), etc., for example, to processor 100 or SoC 520. Specifically, the relevant steps in this method can be executed by specific circuits in processor 100 or SoC 520. For example, the synchronous decoupling trajectory queue can be a synchronous decoupling trajectory circuit 120, which has corresponding functions and executes the relevant steps. The processor can be a CPU, specifically implemented based on a reduced instruction set architecture. In a specific embodiment, the processor can be a RISC-V based processor configured to execute user programs and generate corresponding proof trajectory records. The processor can be integrated into the SoC or located in an electronic device, and the SoC can also be located in an electronic device. The electronic device can be a computer, and the electronic device can execute the method through a processor or SoC, or it can implement the method through a program. The method steps are described with a processor or SoC as the execution subject. The method includes the following steps: S91: Construct a trajectory record or operation log corresponding to the retirement instruction. The trajectory record or operation log includes multiple trajectory fields or log fields.

[0169] Step S91 can be executed by the trajectory processing circuit in the processor. The trajectory processing circuit can be a circuit used to execute instructions in the user program and construct trajectory records or operation logs corresponding to the retirement instructions.

[0170] Retirement instructions can be instructions that are being executed in a user program but have not yet been retired. Taking instructions currently being executed in the processor as an example, retirement instructions can be instructions in a user program that have entered the write-back phase and are waiting to be retired.

[0171] Trajectory records or operation logs can be a data form of instruction execution evidence structure. Instruction execution evidence structure can be a data set automatically captured and constructed from relevant data generated by the execution of an instruction, used to record and prove the instruction execution process and results. In different implementations or application scenarios, instruction execution evidence structure can be called trajectory records, operation logs, execution traces, verification data packets, etc. That is to say, it can also be used to construct execution trajectories and verification data packets corresponding to instructions to be retired. This application's use of "trajectory records" or "operation logs" does not limit this application to constructing only trajectory records or operation logs corresponding to instructions to be retired.

[0172] As mentioned above, trajectory records or operation logs can be a data set that is automatically captured and constructed from the relevant data generated by the execution of instructions, used to record and prove the execution process and results of the instructions. The trajectory field or log field can be the data in the set used to record and prove the execution process and results of the instructions.

[0173] In one implementation, the constructed trajectory record or operation log includes multiple trajectory fields or log fields. Taking the trajectory field as an example, the trajectory field may include, but is not limited to, at least one of the following: valid, used to indicate whether the current trajectory data is valid; zk_clk or base_timestamp derived from zk_clk, used to record the position of the instruction in the global instruction clock sequence, or as a reference for derived timestamps; pc, used to record the program counter address of the instruction; inst, used to record the opcode and operand encoding of the instruction; rs1Index, used to record the number (index) of source register 1; rs1Val, used to record the value of source register 1; rs1Tsp, used to record the old time corresponding to source register 1. The system contains several time stamps: rs2OrMemIndex (used to record the source register 2's index or the memory access address); rs2OrMemVal (used to record the value of source register 2 or the value read from the memory access address); rs2OrMemTsp (used to record the old timestamp corresponding to source register 2 or the memory access address); rdOrMemIndex (used to record the destination register's index or the address written to memory); rdOrMemReadValue (used to record the old value of the destination register or the old value of the memory address); rdOrMemWriteValue (used to record the destination register's write-back value or the value written to memory); and rdOrMemTsp (used to record the old timestamp corresponding to the destination register or the memory address). When the instruction execution evidence structure is an operation log, its log fields are structurally and functionally similar to the trace fields, all used to record relevant information generated during instruction execution; these will not be repeated here.

[0174] The constructed trajectory record or operation log may include complete fields and complete field values, or it may include complete fields but not complete field values. For example, multiple trajectory fields or log fields in the constructed trajectory record or operation log may include fully filled trajectory fields or log fields and / or unfilled trajectory fields or log fields. When the instruction reaches the write-back stage, the constructed trajectory record or operation log may be in its initial form. In this trajectory record or operation log, the corresponding values ​​of multiple trajectory fields or log fields are all filled, partially filled, or none of them are filled.

[0175] In one implementation, the instructions in the user program are executed instruction by instruction. For example, the user program includes instructions A, B and C. The trajectory processing circuit 110 executes instructions A, B and C in sequence and constructs trajectory records or operation logs corresponding to instructions A, B and C respectively.

[0176] S92: Send the trajectory record or operation log to the synchronous decoupled trajectory queue, and fill the incomplete trajectory field or log field in the synchronous decoupled trajectory queue with data. If there is no incomplete trajectory field or log field in the trajectory record or operation log, output the trajectory record or operation log to generate the proof trajectory record.

[0177] The synchronous decoupled trajectory queue can be a circuit used to receive trajectory records or operation logs that are awaiting retirement instructions, wherein the retirement instruction is completed when it is received by the synchronous decoupled trajectory queue.

[0178] In one implementation, the synchronous decoupling trajectory queue includes storage space for accommodating trajectory records or operation logs. For example, the synchronous decoupling trajectory queue receives trajectory records or operation logs corresponding to a retirement instruction, and the retirement instruction completes its retirement upon receiving the trajectory record or operation log. The trajectory record or operation log is output by the synchronous decoupling trajectory queue as a proof trajectory record, which can be used for zero-knowledge proofs, or for proofs in other cryptographic or secure computing domains.

[0179] As mentioned above, the constructed trajectory record or operation log may include incomplete trajectory fields or log fields. For example, since ordinary operation instructions, loading instructions or storage instructions require different data sources when generating trajectory records or operation logs, and there may be multi-cycle delays in reading and writing memory values ​​and timestamp values, there may be delays in filling the corresponding field values ​​in the trajectory record or operation log. That is, the constructed trajectory record or operation log may include complete fields but not complete field values.

[0180] Furthermore, the synchronous decoupled trajectory queue can receive trajectory records or operation logs that include complete fields but not complete field values, and can continue to fill in the field values ​​corresponding to incomplete trajectory fields or log fields, and output them after filling to generate proof trajectory records.

[0181] Taking the constructed trajectory record as an example, which does not include the field values ​​corresponding to the memory write value, timestamp read value, and timestamp write value, after receiving the trajectory record, the synchronous decoupled trajectory queue can continue to process the memory write value, timestamp read value, and timestamp write value required by the trajectory record, and continue to send them to the synchronous decoupled trajectory queue. The synchronous decoupled trajectory queue will fill the memory write value, timestamp read value, and timestamp write value into the corresponding incomplete fields.

[0182] The asynchronously returned memory write values, timestamp read values, and timestamp write values ​​can be filled according to preset filling rules. For example, they can be filled by finding the corresponding trajectory record based on the preset identifier fields (pc and / or inst), by filling according to the field name of the incomplete field, or by blocking filling. The preset filling rules can be changed according to actual design requirements.

[0183] In one implementation, when the synchronous decoupled trajectory queue does not contain an incomplete trajectory field or log field in the trajectory record or operation log, it outputs the trajectory record or operation log to generate a proof trajectory record. For example, if the trajectory record received by the synchronous decoupled trajectory queue does not contain an incomplete field, the trajectory record can be output as a proof trajectory record; or, if the trajectory record received by the synchronous decoupled trajectory queue contains an incomplete field, it receives the asynchronously returned field value and fills it into the corresponding field. When the trajectory record does not contain an incomplete trajectory field, the trajectory record can be output as a proof trajectory record.

[0184] In one example, when a trajectory record in the synchronous decoupling trajectory queue meets the following conditions: valid, no exception has occurred or the exception trajectory record or operation log ends according to the exception handling rules, and it is a non-memory access instruction, there is no need to wait for the return of the field value related to the memory access, and the trajectory record can be output as a proof trajectory record.

[0185] In another example, when a trajectory record in the synchronous decoupled trajectory queue meets the following conditions: valid, no exception occurred, or the exception trajectory record or operation log ended according to the exception handling rules, and it is a memory access instruction, it is necessary to wait for the return of the field values ​​related to the memory access. After the values ​​are returned and filled, the trajectory record can be output as a proof trajectory record. For example, a dDone field can be constructed to record whether the memory data return is complete; a tReadDone field can be constructed to record the completion of the memory timestamp read operation; and a tWriteDone field can be constructed to record the completion of the memory timestamp write operation. When the above three constructed fields are valid, it indicates that the corresponding values ​​have been asynchronously returned / filled, and the trajectory record can be output as a proof trajectory record.

[0186] In the above scheme, instruction execution and proof trajectory record generation are decoupled into two collaborative stages. A proof trajectory record or a prototype proof trajectory record containing multiple fields is constructed to ensure that the execution information of each instruction is fully captured. The synchronously decoupled trajectory queue receives the proof trajectory record or the prototype proof trajectory record and asynchronously fills in any incomplete fields. This avoids blocking during instruction execution and ensures that the final output proof trajectory record has complete fields and field values, and that the order strictly follows the instruction execution order. At the same time, the instruction retirement condition is bound to the synchronously decoupled trajectory queue's successful reception of the trajectory record or operation log. This makes the instruction's update to the architecture state and the entry of the trajectory record or operation log into the synchronously decoupled trajectory queue an atomic event, eliminating the semantic inconsistency problem of submission. This achieves high-performance execution of user programs while providing complete, ordered, and semantically consistent execution witness data for subsequent proofs.

[0187] In some embodiments, constructing a trajectory record corresponding to a retirement instruction includes: constructing a trajectory record or operation log corresponding to the type of the retirement instruction based on the type of the retirement instruction.

[0188] In one implementation, a trajectory record corresponding to the type of retirement instruction is constructed. For example, multiplexed fields are differentiated according to the instruction type to form a valid set of fields that matches the instruction type.

[0189] Taking the trajectory field in the above embodiment as an example, for ordinary operation instructions, the trajectory processing circuit 110 fills in: valid, zk_clk or base_timestamp, pc, inst, and rs1Index, rs1Val and rs1Tsp (the number, value and old timestamp of source register 1), and rs2OrMemIndex, rs2OrMemVal, rs2OrMemTsp (the number, value and old timestamp of source register 2), and rdOrMemIndex, rdOrMemReadValue, rdOrMemWriteValue, rdOrMemTsp (the number, old value, write-back value and old timestamp of the destination register).

[0190] Taking the trajectory field in the above embodiment as an example, for the load instruction, the trajectory processing circuit 110 fills in: valid, zk_clk or base_timestamp, pc, inst, and rs1Index, rs1Val and rs1Tsp (base address register number, value and old timestamp), and rs2OrMemIndex, rs2OrMemVal, rs2OrMemTsp (memory access address, memory read value and old timestamp), and rdOrMemIndex, rdOrMemReadValue, rdOrMemWriteValue, rdOrMemTsp (destination register number, old value, write-back value and old timestamp).

[0191] Taking the trajectory field in the above embodiment as an example, for the storage instruction, the trajectory processing circuit 110 fills in: valid, zk_clk or base_timestamp, pc, inst, and rs1Index, rs1Val and rs1Tsp (the number, value and old timestamp of the base address register), and rs2OrMemIndex, rs2OrMemVal, rs2OrMemTsp (the number, value and old timestamp of the source register 2), and rdOrMemIndex, rdOrMemReadValue, rdOrMemWriteValue, rdOrMemTsp (the address, old value, written value and old timestamp of the memory to be written).

[0192] In one implementation, a trajectory record corresponding to the type of retirement instruction is constructed. For example, a corresponding trajectory field is generated based on the instruction type and filled accordingly to form a valid field that matches the instruction type.

[0193] Taking the trajectory field in the above embodiment as an example, for the loading instruction, the field names are not reused. Instead, rs2OrMemIndex, rs2OrMemVal, and rs2OrMemTsp are replaced with memAddr, memReadVal, and memTsp. In this example, only the field names are changed, and the actual meaning represented by the fields is not changed.

[0194] Taking the trajectory field in the above embodiment as an example, for the storage instruction, the field name is not reused. Instead, rdOrMemIndex, rdOrMemReadValue, rdOrMemWriteValue, and rdOrMemTsp are replaced with memAddr, memOldVal, memNewVal, and memTsp. In this example, only the field name is changed, and the actual meaning represented by the field is not changed.

[0195] It should be noted that, depending on the command type, a number of fields corresponding to the command type can be generated. That is, the number of trajectory fields or log fields included in the trajectory record or operation log can vary for different commands. A first number of fields can also be preset. If a command requires a second number of fields, and the second number is less than the first number, the fields not needed by the command can be marked as invalid, and the trajectory record will be output normally after the required fields for the command are filled. Examples will not be provided here.

[0196] In the above scheme, corresponding trajectory records or operation logs are generated according to the type of retirement instruction, providing clear structured data, ensuring the completeness and correctness of the trajectory records in the final proof, and reserving sufficient compatibility space for future instruction set expansion.

[0197] In some embodiments, constructing the trajectory record or operation log corresponding to the type of the retirement instruction includes: providing the synchronous decoupled trajectory queue with the data required for the incomplete trajectory field or log field in the trajectory record or operation log, based on the trajectory record or operation log.

[0198] In one implementation, when populating trajectory records or operation logs, trajectory records or operation logs including complete fields but not complete field values ​​can be sent to a synchronous decoupled trajectory queue, and the field values ​​corresponding to incomplete trajectory fields or operation fields can be continuously sent to the synchronous decoupled trajectory queue. For example, for a load instruction, the read value of memory access and the old timestamp can be sent asynchronously to the synchronous decoupled trajectory queue. As another example, for a store instruction, the old value of memory access, the write value, and the old timestamp can be sent asynchronously to the synchronous decoupled trajectory queue.

[0199] In the above scheme, the held instruction context is used to ensure accurate matching between asynchronous data and trajectory records or operation logs. While ensuring the integrity and correctness of the trajectory records, the scheme optimizes the division of responsibilities and timing convergence between modules.

[0200] In some embodiments, before sending the trajectory record or operation log to the synchronous decoupled trajectory queue, the method includes: sending the trajectory record or operation log to the synchronous decoupled trajectory queue when the retirement instruction meets the preset retirement conditions.

[0201] In one implementation, instructions are executed in strict sequence according to the program. For example, instruction execution includes five stages: fetch, decode, execute, memory access, and write back. Instructions in the program are executed sequentially in these five stages. When an instruction reaches the write back stage, a trajectory record or operation log corresponding to that instruction is constructed. The construction order of the trajectory record or operation log is consistent with the instruction execution order.

[0202] In one implementation, a trajectory record or operation log is sent to the synchronous decoupled trajectory queue when the instruction to be retired meets preset retirement conditions. For example, the trajectory record or operation log corresponding to the instruction to be retired and / or the trajectory record or operation log corresponding to the instruction to be retired meets preset retirement conditions. In one example, the instruction to be retired meeting the preset retirement conditions may mean that the instruction to be retired meets the retirement semantics of a standard RISC-V five-stage pipeline, and the trajectory record or operation log corresponding to the instruction to be retired meeting the preset retirement conditions may mean that fields in the trajectory record or operation log meet preset requirements, for example, the pc is located in a pre-configured user program address space.

[0203] In the above scheme, when the retirement instruction meets the preset retirement conditions, a trajectory record or operation log is sent to the synchronous decoupled trajectory queue. This ensures that the trajectory record or operation log originates from a real and valid instruction execution and has a complete initial structure, thus providing a reliable and compliant input basis for the subsequent asynchronous backfilling and proof trajectory record generation of the synchronous decoupled trajectory queue. At the same time, this mechanism can automatically filter out invalid instructions such as replays and exceptions, avoiding the generation of useless trajectory records, saving storage and bandwidth resources of the synchronous decoupled trajectory queue, and ensuring that the final output proof trajectory record strictly corresponds to the real and valid instruction execution history in the user program.

[0204] In some embodiments, the preset retirement conditions include a first preset condition and a second preset condition; the step of sending the trajectory record or operation log to the synchronous decoupled trajectory queue when the retirement instruction meets the preset retirement conditions includes: when the retirement instruction meets both the first and second preset conditions, sending the trajectory record or operation log to the synchronous decoupled trajectory queue, wherein the first preset condition is used to determine whether the retirement instruction has been successfully executed and has not triggered an exception, and the second preset condition is used to determine whether the address of the retirement instruction is located in the proof area.

[0205] The first preset condition can be the continuation of the retirement semantics of the standard RISC-V five-stage pipeline, that is, whether the instruction to be retired is valid, whether a return has occurred, and whether an exception has occurred. If all of these conditions are met, then the instruction to be retired satisfies the first preset condition.

[0206] In one implementation, it is possible to simultaneously determine whether the retirement instruction meets the first preset condition and the second preset condition, or the second preset condition can be used as a further determination of the first preset condition.

[0207] In one implementation, the second preset condition is used to determine whether the address of the instruction to be retired is located in the proof region. That is, proof is only required for the trajectory record or operation log corresponding to the instruction to be retired if the address of the instruction to be retired is located in the proof region. The proof region can be a pre-configured user program address space. For example, it can be determined whether the PC of the instruction to be retired is located in the pre-configured user program address space. If the PC is located in the pre-configured user program address space, the trajectory record or operation log is sent to the synchronous decoupled trajectory queue. In one example, the proof region is [userMemBase, userMemBase + userMemSize), which can be configured by the HOST (host side / host machine), where userMemBase is the starting address and userMemSize is the address size. In addition, if the instruction to be retired does not meet the second preset condition, for example, if the PC is located in the Boot ROM, MMIO, boot code, or other non-proof regions, the instruction to be retired can be retired according to the semantics of a normal processor, without sending the trajectory record or operation log to the synchronous decoupled trajectory queue, and without generating a proof trajectory record.

[0208] The above scheme is compatible with the retirement semantics of the standard RISC-V pipeline and precisely defines the generation range of the proof trajectory record, so that only instructions within the proof area enter the generation path of the proof trajectory record. This avoids generating useless trajectory records or operation logs for instructions that do not require proof, and saves storage and bandwidth resources of the synchronous decoupled trajectory queue.

[0209] In some embodiments, after sending the trajectory record or operation log to the synchronous decoupled trajectory queue when the retirement instruction meets preset retirement conditions, the method includes: providing memory data to the synchronous decoupled trajectory queue to fill the corresponding incomplete trajectory field or log field in the trajectory record or operation log through the synchronous decoupled trajectory queue; and providing a memory timestamp to the synchronous decoupled trajectory queue to fill the corresponding incomplete trajectory field or log field in the trajectory record or operation log through the synchronous decoupled trajectory queue.

[0210] In one implementation, the processor includes a memory data cache circuit for providing memory data to a synchronous decoupling trajectory queue. For example, when processing a load instruction, the processor provides the memory read value corresponding to the memory access address to the synchronous decoupling trajectory queue. As another example, when processing a store instruction, the processor provides the old value corresponding to the memory write address to the synchronous decoupling trajectory queue.

[0211] In one implementation, the memory data cache circuit is also used to update the old value corresponding to the memory write address when processing instructions. For example, when the instruction type being processed is a store instruction, a new value is written to the memory write address.

[0212] In one implementation, the processor further includes a memory timestamp cache circuit for providing memory timestamps to the synchronization decoupling trajectory queue. For example, when the instruction being processed is a load instruction, the old timestamp corresponding to the memory access address is provided to the synchronization decoupling trajectory queue. As another example, when the instruction being processed is a store instruction, the old timestamp corresponding to the memory write address is provided to the synchronization decoupling trajectory queue.

[0213] In one implementation, the memory timestamp caching circuit is also used to update the old timestamp corresponding to the memory write address when processing instructions. For example, when the instruction type being processed is a store instruction, the new timestamp is written to the corresponding memory address, wherein the new timestamp represents the timestamp corresponding to the memory write event (storing the write value to the memory write address).

[0214] In the above scheme, memory data and memory timestamp data are provided during instruction execution to maintain memory-related data while executing user programs, providing clear and provable data for backend memory consistency proof.

[0215] In some embodiments, sending the trajectory record or operation log to the synchronous decoupled trajectory circuit when the retirement instruction meets the preset retirement conditions includes: providing register service data to the synchronous decoupled trajectory queue to fill the corresponding incomplete trajectory field or log field in the trajectory record or operation log through the synchronous decoupled trajectory queue; and providing a register timestamp to the synchronous decoupled trajectory queue to fill the corresponding incomplete trajectory field or log field in the trajectory record or operation log through the synchronous decoupled trajectory queue.

[0216] In one implementation, the processor includes general-purpose register circuitry for providing register service data to a synchronous decoupling trace queue. For example, when processing a normal arithmetic instruction, the processor provides the value of source register 1, the value of source register 2, and the old value of the destination register to the synchronous decoupling trace queue. Similarly, when processing a load instruction, the processor provides the value of source register 1 and the old value of the destination register to the synchronous decoupling trace queue. And again, when processing a store instruction, the processor provides the values ​​of source register 1 and source register 2 to the synchronous decoupling trace queue.

[0217] In one implementation, the general-purpose register circuit is also used to receive the write-back value of the destination register, for example, when the instruction type being processed is a normal arithmetic instruction. Another example is when the instruction type being processed is a load instruction.

[0218] In one implementation, the processor further includes a register timestamp circuit for providing register timestamps to the synchronization decoupling trajectory queue. For example, when processing a normal arithmetic instruction, the old timestamps of source register 1, source register 2, and destination register are provided to the synchronization decoupling trajectory queue. As another example, when processing a load instruction, the old timestamps of source register 1 and destination register are provided to the synchronization decoupling trajectory queue. As yet another example, when processing a store instruction, the old timestamps of source register 1 and source register 2 are provided to the synchronization decoupling trajectory queue.

[0219] In one implementation, the register timestamp circuit 112 is also used to receive a new timestamp of the destination register. For example, when the instruction type being processed is a load instruction or a normal arithmetic instruction, the new timestamp of the destination register is received. The new timestamp of the destination register represents the timestamp corresponding to the register write-back event (storing a new value in the destination register).

[0220] The above scheme provides register business data and register timestamp data to maintain register-related data while executing user programs, avoiding the need to supplement the fields required for proof through additional microinstructions, software scanning, or multi-cycle register reads, and providing clear and provable data for backend register consistency proof.

[0221] In some embodiments, when the type of the retirement instruction is a precompiled call instruction, a first trajectory record and a second trajectory record corresponding to the retirement instruction are constructed through a first trajectory construction path and a second trajectory construction path, respectively. After the first trajectory record and the second trajectory record are encapsulated into the trajectory record, they are sent to the synchronous decoupled trajectory queue.

[0222] The first trajectory construction path can be a path for processing a first instruction type, such as ordinary arithmetic instructions, load instructions, and store instructions. The second trajectory construction path can be a path for processing a second instruction type, such as a pre-compiled arithmetic call instruction.

[0223] In one implementation, the processor is integrated into a system-on-a-chip (SoC). The processor includes a trajectory processing circuit, and the SoC includes a pre-compilation operation circuit. The trajectory processing circuit can serve as a first trajectory construction path, and the pre-compilation operation circuit can serve as a second trajectory construction path. The pre-compilation operation circuit can be an integrated circuit for processing pre-compilation operations; for example, it can be a coprocessor. Specifically, the coprocessor is scheduled by the processor and executes instructions from the processor. In one example, the pre-compilation operation circuit performs pre-compilation operations, including but not limited to hash operations, large integer operations, elliptic curve operations, finite field operations, and signature verification. In another example, the pre-compilation call instruction can be a pre-defined instruction in the user program, such as a custom RoCC instruction.

[0224] In one implementation, the trajectory processing circuit identifies the retirement instruction to be retired and, if the type of the retirement instruction is a precompiled call instruction, sends the precompiled call instruction to the precompiled operation circuit. In one example, the precompiled call instruction may include preset field information, such as a precompiled operation type field, used to identify the specific precompiled operation type (e.g., hash operation), the value of source register 1, the value of source register 2, and the old value of the destination register, etc.

[0225] In one implementation, if memory-related operations are involved, the pre-compilation operation circuit can obtain relevant memory data or memory timestamps, for example, by obtaining the corresponding memory data or memory timestamps from the memory data cache circuit and the memory timestamp cache circuit.

[0226] In one implementation, the first trajectory construction path and the second trajectory construction path collaboratively construct trajectory records or operation logs corresponding to the instruction to be retired. For example, when the type of the instruction to be retired is a precompiled call instruction, the first trajectory construction path constructs a portion of the trajectory records or operation logs for the instruction to be retired, and the second trajectory construction path constructs another portion of the trajectory records or operation logs for the instruction to be retired. Further, the second trajectory construction path can return the constructed trajectory records or operation logs to the first trajectory construction path, and the first trajectory construction path sends them to the synchronous decoupling trajectory circuit 120. In one example, the fields constructed by the first trajectory construction path may include valid, zk_clk or base_timestamp, pc, inst, rs1Index, rs1Val, rs1Tsp, rs2OrMemIndex, rs2OrMemVal, rs2OrMemTsp, rdOrMemIndex, rdOrMemReadValue, and rdOrMemTsp, and the fields constructed by the second trajectory construction path may include rdOrMemWriteValue.

[0227] It should be noted that the fields related to the precompile call instruction are not limited to the examples above. In another example, the precompile call instruction may also include: precompile_id, which identifies the type of precompile operation; input_digest and output_digest, which can be used to compress large inputs and large outputs, and can be selected to record complete data, summary data or address range pointing to a memory table according to the constraint format of the back-end proof circuit; and status, which is used to indicate the operation success, invalid input, exception or rollback status, etc.

[0228] In the above scheme, a second trajectory construction path is introduced and used to process pre-compiled call instructions in user programs, which greatly improves the execution efficiency of such heavy-load operations. Furthermore, the second trajectory construction path and the first trajectory construction path work together to construct the trajectory record or operation log of the instruction to be retired, realizing the generation mechanism of the reuse of trajectory record or operation log, ensuring the integrity and correctness of the fields in the trajectory record or operation log, thereby providing reliable and complete witness data for subsequent proof.

[0229] In some embodiments, when the synchronous decoupled trajectory queue is unable to output the trajectory record or operation log, and / or is unable to receive the trajectory record or operation log, a signal indicating to suspend sending the trajectory record or operation log is sent.

[0230] In one implementation, the synchronous decoupling trajectory queue sends a signal indicating a pause in the transmission of trajectory records. For example, the synchronous decoupling trajectory queue sends a signal to the trajectory processing circuit to instruct the trajectory processing circuit to pause the transmission of trajectory records or operation logs to the synchronous decoupling trajectory queue. In one example, if the consumer end of the synchronous decoupling trajectory queue can no longer consume trajectory records or operation logs in the synchronous decoupling queue, then the synchronous decoupling trajectory queue sends a signal indicating a pause in the transmission of the trajectory records or operation logs. In another example, if the synchronous decoupling trajectory queue can no longer store the trajectory records or operation logs corresponding to the next instruction, the synchronous decoupling trajectory queue sends a signal indicating a pause in the transmission of the trajectory records or operation logs.

[0231] In one implementation, the trajectory processing circuit self-triggers a signal indicating a pause in sending trajectory records or operation logs under preset conditions. For example, the preset conditions include, but are not limited to, at least one of the following: for a load instruction, the old value corresponding to the memory access address was not read; for a store instruction, the old value corresponding to the memory write address was not read.

[0232] In the above scheme, the transmission of trajectory records or operation logs is paused when fields in the trajectory records or operation logs are incomplete or when the synchronous decoupled trajectory queue cannot receive them. This ensures the integrity of the trajectory records or operation logs on one hand, and dynamically adjusts the transmission rhythm of trajectory records or operation logs based on the pause signal from the synchronous decoupled trajectory queue on the other. This guarantees that instructions are not erroneously advanced and the architecture state is not illegally updated during backpressure, providing a safe timing boundary for the construction and asynchronous backfilling of trajectory records or operation logs.

[0233] In some embodiments, the synchronous decoupling trajectory queue includes a trajectory queue for storing a preset number of trajectory records or operation logs.

[0234] Taking the synchronous decoupling trajectory queue, which includes trajectory queue A1, trajectory queue A2, ..., trajectory queue An, as an example, trajectory queue A1, trajectory queue A2, ..., trajectory queue An are used to store trajectory records or operation logs corresponding to different instructions. For example, trajectory queue A1 stores trajectory record or operation log B1, trajectory queue A2 stores trajectory record or operation log B2, ..., trajectory queue A3 stores trajectory record or operation log B3. The trajectory record or operation log B1, trajectory record or operation log B2, and trajectory record or operation log B3 are all different.

[0235] In the above scheme, a preset number of independent storage areas are set in the synchronous decoupled trajectory queue, enabling the synchronous decoupled trajectory queue to simultaneously cache trajectory records or operation logs of multiple different instructions, providing multi-depth buffering for asynchronous backfilling. This design supports parallel data backfilling of multiple trajectory records, improving backfilling efficiency. At the same time, the elastic buffer formed can absorb the sudden sending pressure from the front end, reduce the back pressure frequency on the instruction pipeline, and ensure the isolation and integrity of each instruction trajectory data.

[0236] In some embodiments, filling the incomplete trajectory field or log field among the plurality of trajectory fields or log fields in the synchronous decoupled trajectory queue with data further includes: filling the incomplete trajectory field or log field in the trajectory record or operation log in the synchronous decoupled trajectory queue with data in sequence according to the receiving order of the trajectory record or operation log.

[0237] In one implementation, the synchronous decoupled trajectory queue employs a blocking data filling method. Continuing with the example of trajectory queues A1, A2, ..., An, and trajectory records or operation logs B1, B2, and B3 being received sequentially by the synchronous decoupled trajectory queue, if trajectory record or operation log B1 contains incomplete trajectory fields or log fields, then these incomplete trajectory fields or log fields in trajectory record or operation log B1 are filled. In response to the absence of incomplete trajectory fields or log fields in trajectory record or operation log B1, it is determined whether trajectory record or operation log B2 contains incomplete trajectory fields or log fields. If so, these incomplete trajectory fields or log fields in trajectory record or operation log B2 are filled. This process is repeated to fill in the incomplete trajectory fields or log fields in the trajectory records or operation logs sequentially according to the receiving order.

[0238] In one implementation, the synchronous decoupling trajectory queue is filled with preset identifiers. These preset identifiers include, but are not limited to, pc, inst, and zk_clk. Taking zk_clk as an example, zk_clk increments when the retirement instruction is completed; that is, it increments when a trajectory record or operation log is received by the synchronous decoupling trajectory queue. Each trajectory record or operation log entering the synchronous decoupling trajectory queue includes a unique zk_clk field that monotonically increments according to the order of entry. For field values ​​asynchronously returned to the synchronous decoupling trajectory queue, the corresponding trajectory record or operation log can be found based on zk_clk, and the corresponding field can be filled.

[0239] In the above scheme, the synchronously decoupled trajectory queue can asynchronously backfill in incomplete trajectory fields or operation logs in an orderly and correct manner according to the received order of trajectory records or operation logs. This ensures that the fields of the final output trajectory records or operation logs are complete and in the correct order, providing reliable witness data for subsequent proof.

[0240] In some embodiments, the synchronous decoupled trajectory queue outputs the trajectory records or operation logs, including: sequentially outputting the trajectory records or operation logs in the synchronous decoupled trajectory queue according to the receiving order of the trajectory records or operation logs.

[0241] In one implementation, the synchronous decoupled trajectory queue adopts a blocking data filling method, which strictly follows the receiving order to fill in the unfinished fields of the trajectory records or operation logs B1 to Bn in the trajectory queue A1 to An one by one. Only after all the unfinished fields of the previous trajectory record are filled is it output and the filling of the next record continues, thereby realizing the sequential output according to the receiving order.

[0242] In one implementation, the synchronous decoupling trajectory queue uses a preset identifier for filling. Each trajectory record or operation log entering the synchronous decoupling trajectory queue includes a unique zk_clk field that monotonically increases in the order of entry. The synchronous decoupling trajectory queue fills the corresponding field of the corresponding trajectory record with asynchronously returned data according to zk_clk. In response to all incomplete fields of any trajectory record or operation log being filled, the synchronous decoupling trajectory queue outputs the trajectory records or operation logs sequentially in monotonically increasing order of zk_clk.

[0243] In the above scheme, the synchronous decoupled trajectory queue outputs trajectory records in the order of receipt, ensuring that the output trajectory records or operation logs strictly follow the order of instruction execution, which meets the strict requirements of subsequent proof on trajectory order, so that the backend proof does not need to reorder the trajectory, reducing the complexity of data processing, and taking into account both the efficiency of internal asynchronous backfilling and the timing correctness of external data consumption.

[0244] Please see Figure 10 and Figure 11 , Figure 10 This is a schematic diagram of the structure of a system-on-a-chip according to some embodiments of this application. Figure 2 , Figure 11 This is a schematic diagram of the structure of a system-on-a-chip according to some embodiments of this application. Figure 3 .like Figure 10 As shown, the system-on-chip 1000 includes a processor 1010, wherein the processor 1010 may be the processor 100 in the above embodiments. Figure 11 As shown, the system-on-chip 1100 includes a connected processor 1110 and a pre-compiled computing circuit 1120, wherein the processor 1110 may be the processor 100 in the above embodiment, and the pre-compiled computing circuit 1120 may be the pre-compiled computing circuit 200 in the above embodiment.

[0245] In the above scheme, instruction execution and proof trajectory record generation are decoupled into two collaborative stages. A proof trajectory record or a prototype proof trajectory record containing multiple fields is constructed, ensuring that the execution information of each instruction is fully captured. Simultaneously, by asynchronously backfilling incomplete fields, blocking during instruction execution is avoided, and the final output proof trajectory record is guaranteed to have complete fields and values, with the order strictly adhering to the instruction execution order. This eliminates the semantic inconsistency problem caused by the disconnect between hardware state updates and trajectory records or operation logs, enabling high-performance execution of user programs while providing complete, ordered, and semantically consistent execution witness data for subsequent proofs.

[0246] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0247] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0248] In the several embodiments provided in this application, it should be understood that the disclosed methods and apparatus can be implemented in other ways. For example, the apparatus implementations described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0249] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0250] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A processor, characterized in that, include: A trajectory processing circuit is used to construct a trajectory record or operation log corresponding to the retirement instruction, wherein the trajectory record or operation log includes multiple trajectory fields or log fields. A synchronous decoupled trajectory circuit, connected to the trajectory processing circuit, is used to fill in the incomplete trajectory field or log field among the multiple trajectory fields or log fields with data after receiving the trajectory record or operation log sent by the trajectory processing circuit. When the incomplete trajectory field or log field does not exist in the trajectory record or operation log, the trajectory record or operation log is output to generate a proof trajectory record. The retirement instruction is executed when the synchronous decoupling trajectory circuit receives the trajectory record or operation log.

2. The processor according to claim 1, characterized in that, The trajectory processing circuit is also used to construct a trajectory record or operation log corresponding to the type of the retirement instruction, based on the type of the retirement instruction.

3. The processor according to claim 2, characterized in that, The trajectory processing circuit is also used to provide the synchronous decoupled trajectory circuit with the data required for the incomplete trajectory field or log field in the trajectory record or operation log, based on the trajectory record or operation log.

4. The processor according to claim 1, characterized in that, The trajectory processing circuit includes: The processor core includes an instruction pipeline circuit connected to the synchronous decoupled trajectory circuit. The instruction pipeline circuit is used to construct the trajectory record or operation log and send the trajectory record or operation log to the synchronous decoupled trajectory circuit when the retirement instruction meets the preset retirement conditions.

5. The processor according to claim 4, characterized in that, The preset retirement conditions include a first preset condition and a second preset condition; The trajectory processing circuit is further configured to send the trajectory record or operation log to the synchronous decoupled trajectory circuit when the retirement instruction satisfies both the first and second preset conditions. The first preset condition is used to determine whether the retirement instruction has been successfully executed without triggering an exception, and the second preset condition is used to determine whether the address of the retirement instruction is located in the proof area.

6. The processor according to claim 4, characterized in that, The processor core includes: A memory data cache circuit, connected to the instruction pipeline circuit, is used to provide memory data to the synchronous decoupling trajectory circuit so that the memory data is filled into the corresponding incomplete trajectory field or log field in the trajectory record or operation log by the synchronous decoupling trajectory circuit. A memory timestamp cache circuit, connected to the instruction pipeline circuit, is used to provide a memory timestamp to the synchronous decoupled trajectory circuit so that the synchronous decoupled trajectory circuit can fill the memory timestamp into the corresponding incomplete trajectory field or log field in the trajectory record or operation log.

7. The processor according to claim 4, characterized in that, The processor core includes: A general-purpose register circuit, connected to the instruction pipeline circuit, is used to provide register service data to the synchronous decoupling trajectory circuit, so that the synchronous decoupling trajectory circuit can fill the register service data into the corresponding incomplete trajectory field or log field in the trajectory record or operation log. The trajectory processing circuit further includes: A register timestamp circuit, connected between the instruction pipeline circuit and the synchronous decoupling trajectory circuit, is used to provide a register timestamp to the synchronous decoupling trajectory circuit so that the synchronous decoupling trajectory circuit can fill the register timestamp into the corresponding incomplete trajectory field in the trajectory record.

8. The processor according to claim 4, characterized in that, The processor is located in a system-on-a-chip, and the system-on-a-chip includes a pre-compiled computation circuit, which is connected between the instruction pipeline circuit and the synchronous decoupling trajectory circuit. The instruction pipeline circuit is also used to, in conjunction with the pre-compilation operation circuit, construct the trajectory record or operation log corresponding to the instruction to be retired when the type of the instruction to be retired is a pre-compiled call instruction.

9. The processor according to claim 1, characterized in that, The trajectory processing circuit is also configured to stop sending the trajectory record or operation log to the synchronous decoupled trajectory circuit when it receives a signal indicating to pause sending the trajectory record or operation log.

10. The processor according to claim 1, characterized in that, The synchronous decoupling trajectory circuit is also used to send a signal to the trajectory processing circuit to suspend sending the trajectory record or operation log when the synchronous decoupling trajectory circuit is unable to output the trajectory record or operation log and / or is unable to receive the trajectory record or operation log.

11. The processor according to claim 1, characterized in that, The synchronous decoupling trajectory circuit includes a storage area for storing a preset number of trajectory records or operation logs.

12. The processor according to claim 11, characterized in that, The synchronous decoupling trajectory circuit is also used to fill in the incomplete trajectory field or log field in the trajectory record or operation log in the synchronous decoupling trajectory circuit in the order of receiving the trajectory record or operation log.

13. The processor according to claim 11, characterized in that, The synchronous decoupling trajectory circuit is also used to output the trajectory records or operation logs in the synchronous decoupling trajectory circuit in sequence according to the receiving order of the trajectory records.

14. A zero-knowledge proof system, characterized in that, include: A host computer is used to provide programs, input parameters, and configuration data, wherein the program includes at least one instruction; The system-on-a-chip includes a processor as described in any one of claims 1-13, configured to acquire the program, the input parameters, and the configuration data, and generate a proof trajectory record corresponding to the at least one instruction; The proof circuit is used to acquire the proof trajectory record and, after generating proof data corresponding to the proof trajectory record, return the proof data to the host.

15. The zero-knowledge proof system according to claim 14, characterized in that, The host is also used to write the program, the input parameters and the configuration data into shared memory, and to perform a cache refresh operation after the writing is completed.

16. The zero-knowledge proof system according to claim 15, characterized in that, The host computer is also used to send a trajectory generation start signal to the on-chip system; The on-chip system is also used to, upon receiving the trajectory generation start signal, acquire the program, the input parameters, and the configuration data, and generate the proof trajectory record corresponding to the at least one instruction.

17. The zero-knowledge proof system according to claim 14, characterized in that, The on-chip system is also used to send a trajectory generation end signal to the host after generating the proof trajectory record corresponding to the at least one instruction, so as to start the proof circuit through the host.

18. The zero-knowledge proof system according to claim 17, characterized in that, The host is also configured to perform a memory barrier operation after receiving the trajectory generation end signal, and send a proof start signal to the proof circuit after performing the memory barrier operation to start the proof circuit.

19. The zero-knowledge proof system according to claim 18, characterized in that, The proof circuit is also used to write the proof data corresponding to the proof trajectory record into shared memory after generating the proof data, and send a proof completion signal to the host.

20. A method for proving trajectory generation, characterized in that, include: Construct a trajectory record or operation log corresponding to the retirement instruction, wherein the trajectory record or operation log includes multiple trajectory fields or log fields; The trajectory record or operation log is sent to the synchronous decoupled trajectory queue, and the incomplete trajectory field or log field among the multiple trajectory fields or log fields is filled with data in the synchronous decoupled trajectory queue. When the incomplete trajectory field or log field does not exist in the trajectory record or operation log, the trajectory record or operation log is output to generate a proof trajectory record. The retirement instruction is executed when the synchronous decoupled trajectory queue receives the trajectory record or operation log.

21. The method according to claim 20, characterized in that, The construction of the trajectory record corresponding to the retirement instruction includes: Based on the type of the retirement instruction, construct the trajectory record or operation log corresponding to the type of the retirement instruction.

22. The method according to claim 21, characterized in that, The step of constructing the trajectory record or operation log corresponding to the type of the retirement instruction includes: Based on the trajectory records or operation logs, provide the synchronous decoupled trajectory queue with the data required for the incomplete trajectory fields or log fields in the trajectory records or operation logs.

23. The method according to claim 20, characterized in that, Before sending the trajectory record or operation log to the synchronous decoupled trajectory queue, the following steps are included: When the retirement instruction meets the preset retirement conditions, the trajectory record or operation log is sent to the synchronous decoupled trajectory queue.

24. The method according to claim 23, characterized in that, The preset retirement conditions include a first preset condition and a second preset condition; The step of sending the trajectory record or operation log to the synchronous decoupled trajectory queue when the retirement instruction meets the preset retirement conditions includes: When the retirement instruction meets both the first and second preset conditions, the trajectory record or operation log is sent to the synchronous decoupled trajectory queue. The first preset condition is used to determine whether the retirement instruction has been successfully executed without triggering an exception, and the second preset condition is used to determine whether the address of the retirement instruction is located in the proof area.

25. The method according to claim 23, characterized in that, After sending the trajectory record or operation log to the synchronous decoupled trajectory queue when the retirement instruction meets the preset retirement conditions, the process includes: Provide memory data to the synchronous decoupled trajectory queue, so that the memory data is used to fill the corresponding incomplete trajectory field or log field in the trajectory record or operation log; and A memory timestamp is provided to the synchronous decoupled trajectory queue so that the memory timestamp is filled into the corresponding incomplete trajectory field or log field in the trajectory record or operation log through the synchronous decoupled trajectory queue.

26. The method according to claim 23, characterized in that, The step of sending the trajectory record or operation log to the synchronous decoupled trajectory queue when the retirement instruction meets the preset retirement conditions includes: Provide register service data to the synchronous decoupled trajectory queue, so that the register service data is used to fill the corresponding incomplete trajectory field or log field in the trajectory record or operation log through the synchronous decoupled trajectory queue; and A register timestamp is provided to the synchronous decoupled trajectory queue so that the register timestamp is filled into the corresponding incomplete trajectory field or log field in the trajectory record or operation log through the synchronous decoupled trajectory queue.

27. The method according to claim 23, characterized in that, Also includes: When the type of the retirement instruction is a precompiled call instruction, a first trajectory record and a second trajectory record corresponding to the retirement instruction are constructed through the first trajectory construction path and the second trajectory construction path, respectively. After the first trajectory record and the second trajectory record are encapsulated into the trajectory record, they are sent to the synchronous decoupled trajectory queue.

28. The method according to claim 20, characterized in that, include: When the synchronous decoupled trajectory queue is unable to output the trajectory record or operation log, and / or is unable to receive the trajectory record or operation log, a signal indicating to suspend sending the trajectory record or operation log is sent.

29. The method according to claim 20, characterized in that, The synchronous decoupled trajectory queue includes a trajectory queue for storing a preset number of trajectory records or operation logs.

30. The method according to claim 29, characterized in that, The synchronous decoupled trajectory queue also includes filling in the incomplete trajectory field or log field among the multiple trajectory fields or log fields with data: According to the receiving order of the trajectory records or operation logs, the incomplete trajectory fields or log fields in the trajectory records or operation logs in the synchronous decoupled trajectory queue are populated with data in sequence.

31. The method according to claim 29, characterized in that, The synchronous decoupled trajectory queue outputs the trajectory records or operation logs, including: The trajectory records or operation logs in the synchronous decoupled trajectory queue are output sequentially according to the receiving order of the trajectory records or operation logs.

32. A system-on-a-chip, characterized in that, Includes the processor as described in any one of claims 1-13, or for performing the method as described in any one of claims 20-31.

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