Instruction scheduling apparatus, computer system and instruction scheduling method

Abstract

The application provides an instruction scheduling device, a computer system and an instruction scheduling method, and belongs to the technical field of computers. The controller is additionally arranged in the instruction scheduling device, and the controller can record the number of times of being preempted by each instruction in the instruction queue. Before a certain instruction is about to be starved, once the number of times of being preempted by the instruction reaches a certain number threshold, the controller will actively increase the priority of the instruction in the arbitrator, so that the arbitrator can send out the instruction as soon as possible based on the adjusted priority of the instruction. In this process, the whole working process of the arbitrator does not need to be stopped, the time sequence overhead caused by stopping the working process of the arbitrator is avoided, and therefore the working efficiency and service efficiency of the arbitrator can be improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an instruction scheduling device, a computer system, and an instruction scheduling method. Background Technology

[0002] The hardware device responsible for instruction scheduling in a computer system is called the instruction scheduler, such as the memory controller and bus controller. The instruction scheduler includes an instruction queue and an arbitrator. The instruction queue stores instructions sent from upstream devices. The arbitrator arbitrates the instructions in the instruction queue and sends the successfully arbitrated instruction to the downstream device.

[0003] When an instruction is about to starve due to prolonged arbitration failures, the arbitrator will forcibly prioritize issuing that instruction to prevent it from starving. However, in order to forcibly prioritize issuing the instruction, the arbitrator needs to perform a series of actions, stopping its entire workflow, which incurs timing overhead and thus affects the arbitrator's efficiency. Summary of the Invention

[0004] This application provides an instruction scheduling device, a computer system, and an instruction scheduling method, which can improve the working efficiency of the arbitrator in the instruction scheduling device. The technical solution of this application is as follows: According to a first aspect of the embodiments of this application, an instruction scheduling device is provided, the instruction scheduling device including an instruction queue, an arbitrator and a controller interconnected in pairs; The instruction queue is used to store multiple input instructions; The arbitrator is used to arbitrate the instructions in the instruction queue based on the priority of the plurality of instructions; The controller is configured to increase the priority of the first instruction in the arbitrator in response to the first instruction in the instruction queue being overtaken a target number of times. The number of times the first instruction is overtaken refers to the number of times it is overtaken by an instruction whose enqueue time is later than its own during multiple arbitration processes. The enqueue time refers to the time when the instruction enters the instruction queue. The target number threshold is less than the number of times the instruction will be overtaken before it is about to starve.

[0005] The instruction scheduling device is equipped with a controller that records the number of times each instruction in the instruction queue has been overtaken. Before an instruction is starved, once the number of times the instruction has been overtaken reaches a certain threshold, the controller will actively increase the priority of the instruction in the arbitrator. This allows the arbitrator to send out the instruction as soon as possible based on the adjusted priority. During this process, it is not necessary to stop the entire workflow of the arbitrator, thus avoiding the timing overhead caused by stopping the workflow of the arbitrator and improving the working efficiency and service efficiency of the arbitrator.

[0006] Optionally, the target number threshold includes a first number threshold and a second number threshold, wherein the second number threshold is greater than the first number threshold; The controller is used for: In response to the first instruction being overtaken reaching the first threshold number of times but not reaching the second threshold number of times, the priority of the first instruction is increased by m priority levels, where m is an integer greater than 0; In response to the first instruction being overtaken a certain number of times, the priority of the first instruction is increased by n priority levels, where n is an integer greater than 0.

[0007] Optionally, the number of times the starvation command is to be triggered is a starvation threshold, and the controller is further configured to: In response to the first instruction being overtaken reaching the target number threshold but not the starvation threshold, the priority of the first instruction in the arbitrator is increased; In response to the first instruction being overtaken a certain number of times, reaching the starvation threshold, the first instruction is configured in the arbitrator to be forcibly issued, wherein the forcibly issued instruction is an instruction that is forcibly prioritized for issuance.

[0008] Optionally, the priority of the first instruction after being increased is the target priority; The controller is further configured to, if there is a second instruction in the instruction queue that has been overtaken more than 0 times and is associated with the first instruction, raise the priority of the second instruction in the arbitrator to the target priority.

[0009] Optionally, the association between the first instruction and the second instruction includes: the first instruction and the second instruction being used to access the same memory page in the memory.

[0010] Optionally, the first instruction is a read / write instruction.

[0011] Optionally, the instruction scheduling device is a memory controller or a bus controller.

[0012] According to a second aspect of the embodiments of this application, a computer system is provided, the computer system including an instruction sending device and an instruction scheduling device, the instruction scheduling device including an instruction queue, an arbitrator and a controller interconnected in pairs; The instruction sending device is used to send multiple instructions to the instruction scheduling device; The instruction queue is used to store the input instructions; The arbitrator is used to arbitrate the instructions in the instruction queue based on the priority of the plurality of instructions; The controller is configured to increase the priority of the first instruction in the arbitrator in response to the first instruction in the instruction queue being overtaken a target number of times. The number of times the first instruction is overtaken refers to the number of times it is overtaken by an instruction whose enqueue time is later than its own during multiple consecutive arbitration processes. The enqueue time refers to the time when the instruction enters the instruction queue. The target number threshold is less than the number of times the instruction will be overtaken before it is about to starve.

[0013] According to a third aspect of the embodiments of this application, an instruction scheduling method is provided, the method being applied to an instruction scheduling device, the method comprising: Multiple input instructions are stored in the instruction queue; Arbitration is performed on the instructions in the instruction queue based on the priority of the multiple instructions; In response to the first instruction in the instruction queue being overtaken a number of times greater than or equal to a target threshold, the priority of the first instruction is increased; The number of times the first instruction is overtaken refers to the number of times it is overtaken by an instruction whose enqueue time is later than its own during multiple consecutive arbitration processes. The enqueue time refers to the time when the instruction enters the instruction queue. The target number threshold is less than the number of times the instruction will be overtaken before it is about to starve.

[0014] According to a fourth aspect of the embodiments of this application, an instruction scheduling apparatus is provided. The instruction scheduling apparatus includes a processor and a memory, wherein the memory stores at least one instruction, and the processor executes the at least one instruction, causing the instruction scheduling apparatus to implement at least one step of the instruction scheduling method provided in the embodiments of this application. The at least one step includes each step of the instruction scheduling method, or includes method steps of the instruction scheduling method executed by a controller in the instruction scheduling apparatus, or includes method steps of the instruction scheduling method executed by an arbitrator and a controller in the instruction scheduling apparatus.

[0015] According to a fifth aspect of the embodiments of this application, a computer-readable storage medium is provided, which, when at least one instruction in the computer-readable storage medium is executed by a processor of an instruction scheduling device, enables the instruction scheduling device to perform at least one step of the instruction scheduling method provided in the embodiments of this application. The at least one step includes each step of the instruction scheduling method, or includes a method step of the instruction scheduling method executed by a controller in the instruction scheduling device, or includes a method step of the instruction scheduling method executed by an arbitrator and a controller in the instruction scheduling device.

[0016] According to a sixth aspect of the embodiments of this application, a computer program product is provided, including one or more instructions, which can be executed by a processor of an instruction scheduling device, causing the instruction scheduling device to implement at least one step of the instruction scheduling method provided in the embodiments of this application. Wherein, the at least one step includes each step of the instruction scheduling method, or includes a method step of the instruction scheduling method executed by a controller in the instruction scheduling device, or includes a method step of the instruction scheduling method executed by an arbitrator and a controller in the instruction scheduling device.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application, and do not constitute an undue limitation of this application.

[0019] Figure 1 This is a schematic diagram of a computer system provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of an instruction scheduling device provided in an embodiment of this application; Figure 3 This is a schematic diagram of a starvation prevention mechanism provided in an embodiment of this application; Figure 4 This is a schematic diagram illustrating the number of times an item is overtaken, provided in an embodiment of this application. Figure 5 This is a schematic diagram of the structure of a controller provided in an embodiment of this application. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0021] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0022] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application are authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the read / write requests or data involved in this application were obtained with full authorization.

[0023] In response, it is used to indicate the conditions or states on which the operation performed depends. When the conditions or states on which it depends are met, one or more operations performed can be performed in real time or with a set delay. Unless otherwise specified, there is no restriction on the order in which the multiple operations are performed.

[0024] In some embodiments, the meaning of A and / or B includes three cases: A and B, and A and B.

[0025] In a computer system, the hardware device responsible for instruction scheduling is called the instruction scheduling unit, such as a memory controller or a bus controller. The hardware that issues instructions to the instruction scheduling unit and relies on the instruction scheduling unit to schedule those instructions is called the upstream device of the instruction scheduling unit. The hardware that receives and executes the instructions scheduled by the instruction scheduling unit is called the downstream device of the instruction scheduling unit. In some embodiments, the upstream device may also be called the master device, and the downstream device may also be called the slave device. Taking a memory controller as an example, the upstream device of the memory controller is a processor or Direct Memory Access (DMA), and the downstream device of the memory controller is the memory.

[0026] The upstream device sends instructions to the instruction scheduling device. The instruction scheduling device caches the instructions from the upstream device through an instruction queue. The arbitrator in the instruction scheduling device arbitrates the instructions in the instruction queue based on the continuity of the access address of the instructions, and sends the successfully arbitrated instructions to the downstream device.

[0027] For example, to maximize bandwidth utilization, the arbitrator sorts the instructions in the instruction queue based on the continuity of their access addresses, resulting in instruction ordering. Instruction ordering includes the scheduling order of the instructions in the instruction queue. In instruction ordering, the better the continuity of the access addresses, the earlier the instructions are scheduled; conversely, the worse the continuity, the later they are scheduled. Access address continuity refers to multiple instructions having consecutive access addresses forming a contiguous block. The more instructions whose access addresses are consecutive, the better the access address continuity. For example, assuming instructions 1 to 10 have consecutive access addresses, and instructions 15 to 17 have consecutive access addresses, then the access address continuity of instructions 1 to 10 is better than that of instructions 15 to 17. Therefore, in instruction ordering, instructions 1 to 10 are placed before instructions 15 to 17.

[0028] This instruction sorting is highly efficient. Sending instructions to downstream devices according to this sorting ensures the highest service efficiency and bandwidth utilization for the arbitrator. Therefore, the arbitrator arbitrates instructions in the instruction sequence based on this sorting. For example, during each arbitration, the instruction with the highest scheduling order in the instruction sorting is selected as the successfully arbitrated instruction (i.e., the selected instruction), and the other instructions are considered unsuccessful (i.e., not selected instructions). The arbitrator sends the successfully arbitrated instructions to the downstream device, while the unsuccessful instructions remain in the instruction sequence awaiting the next arbitration. Therefore, instructions that are later in the instruction sorting order wait longer in the instruction sequence (i.e., waiting time). When a new instruction enters the instruction queue and its access address is contiguous with that of a previous instruction in the instruction sorting order, the new instruction will be pushed forward, further increasing the waiting time of instructions with lower scheduling orders. If the waiting time of any instruction exceeds a certain period of time, and the instruction remains in the instruction queue for an extended period of time without being sent downstream for execution, the instruction is considered to be starved, which is to say, an instruction starvation event is triggered.

[0029] Taking an instruction scheduler as the memory controller, downstream devices as memory, and instructions to be scheduled as memory access instructions as an example, in related technologies, to avoid instruction starvation, when an instruction in the instruction queue is about to be starved due to prolonged arbitration failure (the instruction's waiting time reaches a preset time, and continued waiting will lead to starvation), the arbitrator will forcibly prioritize issuing the instruction about to be starved. To forcibly prioritize issuing the instruction about to be starved, the arbitrator needs to perform a series of actions, stopping its entire workflow. For example, the instruction at the top of the current instruction sequence is used to access certain memory banks, which are already active. However, the access address of the instruction about to be starved needs to access other banks in memory (the access address of the instruction about to be starved is not contiguous with the access address of the instruction at the top of the sequence). Therefore, the arbitrator needs to perform a series of actions to close these already active banks. Performing this series of actions incurs timing overhead, causing a significant efficiency loss for the arbitrator, thus affecting the overall efficiency of the arbitrator. There may be multiple instructions in the instruction queue that are about to be starved. Each time an instruction about to be starved is forcibly prioritized, timing overhead is incurred. The more instructions about to be starved are forcibly prioritized, the greater the timing overhead becomes, further impacting the overall efficiency of the arbitrator. Moreover, there may be nested relationships among the multiple instructions about to be starved (for example, multiple instructions may have data or access dependencies on each other). The timing overhead incurred by one instruction about to be starved may cause other instructions with nested relationships to be starved as well.

[0030] Based on this, this application provides a novel anti-starvation mechanism for the arbitrator. This mechanism monitors the status of each instruction in the instruction queue and increases the priority of an instruction before it reaches the point of imminent starvation, given that the instruction has a certain risk of starvation. This allows the arbitrator to adjust the scheduling order of the instruction according to its increased priority, without halting the entire arbitrator workflow and incurring the timing overhead of doing so. This compensates for the efficiency loss caused by stopping the entire arbitrator workflow when an instruction is about to starve, thereby reducing the impact on the overall efficiency of the arbitrator and improving its overall performance.

[0031] It should be understood that the arbitrator adjusts the scheduling order of the instruction in the instruction ordering according to the increased priority of the instruction. This allows the instruction to be scheduled earlier, thus preventing it from starving. This method of slowly increasing the priority of instructions during scheduling only partially adjusts the scheduling order of instructions in the instruction ordering. The timing overhead of adjusting the scheduling order is far less than the timing overhead of stopping the entire workflow. Therefore, it can, to some extent, compensate for the efficiency loss caused by stopping the entire workflow of the arbitrator when an instruction is about to starve. The instruction with the lowest scheduling order in the instruction ordering is called an inefficient instruction. Since the priority of each instruction is adjusted when it has a certain risk of starvation, so that the instruction can be scheduled as soon as possible, the waiting time of the instruction can be reduced, and the risk of the instruction being starved can be reduced. Therefore, even inefficient instructions can have their risk of starvation significantly reduced, thus reducing the number of starved instructions.

[0032] This application applies the aforementioned novel anti-starvation mechanism to an instruction scheduling device. Below, we will first combine... Figure 1 This paper introduces computer systems that utilize this instruction scheduling device.

[0033] Figure 1 This is a schematic diagram of a computer system provided in an embodiment of this application. For example... Figure 1 As shown, the computer system includes an instruction sending device 100, an instruction scheduling device 200, and an instruction receiving device 300. The instruction scheduling device 200 is connected to the instruction sending device 100 and the instruction receiving device 300.

[0034] The instruction scheduling device 200 can be a memory controller, a bus controller, or other hardware capable of instruction scheduling. Here, this application embodiment does not limit the device type of the instruction scheduling device 200.

[0035] The instruction sending device 100 and the instruction receiving device 300 are the upstream and downstream devices of the instruction scheduling device 200, respectively. Taking the instruction scheduling device 200 as a memory controller as an example, the instruction sending device 100 is a processor or DMA, and the instruction receiving device 300 is a memory. The processor includes, but is not limited to, a Central Processing Unit (CPU), and the memory includes, but is not limited to, Random Access Memory (RAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Read-Only Memory (ROM), NAND Flash, Hard Disk Drive (HDD), or Solid State Drive (SSD), etc.

[0036] The instruction sending device 100 is used to send multiple instructions to the instruction scheduling device 100. These multiple instructions are used to access the instruction receiving device 300.

[0037] The instruction scheduling device 200 stores multiple instructions sent by the instruction sending device 100 through an instruction sequence. Based on the priority of the multiple instructions, it arbitrates the instructions in the instruction queue and schedules the successfully arbitrated instructions from the instruction sequence to the instruction receiving device 300. For example, it reads the successfully arbitrated instructions from the instruction sequence and sends the read instructions to the instruction receiving device 300. The instruction scheduling device 200 also prevents the instructions in the instruction queue from being starved based on the aforementioned new anti-starvation mechanism.

[0038] Figure 1 This example illustrates a computer system including a single instruction sending device 100. In some embodiments, the computer system includes multiple instruction sending devices 100, each connected to an instruction scheduling device 200. Each instruction sending device 100 can send at least one instruction to the instruction scheduling device 200, and each instruction is used to access the instruction receiving device 300. The instruction scheduling device 200 can store multiple instructions sent by these multiple instruction sending devices 100 through the same instruction queue. Here, the number of instruction sending devices 100 in the computer system is not limited in this embodiment.

[0039] Figure 1The computer system shown can be applied to electronic devices, that is, electronic devices include the computer system. Electronic devices can be terminals or servers. Terminals include, but are not limited to, personal computers (such as laptops, tablets, desktops, ultrabooks, etc.), devices with network product interface design and functions, mobile phones, smart home devices, wearable devices, artificial intelligence devices, smart cars, smart instruments, Internet of Things terminals, or extended reality devices.

[0040] Figure 2 This is a schematic diagram of the structure of an instruction scheduling device provided in an embodiment of this application, as shown below. Figure 2 As shown, the instruction scheduling device 200 includes an input interface 21, an instruction queue 22, an arbitrator 23, a controller 24, and an output interface 25. The input interface 21 is connected to the instruction queue 22, the arbitrator 23 is connected to the output interface 25, and the instruction queue 22, the arbitrator 23, and the controller 24 are interconnected in pairs, that is, the instruction queue 22 is connected to the arbitrator 23 and the controller 24, and the arbitrator 23 is connected to the controller 24.

[0041] Input interface 21, also known as the front-end interface, is the interface for inputting instructions in the instruction scheduling device 200 and is used to connect to the instruction sending device 100. Output interface 25, also known as the back-end interface, is the interface for outputting instructions in the instruction scheduling device 200 and is used to connect to the instruction receiving device 300.

[0042] Input interface 21 is used to receive multiple instructions sent by instruction sending device 100 and send the multiple instructions to instruction queue 22.

[0043] The instruction queue 22 is used to receive and store multiple input instructions. These multiple instructions are sent by the instruction sending device 100 and originate from the input interface 21. The instruction queue 22 can be any hardware with data storage capabilities, storing instructions in a queue format.

[0044] Arbitrator 23 is used to arbitrate the instructions in instruction queue 22 based on the priority of multiple instructions in instruction queue 22, and schedule the successfully arbitrated instructions from instruction queue 22 to the output interface.

[0045] Output interface 25 is used to receive instructions scheduled by arbitrator 23 and send the instructions to instruction sending device 300.

[0046] The controller 24 is a piece of hardware in the instruction scheduling device 200 that applies the new anti-starvation mechanism provided in this application. It is used to provide anti-starvation function for the arbitrator 23. The controller 24 can also be called an anti-starvation structure, an anti-starvation device, or an anti-starvation controller.

[0047] To facilitate understanding, the working principle of the instruction scheduling device 200 is described below.

[0048] When input interface 21 receives any instruction sent by instruction sending device 100, it stores the instruction in instruction queue 22. As the number of instructions sent by instruction sending device 100 increases, the number of instructions stored in instruction queue 22 also increases, allowing instruction queue 22 to store multiple instructions from instruction sending device. Instructions in instruction queue 22 all have priorities in arbitrator 23. Arbitrator 23 arbitrates the instructions in instruction queue 22 based on their priorities, scheduling successfully arbitrated instructions from instruction queue 22 to output interface 25. After receiving the instruction scheduled by arbitrator 23, output interface 25 sends the received instruction to instruction receiving device 300. Based on the anti-starvation mechanism provided in this application, controller 24 increases the priority of instructions at risk of starvation in arbitrator 23, so that arbitrator 23 can issue the instruction earlier based on the increased priority, thereby reducing the risk of the instruction being starved.

[0049] The functions and structures of the arbitrator 23 and the controller 24 will be described in detail below, in conjunction with (1) to (2).

[0050] (1) Arbitrator 23 is used to arbitrate the instructions in instruction queue 22 based on the priority of multiple instructions in instruction queue 22.

[0051] Arbitrator 23 is responsible for instruction arbitration and instruction scheduling.

[0052] Arbitrator 23 is also used to determine the priority of each instruction in instruction queue 22. For example, in response to any instruction entering instruction queue 22, arbitrator 23 assigns a priority to the instruction from multiple preset priorities based on the continuity of the instruction's access address. The priority assigned to the instruction is the priority ultimately determined by arbitrator 23 for the instruction.

[0053] The instruction is used to access the instruction receiving device 300, such as to access a certain hardware within the instruction receiving device 300. This instruction has an access address, which indicates the address of the hardware that the instruction requests to access. Taking the instruction receiving device 300 as a memory as an example, the instruction can be a read / write instruction. A read / write instruction is used to access a storage unit in the memory, instructing the reading or writing of data to that storage unit. The access address of the instruction is the address of the storage unit.

[0054] The default priority is the internal priority of arbitrator 23, which is used to sort instructions.

[0055] The continuity of access addresses for any instruction refers to the continuity between the access addresses of that instruction and other instructions in instruction queue 22. The better the continuity of access addresses, the higher the priority assigned to that instruction by arbitrator 23; conversely, the worse the continuity of access addresses, the lower the priority assigned by arbitrator 23. Multiple instructions with consecutive access addresses are assigned the same priority.

[0056] In some embodiments, the instruction's inherent priority is the priority assigned to the instruction by the instruction sending device 100, and this priority includes, but is not limited to, services. The arbitrator 23 determines the priority of an instruction from multiple preset priorities based on the inherent priority of any instruction and the continuity of the instruction's access address. For example, instructions with higher inherent priorities and better access address continuity are assigned higher priorities; instructions with lower inherent priorities or worse access address continuity are assigned lower priorities.

[0057] Before the instructions in instruction queue 22 have been sorted, they are sorted according to their priority and continuity to obtain an instruction order. Here, priority refers to the assigned priority of each instruction, and instruction order includes the scheduling order of the instructions in instruction queue 22. In this instruction order, higher priority instructions are scheduled earlier, and lower priority instructions are scheduled later. Instructions of the same priority correspond to the same scheduling sequence segment in the instruction order, which includes multiple consecutive scheduling sequences. Any two instructions accessing consecutive addresses are scheduled adjacently in this instruction order.

[0058] If the instructions in instruction queue 22 have already been sorted, in response to any instruction entering instruction queue 22, after assigning a priority to the instruction, arbitrator 23 adjusts the scheduling order in the instruction sorting based on the instruction's priority and the continuity of its access address, so as to insert the instruction into the instruction sorting order. Specifically, the higher the instruction's priority, the earlier its scheduling order in the instruction sorting; the lower the instruction's priority, the later its scheduling order. If there are other instructions in instruction queue 22 with a contiguous access address to the instruction, the instruction's scheduling order is adjacent to and follows the scheduling order of those other instructions.

[0059] It should be understood that after obtaining the instruction order, each time an instruction enters the instruction queue 22, the arbitrator 23 locally adjusts the instruction order to insert the scheduling order of that instruction into the instruction order.

[0060] Arbitrator 23 arbitrates the instructions in instruction queue 22 by selecting the instruction with the highest scheduling order as the successfully arbitrated instruction. Correspondingly, all other instructions in instruction queue 22 besides the one with the highest scheduling order are arbitrated instructions.

[0061] The successfully arbitrated instruction is the instruction to be scheduled selected from the instruction queue 22 through arbitration. Arbitrator 23 can arbitrate the instruction queue 22 multiple times, selecting one instruction to be scheduled from the queue 22 each time. After each arbitration, arbitrator 23 schedules the successfully arbitrated instruction from the instruction queue 22 to the output interface 25, so that the output interface 25 can send the successfully arbitrated instruction to the instruction receiving device. After each arbitration, arbitrator 23 shifts each scheduling order in the instruction sequence forward by one position, so that the scheduling order of the successfully arbitrated instruction is dequeued, and the second-to-last scheduling order in the instruction sequence becomes the first-to-last scheduling order.

[0062] Since multiple instructions with consecutive access addresses are scheduled adjacently in the instruction ordering process, during multiple consecutive arbitration processes, these instructions are scheduled out in turn as successfully arbitrated instructions, thus enabling multiple instructions with consecutive access addresses to be sent out in the same batch.

[0063] In some embodiments, the instructions in the instruction queue 22 include read / write instructions and other types of instructions. The arbitrator 23 determines the priority of each instruction in the instruction queue 22, arbitrates the instructions in the instruction queue 22 based on the priorities of multiple instructions in the instruction queue 22, and sorts the instructions in the instruction queue 22. All of these actions are specific to read / write instructions. That is, the arbitrator 23 determines the priority of each read / write instruction in the instruction queue 22, arbitrates the read / write instructions in the instruction queue 22 based on the priorities of multiple read / write instructions in the instruction queue 22, and sorts the read / write instructions in the instruction queue 22 to obtain the instruction order. The anti-starvation mechanism provided in this application is mainly used for read / write instructions, but it can also be applied to other types of instructions besides read / write instructions.

[0064] Arbitrator 23 arbitrates the read and write instructions in the instruction sequence in the manner described above, and sends the successfully arbitrated read and write instructions to output interface 25, so that output interface 25 can send the read and write instructions to instruction receiving device 300.

[0065] Arbitrator 23 employs a different arbitration mechanism to arbitrate other types of instructions in instruction queue 22, excluding read and write instructions. The other types of instructions that are successfully arbitrated are sent to output interface 25, so that output interface 25 can send the other types of instructions to instruction receiving device 300.

[0066] (2) Controller 24 is used to increase the priority of the first instruction in arbitrator 23 in response to the first instruction in instruction queue 22 being overtaken more than or equal to the target number threshold.

[0067] Here, the first instruction refers to any instruction in instruction queue 22, such as any read or write instruction in instruction queue 22. The number of times an instruction is overtaken refers to the number of times that instruction is overtaken by instructions whose enqueue time is later than its own during multiple arbitration processes. Enqueue time refers to the time the instruction enters instruction queue 22. Overtaking occurs when an instruction that enters instruction queue 22 later succeeds in arbitration before an instruction that entered instruction queue 22 earlier. For example, if instruction 1 enters instruction queue 22 first, and instruction 2 enters instruction queue 22 later, and during arbitration, instruction 2 succeeds while instruction 1 fails, then instruction 1 is overtaken by instruction 2.

[0068] The controller 24 is also configured to, in response to any instruction entering the instruction queue 22, start a counter for the number of times the instruction has been overtaken. Whenever another instruction whose enqueue time is later than the instruction successfully arbitrates, the counter for the instruction is incremented by 1. Taking any instruction as the first instruction as an example, the controller 24, in response to the first instruction entering the instruction queue 22, starts a counter for the number of times the first instruction has been overtaken. Whenever an instruction whose enqueue time is later than the first instruction successfully arbitrates, the counter for the first instruction is incremented by 1.

[0069] In some embodiments, the controller 24 uses a counter to count the number of times an instruction is overridden.

[0070] For example, when any instruction enters the instruction queue 22, the controller 24 assigns an enqueue order identifier and a counter to the instruction, uses the count value in the counter as the number of times the instruction has been overtaken, and clears the count value in the counter to enable the overtake count for the instruction.

[0071] Optionally, the controller 24 establishes a correspondence between the instruction, the enqueue order identifier, and the counter, thereby indicating through the correspondence that the count value in the counter is the number of times the instruction has been overrun, and the enqueue order identifier belongs to the instruction.

[0072] The enqueue order identifier indicates the order in which instructions enter instruction queue 22 (i.e., the enqueue order of the instructions). Optionally, the enqueue order identifier is the enqueue order number of the instruction. The earlier the instruction is enqueued, the earlier its enqueue order and the smaller its enqueue order number; the later the instruction is enqueued, the later its enqueue order and the larger its enqueue order number. For example, the enqueue number of the first instruction entering instruction queue 22 is 1, the enqueue number of the second instruction entering instruction queue 22 is 2, the enqueue number of the i-th instruction entering instruction queue 22 is i, and so on, where i is an integer greater than or equal to 1.

[0073] The counter value is the number of times the instruction has been overtaken. Each time the instruction is overtaken, the counter value is incremented by 1, which means the counter value is incremented by 1.

[0074] Subsequently, whenever another instruction with a later enqueue time than the current instruction successfully arbitrates, the controller 24 increments the counter value by 1. For example, whenever the arbitrator 23 performs an arbitration, the controller 24 determines whether the enqueue time of the current instruction is later than the enqueue time of the instruction that was successfully arbitrated, based on the enqueue order identifier of the current instruction and the enqueue order identifier of the instruction that was successfully arbitrated. For instance, if the enqueue order identifier of the current instruction indicates an enqueue order that precedes the enqueue order identifier of the instruction that was successfully arbitrated, the enqueue time of the current instruction is later than the enqueue time of the instruction that was successfully arbitrated. If the enqueue order identifier of the current instruction indicates an enqueue order that follows the enqueue order identifier of the instruction that was successfully arbitrated, the enqueue time of the current instruction is earlier than the enqueue time of the instruction that was successfully arbitrated. If it is determined that the enqueue time of the current instruction is later than the enqueue time of the instruction that was successfully arbitrated, the controller 24 increments the counter value corresponding to the current instruction by 1, thereby incrementing the number of times the instruction has been overtaken by 1. If it is determined that the enqueue time of the instruction is earlier than the enqueue time of the instruction that was successfully arbitrated, the controller 24 will not execute the step of incrementing the counter value corresponding to the instruction by 1.

[0075] Taking the queuing order identifier as the queuing order number as an example, such as Figure 3 As shown, when the controller 24 detects any instruction entering the instruction queue 22, it assigns an enqueue sequence number to the instruction, configures a counter for the instruction, and clears the count value in the counter. That is, after an instruction enters the instruction queue 22, the instruction obtains an enqueue sequence number and a counter, and the counter is cleared. The controller 24 waits for the arbitrator 23 to arbitrate the instructions in the instruction queue 22 (i.e., waits for instruction arbitration). Each time the arbitrator 23 performs an arbitration, it determines whether the enqueue sequence number of the successfully arbitrated instruction is greater than the enqueue sequence number of the instruction. If it is greater, it means that the enqueue time of the successfully arbitrated instruction is later than the enqueue time of the instruction, and the controller 24 increments the count value in the counter of that instruction by 1.

[0076] Again Figure 4 For example, assuming the enqueue order identifier is the enqueue order number, the instruction's configuration information is the instruction's enqueue order number and the number of times it was overtaken. That is, the instruction's configuration information includes the instruction's enqueue order number and the number of times it was overtaken, and the instruction's configuration information is represented as {enqueue order number: number of times it was overtaken}. Figure 4 {0:0} represents configuration information for commands that have not yet been received.

[0077] Assume that commands (Command, CMD) 1 and CMD2 are the first and second commands entering command queue 22, respectively. When CMD1 enters command queue 22, controller 24 configures an enqueue sequence number for CMD1, where the enqueue sequence number of CMD1 is 1. A counter C1 is configured for CMD1, and the count value in counter C1 is used to determine the number of times CMD1 has been overtaken. The overtake count of CMD0 in counter C1 is then cleared to 0, thus obtaining the CMD1 configuration information {1:0}. When CMD2 enters instruction queue 22, controller 24 configures an enqueue sequence number for CMD2. The enqueue sequence number of CMD2 is 2. Counter C2 is configured for CMD2. The count value in counter C2 is the number of times CMD2 has been overtaken. The number of times CMD2 has been overtaken in counter C2 is cleared to 0, thus obtaining the configuration information of CMD2 {1:0}. Assuming that a total of 7 instructions enter instruction queue 22, namely CMD1 to CMD7, the configuration information of these 7 instructions is obtained in the same way. The configuration information of CMD3 is {3:0}, the configuration information of CMD4 is {4:0}, the configuration information of CMD5 is {5:0}, the configuration information of CMD6 is {6:0}, and the configuration information of CMD7 is {7:0}. The counters configured for CMD3 to CMD7 are counters C3 to counter C7, respectively. After these 7 instructions enter instruction queue 22, arbitrator 23 arbitrates the instructions in instruction queue 22. CMD5 is the instruction that succeeded in this arbitration, and arbitrator 23 schedules CMD5 from instruction queue 22 to output interface 25 (i.e., the 5th instruction is removed from instruction queue 22). The enqueue order numbers of CMD1 to CMD4 are all less than the enqueue order number of CMD5, so controller 24 increments the overrun count in the counters corresponding to CMD1 to CMD4 by 1, thereby updating the configuration information of CMD1 to CMD4 to: {1:1}, {2:1}, {3:1}, and {4:1}, respectively.

[0078] It should be understood that the number of times the first instruction has been overtaken is incremented by 1 only when an instruction whose enqueue time is later than the first instruction successfully arbitrates. Assuming arbitrator 23 performs S arbitrations, and the first instruction fails in all S arbitrations, it's possible that some instructions with enqueue times later than the first instruction succeed in arbitration, and it's also possible that some instructions with enqueue times earlier than the first instruction succeed. Therefore, after S arbitrations, the number of times the first instruction has been overtaken is greater than or equal to 0 and less than or equal to S, where S is a positive integer. The number of times the first instruction has been overtaken is also the number of times it has been overtaken by instructions whose enqueue times are later than its own during the S arbitrations.

[0079] In some embodiments, in response to a successful arbitration of the third instruction, the controller 24 updates the enqueue order identifier of any instruction in the instruction queue 22 whose enqueue time is later than the third instruction to the enqueue order identifier of the preceding instruction in the instruction queue 22, and updates the overtake count of the instruction to the overtake count of the preceding instruction. This ensures that after the third instruction leaves the instruction queue 22, the enqueue order of each instruction in the instruction queue 22 is continuous, and the overtake counts of each instruction are ordered. Here, the third instruction is any instruction in the instruction queue 22. The preceding instruction in the instruction queue 22 refers to the instruction whose enqueue time is adjacent to and earlier than the third instruction. For example, using the enqueue order identifier as the enqueue order number, the preceding instruction in the instruction queue 22 refers to the instruction in the instruction queue 22 whose enqueue order number is one greater than the third instruction's. Figure 4 As shown, CMD1 is the instruction preceding CMD2 in instruction queue 22, and CMD2 is the instruction preceding CMD3 in instruction queue 22.

[0080] With the third instruction as Figure 4 Taking CMD5 as an example, CMD5 is removed from instruction queue 22 as the successfully arbitrated instruction. The enqueue order numbers of CMD6 and CMD7 are both greater than the enqueue order number of CMD5, indicating that CMD6 and CMD7 were enqueued later than CMD5. CMD5 is the instruction preceding CMD6 in instruction queue 22, and CMD6 is the instruction preceding CMD7 in instruction queue 22. Therefore, controller 24 updates the enqueue order number of CMD6 to the enqueue order number of CMD5, and updates the counter corresponding to CMD6 from counter C6 to counter C5 corresponding to CMD5. This updates the number of times CMD5 was overtaken in counter C5 to the number of times CMD6 was overtaken, thus updating the configuration information of CMD6 from {6:0} to the configuration information of CMD5 {5:0}. The controller 24 updates the enqueue sequence number of CMD7 to the enqueue sequence number of CMD6, and updates the counter corresponding to CMD7 from counter C7 to counter C6 corresponding to CMD6. This updates the number of times CMD6 is overtaken in counter C6 to the number of times CMD7 is overtaken, thus updating the configuration information of CMD7 from {7:0} to the configuration information of CMD6 {6:0}.

[0081] Then take the third instruction as Figure 4Taking CMD7 as an example, after arbitrating CMD5, the arbitrator 23 performs a new arbitration on the instructions in the instruction queue 22. CMD7 is the instruction that succeeded in this arbitration, and the arbitrator 23 schedules CMD7 from the instruction queue 22 to the output interface 25 (i.e., the 7th instruction is removed from the instruction queue 22). Since the enqueue order numbers of CMD1 to CMD4 and CMD6 are all less than the enqueue order number of CMD7, the controller 24 increments the overrun count in the counters corresponding to CMD1 to CMD4 and CMD6 by 1, thereby updating the configuration information of CMD1 to CMD4 and CMD6 to: {1:2}, {2:2}, {3:2}, {4:2}, and {5:1}, respectively.

[0082] Assuming that at the same time the 7th command is discharged from the instruction queue 22, CMD8 enters the queue as the 8th command, and CMD7 is the command preceding CMD8 in the instruction queue 22, and the enqueue sequence number of CMD7 is 6, then the controller 24 assigns the next enqueue sequence number after the enqueue sequence number of CMD7 to CMD8, so the enqueue sequence number of CMD8 is 7. A counter C7 is configured for CMD8, and the count value in counter C7 is the number of times CMD8 has been overtaken. The number of times CMD8 has been overtaken in counter C7 is then cleared to 0, thus obtaining the configuration information {7:0} for CMD8. Since CMD7 is removed from instruction queue 22, and CMD7 is the preceding instruction to CMD8 in instruction queue 22, the controller 24 updates the enqueue sequence number of CMD8 to the enqueue sequence number of CMD7, updates the counter corresponding to CMD8 from counter C7 to counter C6 corresponding to CMD7, and updates the number of times CMD7 is overtaken in counter C6 to the number of times CMD8 is overtaken, thus updating the configuration information of CMD8 from {7:0} to the configuration information of CMD7 {6:0}.

[0083] It should be understood that the third instruction and the first instruction may be the same instruction or different instructions. When the third instruction and the first instruction are different, if the enqueue time of the first instruction is earlier than the enqueue time of the third instruction, the controller 24 will increment the overtake count of the first instruction by 1 and will not update the enqueue order identifier of the first instruction. If the enqueue time of the first instruction is later than the enqueue time of the third instruction, the enqueue order identifier of the first instruction will be updated to the enqueue order identifier of the instruction preceding the first instruction in the instruction queue 22, and the overtake count of the first instruction will be updated to the overtake count of the preceding instruction.

[0084] During arbitration, if an instruction is overtaken by an instruction whose enqueue time is later than its own, it means that the instruction was not output in the normal enqueue order, and the waiting time of the instruction is increased. The more times the instruction is overtaken, the longer the additional waiting time of the instruction, and the higher the risk of the instruction being starved.

[0085] The number of times an instruction is overtaken before it is about to be starved is called the starvation threshold. When the number of times an instruction is overtaken reaches the starvation threshold, it means that the instruction is about to be starved (or will be starved soon). After a very short period of time, the instruction will be starved. In other words, when the number of times an instruction is overtaken reaches the starvation threshold, the risk of that instruction being starved is at its highest.

[0086] The target number of times thresholded is less than the starvation threshold. For any instruction to reach the target threshold in terms of the number of times it is overtaken includes situations where the number of times it is overtaken is greater than or equal to the target number of times thresholded. When the number of times an instruction is overtaken reaches the target threshold, it indicates that the instruction has a certain risk of starvation, but the risk has not yet reached its maximum. The instruction can wait in the instruction queue 22 for a period of time. To reduce the risk of this instruction, the controller 24 can increase its priority in the arbitrator 23 so that the instruction can be issued earlier. The priority of any instruction in the arbitrator 23 refers to the priority assigned to the instruction by the arbitrator 23 for instruction sorting; that is, the priority determined by the arbitrator 23 for the instruction. The target number of times thresholded and the starvation threshold can be set according to the actual application scenario. In this embodiment, the target number of times thresholded is not limited to being less than the starvation threshold.

[0087] Taking any instruction as the first instruction as an example, there is a target number threshold. If the number of times the first instruction is overtaken is greater than or equal to the target number threshold, the controller 24 increases the priority of the first instruction in the arbitrator 23. For example, the priority of the first instruction in the arbitrator 23 is increased by a preset number of priorities. Taking a preset number of 2 as an example, that is, the priority of the first instruction is increased by 2 priorities. Of course, the preset number is not limited to 2. The preset number can be set according to the specific application scenario. Here, this application embodiment does not limit the preset number.

[0088] In some embodiments, there are multiple target number thresholds, each corresponding to a preset number of targets. Different target number thresholds correspond to different levels of starvation risk. The higher the target number threshold, the higher the corresponding starvation risk. The preset number of targets corresponding to different target number thresholds can be the same or different.

[0089] If the number of times the first instruction is overtaken reaches any target threshold, it indicates that the first instruction has a starvation risk corresponding to the target threshold. In order to reduce the starvation risk of the first instruction, the controller 24 can increase the priority of the first instruction in the arbitrator 23 by a preset number of times corresponding to the target threshold.

[0090] That is, the controller 24 is used to increase the priority of the first instruction to the priority of a preset number of times the number of times it is overtaken by the first instruction reaches any target number threshold in response to the first instruction being overtaken.

[0091] Taking a scenario with two target count thresholds as an example, the target count thresholds include a first count threshold and a second count threshold. The second count threshold is greater than the first count threshold. The preset number of items corresponding to the first count threshold is m, and the preset number of items corresponding to the second count threshold is n, where m and n are both integers greater than 0. The first count threshold can be 50, and the second count threshold can be 80, but the first count threshold is not limited to 50, and the second count threshold is not limited to 80. The first count threshold and the second count threshold can be set according to the actual application scenario. Here, this application embodiment does not limit the first count threshold and the second count threshold.

[0092] The controller 24 is configured to increase the priority of the first instruction by m priority levels in response to the first instruction being overtaken by a first threshold number but not by a second threshold number; and to increase the priority of the first instruction by n priority levels in response to the first instruction being overtaken by a second threshold number.

[0093] The condition that the number of times the first instruction is overtaken reaches the first threshold but not the second threshold includes cases where the number of times the first instruction is overtaken is greater than or equal to the first threshold but less than the second threshold. The condition that the number of times the first instruction is overtaken reaches the second threshold includes cases where the number of times the first instruction is overtaken is greater than or equal to the second threshold.

[0094] It should be understood that when the number of times the first instruction is overtaken reaches the first threshold, the controller 24 increases the priority of the first instruction in the arbitrator 23 by one. The number of times the first instruction is overtaken continues to count. When an instruction that was enqueued later than the first instruction is successfully arbitrated, the number of times the first instruction is overtaken is incremented by 1 again, until the number of times the first instruction is overtaken reaches the second threshold. At this point, the controller 24 increases the priority of the first instruction in the arbitrator 23 by one again. Thus, during the operation of the arbitrator 23, the priority of the first instruction is adjusted in stages according to the number of times it is overtaken, thereby achieving fine-grained control over the instructions.

[0095] The controller 24 can increase the priority of the first instruction in the arbitrator 23 by sending a priority adjustment instruction to the arbitrator 23. This priority adjustment instruction indicates that the priority of the first instruction be adjusted to a target preset number. For example, the priority adjustment instruction includes the instruction identifier of the first instruction and a target preset number, which is a threshold number of times the first instruction has been overtaken. For instance, if the first instruction has been overtaken a certain number of times but has not reached a second threshold, the target preset number is m; if the first instruction has been overtaken a certain number of times, the target preset number is n.

[0096] Accordingly, the arbitrator 23 receives a priority adjustment instruction and adjusts the priority of the first instruction based on the instruction. For example, the priority adjustment instruction may include a target preset number. The arbitrator 23 determines the target priority based on the current priority of the first instruction and the target preset number in the priority adjustment instruction, updates the first priority of the first instruction to the target priority, and adjusts the scheduling order of the first instruction in the instruction sorting based on the target priority to improve the scheduling order of the first instruction.

[0097] The target priority is less than or equal to the highest priority among multiple preset priorities. The target priority can be determined as follows: if there is a preset priority among the multiple preset priorities that is higher than the current priority of the first instruction by a preset number of times, then the preset priority that is higher than the current priority of the first instruction by a preset number of times is taken as the target priority; if there is no preset priority among the multiple preset priorities that is higher than the current priority of the first instruction by a preset number of times, then the highest priority among the multiple preset priorities is taken as the target priority.

[0098] Specifically, the arbitrator 23 adjusts the scheduling order of the first instruction in the instruction ordering based on the target priority. This includes adjusting the scheduling order of the first instruction in the instruction ordering based on the target priority of the first instruction and the continuity of the access address of the first instruction, so as to insert the scheduling order of the first instruction into the instruction ordering. This is similar to the process described above where the arbitrator 23 adjusts the scheduling order in the instruction ordering based on the priority of the instruction and the continuity of the access address of the instruction.

[0099] It should be understood that, since the target priority is higher than the priority of the first instruction before adjustment, adjusting the scheduling order of the first instruction in the instruction sorting based on the target priority of the first instruction and the continuity of the access address of the first instruction can improve the scheduling order of the first instruction, so that the first instruction can successfully arbitrate as soon as possible and be scheduled to the input port for issuance as soon as possible, thereby reducing the risk of the first instruction being starved.

[0100] In some embodiments, after determining the priority of each instruction, the arbitrator 23 also notifies the controller 24 of the instruction's priority. Therefore, the controller 24 knows the current priority of the first instruction. Based on the current priority of the first instruction and the target preset number in the priority adjustment instruction, the controller 24 determines the target priority. The priority adjustment instruction sent to the arbitrator 23 includes the instruction identifier of the first instruction and the target priority, indicating that the priority of the first instruction should be increased to the target priority. After receiving the priority adjustment instruction, the arbitrator 23 updates the priority of the first instruction to the target priority based on the priority adjustment instruction, and adjusts the scheduling order of the first instructions in the instruction sorting based on the target priority.

[0101] The instruction sorting is based on the highest efficiency of the arbitrator 23 in terms of both work efficiency and service efficiency (i.e., high-efficiency sorting). If, similar to related technologies, the first instruction is forcibly issued first, the arbitrator 23 would need to halt its entire workflow and adjust the scheduling order of the first instruction to the highest priority in the high-efficiency sorting. However, the first instruction might have poor continuity with other instructions in the high-efficiency sorting, significantly disrupting the high-efficiency sorting and resulting in substantial efficiency loss, thus affecting the overall work efficiency and service efficiency of the arbitrator 23. In this embodiment, however, the scheduling order of the first instruction is not adjusted to the highest priority in the high-efficiency sorting. Instead, based on the priority and continuity of the first instruction, the scheduling order of the first instruction in the high-efficiency sorting is moved forward as much as possible, so that the adjusted scheduling order of the first instruction is similar to the scheduling order of other instructions of the same priority. The continuity between the access addresses of the first instruction and other instructions of the same priority may not be as good, but compared to instructions of other priorities, the continuity between the access addresses of the first instruction and other instructions of the same priority is better. Therefore, compared to forcibly adjusting the instruction scheduling to the top of the high-efficiency order, the method of adjusting the instruction scheduling order by increasing the priority in this embodiment of the application causes less disruption to the high-efficiency order. Therefore, the method of increasing the instruction priority in this embodiment when the number of times an instruction is overtaken reaches a certain threshold (such as a target threshold) before the instruction is about to starve allows the arbitrator 23 to achieve instruction arbitration that is compatible with fairness and efficiency. It can prevent instructions from being starved and reduce the disruption to the high-efficiency order while issuing instructions. This effectively reduces the loss of system bandwidth utilization caused by inefficient instructions in some scenarios.

[0102] In some embodiments, if the number of times the first instruction is overtaken reaches a target threshold, the controller 24 is further configured to raise the priority of the second instruction in the arbitrator 23 to a target priority if there is a second instruction in the instruction queue 22 that has been overtaken more than 0 times and is associated with the first instruction.

[0103] The second instruction refers to the instruction associated with the first instruction, and there is at least one second instruction. Taking the instruction scheduling device 200 as the memory controller 24 and the instruction receiving device 200 as the memory as an example, the first instruction and the second instruction are read / write instructions for reading and writing data to storage units in the memory. Storage units in the same row in the memory are located in the same storage page, that is, a storage page includes storage units in the same row in the memory. The instruction used to read and write data to a storage unit is also the instruction to access the storage page where the storage unit is located (i.e., the instruction to hit the storage page).

[0104] The association between the first instruction and the second instruction includes: the first instruction and the second instruction are used to access the same memory page in memory.

[0105] For example, if the number of times an instruction is overtaken is greater than 0, the controller 24 stores the instruction information of that instruction. The instruction information includes the instruction identifier of the instruction and the page identifier of the memory page accessed by the instruction. The page identifier of any memory page indicates that memory page. When there are multiple instructions in the instruction queue 22 with an overtake count greater than 0, the controller 24 stores the instruction information of these multiple instructions. For ease of description, the instructions with an overtake count greater than 0 are referred to as fourth instructions; that is, the controller 24 stores the instruction information of multiple fourth instructions.

[0106] For example, in response to the first instruction being overtaken a target threshold number of times, the controller 24, based on the access address of the first instruction and the instruction information of multiple fourth instructions, determines the fourth instruction that accesses the same storage page as the first instruction as the second instruction. For instance, based on the access address of the first instruction, the storage page accessed by the first instruction (referred to as the target storage page) is determined. If the instruction information of any fourth instruction includes the page identifier of the target storage page, that fourth instruction is determined as the second instruction.

[0107] Assuming the instruction receiving device 200 is a memory, the memory includes multiple storage pages, such as... Figure 2 As shown, in some embodiments, the instruction scheduling device 200 further includes a page state recorder 26, which is connected to the controller 24. The page state recorder 26 is used to record the page states of multiple storage pages in the memory. The page state of any storage page is either open or closed. When a storage page is in the open state, the storage page is accessible; when the storage page is in the closed state, the storage page is not accessible.

[0108] If the number of times the first instruction is overtaken reaches the target threshold, the controller 24 is also configured to raise the priority of the second instruction in the arbitrator 23 to the target priority if there is a second instruction in the instruction queue 22 that has been overtaken more than 0 times, is used to access the target storage page, and the target storage page is in an open state.

[0109] For example, when the number of times the first instruction is overtaken reaches the target threshold, the controller 24 determines the target storage page accessed by the first instruction based on the access address of the first instruction, checks the page status of the target storage page in the page status recorder 26, and if the page status of the target storage page is open, based on the access address of the first instruction and the instruction information of multiple fourth instructions, determines the fourth instruction that accesses the same storage page (i.e. the target storage page) as the first instruction as the second instruction, and raises the priority of the second instruction in the arbitrator 23 to the target priority.

[0110] Assuming at least one second instruction is identified, the priority adjustment instruction sent by the controller 24 to the arbitrator 23 in response to the first instruction includes the instruction identifier of each second instruction, such that the priority adjustment instruction also indicates that the priority of the second instruction be increased to the same priority as the first instruction. Accordingly, based on the priority adjustment instruction, the arbitrator 23 uses the target priority as the priority of each second instruction. For any second instruction, based on the target priority of the second instruction and the continuity of the access address of the second instruction, the scheduling order of the second instructions in the instruction sorting is adjusted, similar to the adjustment method of the scheduling order of the first instruction, and will not be described again here.

[0111] While raising the priority of the first instruction, the priority of the second instruction is also raised to the same priority as the first instruction. This allows the arbitrator 23 to adjust the scheduling order of multiple instructions (including the first instruction and all second instructions) simultaneously with a single instruction reordering adjustment. Since these multiple instructions have the same adjusted priority, adjusting the scheduling order in the instruction reordering based on these adjusted priorities ensures that the scheduling order of these instructions lies within the same priority segment. This ensures that the scheduling order of these instructions is similar, allowing them to be issued as quickly as possible within the same time period, reducing the risk of these instructions being starved. Furthermore, by adjusting the high-efficiency reordering, ensuring that the scheduling order of these instructions lies within the same priority segment in the high-efficiency reordering (i.e., instruction reordering), it avoids the scheduling order of these instructions being scattered across different instruction reorderings, which could significantly disrupt the high-efficiency reordering process. Furthermore, efficient sorting is based on the contiguousness of instruction access addresses. When multiple instructions hit the same memory page, this ensures a certain degree of address contiguousness. This not only makes the scheduling order of these instructions more similar but also minimizes disruption to the address contiguousness of the efficient sorting process, thus reducing its impact. This approach prevents multiple instructions from being starved while minimizing disruption to the efficient sorting process, effectively reducing the bandwidth utilization loss caused by inefficient instructions in certain scenarios. Furthermore, if multiple instructions hit the same memory page (i.e., the target memory page) and that memory page is in an open state, it indicates that the arbitrator 23 is about to or is scheduling the instructions that hit the memory page to the memory. In this case, the priority of these multiple instructions is raised to the same priority so that these multiple instructions can be issued as soon as possible when the memory page is in an open state, reducing the number of times the memory page is repeatedly opened. This can eliminate the overhead of repeatedly opening the same memory page, increase the memory bus throughput bandwidth, reduce memory power consumption, improve instruction pipeline efficiency, reduce pipeline flushing, and reduce the arbitration and scheduling pressure on the arbitrator 23.

[0112] If the number of times an instruction is overtaken reaches the second threshold, after the controller 24 increases the priority of the instruction for the second time, the instruction may continue to wait for scheduling. If the waiting time is too long, it may also cause the instruction to starve.

[0113] Based on this, in some embodiments, when the number of times an instruction is overtaken reaches a second threshold but has not yet reached the starvation threshold, it indicates that the instruction is at risk of starvation, but there is still some time before it is starved. The instruction's priority can be temporarily increased to improve the probability of successful arbitration. Once the number of times an instruction is overtaken reaches the starvation threshold, it indicates that the instruction is about to be starved. To avoid instruction starvation, it can be forcibly issued with priority. Although forcibly issuing instructions with priority will incur some efficiency loss, because the instruction priority has already been increased, the probability of the instruction reaching the state of imminent starvation is relatively small. This results in a significantly smaller number of instructions that need to be forcibly issued compared to related technologies, thus avoiding instruction starvation while minimizing efficiency loss as quickly as possible.

[0114] For example, controller 24 is configured to increase the priority of the first instruction in arbitrator 23 in response to the first instruction's overtaking count reaching a target threshold but not reaching a starvation threshold. Specifically, if the first threshold is reached but the second threshold is not, the priority of the first instruction is increased by m priority levels; if the second threshold is reached but the starvation threshold is not reached, the priority of the first instruction is increased by n priority levels. Here, "the first instruction's overtaking count not reaching the second threshold" includes situations where the first instruction's overtaking count is less than the second threshold.

[0115] Controller 24 is also configured in arbitrator 23 to force issue the first instruction in response to the first instruction being overtaken a certain number of times, which reaches a starvation threshold. Forced issuance of the instruction means that the instruction is forced to be sent first. In some embodiments, the starvation threshold may also be referred to as the forced threshold.

[0116] by Figure 3 For example, the counter value of any instruction (such as the first instruction) is the number of times the instruction has been overridden. During the counting process, the controller 24 determines whether the counter value of the instruction has reached the starvation threshold. If it has reached the starvation threshold, the instruction is configured to be forcibly issued. If it has not reached the starvation threshold, the controller determines whether the counter value has reached the second count threshold. If it has reached the second count threshold, the priority of the instruction is increased (e.g., the priority of the instruction in the arbitrator 23 is increased by n priorities). If it has not reached the second count threshold, the controller determines whether the counter value has reached the first count threshold. If it has reached the first count threshold, the priority of the instruction is increased (e.g., the priority of the instruction in the arbitrator 23 is increased by m priorities). If it has not reached the first count threshold, the instruction continues to wait for instruction arbitration.

[0117] Specifically, the controller 24 configures the first instruction to be forcibly issued in the arbitrator 23 by sending an instruction configuration command to the arbitrator 23. The instruction configuration command instructs the first instruction to be configured to be forcibly issued, and the instruction configuration command includes an instruction identifier of the first instruction.

[0118] Accordingly, the arbitrator 23 receives a configuration command from the controller 24, and based on the configuration command, configures the first command to be forcibly issued, stops the operation of the arbitrator 23, and schedules the first command from the command to the output interface 25 for output. The first command is issued with mandatory priority.

[0119] When the instruction receiving device is a memory, and the first instruction is a read / write instruction used to access a target memory page (i.e., the first instruction hits the target memory page), if the target memory page is not activated before the first instruction is forcibly issued first, it needs to be activated first, and the first instruction is then scheduled from the instruction queue to the output terminal. Because the first instruction is forcibly issued first, other read / write instructions in the instruction queue 22 that hit other memory pages besides the target memory page cannot be sent. Therefore, other memory pages cannot be activated. Forcibly issuing the first instruction first will mask the activation / deactivation of those other memory pages and other read / write instructions in the instruction queue 22 that hit other memory pages.

[0120] The above is an example of a target number threshold including two number thresholds. In some embodiments, the target number threshold may include more than two number thresholds. Whenever the number of times any instruction is overtaken reaches a target number threshold, the priority of that instruction will be increased once, thereby enabling more refined control over the instruction.

[0121] In this embodiment, a controller 24 is added to the instruction scheduling device 200. The controller 24 records the number of times each instruction in the instruction queue 22 is overtaken. Before an instruction is about to be starved (i.e., before the instruction reaches the state of being starved), once the number of times the instruction is overtaken reaches a certain threshold, the controller 24 will actively increase the priority of the instruction in the arbitrator 23, so that the arbitrator 23 can send the instruction as soon as possible based on the adjusted priority of the instruction. During this process, it is not necessary to stop the entire workflow of the arbitrator 23, avoiding the timing overhead caused by stopping the workflow of the arbitrator 23, thereby improving the working efficiency and service efficiency of the arbitrator 23.

[0122] In some embodiments, the controller 24 may contain multiple modules, each used to implement different functions of the controller 24. Figure 5 The controller 24 provided in the embodiment of this application is shown as an example. Figure 5As shown, the controller 24 includes a cache module 241, a recording module 242, a comparison module 243, and a priority control module 244. The recording module 242 is connected to the instruction queue 22, the cache module 241, and the comparison module, while the priority control module 244 is connected to the comparison module and the arbitrator 23.

[0123] The recording module 242 is used to assign an enqueue order identifier and a counter to each instruction in the instruction queue 22, establish a correspondence between the instruction, the enqueue order identifier, and the counter, and send this correspondence to the comparison module 243. This correspondence is used to determine the count value in the counter as the number of times the corresponding instruction has been overtaken.

[0124] The recording module 242 is also used to record the number of times each instruction in the instruction queue 22 has been overtaken. For example, after each arbitration by the arbitrator 23, in response to the successful arbitration of any instruction in the instruction sequence, the recording module increments the count value in the counters corresponding to each instruction in the instruction queue 22 whose enqueue time is earlier than that instruction, so as to increment the number of times each instruction has been overtaken by 1.

[0125] The recording module 242 is also used to store the instruction information of any instruction in the cache module 241 when the number of times any instruction in the instruction queue 22 has been overridden is greater than 0.

[0126] The cache module 241 is used to store instruction information of instructions in the instruction queue 22 that have been overtaken more than 0 times.

[0127] Comparison module 243 is used to receive the correspondence between each instruction, the enqueue order identifier, and the counter in instruction queue 22, determine the counter corresponding to each instruction based on the correspondence, and compare the count value in the counter corresponding to each instruction with the starvation threshold and the target number threshold (the comparison method can be found in [reference]). Figure 3 When the count value in the counter corresponding to the first instruction reaches the starvation threshold or reaches the target number threshold but does not reach the starvation threshold, a notification message is sent to the memory instruction priority module 344. The notification message indicates that the number of times the first instruction has been overtaken has reached the starvation threshold or the target number threshold.

[0128] The priority control module 244 is used to receive a notification message for the first instruction. When the notification message indicates that the number of times the first instruction has been overtaken has reached the starvation threshold, the module sends an instruction configuration command to the arbitrator 23. When the notification message indicates that the number of times the first instruction has been overtaken has reached the starvation threshold, the module sends a priority adjustment command to the arbitrator 23. The instruction configuration command is used to instruct the first instruction to be configured as a forced instruction, and the priority adjustment command instructs the priority of the first instruction to be adjusted to the target preset number.

[0129] Optionally, if the notification message indicates that the number of times the first instruction has been overtaken has reached the starvation threshold, the priority control module 244 is further configured to determine the second instruction that hits the same storage page as the instruction based on the instruction information stored in the cache module 241, and send a priority adjustment instruction to the arbitrator 23 based on the second instruction and the first instruction. At this time, the priority adjustment instruction also indicates that the priority of the second instruction be raised to the same priority as the first instruction.

[0130] Optionally, the priority control module 244 is also connected to the page status recorder 26. When the notification message indicates that the number of times the first instruction has been overtaken has reached the starvation threshold, the priority control module is also used to query the page status of the target storage page hit by the first instruction in the page status recorder 26. If the page status of the target storage page is open, the second instruction that hits the same storage page as the first instruction is determined according to the instruction information stored in the cache module. Based on the second instruction and the first instruction, a priority adjustment instruction is sent to the arbitrator 23.

[0131] Optionally, the instruction scheduling device 200 further includes a system configuration module, and the controller 24 further includes a configuration module. The configuration module is connected to the system configuration module and the recording module, comparison module, and cache module in the controller 24 via a priority control module.

[0132] The system configuration module is used to configure the configuration parameters required by each module of the controller 24 during operation in the configuration module of the controller 24.

[0133] The configuration module in controller 24 is used to obtain the configuration parameters configured by the system configuration module for each module in controller 24, and send the configuration parameters of each module in controller 24 to the corresponding module so that the corresponding module can work normally.

[0134] exist Figure 5 In this embodiment, the modules of controller 24 are divided according to their functions. Based on the functions of controller 24, the modules in controller 24 can also be divided in other ways. Here, the internal structure of controller 24 in this application embodiment is not limited, as long as it can realize the functions of controller 24 described above.

[0135] Figure 2 The arbitrator 23 and controller 24 shown can be located in different hardware or in the same hardware. Taking the arbitrator 23 and controller 24 as an example, the arbitrator 23 is the arbitration module and the controller 24 is the anti-starvation control module. The arbitration module and the anti-starvation control module are integrated in the same hardware. Alternatively, the page recording module, the arbitration module and the anti-starvation control module can be integrated in the same hardware. The hardware that integrates the arbitration module and the anti-starvation control module can be called an arbitrator, and the arbitrator has an anti-starvation function.

[0136] Figure 2 The instruction scheduling device 200 is illustrated by an example comprising an input interface 21, an arbitrator 23, and a controller 24. In some embodiments, the instruction scheduling device 200 may also include multiple input interfaces 21, multiple arbitrators 23, and multiple controllers 24. Each input interface 21 corresponds to an instruction queue 22, each instruction queue 22 corresponds to an arbitrator 23, and each arbitrator 23 corresponds to a controller 24. The input interface 21 is connected to the corresponding instruction queue 22, and the arbitrator 23 is connected to both the corresponding instruction queue 22 and the controller 24. Each controller 24 provides an anti-starvation function for its corresponding arbitrator 23.

[0137] Figure 2 The instruction scheduling device 200 is illustrated with an example of an output interface. In some embodiments, the instruction scheduling device 200 may include multiple output interfaces, each of which is connected to an arbitrator 23.

[0138] This application provides an instruction scheduling method, which is applied to an instruction scheduling device, such as the instruction scheduling device 200 described above. The method includes steps 601 to 603.

[0139] 601. Store multiple input instructions in the instruction queue.

[0140] Step 601 can be executed by the input interface of the instruction queue connected to the instruction scheduling device.

[0141] 602. Arbitrate the instructions in the instruction queue based on the priority of the plurality of instructions.

[0142] Step 602 can be executed by the arbitrator in the instruction scheduling device.

[0143] 603. In response to the first instruction in the instruction queue being overtaken more than or equal to a target threshold number of times, the priority of the first instruction is increased.

[0144] Wherein, the number of times the first instruction is overtaken refers to the number of times it is overtaken by instructions whose enqueue time is later than its own during multiple consecutive arbitration processes. The enqueue time refers to the time when the instruction enters the instruction queue. The target number threshold is less than the number of times the instruction will be overtaken before it is about to trigger instruction starvation. The priority of the first instruction can be the priority of the first instruction in the arbitrator of the instruction scheduling device. This step 602 can be executed by the controller in the instruction scheduling device.

[0145] Optionally, the target number threshold includes a first number threshold and a second number threshold, wherein the second number threshold is greater than the first number threshold; The step of increasing the priority of the first instruction in response to the first instruction being overtaken more than or equal to a target threshold number of times includes: In response to the first instruction being overtaken reaching the first threshold number of times but not reaching the second threshold number of times, the priority of the first instruction is increased by m priority levels, where m is an integer greater than 0; In response to the first instruction being overtaken a certain number of times, the priority of the first instruction is increased by n priority levels, where n is an integer greater than 0.

[0146] Optionally, the number of times the instruction is overtaken to trigger starvation is set as the starvation threshold. The method further includes: in response to the first instruction being overtaken a number of times but not reaching the target number threshold, increasing the priority of the first instruction. In response to the first instruction being overtaken a certain number of times, reaching the starvation threshold, the first instruction is configured to be forcibly issued, wherein the forcibly issued instruction is an instruction that is forcibly prioritized for issuance.

[0147] Optionally, the priority of the first instruction after being raised is the target priority; the method further includes: if there is a second instruction in the instruction queue that has been overtaken more than 0 times and is associated with the first instruction, raising the priority of the second instruction in the arbitrator to the target priority.

[0148] Optionally, the association between the first instruction and the second instruction includes: the first instruction and the second instruction being used to access the same memory page in the memory.

[0149] Optionally, the first instruction is a read / write instruction.

[0150] Optionally, the instruction scheduling device is a memory controller or a bus controller.

[0151] The specific methods and procedures for each step in the above-described method embodiments have been described in detail in the embodiments of the instruction scheduling device 200, and will not be elaborated upon here. This method achieves the beneficial effects achievable by the instruction scheduling device 200, and will not be repeated here.

[0152] The above-described method and apparatus embodiments of this application provide a variety of possible implementations. At least two of these possible implementations can be combined to obtain even more possible implementations.

[0153] In an exemplary embodiment, this application provides an instruction scheduling apparatus, which includes a processor and a memory. The memory stores at least one instruction, and the processor executes the at least one instruction, causing the instruction scheduling apparatus to implement at least one step of the instruction scheduling method provided in the embodiments of this application. The at least one step includes each step of the instruction scheduling method, or includes a method step executed by a controller in the instruction scheduling apparatus, or includes a method step executed by an arbitrator and a controller in the instruction scheduling apparatus.

[0154] In an exemplary embodiment, this application provides a computer-readable storage medium that, when at least one instruction in the computer-readable storage medium is executed by a processor of an instruction scheduling device, enables the instruction scheduling device to perform at least one step of the instruction scheduling method provided in the embodiments of this application. The at least one step includes various steps of the instruction scheduling method, or includes method steps of the instruction scheduling method executed by a controller in the instruction scheduling device, or includes method steps of the instruction scheduling method executed by an arbitrator and a controller in the instruction scheduling device.

[0155] In an exemplary embodiment, this application provides a computer program product including one or more instructions, which can be executed by a processor of an instruction scheduling device, causing the instruction scheduling device to implement at least one step of the instruction scheduling method provided in the embodiments of this application. The at least one step includes each step of the instruction scheduling method, or includes a method step executed by a controller in the instruction scheduling device, or includes a method step executed by an arbitrator and a controller in the instruction scheduling device.

[0156] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0157] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A command scheduling device, characterized in that, The instruction scheduling device includes two interconnected instruction queues, an arbitrator, and a controller; The instruction queue is used to store multiple input instructions; The arbitrator is used to arbitrate the instructions in the instruction queue based on the priority of the plurality of instructions; The controller is configured to increase the priority of the first instruction in the arbitrator in response to the first instruction in the instruction queue being overtaken a target number of times. The number of times the first instruction is overtaken refers to the number of times it is overtaken by an instruction whose enqueue time is later than its own during multiple arbitration processes. The enqueue time refers to the time when the instruction enters the instruction queue. The target number threshold is less than the number of times the instruction will be overtaken before it is about to starve.

2. The instruction scheduling device according to claim 1, characterized in that, The target number threshold includes a first number threshold and a second number threshold, wherein the second number threshold is greater than the first number threshold. The controller is used for: In response to the first instruction being overtaken reaching the first threshold number of times but not reaching the second threshold number of times, the priority of the first instruction is increased by m priority levels, where m is an integer greater than 0; In response to the first instruction being overtaken a certain number of times, the priority of the first instruction is increased by n priority levels, where n is an integer greater than 0.

3. The instruction scheduling device according to claim 1, characterized in that, The number of times the instruction to be starved is overtaken is the starvation threshold, and the controller is further configured to: In response to the first instruction being overtaken reaching the target number threshold but not the starvation threshold, the priority of the first instruction in the arbitrator is increased; In response to the first instruction being overtaken a certain number of times, reaching the starvation threshold, the first instruction is configured in the arbitrator to be forcibly issued, wherein the forcibly issued instruction is an instruction that is forcibly prioritized for issuance.

4. The instruction scheduling device according to claim 1, characterized in that, The priority of the first instruction after being raised is the target priority; The controller is further configured to, if there is a second instruction in the instruction queue that has been overtaken more than 0 times and is associated with the first instruction, raise the priority of the second instruction in the arbitrator to the target priority.

5. The instruction scheduling device according to claim 1, characterized in that, The association between the first instruction and the second instruction includes: the first instruction and the second instruction are used to access the same memory page in the memory.

6. The instruction scheduling device according to claim 1, characterized in that, The first instruction is a read / write instruction.

7. The instruction scheduling device according to claim 1, characterized in that, The instruction scheduling device is a memory controller or a bus controller.

8. A computer system, characterized in that, The computer system includes an instruction sending device and an instruction scheduling device, wherein the instruction scheduling device includes an instruction queue, an arbitrator, and a controller that are interconnected in pairs; The instruction sending device is used to send multiple instructions to the instruction scheduling device; The instruction queue is used to store the input instructions; The arbitrator is used to arbitrate the instructions in the instruction queue based on the priority of the plurality of instructions; The controller is configured to increase the priority of the first instruction in the arbitrator in response to the first instruction in the instruction queue being overtaken a target number of times. The number of times the first instruction is overtaken refers to the number of times it is overtaken by an instruction whose enqueue time is later than its own during multiple consecutive arbitration processes. The enqueue time refers to the time when the instruction enters the instruction queue. The target number threshold is less than the number of times the instruction will be overtaken before it is about to starve.

9. An instruction scheduling method, characterized in that, The method is applied to an instruction scheduling device, and the method includes: Multiple input instructions are stored in the instruction queue; Arbitration is performed on the instructions in the instruction queue based on the priority of the multiple instructions; In response to the first instruction in the instruction queue being overtaken a number of times greater than or equal to a target threshold, the priority of the first instruction is increased; The number of times the first instruction is overtaken refers to the number of times it is overtaken by an instruction whose enqueue time is later than its own during multiple consecutive arbitration processes. The enqueue time refers to the time when the instruction enters the instruction queue. The target number threshold is less than the number of times the instruction will be overtaken before it is about to starve.

10. A computer-readable storage medium, characterized in that, When at least one instruction in the computer-readable storage medium is executed by a processor in an instruction scheduling device, the instruction scheduling device is able to perform the instruction scheduling method as described in claim 9.

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