A domestic large-computing-power load calculation platform based on a dual-domain architecture

Abstract

The application discloses a domestic high-computing-load calculation platform based on a dual-domain architecture, and relates to the technical field of electric digital data processing.The platform comprises an interface expansion module, a fault management module and a running recovery module.The interface expansion module calls the calculation output in the load calculation state, converts the GTX high-speed serial channel and the GPIO channel on the expansion board into target load interfaces through the FPGA, and transmits the calculation output to form an interface transmission state.The fault management module continuously monitors the load calculation state and the interface transmission state, and implements fault isolation, reset recovery and power control by a high-reliability domain controller to obtain a dual-domain recovery state.The running recovery module verifies the communication state and the power supply state of the high-performance domain and the high-reliability domain by using the dual-domain recovery state, isolates abnormal communication links and independent power supply rails, and keeps the remaining functional domains continue to run to form a platform running state.The application can limit the propagation of high-performance domain faults to the high-reliability domain, and keep the functional parts not affected by the faults continue to run.

Description

Technical Field

[0001] This invention relates to the field of electronic digital data processing technology, and in particular to a domestically developed high-computing-power load computing platform based on a dual-domain architecture. Background Technology

[0002] With the development of payload applications such as inter-satellite collaboration, on-orbit intelligent identification, and real-time image processing, payload computing platforms are gradually evolving towards high computing power, domestic production, high reliability, and flexible interface expansion. They also collaborate with server-grade processors, GPU / NPU modules, high-speed network interfaces, and FPGA expansion modules to undertake parallel computing and payload data transmission tasks.

[0003] Existing load computing platforms often centralize load computing, operation control, fault management, and interface expansion within the same processor domain, operating through a single boot memory, a shared management bus, and a shared power supply link. When a computing task crashes, deadlocks, or experiences communication anomalies, fault detection and recovery functions are prone to simultaneous failure; when the boot image is flipped or damaged, the platform lacks a replacement boot image; when the load interface is fixed to the motherboard, changing the load type requires redesigning the motherboard; and when a local power rail or management bus malfunctions, the fault can easily propagate to other functional parts, causing the entire platform to fail to boot or to be interrupted. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides a domestically developed high-computing-power load computing platform based on a dual-domain architecture to solve the problem of fault propagation and system failure caused by the coupling of load computing tasks and fault management tasks.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] This invention provides a domestically developed high-performance payload computing platform based on a dual-domain architecture. It includes: a startup management module, which collects the power supply status of the independent power rails corresponding to the high-performance domain and the high-reliability domain; the high-reliability domain controller performs a two-out-of-three vote on the startup images in three Q-FLASH chips and starts the S5000C processor and GPU / NPU module to obtain a dual-domain startup state; a computing scheduling module, which receives payload data in response to the dual-domain startup state; the S5000C processor schedules the GPU / NPU module to execute payload data calculations to obtain a payload calculation state; an interface expansion module, which calls the calculation output from the payload calculation state; the FPGA on the expansion board converts the GTX high-speed serial channel and GPIO channel into a target payload interface and transmits the calculation output to form an interface transmission state; a fault management module, which continuously monitors the payload calculation state and the interface transmission state; the high-reliability domain controller implements fault isolation, reset recovery, and power control to obtain a dual-domain recovery state; and a running recovery module, which uses the dual-domain recovery state to verify the communication and power supply status of the high-performance domain and the high-reliability domain, isolates abnormal communication links and independent power rails, and keeps the remaining functional domains running to form a platform running state.

[0008] As a preferred embodiment of the domestic high-performance load computing platform based on a dual-domain architecture described in this invention, the step of collecting the power supply status of the independent power rails corresponding to the high-performance domain and the high-reliability domain specifically includes:

[0009] Connect the three power rails corresponding to the high-performance domain and the one power rail corresponding to the high-reliability domain to establish an independent power supply relationship between the two domains.

[0010] The output voltage, output current, and overcurrent protection status of each power rail in the dual-domain independent power supply relationship are collected to obtain the power rail power supply data;

[0011] Verify the power supply status of the power rail corresponding to the high reliability domain according to the power rail power supply data, and start the high reliability domain controller after the power rail corresponding to the high reliability domain is powered normally, and generate the high reliability domain start record.

[0012] According to the high-reliability domain boot record, the high-reliability domain controller reads the boot images pre-stored in the three Q-FLASH chips respectively, records the Q-FLASH chips to which each boot image belongs, and obtains the boot image read record.

[0013] As a preferred embodiment of the domestically developed high-performance computing platform based on a dual-domain architecture described in this invention, the process of obtaining the dual-domain startup state specifically includes:

[0014] Extract the boot images corresponding to the three Q-FLASH chips from the boot image read record, perform consistency checks on the three boot images, and take at least two boot images with consistent content as valid boot images, and generate a boot image voting record;

[0015] Load the valid boot image from the boot image voting record into the S5000C processor, start the S5000C processor and establish the operating environment for the GPU / NPU module, storage resources, communication links and expansion board connection links, and obtain the dual-domain boot state.

[0016] As a preferred embodiment of the domestically developed high-performance load computing platform based on a dual-domain architecture as described in this invention, the step of receiving load data in response to the dual-domain startup state specifically includes:

[0017] In response to the dual-domain startup state, the payload data is received through the payload interface and the 10 Gigabit network interface. The data length, storage location and transmission source of the payload data are recorded according to the receiving channel, and a payload data receiving record is generated.

[0018] Using the storage location and transmission source in the payload data reception record as an index, verify the availability status of the S5000C processor, GPU / NPU module, storage resources, high-speed interconnect links and communication links, and generate a computing resource status record;

[0019] By using the computing resource status record, the control operations corresponding to the load data are configured to the S5000C processor, the parallel computing corresponding to the load data is configured to the available GPU / NPU module, and the load data distribution object and the computing output storage location are recorded accordingly to generate the task resource corresponding record;

[0020] The execution order of control operations and parallel computations, the load data distribution path, the computation output feedback path, and the task status feedback path are configured according to the corresponding records of task resources to obtain the computation task scheduling relationship.

[0021] As a preferred embodiment of the domestically developed high-computing-power load computing platform based on a dual-domain architecture described in this invention, the process of obtaining the load computing state specifically includes:

[0022] According to the computing task scheduling relationship, load data is retrieved from the storage location recorded in the load data receiving record, control operations are sent to the S5000C processor, and parallel computing is sent to the GPU / NPU module specified in the corresponding task resource record to generate a load task execution record.

[0023] Based on the execution record of the payload task, the S5000C processor coordinates storage resources and high-speed interconnect links to drive the GPU / NPU module to perform at least one of AI inference, image processing, model calculation and data fusion, and records the execution object, running stage and calculation output location of the calculation task to generate payload data calculation record;

[0024] By utilizing the payload data to record the corresponding GPU / NPU module's operating status, computation output update status, and high-speed interconnect link communication status, the payload computation status can be obtained by distinguishing between normal execution, execution interruption, and execution completion computation tasks.

[0025] As a preferred embodiment of the domestically developed high-performance computing platform based on a dual-domain architecture described in this invention, the formation of the interface transmission state specifically includes:

[0026] Retrieve the calculation output from the load calculation status, match the calculation output according to the protocol type, transmission direction and synchronization method corresponding to the target load interface, and generate an interface adaptation record;

[0027] Using the interface adaptation record, select the expansion module that supports the target payload interface, connect the GTX high-speed serial channel and GPIO channel to the expansion module, configure the data channel and synchronization signal channel, and generate the expansion channel configuration record;

[0028] Set the FPGA's protocol conversion path according to the extended channel configuration record, convert the calculation output into the data format corresponding to the target payload interface, configure the synchronization control information, and generate protocol conversion data;

[0029] The protocol conversion data is sent through the corresponding extended channel configured in the extended channel configuration record. The transmitted data, currently transmitted data, untransmitted data, and extended channel operation status are recorded according to the transmission order of the calculated output, forming the interface transmission status.

[0030] As a preferred embodiment of the domestically developed high-performance load computing platform based on a dual-domain architecture as described in this invention, the continuous monitoring of the load computing status and interface transmission status specifically includes:

[0031] The GPU / NPU module operating status, computing output update status, and high-speed interconnect link communication status in the load computing status are continuously correlated with the extended channel operating status and protocol conversion status in the interface transmission status, and the power status and temperature status of the high-performance domain are collected synchronously to generate dual-domain operation monitoring records.

[0032] Taking the state changes of adjacent monitoring times in the dual-domain operation monitoring record as the object, distinguish between calculation anomalies, communication anomalies, power supply anomalies, temperature anomalies and expansion interface anomalies, and generate dual-domain anomaly classification records according to the functional domain and connection link where the anomaly occurred.

[0033] Extract computational anomalies, communication anomalies, power supply anomalies, temperature anomalies, and expansion interface anomalies from the dual-domain anomaly classification records. Assign computational and communication anomalies to the reset control link, power supply anomalies to the power control link, temperature anomalies to the status monitoring link, and expansion interface anomalies to the expansion board connection link. Record the handling link corresponding to each anomaly type and generate a fault handling path record.

[0034] Record the operation process corresponding to the abnormal location according to the fault handling path, and generate an isolation recovery record by performing at least one of the following through the high reliability domain controller: status recording, fault isolation, reset recovery, power control and management information reporting.

[0035] As a preferred embodiment of the domestically developed high-performance computing platform based on a dual-domain architecture described in this invention, the process of obtaining the dual-domain recovery state specifically includes:

[0036] The operating status, power status, temperature status, and communication status of the high-performance domain are re-acquired according to the isolation recovery record, while the continuous operation of the high-reliability domain controller and management link is recorded to generate a recovery status re-acquisition record.

[0037] The recovery status is verified by re-collecting records of the recovery status to check the recovery status of the corresponding operating status at the abnormal location, and the operation continuity of the high reliability domain controller during fault isolation and reset recovery is verified to generate dual-domain recovery verification records;

[0038] By utilizing dual-domain recovery verification records, the anomaly type, anomaly location, handling method, and recovery status are transmitted to the management side via a high-reliability domain CAN bus, generating a recovery status reporting record.

[0039] The recovery status reporting records and dual-domain recovery verification records are collected, and the dual-domain operational availability is marked according to the recovery status of the high-performance domain and the continuous operation status of the high-reliability domain to obtain the dual-domain recovery status.

[0040] As a preferred embodiment of the domestic high-performance computing platform based on a dual-domain architecture described in this invention, the step of verifying the communication and power supply status of the high-performance domain and the high-reliability domain using the dual-domain recovery state specifically includes:

[0041] Extract the service communication recovery status of the high-performance domain and the management communication continuity status of the high-reliability domain from the dual-domain recovery status, and generate a dual-domain communication recovery record corresponding to the high-performance domain CAN bus and the high-reliability domain CAN bus.

[0042] Based on the dual-domain communication recovery record, the service instructions, load control information and high-performance domain status information are transmitted via the high-performance domain CAN bus, while the health status, fault status, recovery status and management instructions are transmitted via the high-reliability domain CAN bus, generating a dual-domain communication split record.

[0043] By utilizing dual-domain communication splitting records to verify the physical link and transmission content of the high-performance domain CAN bus and the high-reliability domain CAN bus, the service-side communication and management-side communication are kept isolated from each other, thus obtaining the dual-domain communication operation status.

[0044] As a preferred embodiment of the domestically developed high-performance computing platform based on a dual-domain architecture as described in this invention, the formation of the platform's operating state specifically includes:

[0045] Power management information is transmitted using dual-domain communication operation status. The output voltage, output current and overcurrent protection status of the three independent power rails in the high-performance domain and the one independent power rail in the high-reliability domain are collected respectively to generate a dual-domain power supply operation record.

[0046] The power supply relationship between each independent power rail and the corresponding functional domain is verified by using the dual-domain power operation record. The independent power rail with abnormal output is mapped to the GPU / NPU module, high-speed interconnect circuit and high-reliability domain controller that it supplies, and a power rail handling record is generated.

[0047] According to the power rail handling record, isolate the independent power rail with abnormal output, keep the other independent power rails, high-performance domain CAN bus and high-reliability domain CAN bus running, and record the operating availability status of the high-performance domain and high-reliability domain to form the platform operating status.

[0048] The beneficial effects of this invention are as follows: By configuring the load calculation task and the fault management task in the high-performance domain and the high-reliability domain respectively, the high-reliability domain controller can independently perform health monitoring, fault detection, fault isolation, fault recovery, power status monitoring and management information reporting. When the high-performance domain experiences a crash, deadlock, response timeout, communication abnormality or local power supply abnormality, the high-reliability domain controller can still perform reset recovery and power control through an independent management link, reset control interface and power control interface, and use independent CAN bus and power rail to limit the fault propagation range, thereby maintaining the continuous operation of the high-reliability domain and the functional parts unaffected by the fault, and enhancing the platform's fault isolation capability, recovery capability and overall operational reliability. Attached Figure Description

[0049] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a flowchart of a domestically developed high-performance computing platform based on a dual-domain architecture.

[0051] Figure 2 This is a flowchart for dual-domain startup.

[0052] Figure 3 This is a flowchart for fault recovery.

[0053] Figure 4 This is a schematic diagram of a high-performance domain computing power structure.

[0054] Figure 5 This is a schematic diagram of a load interface expansion structure where the motherboard and expansion board are separate.

[0055] Figure 6 This is a schematic diagram of a dual-domain isolation and fault recovery structure. Detailed Implementation

[0056] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0057] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0058] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0059] Reference Figures 1-6 This is one embodiment of the present invention, which provides a domestically developed high-computing-power load computing platform based on a dual-domain architecture, comprising the following steps:

[0060] The domestically developed high-performance computing platform includes a motherboard, expansion boards, and a power management module. The motherboard houses an S5000C processor, a GPU / NPU module, a high-reliability domain controller, storage resources, a 10 Gigabit network interface, and basic management interfaces. The S5000C processor and GPU / NPU module constitute a high-performance domain, while the high-reliability domain controller and management peripherals constitute a high-reliability domain. The high-reliability domain controller operates independently of the S5000C processor. It receives the operating status of the high-performance domain through a management link, collects the temperature status of the high-performance domain and the power supply status of each independent power rail through a status monitoring link, sends a reset signal to the S5000C processor through a reset control link, and controls the connection and disconnection of each independent power rail through a power control link.

[0061] The motherboard and expansion board are connected via a board-side connector. The motherboard leads out a GTX high-speed serial channel, a GPIO channel, and a synchronization signal channel to the expansion board. The FPGA on the expansion board is configured with a protocol conversion path according to the installed interface expansion module, so that the computing output can be converted into at least one of the following payload interface signals: CXP, Aurora, LVDS, RS422, or CameraLink.

[0062] The startup management module collects the power supply status of the independent power rails corresponding to the high-performance domain and the high-reliability domain. The high-reliability domain controller performs a two-out-of-three vote on the startup image in the three Q-FLASH chips and starts the S5000C processor and GPU / NPU module to obtain the dual-domain startup status.

[0063] Connect the three power rails corresponding to the high-performance domain and the one power rail corresponding to the high-reliability domain to establish an independent power supply relationship between the two domains.

[0064] Specifically, after passing through surge protection fuses and EMC filters, the primary power supply is connected to three power rails corresponding to the high-performance domain and one power rail corresponding to the high-reliability domain. The three power rails corresponding to the high-performance domain are connected to supply power to the GPU / NPU module and high-speed interconnect circuits, and the one power rail corresponding to the high-reliability domain is connected to supply power to the high-reliability domain controller and management peripherals. Each power rail is kept independent of the others, establishing a dual-domain independent power supply relationship.

[0065] It should be noted that surge protection fuses are used to limit power-on inrush current and abnormal overcurrent, EMC filters are used to suppress conducted interference in the primary power supply, and the dual-domain independent power supply relationship means that the three power rails corresponding to the high-performance domain and the one power rail corresponding to the high-reliability domain have independent power conversion and output paths, so that when an overcurrent occurs on a single power rail, the corresponding power output can be isolated without affecting the continued power supply of the other power rails.

[0066] The output voltage, output current, and overcurrent protection status of each power rail in the dual-domain independent power supply relationship are collected to obtain the power rail power supply data.

[0067] Specifically, each power rail in the dual-domain independent power supply relationship is connected to a voltage sampling branch, a current sampling branch, and an overcurrent detection branch. The multi-channel selection circuit sequentially selects the three power rails corresponding to the high-performance domain and the one power rail corresponding to the high-reliability domain. The voltage sampling signal and the current sampling signal are sent to the analog-to-digital conversion circuit, and the overcurrent protection status of each power rail is recorded simultaneously. According to the output voltage, output current, and overcurrent protection status corresponding to the functional domain to which each power rail belongs, the power rail power supply data is obtained.

[0068] Verify the power supply status of the power rail corresponding to the high reliability domain according to the power rail power supply data, and start the high reliability domain controller after the power rail corresponding to the high reliability domain is powered normally, and generate the high reliability domain start record.

[0069] Specifically, the output voltage, output current, and overcurrent protection status of the power rail corresponding to the high-reliability domain are extracted from the power rail supply data. The output voltage is compared with the allowable output voltage range of the power rail corresponding to the high-reliability domain, and the output current is compared with the rated output current of the DC / DC converter connected to the power rail corresponding to the high-reliability domain. The overcurrent protection status is also verified. When the output voltage is within the allowable output voltage range of the power rail corresponding to the high-reliability domain, the output current does not exceed the rated output current, and the overcurrent protection status is in an untriggered state, a start-up enable signal is sent to the high-reliability domain controller. The start-up time, the output voltage, output current, overcurrent protection status of the power rail corresponding to the high-reliability domain, and the start-up status of the high-reliability domain controller are recorded to generate a high-reliability domain start-up record.

[0070] It should also be noted that the allowable output voltage range of the power rail corresponding to the high reliability domain is based on the allowable input voltage range recorded in the manuals of the high reliability domain controller and the management peripheral device, respectively, and takes the overlapping voltage range in which both the high reliability domain controller and the management peripheral device can work normally; the rated output current is based on the rated output current recorded in the manual of the DC / DC converter device connected to the power rail corresponding to the high reliability domain; the power supply conditions refer to the output voltage being within the allowable output voltage range of the power rail corresponding to the high reliability domain, the output current not exceeding the rated output current, and the overcurrent protection being in an untriggered state.

[0071] According to the high-reliability domain boot record, the high-reliability domain controller reads the boot images pre-stored in the three Q-FLASH chips respectively, records the Q-FLASH chips to which each boot image belongs, and obtains the boot image read record.

[0072] Specifically, the startup status of the high-reliability domain controller is extracted from the high-reliability domain startup record. When the high-reliability domain controller is in the startup status, the high-reliability domain controller accesses the corresponding startup image storage area one by one according to the connection order of the three Q-FLASH chips, and obtains the startup images pre-stored in the three Q-FLASH chips respectively. Each startup image is matched with the corresponding Q-FLASH identifier, reading order and reading completion status. After all three startup images have been read, the startup images and their respective Q-FLASH chips are collected to obtain the startup image reading record.

[0073] Extract the boot images corresponding to the three Q-FLASH chips from the boot image read record, perform consistency checks on the three boot images, and take at least two boot images with consistent content as valid boot images, and generate a boot image voting record.

[0074] Specifically, the boot images, Q-FLASH identifiers, and reading order corresponding to the three Q-FLASH chips are extracted from the boot image reading records. The contents of the three boot images are checked pairwise according to the reading order, and the consistency check result of each pair of boot images is recorded. When two boot images have the same contents, either one of the two boot images is taken as the valid boot image, and the valid boot image, the corresponding Q-FLASH identifier, and the consistency check result are recorded to generate a boot image voting record.

[0075] It should also be noted that when all three boot images from the three Q-FLASH chips are successfully read, the high-reliability domain controller performs pairwise consistency checks on the three boot images. If at least two boot images have identical content, the boot image with identical content is considered the valid boot image. If one Q-FLASH chip fails to read but the boot images from the remaining two Q-FLASH chips have identical content, one of the remaining two boot images is still considered the valid boot image. When fewer than two boot images are successfully read, all three boot images are inconsistent, or no two boot images with identical content are obtained, the high-reliability domain controller stops the S5000C processor boot process, maintains the operation of the high-reliability domain CAN bus, and reports the Q-FLASH identifier, image read status, and boot voting failure status.

[0076] Load the valid boot image from the boot image voting record into the S5000C processor, start the S5000C processor and establish the operating environment for the GPU / NPU module, storage resources, communication links and expansion board connection links, and obtain the dual-domain boot state.

[0077] Specifically, the high-reliability domain controller locks the valid boot image and its corresponding Q-FLASH identifier based on the boot image voting record, loads the valid boot image into the boot storage area of ​​the S5000C processor, and sends a boot command. After the S5000C processor completes booting, it sequentially establishes high-speed interconnection with the GPU / NPU module, access to storage resources, transmission of communication links, and connection of expansion board links. It records the corresponding status of GPU / NPU module operation, storage resource access, communication link connectivity, and expansion board connection links with the boot status of the high-reliability domain controller to obtain the dual-domain boot status.

[0078] like Figure 4As shown, the domestically produced high-performance computing platform includes an S5000C processor 1 and at least one GPU / NPU module 2. The S5000C processor 1 is connected to the GPU / NPU module 2 via a high-speed interconnect link, and is also connected to storage resources, a 10 Gigabit network interface, and a basic management interface. The S5000C processor 1 is used to run the operating system, perform computing task scheduling, manage payload data transmission, and coordinate storage resources. The GPU / NPU module 2 is used to perform at least one parallel operation in AI inference, image processing, model computation, and data fusion. The S5000C processor 1 and the GPU / NPU module 2 together constitute a high-performance domain.

[0079] The computation scheduling module receives payload data in response to the dual-domain startup state, and the S5000C processor schedules the GPU / NPU module to perform payload data calculations to obtain the payload calculation status.

[0080] In response to the dual-domain startup state, it receives payload data through the payload interface and the 10 Gigabit network interface, and generates a payload data reception record according to the data length, storage location and transmission source of the payload data recorded by the receiving channel.

[0081] Specifically, after the dual-domain startup state indicates that the S5000C processor, GPU / NPU module, storage resources, communication links, and expansion board connection links are available, the payload interface and 10 Gigabit network interface are opened to receive payload data. The transmission source is marked according to the receiving channel corresponding to the payload interface or 10 Gigabit network interface. The data length of the payload data is counted and the payload data is stored in the storage location allocated in the storage resources. The receiving channel, transmission source, data length, and storage location are recorded item by item to generate a payload data receiving record.

[0082] Using the storage location and transmission source in the payload data reception record as an index, the availability status of the S5000C processor, GPU / NPU module, storage resources, high-speed interconnect links and communication links is verified, and a computing resource status record is generated.

[0083] Specifically, the storage resource containing the payload data is located based on the storage location in the payload data reception record. An access request is initiated to the corresponding storage location, and the access status returned by the storage resource and the actual length occupied by the payload data are verified against the data length in the payload data reception record. According to the payload interface or 10 Gigabit network interface corresponding to the transmission source in the payload data reception record, the connection status, data reception status, and transmission interruption status of the communication link are checked. After the storage resource can be accessed normally and the communication link remains connected, the startup completion status and running response status of the S5000C processor are verified. A status query request is sent to the GPU / NPU module corresponding to the payload data execution object, the running response status of the GPU / NPU module is recorded, and the connection status and data interaction status of the high-speed interconnect link between the S5000C processor and the GPU / NPU module are checked. The storage resource access status, communication link connectivity status, S5000C processor running status, GPU / NPU module running status, and high-speed interconnect link connectivity status are matched with the corresponding storage location and transmission source item by item to generate a computing resource status record.

[0084] By utilizing the computing resource status record, the control operations corresponding to the payload data are configured to the S5000C processor, the parallel computing corresponding to the payload data is configured to the available GPU / NPU module, and the payload data distribution object and computing output storage location are recorded accordingly to generate a task resource corresponding record.

[0085] Specifically, the S5000C processor's running status, GPU / NPU module's running status, storage resource access status, and high-speed interconnect link connectivity status are checked according to the computing resource status records. The control operations corresponding to task initiation, payload data distribution, and computational output feedback are configured to the S5000C processor. At least one parallel operation among AI inference, image processing, model computation, and data fusion is configured to the GPU / NPU module that is running normally and has a high-speed interconnect link connectivity. The computational output storage location is configured from the accessible storage resources. The control operations, parallel operations, payload data distribution objects, and computational output storage locations are matched item by item to generate a corresponding record of task resources.

[0086] It should also be noted that AI inference refers to inputting payload data into the GPU / NPU module, performing feature calculations according to the deployed algorithm parameters, and outputting inference results; image processing refers to performing at least one of the following processing methods on the payload image: decoding, correction, enhancement, transformation, and feature extraction; model computation refers to performing parameter calculations, updating intermediate results, and generating computational outputs according to the computational model corresponding to the payload task; and data fusion refers to aligning, combining, and jointly operating multi-source payload data according to the transmission source and task correspondence of the payload data to form a fused computational output oriented towards the payload task.

[0087] The execution order of control operations and parallel computations, the load data distribution path, the computation output feedback path, and the task status feedback path are configured according to the corresponding records of task resources to obtain the computation task scheduling relationship.

[0088] Specifically, based on the correspondence between control operations, parallel computations, payload data distribution objects, and computation output storage locations in the task resource correspondence record, the S5000C processor is configured to execute task initiation and payload data distribution, and available GPU / NPU modules are configured to execute parallel computations and computation output feedback. Starting from the storage location in the payload data receiving record, the payload data distribution object is connected via the S5000C processor and a high-speed interconnect link to form a payload data distribution path. The computation output is then transmitted from the available GPU / NPU module to the computation output storage location via the high-speed interconnect link, forming a computation output feedback path. The task initiation, execution, completion, and interruption statuses are fed back to the S5000C processor along the high-speed interconnect link, forming a task status feedback path. The execution order of control operations and parallel computations, the payload data distribution path, the computation output feedback path, and the task status feedback path are recorded to obtain the computation task scheduling relationship.

[0089] According to the computing task scheduling relationship, the load data is retrieved from the storage location recorded in the load data receiving record, the control operation is sent to the S5000C processor, and the parallel operation is sent to the GPU / NPU module specified in the corresponding task resource record to generate the load task execution record.

[0090] Specifically, the system accesses the storage location recorded in the payload data receiving record according to the execution order in the computing task scheduling relationship. After verifying the storage resource access status and payload data length, it retrieves the payload data and sends the corresponding control operations for task startup, payload data distribution, and computing output feedback to the S5000C processor. The S5000C processor locks the specified GPU / NPU module according to the task resource corresponding record, sends the payload data and parallel computing content through the payload data distribution path, and configures the computing output feedback path and computing output storage location. It records the control operation distribution status, parallel computing distribution status, payload data transmission status, and GPU / NPU module receiving status along the task status feedback path, generating a payload task execution record.

[0091] Based on the execution record of the payload task, the S5000C processor coordinates storage resources and high-speed interconnect links to drive the GPU / NPU module to perform at least one of AI inference, image processing, model calculation and data fusion, and records the execution object, running stage and calculation output location of the calculation task to generate payload data calculation record.

[0092] Specifically, based on the payload data, parallel computation content, GPU / NPU module, and computation output storage location in the payload task execution record, the S5000C processor controls storage resources to send payload data to the high-speed interconnect link and drives the GPU / NPU module to execute at least one of AI inference, image processing, model computation, and data fusion. After the GPU / NPU module completes the current running stage, it feeds back the running stage to the S5000C processor via the high-speed interconnect link and transmits the computation output to the computation output storage location. The GPU / NPU module is used as the execution object of the computation task, and the task start-up, payload data computation, and computation output storage are recorded as running stages, corresponding to the computation output storage location, to generate a payload data computation record.

[0093] By utilizing the payload data to record the corresponding GPU / NPU module's operating status, computation output update status, and high-speed interconnect link communication status, the payload computation status can be obtained by distinguishing between normal execution, execution interruption, and execution completion computation tasks.

[0094] Specifically, based on the computational task execution object, running stage, and computational output location in the payload data computation record, the GPU / NPU module running status, computational output update status, and high-speed interconnect link communication status are obtained respectively. When the GPU / NPU module continues to run, the computational output continues to update, and the high-speed interconnect link remains connected, the computational task is marked as normally executed. When the GPU / NPU module stops responding, the computational output stops updating, or the high-speed interconnect link is interrupted, the computational task is marked as execution interrupted. When the GPU / NPU module completes parallel computation, the computational output is updated, and the computational output is stored in the computational output location, the computational task is marked as execution completed. The computational task execution object, running stage, computational output location, and corresponding markers are recorded item by item to obtain the payload computation status.

[0095] like Figure 5 As shown, the domestically produced high-performance computing platform adopts a structure where the motherboard 4 and expansion board 5 are separate. The motherboard 4 houses the S5000C processor 1, GPU / NPU module 2, high-reliability domain controller 3, storage resources, a 10 Gigabit network interface, a basic management interface, and a power management module 6, forming the core board of the computing platform. The expansion board 5 is connected to the motherboard 4 via a board-side connector. The motherboard 4 provides the expansion board 5 with a GTX high-speed serial channel, GPIO channel, and synchronization signal channel. The expansion board 5 is equipped with an interface module 7, which uses an FPGA to convert the GTX high-speed serial channel and GPIO channel into at least one of the following payload interface signals: CXP, Aurora, LVDS, RS422, or CameraLink.

[0096] The interface expansion module calls the calculation output in the load calculation state, and converts the GTX high-speed serial channel and GPIO channel into the target load interface through the FPGA on the expansion board and transmits the calculation output, forming the interface transmission state.

[0097] Retrieve the calculation output from the load calculation status, match the calculation output according to the protocol type, transmission direction and synchronization method corresponding to the target load interface, and generate an interface adaptation record.

[0098] Specifically, the calculation output location is located according to the completed calculation task in the load calculation state. The calculation output is retrieved from the calculation output location, and the protocol type, transmission direction and synchronization method corresponding to the target load interface are obtained. The calculation output is mapped to the data transmission channel supported by the protocol type. The sending end and receiving end of the calculation output are limited according to the transmission direction. The timing correspondence between the calculation output and the synchronization signal is established according to the synchronization method. The calculation output, target load interface, protocol type, transmission direction and synchronization method are recorded item by item to generate an interface adaptation record.

[0099] Using the interface adapter record, select the expansion module that supports the target payload interface, connect the GTX high-speed serial channel and GPIO channel to the expansion module, configure the data channel and synchronization signal channel, and generate the expansion channel configuration record.

[0100] Specifically, according to the target payload interface, protocol type, transmission direction, and synchronization method in the interface adaptation record, select an expansion module from the expansion board that can carry the corresponding protocol type, connect the GTX high-speed serial channel and GPIO channel that match the target payload interface to the expansion module, configure the channel carrying the calculation output as the data channel, configure the GPIO channel that transmits synchronization control information as the synchronization signal channel, and record the target payload interface, expansion module, data channel, synchronization signal channel, and transmission direction item by item to generate an expansion channel configuration record.

[0101] Configure the FPGA's protocol conversion path according to the extended channel configuration record, convert the calculation output into the data format corresponding to the target payload interface, configure the synchronization control information, and generate protocol conversion data.

[0102] Specifically, according to the extended channel configuration record, the data channel is connected to the protocol conversion path corresponding to the target payload interface in the FPGA, the synchronization signal channel is connected to the synchronization control path of the FPGA, the calculation output is segmented, arranged in fields and adapted in bit width according to the protocol type, the data input and data output terminals are configured according to the transmission direction, the transmission timing of the converted data and the synchronization signal is configured according to the synchronization method, and the converted data, synchronization control information, target payload interface and extended channel are collected to generate protocol conversion data.

[0103] The protocol conversion data is sent through the corresponding extended channel configured in the extended channel configuration record. The transmitted data, currently transmitted data, untransmitted data, and extended channel operation status are recorded according to the transmission order of the calculated output, forming the interface transmission status.

[0104] Specifically, according to the extended channel configuration record, the extended channel corresponding to the target payload interface is locked. The protocol conversion data is sent into the data channel according to the transmission order of the calculation output, and the synchronization control information is output through the synchronization signal channel. During the transmission process, the transmitted data, the currently transmitted data, and the untransmitted data are divided according to the completion status of the transmission of the calculation output. At the same time, the connection status of the extended channel, the synchronization signal status, and the data transmission status are recorded. The transmission progress of the calculation output and the operation status of the extended channel are summarized to form the interface transmission status.

[0105] like Figure 6 As shown, the domestically produced high-performance computing platform is divided into a high-performance domain and a high-reliability domain. The high-performance domain includes the S5000C processor 1 and the GPU / NPU module 2, while the high-reliability domain includes the high-reliability domain controller 3 and management peripherals. The high-reliability domain controller 3 operates independently of the S5000C processor 1. It receives the operating status of the high-performance domain through the management link, collects the temperature and power supply status of the high-performance domain through the status monitoring link, sends a reset signal to the S5000C processor 1 through the reset control link, and controls the connection and disconnection of each independent power rail through the power control link.

[0106] The fault management module continuously monitors the load calculation status and interface transmission status. The high-reliability domain controller implements fault isolation, reset recovery, and power control to obtain the dual-domain recovery status.

[0107] The GPU / NPU module operating status, computation output update status, and high-speed interconnect link communication status in the load calculation state are continuously correlated with the extended channel operating status and protocol conversion status in the interface transmission state, and the power status and temperature status of the high-performance domain are collected synchronously to generate dual-domain operation monitoring records.

[0108] Specifically, the GPU / NPU module operating status, computation output update status, and high-speed interconnect link communication status are recorded in the same monitoring cycle, and the extended channel operating status and protocol conversion status are recorded in the interface transmission status. Using the monitoring time as the corresponding field, the load computation status and interface transmission status at the same monitoring time are linked. At the same time, the power status and temperature status of the high-performance domain are collected. The status changes are arranged according to the monitoring time, and the GPU / NPU module operating status, computation output update status, high-speed interconnect link communication status, extended channel operating status, protocol conversion status, power status, and temperature status are aggregated to generate a dual-domain operation monitoring record.

[0109] It should also be noted that the protocol conversion status refers to the status of the current conversion process after the FPGA completes the protocol conversion according to the protocol type, data format and synchronization method corresponding to the target payload interface, marking the conversion status as either a successful conversion or a failed conversion.

[0110] The high-reliability domain controller sends status query information to the S5000C processor via the management link according to the monitoring cycle, and receives the running status information returned by the S5000C processor. At the same time, it obtains the running status and computation output update status of the GPU / NPU module according to the task status feedback path. If the S5000C processor fails to return running status information within the communication response time limit, or if the GPU / NPU module fails to provide feedback on the running stage and computation output update status within the task update time limit, it records the unresponsive execution object, the status query time, and the response waiting time as data for judging computational or communication anomalies.

[0111] Taking the state changes of adjacent monitoring times in the dual-domain operation monitoring records as the object, distinguish between calculation anomalies, communication anomalies, power supply anomalies, temperature anomalies, and expansion interface anomalies, and generate dual-domain anomaly classification records according to the functional domain and connection link where the anomaly occurred.

[0112] Specifically, the status changes of adjacent monitoring times in the dual-domain operation monitoring records are checked according to the monitoring time sequence. When the GPU / NPU module stops responding or the calculation output stops updating, it is marked as a calculation anomaly. When the communication status of the high-speed interconnect link changes from connected to interrupted, it is marked as a communication anomaly. When the power supply status exceeds the allowable power supply range of the corresponding device or the overcurrent protection status is triggered, it is marked as a power supply anomaly. When the temperature status exceeds the allowable operating temperature range of the corresponding device, it is marked as a temperature anomaly. When the operation status of the expansion channel is interrupted or the protocol conversion status stops updating, it is marked as an expansion interface anomaly. Calculation anomalies, communication anomalies, power supply anomalies, and temperature anomalies are marked to the high-performance domain and the corresponding high-speed interconnect link. Expansion interface anomalies are marked to the expansion board connection link. The anomaly type, anomaly occurrence time, functional domain, and connection link are recorded to generate a dual-domain anomaly classification record.

[0113] It should be noted that the allowable output voltage range of each independent power rail is taken as the overlapping range of the allowable input voltage range of the corresponding powered device, and the rated output current is taken as the rated output current recorded in the corresponding DC / DC converter device manual; the allowable operating temperature range of the high-performance domain is taken as the allowable operating temperature range recorded in the manuals of the S5000C processor, GPU / NPU module and high-speed interconnect device respectively, and the allowable operating temperature range of the corresponding device is selected according to the abnormal location; the communication response time limit is taken as the normal round-trip time from the high reliability domain controller sending status query information to receiving valid operating status information, and the time that can cover the normal communication delay is selected after communication test statistics; the task update time limit is taken as the allowable execution time of each operating stage of the corresponding load task, and is set according to the task scheduling configuration and load processing test records; the reset waiting time limit is taken as the time required for the S5000C processor or GPU / NPU module to receive the reset signal and resume operation response, and the power release time limit is taken as the time required for the corresponding DC / DC converter to stop output and for the output voltage to drop to the required range for re-powering. The reset waiting time limit and the power release time limit are both verified through whole machine reset test and power-off restart test.

[0114] Extract computational anomalies, communication anomalies, power supply anomalies, temperature anomalies, and expansion interface anomalies from the dual-domain anomaly classification records. Map computational and communication anomalies to the reset control link, power supply anomalies to the power control link, temperature anomalies to the status monitoring link, and expansion interface anomalies to the expansion board connection link. Record the handling link corresponding to each anomaly type to generate a fault handling path record.

[0115] Specifically, based on the anomaly type, occurrence time, functional domain, and connection link in the dual-domain anomaly classification record, computational and communication anomalies are mapped to the reset control link in the high-performance domain, recording the reset object, reset trigger position, and reset control entry; power anomalies are mapped to the power control link of the abnormal power rail, recording the abnormal power rail, affected power supply object, and power control entry; temperature anomalies are mapped to the status monitoring link in the high-performance domain, recording the temperature anomaly location, temperature status change, and continuous monitoring entry; and expansion interface anomalies are mapped to the expansion board connection link, recording the abnormal expansion channel, protocol conversion status, and expansion board connection location. The handling links, anomaly locations, and control entry points corresponding to computational, communication, power, temperature, and expansion interface anomalies are compiled to generate a fault handling path record.

[0116] Record the operation process corresponding to the abnormal location according to the fault handling path, and generate an isolation recovery record by performing at least one of the following through the high reliability domain controller: status recording, fault isolation, reset recovery, power control and management information reporting.

[0117] Specifically, according to the anomaly type, anomaly location, handling link, and control entry point recorded in the fault handling path record, the load data calculation, communication transmission, or expansion interface transmission involved in the anomaly location is suspended, and the suspension time and suspension status are recorded by the high-reliability domain controller; calculation anomalies or communication anomalies are isolated and reset through the reset control link; power anomalies are disconnected from the abnormal power rail through the power control link while maintaining power supply to the remaining independent power rails; temperature anomalies are continuously collected and reported to management information through the status monitoring link; expansion interface anomalies are isolated from the abnormal expansion channel through the expansion board connection link; the anomaly type, anomaly location, handling method, handling time, and post-handling operating status are recorded to generate an isolation and recovery record.

[0118] It should also be noted that when a calculation or communication anomaly corresponds to a reset control link, the high-reliability domain controller first stops data transmission and calculation output feedback at the abnormal location, and sends a reset signal to the S5000C processor or the corresponding GPU / NPU module via the reset control link. During the reset waiting time limit, it continuously collects the running response status of the corresponding execution object and the communication status of the high-speed interconnect link. If the abnormal status is not eliminated after the reset waiting time limit expires, the high-reliability domain controller disconnects the independent power rail corresponding to the abnormal location via the power control link. After the power release time limit expires, it reconnects the corresponding independent power rail and re-executes the startup status verification. When the abnormal status is eliminated, the corresponding running process is restored. If the abnormal status is not eliminated, the abnormal location is kept isolated, and the anomaly type, anomaly location, and recovery failure status are reported through the high-reliability domain CAN bus.

[0119] The operating status, power status, temperature status, and communication status of the high-performance domain are re-acquired according to the isolation recovery record. At the same time, the continuous operation of the high-reliability domain controller and management link is recorded to generate a recovery status re-acquisition record.

[0120] Specifically, based on the anomaly type, anomaly location, handling method, and post-handling operation status in the isolation and recovery record, the S5000C processor operation status, GPU / NPU module operation status, high-speed interconnect link communication status, output voltage, output current, overcurrent protection status, temperature status, and communication link transmission status of each independent power rail are re-acquired at the moment of handling completion. The high-reliability domain controller startup status, management command transmission and reception status, and management information reporting status are continuously recorded along the management link. The re-acquired status is matched with the anomaly location and handling method in the isolation and recovery record. The operation status, power status, temperature status, and communication status of the high-performance domain are arranged according to the acquisition time. At the same time, the continuous operation of the high-reliability domain controller and management link during fault isolation, reset recovery, and power control is recorded to generate a recovery status re-acquisition record.

[0121] The recovery status is verified by re-collecting records of the recovered status to check the recovery status of the corresponding operating status of the abnormal location, and the operation continuity of the high reliability domain controller during fault isolation and reset recovery is verified to generate dual-domain recovery verification records.

[0122] Specifically, based on the anomaly type, anomaly location, handling method, and acquisition time in the recovery status re-acquisition record, the operating status of the S5000C processor, the operating status of the GPU / NPU module, the communication status of the high-speed interconnect link, the output voltage and current of the independent power rail, the overcurrent protection status, the temperature status, and the transmission status of the communication link are verified respectively. When the S5000C processor and GPU / NPU module recover response, the computing output recovers update, the high-speed interconnect link and communication link recover connectivity, the power supply status of the independent power rail returns to normal, and the temperature status is within the allowable operating temperature range, the anomaly location is marked as recovered; otherwise, it is marked as unrecovered. Based on the acquisition time, the startup status, management command transmission and reception status, and management information reporting status of the high-reliability domain controller are verified. When the startup status of the high-reliability domain controller remains valid and management commands and management information are continuously transmitted, the high-reliability domain controller is marked as continuously running. The anomaly location recovery mark and the high-reliability domain controller continuous running mark are combined to generate a dual-domain recovery verification record.

[0123] By utilizing dual-domain recovery verification records, the anomaly type, anomaly location, handling method, and recovery status are transmitted to the management side via a high-reliability domain CAN bus, generating a recovery status reporting record.

[0124] Specifically, the recovery status report content is organized according to the anomaly type, anomaly location, handling method, anomaly location recovery flag, and high-reliability domain controller continuous operation flag in the dual-domain recovery verification record. The high-reliability domain controller sends the recovery status report content to the high-reliability domain CAN bus transmission queue, and transmits the anomaly type, anomaly location, handling method, recovery status, and verification time in sequence, and records the transmission time, transmission status, and management side reception status. After the management side completes the reception, it records the recovery status report content, transmission status, and management side reception status together to generate a recovery status report record.

[0125] The recovery status reporting records and dual-domain recovery verification records are collected, and the dual-domain operational availability is marked according to the recovery status of the high-performance domain and the continuous operation status of the high-reliability domain to obtain the dual-domain recovery status.

[0126] Specifically, the anomaly type, anomaly location, handling method, recovery status, and management side reception status in the recovery status reporting record are correlated with the anomaly location recovery marker and the high-reliability domain controller continuous operation marker in the dual-domain recovery verification record. When the anomaly location recovery marker is "recovered" and the operating status, power status, temperature status, and communication status of the high-performance domain are back to normal, the high-performance domain recovery status is recorded. When the high-reliability domain controller continuous operation marker is valid and management commands and management information are continuously transmitted, the high-reliability domain continuous operation status is recorded. The dual-domain operational availability is then marked by the high-performance domain recovery status and the high-reliability domain continuous operation status. The anomaly handling, recovery verification, and status reporting content are summarized to obtain the dual-domain recovery status.

[0127] The operation recovery module uses dual-domain recovery status verification to check the communication and power supply status of the high-performance domain and the high-reliability domain, isolates abnormal communication links and independent power rails, and keeps the remaining functional domains running, thus forming the platform operation status.

[0128] Extract the service communication recovery status of the high-performance domain and the management communication continuity status of the high-reliability domain from the dual-domain recovery status, and generate dual-domain communication recovery records corresponding to the high-performance domain CAN bus and the high-reliability domain CAN bus.

[0129] Specifically, based on the recovery status of the high-performance domain and the continuous operation status of the high-reliability domain in the dual-domain recovery state, the transmission and reception status of the high-performance domain service commands, load control information, and high-performance domain status information are checked to form the service communication recovery status of the high-performance domain. At the same time, the health status, fault status, recovery status, and continuous transmission and reception status of the management commands of the high-reliability domain are checked to form the management communication continuity status of the high-reliability domain. The service communication recovery status of the high-performance domain is mapped to the high-performance domain CAN bus, and the management communication continuity status of the high-reliability domain is mapped to the high-reliability domain CAN bus. The link status, transmission status, and recovery time of the high-performance domain CAN bus and the high-reliability domain CAN bus are recorded to generate a dual-domain communication recovery record.

[0130] Based on the dual-domain communication recovery record, the service instructions, load control information and high-performance domain status information are transmitted via the high-performance domain CAN bus, while the health status, fault status, recovery status and management instructions are transmitted via the high-reliability domain CAN bus, generating a dual-domain communication split record.

[0131] Specifically, based on the link status, transmission status, and recovery time of the high-performance domain CAN bus and the high-reliability domain CAN bus in the dual-domain communication recovery record, after verifying that the high-performance domain CAN bus is in a transmittable state, the service commands, load control information, and high-performance domain status information are sent to the high-performance domain CAN bus transmission queue according to the generation time, and the transmission order, transmission status, and reception status are recorded; after verifying that the high-reliability domain CAN bus is in a continuous communication state, the health status, fault status, recovery status, and management commands are sent to the high-reliability domain CAN bus transmission queue according to the generation time, and the transmission order, transmission status, and reception status are recorded; the transmission content, transmission order, transmission status, and reception status corresponding to the high-performance domain CAN bus and the high-reliability domain CAN bus are collected to generate a dual-domain communication split record.

[0132] By utilizing dual-domain communication splitting records to verify the physical link and transmission content of the high-performance domain CAN bus and the high-reliability domain CAN bus, the service-side communication and management-side communication are kept isolated from each other, thus obtaining the dual-domain communication operation status.

[0133] Specifically, based on the transmission content, transmission order, transmission status, and reception status in the dual-domain communication splitting record, the connection status, transmission channel, and reception channel of the high-performance domain CAN bus and the high-reliability domain CAN bus are verified respectively. It is checked that the high-performance domain CAN bus only transmits service commands, load control information, and high-performance domain status information, while the high-reliability domain CAN bus only transmits health status, fault status, recovery status, and management commands. When a link interruption, transmission failure, reception failure, or transmission content exceeds the corresponding transmission range occurs, the corresponding CAN bus is marked as abnormal and abnormal transmission is stopped. When the transmission is normal, the service-side communication and management-side communication are kept isolated from each other. The operating status of the high-performance domain CAN bus, the operating status of the high-reliability domain CAN bus, and the transmission isolation status are recorded to obtain the dual-domain communication operating status.

[0134] Power management information is transmitted using dual-domain communication. The output voltage, output current, and overcurrent protection status of the three independent power rails in the high-performance domain and the one independent power rail in the high-reliability domain are collected respectively to generate a dual-domain power supply operation record.

[0135] Specifically, based on the transmission content, transmission order, transmission status, and reception status in the dual-domain communication splitting record, the connection status, transmission channel, and reception channel of the high-performance domain CAN bus and the high-reliability domain CAN bus are verified respectively. It is checked that the high-performance domain CAN bus only transmits service commands, load control information, and high-performance domain status information, while the high-reliability domain CAN bus only transmits health status, fault status, recovery status, and management commands. When a link interruption, transmission failure, reception failure, or transmission content exceeds the corresponding transmission range occurs, the corresponding CAN bus is marked as abnormal and abnormal transmission is stopped. When the transmission is normal, the service-side communication and management-side communication are kept isolated from each other. The operating status of the high-performance domain CAN bus, the operating status of the high-reliability domain CAN bus, and the transmission isolation status are recorded to obtain the dual-domain communication operating status.

[0136] It should also be noted that the transmission range is based on the functional division of the high-performance domain CAN bus for service-side communication and the high-reliability domain CAN bus for management-side communication. The transmission range of the high-performance domain CAN bus includes service commands, load control information, and high-performance domain status information. The transmission range of the high-reliability domain CAN bus includes health status, fault status, recovery status, and management commands. Transmission content that exceeds the corresponding information category is considered to be inconsistent with the transmission range of the corresponding CAN bus.

[0137] The power supply relationship between each independent power rail and the corresponding functional domain is verified by using the dual-domain power operation record. The independent power rail with output abnormality is mapped to the GPU / NPU module, high-speed interconnect circuit and high-reliability domain controller that it supplies, and a power rail handling record is generated.

[0138] Specifically, based on the independent power rail identifiers, output voltages, output currents, and overcurrent protection status in the dual-domain power supply operation log, verify the power supply connection relationships between the three independent power rails in the high-performance domain and the GPU / NPU module and high-speed interconnect circuit. At the same time, verify the power supply connection relationship between one independent power rail in the high-reliability domain and the high-reliability domain controller. When the output voltage exceeds the allowable input voltage range of the corresponding power supply object, the output current exceeds the rated output current of the corresponding DC / DC converter, or the overcurrent protection status is triggered, mark the corresponding independent power rail as an output abnormality, and record the independent power rail with the output abnormality, the affected GPU / NPU module, high-speed interconnect circuit or high-reliability domain controller, and the abnormality type to generate a power rail handling record.

[0139] According to the power rail handling record, isolate the independent power rail with abnormal output, keep the other independent power rails, high-performance domain CAN bus and high-reliability domain CAN bus running, and record the operating availability status of the high-performance domain and high-reliability domain to form the platform operating status.

[0140] Specifically, based on the independent power rails with abnormal outputs, the affected power supply objects, and the type of abnormality in the power rail handling record, shut down the power supply output of the DC / DC converter corresponding to the independent power rail with abnormal outputs, and confirm that the independent power rail with abnormal outputs has entered the isolation state; review the output voltage, output current, and overcurrent protection status of the remaining independent power rails, and ensure that the independent power rails with normal power supply status continue to supply power to the GPU / NPU module, high-speed interconnect circuit, or high-reliability domain controller, while maintaining the connection and transmission status of the high-performance domain CAN bus and the high-reliability domain CAN bus; record the operational availability status of the high-performance domain and the high-reliability domain according to the operating status of the GPU / NPU module, high-speed interconnect circuit, high-reliability domain controller, high-performance domain CAN bus, and high-reliability domain CAN bus, forming the platform operating status.

[0141] In summary, this invention configures the load calculation task and fault management task in the high-performance domain and the high-reliability domain respectively, enabling the high-reliability domain controller to independently perform health monitoring, fault detection, fault isolation, fault recovery, power status monitoring, and management information reporting. When the high-performance domain experiences a crash, deadlock, response timeout, communication anomaly, or local power supply anomaly, the high-reliability domain controller can still perform reset recovery and power control through an independent management link, reset control interface, and power control interface. Furthermore, it utilizes independent CAN buses and power rails to limit the fault propagation range, thereby maintaining the continuous operation of the high-reliability domain and the functional parts unaffected by the fault, enhancing the platform's fault isolation capability, recovery capability, and overall operational reliability.

[0142] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A domestically developed high-performance computing platform based on a dual-domain architecture, characterized in that: include, The startup management module collects the power supply status of the independent power rails corresponding to the high-performance domain and the high-reliability domain. The high-reliability domain controller performs a two-out-of-three vote on the startup image in the three Q-FLASH chips and starts the S5000C processor and GPU / NPU module to obtain the dual-domain startup status. The computation scheduling module receives payload data in response to the dual-domain startup state, and the S5000C processor schedules the GPU / NPU module to perform payload data calculations to obtain the payload calculation status. The interface expansion module calls the calculation output in the load calculation state, and converts the GTX high-speed serial channel and GPIO channel into the target load interface through the FPGA on the expansion board and transmits the calculation output, forming the interface transmission state. The fault management module continuously monitors the load calculation status and interface transmission status. The high-reliability domain controller implements fault isolation, reset recovery and power control to obtain the dual-domain recovery status. The operation recovery module uses dual-domain recovery status verification to check the communication and power supply status of the high-performance domain and the high-reliability domain, isolates abnormal communication links and independent power rails, and keeps the remaining functional domains running, thus forming the platform operation status.

2. The domestically developed high-performance computing platform based on a dual-domain architecture as described in claim 1, characterized in that: The acquisition of the power supply status of the independent power rails corresponding to the high-performance domain and the high-reliability domain specifically includes: Connect the three power rails corresponding to the high-performance domain and the one power rail corresponding to the high-reliability domain to establish an independent power supply relationship between the two domains. The output voltage, output current, and overcurrent protection status of each power rail in the dual-domain independent power supply relationship are collected to obtain the power rail power supply data; Verify the power supply status of the power rail corresponding to the high reliability domain according to the power rail power supply data, and start the high reliability domain controller after the power rail corresponding to the high reliability domain is powered normally, and generate the high reliability domain start record. According to the high-reliability domain boot record, the high-reliability domain controller reads the boot images pre-stored in the three Q-FLASH chips respectively, records the Q-FLASH chips to which each boot image belongs, and obtains the boot image read record.

3. The domestically developed high-performance computing platform based on a dual-domain architecture as described in claim 2, characterized in that: The process of obtaining the dual-domain startup state specifically includes: Extract the boot images corresponding to the three Q-FLASH chips from the boot image read record, perform consistency checks on the three boot images, and take at least two boot images with consistent content as valid boot images, and generate a boot image voting record; Load the valid boot image from the boot image voting record into the S5000C processor, start the S5000C processor and establish the operating environment for the GPU / NPU module, storage resources, communication links and expansion board connection links, and obtain the dual-domain boot state.

4. The domestically developed high-performance computing platform based on a dual-domain architecture as described in claim 3, characterized in that: The response dual-domain startup state receives payload data, specifically including: In response to the dual-domain startup state, the payload data is received through the payload interface and the 10 Gigabit network interface. The data length, storage location and transmission source of the payload data are recorded according to the receiving channel, and a payload data receiving record is generated. Using the storage location and transmission source in the payload data reception record as an index, verify the availability status of the S5000C processor, GPU / NPU module, storage resources, high-speed interconnect links and communication links, and generate a computing resource status record; By using the computing resource status record, the control operations corresponding to the load data are configured to the S5000C processor, the parallel computing corresponding to the load data is configured to the available GPU / NPU module, and the load data distribution object and the computing output storage location are recorded accordingly to generate the task resource corresponding record; The execution order of control operations and parallel computations, the load data distribution path, the computation output feedback path, and the task status feedback path are configured according to the corresponding records of task resources to obtain the computation task scheduling relationship.

5. The domestically developed high-performance computing platform based on a dual-domain architecture as described in claim 4, characterized in that: The obtained load calculation state specifically includes: According to the computing task scheduling relationship, load data is retrieved from the storage location recorded in the load data receiving record, control operations are sent to the S5000C processor, and parallel computing is sent to the GPU / NPU module specified in the corresponding task resource record to generate a load task execution record. Based on the execution record of the payload task, the S5000C processor coordinates storage resources and high-speed interconnect links to drive the GPU / NPU module to perform at least one of AI inference, image processing, model calculation and data fusion, and records the execution object, running stage and calculation output location of the calculation task to generate payload data calculation record; By utilizing the payload data to record the corresponding GPU / NPU module's operating status, computation output update status, and high-speed interconnect link communication status, the payload computation status can be obtained by distinguishing between normal execution, execution interruption, and execution completion computation tasks.

6. The domestically developed high-performance computing platform based on a dual-domain architecture as described in claim 5, characterized in that: The formation of the interface transmission state specifically includes: Retrieve the calculation output from the load calculation status, match the calculation output according to the protocol type, transmission direction and synchronization method corresponding to the target load interface, and generate an interface adaptation record; Using the interface adaptation record, select the expansion module that supports the target payload interface, connect the GTX high-speed serial channel and GPIO channel to the expansion module, configure the data channel and synchronization signal channel, and generate the expansion channel configuration record; Set the FPGA's protocol conversion path according to the extended channel configuration record, convert the calculation output into the data format corresponding to the target payload interface, configure the synchronization control information, and generate protocol conversion data; The protocol conversion data is sent through the corresponding extended channel configured in the extended channel configuration record. The transmitted data, currently transmitted data, untransmitted data, and extended channel operation status are recorded according to the transmission order of the calculated output, forming the interface transmission status.

7. The domestically developed high-performance computing platform based on a dual-domain architecture as described in claim 6, characterized in that: The continuous monitoring of the load calculation status and interface transmission status specifically includes: The GPU / NPU module operating status, computing output update status, and high-speed interconnect link communication status in the load computing status are continuously correlated with the extended channel operating status and protocol conversion status in the interface transmission status, and the power status and temperature status of the high-performance domain are collected synchronously to generate dual-domain operation monitoring records. Taking the state changes of adjacent monitoring times in the dual-domain operation monitoring record as the object, distinguish between calculation anomalies, communication anomalies, power supply anomalies, temperature anomalies and expansion interface anomalies, and generate dual-domain anomaly classification records according to the functional domain and connection link where the anomaly occurred. Extract computational anomalies, communication anomalies, power supply anomalies, temperature anomalies, and expansion interface anomalies from the dual-domain anomaly classification records. Assign computational and communication anomalies to the reset control link, power supply anomalies to the power control link, temperature anomalies to the status monitoring link, and expansion interface anomalies to the expansion board connection link. Record the handling link corresponding to each anomaly type and generate a fault handling path record. Record the operation process corresponding to the abnormal location according to the fault handling path, and generate an isolation recovery record by performing at least one of the following through the high reliability domain controller: status recording, fault isolation, reset recovery, power control and management information reporting.

8. The domestically developed high-performance computing platform based on a dual-domain architecture as described in claim 7, characterized in that: The obtained dual-domain recovery state specifically includes: The operating status, power status, temperature status, and communication status of the high-performance domain are re-acquired according to the isolation recovery record, while the continuous operation of the high-reliability domain controller and management link is recorded to generate a recovery status re-acquisition record. The recovery status is verified by re-collecting records of the recovery status to check the recovery status of the corresponding operating status at the abnormal location, and the operation continuity of the high reliability domain controller during fault isolation and reset recovery is verified to generate dual-domain recovery verification records; By utilizing dual-domain recovery verification records, the anomaly type, anomaly location, handling method, and recovery status are transmitted to the management side via a high-reliability domain CAN bus, generating a recovery status reporting record. The recovery status reporting records and dual-domain recovery verification records are collected, and the dual-domain operational availability is marked according to the recovery status of the high-performance domain and the continuous operation status of the high-reliability domain to obtain the dual-domain recovery status.

9. The domestically developed high-performance computing platform based on a dual-domain architecture as described in claim 8, characterized in that: The method of verifying the communication and power supply status of the high-performance domain and the high-reliability domain using dual-domain recovery state specifically includes: Extract the service communication recovery status of the high-performance domain and the management communication continuity status of the high-reliability domain from the dual-domain recovery status, and generate a dual-domain communication recovery record corresponding to the high-performance domain CAN bus and the high-reliability domain CAN bus. Based on the dual-domain communication recovery record, the service instructions, load control information and high-performance domain status information are transmitted via the high-performance domain CAN bus, while the health status, fault status, recovery status and management instructions are transmitted via the high-reliability domain CAN bus, generating a dual-domain communication split record. By utilizing dual-domain communication splitting records to verify the physical link and transmission content of the high-performance domain CAN bus and the high-reliability domain CAN bus, the service-side communication and management-side communication are kept isolated from each other, thus obtaining the dual-domain communication operation status.

10. The domestically developed high-performance computing platform based on a dual-domain architecture as described in claim 9, characterized in that: The aforementioned platform operating status specifically includes: Power management information is transmitted using dual-domain communication operation status. The output voltage, output current and overcurrent protection status of the three independent power rails in the high-performance domain and the one independent power rail in the high-reliability domain are collected respectively to generate a dual-domain power supply operation record. The power supply relationship between each independent power rail and the corresponding functional domain is verified by using the dual-domain power operation record. The independent power rail with abnormal output is mapped to the GPU / NPU module, high-speed interconnect circuit and high-reliability domain controller that it supplies, and a power rail handling record is generated. According to the power rail handling record, isolate the independent power rail with abnormal output, keep the other independent power rails, high-performance domain CAN bus and high-reliability domain CAN bus running, and record the operating availability status of the high-performance domain and high-reliability domain to form the platform operating status.

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