A heterogeneous collaborative computing and data reliable transmission system and method

Abstract

The application provides a heterogeneous cooperative computing and data reliable transmission system and method, which comprises the following steps: a field programmable gate array module receives a UDP market data packet, performs hardware decoding and basic strategy signal calculation tasks, and generates decoded market data; a central processing unit module receives the decoded market data through a shared memory space, performs complex strategy calculation tasks, and generates transaction decision data; a graphics processing unit module obtains the transaction decision data through a unified memory access mechanism, and performs strategy backtesting and data analysis tasks; and a task priority scheduling module divides priorities according to delay requirements and dynamically allocates tasks. The field programmable gate array module further detects the continuity of a sequence number in the UDP data packet through hardware logic, sends a retransmission request in a preset time window in a gap, and the sending end retransmits the lost packet in the next period. The retransmission request in the gap is stopped after a preset effective duration. The application realizes the cooperative optimization of nanosecond delay and microsecond reliable retransmission.

Description

Technical Field

[0001] This application relates to the fields of financial data processing and high-performance computing technology, and in particular to a heterogeneous collaborative computing and reliable data transmission system and method. Background Technology

[0002] In the field of high-frequency financial data processing and trade execution, a single type of computing hardware can no longer simultaneously meet the three requirements of nanosecond-level deterministic latency, flexible deployment of complex strategy logic, and batch analysis of massive historical data. Pure software solutions based on general-purpose central processing units (CPUs) offer high flexibility, but network protocol stack overhead and operating system scheduling jitter make it difficult to stably control processing latency below microseconds. Pure hardware solutions based on field-programmable gate arrays (FPGAs) can achieve nanosecond-level deterministic latency, but their long development cycles and high costs for modifying strategy logic make them unsuitable for frequent strategy logic updates. Graphics processors (GPUs) have throughput advantages in batch data parallel analysis, but their high invocation latency prevents them from directly participating in the nanosecond-level processing chain of real-time data processing. Existing heterogeneous computing solutions mostly adopt simple collaboration between two hardware components, lacking a system-level architecture that unifies the scheduling of the three computing resources and enables efficient data flow.

[0003] At the data transmission level, real-time data transmission scenarios typically employ the User Datagram Protocol (UDP) to circumvent the congestion control delays of the Transmission Control Protocol (TCP). However, UDP does not guarantee reliable delivery, and network link jitter can lead to packet loss. Existing reliable transmission schemes either rely on the TCP's retransmission mechanism, whose retransmission timeout period is far higher than the microsecond latency limit; or they rely on application-layer customized retransmission strategies, but their detection and response are implemented in software on the central processing unit, resulting in significant latency fluctuations from packet loss identification to retransmission request issuance, making it difficult to meet the deterministic low-latency requirements of real-time data processing scenarios. Summary of the Invention

[0004] To address the aforementioned issues, this application provides a heterogeneous collaborative computing and reliable data transmission system and method. By constructing a three-level collaborative architecture consisting of a field-programmable gate array (FPGA) module, a central processing unit (CPU) module, and a graphics processing unit (GPU) module, and implementing a lightweight reliable retransmission protocol in hardware logic at the receiving end of the FPGA module, this system satisfies nanosecond-level deterministic processing latency while also considering the flexible deployment capability of complex strategy logic and the throughput of batch analysis of massive amounts of data. Furthermore, it achieves microsecond-level response and reliable data delivery at the user datagram protocol transmission layer.

[0005] The first aspect of this application proposes a heterogeneous collaborative computing and reliable data transmission system, comprising: Field-programmable gate array (FPGA) module, central processing unit (CPU) module, graphics processing unit (GPU) module, and task priority scheduling module; The field-programmable gate array (FPGA) module is used to receive UDP market data packets from the network via the UDP protocol, perform hardware decoding on the UDP market data packets to generate decoded market data, and perform basic strategy signal calculation tasks on the decoded market data; the FPGA module implements a reliable retransmission protocol through hardware logic at the corresponding receiving end. The central processing unit module is connected to the field-programmable gate array module and is used to receive the decoded market data through a shared memory space, and to perform complex strategy calculation tasks based on the decoded market data to generate trading decision data. The graphics processing unit module is connected to the central processing unit module and is used to acquire transaction decision data through a unified memory access mechanism in order to execute strategy backtesting and data analysis tasks corresponding to the transaction decision data. The task priority scheduling module is used to divide the basic policy signal calculation task, the complex policy calculation task, and the policy backtesting and data analysis task into multiple priorities according to the task delay requirements, and dynamically allocate task execution among the field programmable gate array module, the central processing unit module, and the graphics processing unit module according to the priorities. The field-programmable gate array module detects the continuity of the cyclic sequence number carried in the UDP market data packet through the hardware logic; in response to the detection of the sequence number gap, the field-programmable gate array module generates a retransmission request message within a preset time window and sends it to the data sending end corresponding to the UDP market data packet. In the next transmission cycle after receiving the retransmission request message, the data sending end shall prioritize retransmitting the lost market data packet corresponding to the retransmission request message. The field-programmable gate array module is also used to record the detection time when the sequence number gap is detected, and to stop initiating retransmission request messages for the sequence number gap when the difference between the current time and the detection time exceeds a preset data validity period.

[0006] A heterogeneous collaborative computing and reliable data transmission system according to the first aspect of the embodiments of this application has at least the following beneficial effects: By constructing a three-tiered heterogeneous collaborative architecture consisting of a field-programmable gate array (FPGA) module, a central processing unit (CPU) module, and a graphics processing unit (GPU) module, nanosecond-level deterministic latency, flexible deployment of complex logic, and high throughput of batch data are unified within a single system. The three computing modules exchange data through a shared memory space and a unified memory access mechanism. The FPGA module achieves zero-copy data writing via direct memory access, eliminating the copy overhead of data transfer between modules and compressing cross-module data transfer latency to below microseconds. The task priority scheduling module allocates latency-sensitive tasks to the appropriate hardware processing units based on priority allocation, ensuring the deterministic completion of real-time tasks while also accommodating high-throughput processing of batch tasks.

[0007] In one possible implementation, the shared memory space is provided with a lock-free circular buffer, the number of slots in the lock-free circular buffer is a power of 2, and the read and write operations of the lock-free circular buffer are based on compare-and-swap atomic operations to achieve concurrent access control; the field-programmable gate array module writes the decoded market data into the lock-free circular buffer through direct memory access, and the central processing unit module reads the decoded market data from the lock-free circular buffer.

[0008] In one possible implementation, the multiple priorities include the highest priority, the second highest priority, the third highest priority, and the lowest priority; the task priority scheduling module assigns the real-time message sending task for sending transaction instructions to the highest priority, the basic strategy signal calculation task to the second highest priority, the complex strategy calculation task to the third priority, and the strategy backtesting and data analysis task to the lowest priority.

[0009] In one possible implementation, the first processing delay corresponding to the highest priority is less than 1 microsecond, the second processing delay corresponding to the second highest priority is less than 10 microseconds, the third processing delay corresponding to the third priority is less than 100 microseconds, and the fourth processing delay corresponding to the lowest priority is less than 1 second.

[0010] In one possible implementation, the retransmission request message is encapsulated in a UDP datagram for transmission; the retransmission request message carries the range of missing sequences corresponding to the sequence number gap; the time window is 50 microseconds; and the data validity period is 500 microseconds.

[0011] In one possible implementation, the task priority scheduling module is further configured to collect in real time the first resource utilization rate corresponding to the field-programmable gate array module and the second resource utilization rate corresponding to the central processing unit module; when the first resource utilization rate exceeds a first preset threshold, the first transferable part of the basic policy signal calculation task is scheduled to be executed by the central processing unit module; when the second resource utilization rate exceeds a second preset threshold, the second transferable part of the complex policy calculation task is scheduled to be executed by the graphics processing unit module.

[0012] The second aspect of this application proposes a method for heterogeneous collaborative computing and reliable data transmission, including the following steps: The field-programmable gate array module receives UDP market data packets from the network via the UDP protocol, performs hardware decoding on the UDP market data packets to generate decoded market data, and performs basic strategy signal calculation tasks on the decoded market data. The field-programmable gate array module writes the decoded market data into the shared memory space via direct memory access. The central processing unit module reads the decoded market data from the shared memory space, performs complex strategy calculation tasks based on the decoded market data, and generates trading decision data. The graphics processing unit module acquires the transaction decision data through a unified memory access mechanism and executes the strategy backtesting and data analysis tasks corresponding to the transaction decision data. The task priority scheduling module divides the basic policy signal calculation task, the complex policy calculation task, and the policy backtesting and data analysis task into multiple priorities according to the task delay requirements, and dynamically allocates task execution among the field programmable gate array module, the central processing unit module, and the graphics processing unit module according to the priorities. The field-programmable gate array (FPGA) module detects the continuity of the cyclic sequence number carried in the UDP market data packet through hardware logic; in response to the detection of a sequence number gap, the FPGA module records the detection time, generates a retransmission request message within a preset time window, and sends it to the data sending end corresponding to the UDP market data packet; in the next transmission cycle after receiving the retransmission request message, the data sending end prioritizes retransmitting the lost market data packet corresponding to the retransmission request message. When the difference between the current time and the detection time exceeds the preset data validity period, the field-programmable gate array module stops initiating retransmission request messages for the sequence number gap.

[0013] In one possible implementation, the method further includes: determining the expected sequence number corresponding to the field-programmable gate array module; when the sequence number of the received UDP market data packet is greater than the expected sequence number, determining that there is a sequence number gap, and recording the sequence number range between the expected sequence number and the data packet sequence number as a missing sequence range; the retransmission request message carries the missing sequence range.

[0014] In one possible implementation, the method further includes: real-time acquisition of a first resource utilization rate corresponding to the field-programmable gate array module and a second resource utilization rate corresponding to the central processing unit module; when the first resource utilization rate exceeds a first preset threshold, scheduling a first transferable portion of the basic policy signal calculation task to the central processing unit module for execution; when the second resource utilization rate exceeds a second preset threshold, scheduling a second transferable portion of the complex policy calculation task to the graphics processing unit module for execution.

[0015] The heterogeneous collaborative computing and reliable data transmission method according to the second aspect of the embodiments of this application has at least the following beneficial effects: By using a field-programmable gate array (FPGA) module to perform real-time data decoding, basic calculations, and sequence number continuity detection at the hardware level, the end-to-end processing latency of the system is controlled at the nanosecond level. At the same time, the task priority scheduling module dynamically allocates tasks according to their latency requirements, improving the system's resource utilization and processing efficiency. By implementing a lightweight retransmission protocol at the hardware level, the response time for packet loss retransmission is shortened, and the data validity period is used to avoid expired retransmissions, ensuring the reliability of data transmission.

[0016] A third aspect of this application provides a readable medium including executable instructions, which, when executed by a processor of an electronic device, cause the electronic device to perform any of the methods described in the second aspect. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a heterogeneous collaborative computing and reliable data transmission system provided in one embodiment of this application; Figure 2 This is a flowchart illustrating a heterogeneous collaborative computing and reliable data transmission method provided in an embodiment of this application. Detailed Implementation

[0019] The embodiments of this implementation are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this implementation, and should not be construed as limiting this implementation.

[0020] In the description of this embodiment, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this embodiment and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this embodiment.

[0021] In the description of this embodiment, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0022] In the description of this embodiment, unless otherwise explicitly limited, terms such as setting, installing, and connecting should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this embodiment in conjunction with the specific content of the technical solution.

[0023] Please refer to Figure 1 The diagram illustrates a structural schematic of a heterogeneous collaborative computing and reliable data transmission system according to an embodiment of this application. The system includes a field-programmable gate array module 101, a central processing unit module 102, a graphics processing unit module 103, and a task priority scheduling module 104.

[0024] In this embodiment, the Field-Programmable Gate Array (FPGA) module 101, the Central Processing Unit (CPU) module 102, and the Graphics Processing Unit (GPU) module 103 constitute a three-level heterogeneous collaborative computing architecture, complementing each other in terms of computing characteristics. The FPGA module 101 possesses deterministic nanosecond-level processing latency and highly parallel hardware logic execution capabilities, making it suitable for handling latency-sensitive real-time data processing tasks. The CPU module 102 has flexible program control capabilities, making it suitable for executing computationally complex tasks with numerous branches. The GPU module 103 boasts massively parallel computing throughput advantages, making it suitable for handling batch-based data analysis tasks. The task priority scheduling module 104 is responsible for unified task allocation and resource coordination among the three computing units.

[0025] The field-programmable gate array (FPGA) module 101 is used to receive UDP market data packets from the network via the UDP protocol, perform hardware decoding on the UDP market data packets to generate decoded market data, and perform basic strategy signal calculation tasks on the decoded market data; the FPGA module implements a reliable retransmission protocol through hardware logic at the corresponding receiving end.

[0026] The Field-Programmable Gate Array (FPGA) module 101 receives UDP market data packets using the UDP protocol. Hardware decoding refers to the FPGA module 101 using pre-programmed hardware logic circuits to perform field parsing and format conversion on the received raw data packet byte stream in a pipelined manner. The entire decoding process does not require operating system intervention, and the processing latency is on the order of nanoseconds. After decoding, the generated decoded market data consists of structured numerical fields. Based on this, the FPGA module 101 can perform parallel calculations of basic signals such as moving averages and price spread monitoring using hardware logic, forming the output results of the basic strategy signal calculation task.

[0027] The central processing unit module 102 is connected to the field programmable gate array module 101 and is used to receive decoded market data through shared memory space, and perform complex strategy calculation tasks based on the decoded market data to generate trading decision data.

[0028] The complex strategy calculation tasks undertaken by the central processing unit (CPU) module 102 involve logic such as multi-condition branch judgment, dynamic parameter adjustment, or cross-cycle state maintenance. Implementing these tasks on the field-programmable gate array (FPGA) module 101 results in high circuit complexity and significant modification costs. However, implementing them in software on the CPU module 102 offers greater flexibility. After performing calculations based on decoded market data, the CPU module 102 outputs trading decision data representing the calculation conclusions after complete strategy logic processing.

[0029] The shared memory space is equipped with a lock-free circular buffer. The number of slots in the lock-free circular buffer is a power of 2. The read and write operations of the lock-free circular buffer are based on the comparison and swap atomic operation to achieve concurrent access control. The field-programmable gate array module writes the decoded market data into the lock-free circular buffer through direct memory access, and the central processing unit module reads the decoded market data from the lock-free circular buffer.

[0030] The shared memory space serves as the channel for data exchange between the field-programmable gate array (FPGA) module 101 and the central processing unit (CPU) module 102. Direct memory access (DMI) allows the FPGA module 101 to bypass the CPU module 102 and directly write decoded market data into a physical memory area accessible to both modules, eliminating the need for data copying and thus reducing inter-module data transfer latency to below microseconds.

[0031] A lock-free circular buffer is a circular queue structure based on an array. The number of slots is set to a power of 2 so that the modulo operation of the buffer index can be replaced by a bitwise AND operation, avoiding the extra overhead of the division instruction and improving access efficiency. The compare-and-swap atomic operation is a hardware-level atomic instruction provided by the processor, which can safely complete the concurrent access control of multiple writes without introducing a mutex lock, fundamentally eliminating the latency jitter caused by lock contention.

[0032] The graphics processing unit module 103 is connected to the central processing unit module 102 and is used to acquire transaction decision data through a unified memory access mechanism in order to execute strategy backtesting and data analysis tasks corresponding to the transaction decision data.

[0033] The unified memory access mechanism enables the central processing unit module 102 and the graphics processing unit module 103 to share the same physical address space. The graphics processing unit module 103 can directly access transaction decision data without triggering additional data copying, thereby controlling the data transfer latency between modules to the microsecond level.

[0034] The strategy backtesting and data analysis tasks performed by the graphics processor module 103 have a high degree of data parallelism. For example, when performing statistical calculations on a large number of historical data samples at the same time, the massively parallel computing unit of the graphics processor module 103 can increase the throughput of such tasks to several to tens of times that of the serial processing mode of the central processing unit module 102.

[0035] The task priority scheduling module 104 is used to divide the basic policy signal calculation task, complex policy calculation task, and policy backtesting and data analysis task into multiple priorities according to the task delay requirements, and dynamically allocate task execution among the field programmable gate array module, central processing unit module, and graphics processing unit module according to the priority.

[0036] The task priority scheduling module 104 enables tasks with different latency requirements to be routed to the hardware module that best matches their computing characteristics for execution. At the same time, it dynamically adjusts the task allocation strategy when the load of each hardware module changes, so as to avoid the overall processing link latency from increasing due to the overload of a single hardware module.

[0037] Multiple priorities include the highest priority, the second highest priority, the third highest priority, and the lowest priority. The task priority scheduling module assigns the real-time message sending task used to send trading instructions to the highest priority, the basic strategy signal calculation task to the second highest priority, the complex strategy calculation task to the third highest priority, and the strategy backtesting and data analysis task to the lowest priority.

[0038] The real-time message transmission task is assigned the highest priority because messages must be sent immediately upon generation. Any queuing or waiting will directly increase the end-to-end latency from decision-making to execution. Therefore, this task has the highest preemption right in the scheduling queue. The real-time message transmission task refers to the task of encapsulating transaction decision data into transaction instruction messages according to the target communication protocol format and sending them outward through the network interface. Once this task is generated, it must be completed within a very short time; otherwise, it will directly increase the latency of the instruction reaching the transaction execution agency, affecting strategy execution. Since any software scheduling or queuing in the transmission path will introduce microsecond-level latency jitter, this task is assigned the highest priority and is directly completed by the hardware logic of the field-programmable gate array module 101.

[0039] The processing results of basic policy signal calculation tasks are prerequisites for subsequent complex calculations, and their latency directly affects the response speed of the entire computation chain; therefore, they are assigned to the second-highest priority. Complex policy calculation tasks have more complete logic and can proceed sequentially after the second-highest priority tasks are completed; therefore, they are assigned to the third priority. Policy backtesting and data analysis tasks perform batch processing based on historical data or completed decision data, have the lowest real-time requirements, and are assigned to the lowest priority. They are executed using remaining computing resources after the processing resources of the first three types of tasks are satisfied.

[0040] The highest priority corresponds to a first processing delay of less than 1 microsecond, the second highest priority corresponds to a second processing delay of less than 10 microseconds, the third priority corresponds to a third processing delay of less than 100 microseconds, and the lowest priority corresponds to a fourth processing delay of less than 1 second.

[0041] The latency requirements for each priority task specify the maximum allowable time from when a task enters the scheduling queue to when it is completed. The latency limit for real-time message transmission is 1 microsecond. This task needs to be completed directly at the hardware logic level of the field-programmable gate array (FPGA) module 101; the software path cannot guarantee this due to operating system scheduling jitter. The latency limit for hardware decoding and basic signal calculation is 10 microseconds, executed by the FPGA module 101. The latency limit for complex policy logic operations is 100 microseconds, allocated to the central processing unit (CPU) module 102 for processing. The latency limit for policy backtesting and data analysis tasks is 1 second, handled by the graphics processing unit (GPU) module 103 for parallel computation in batch processing.

[0042] The task priority scheduling module is also used to collect the first resource utilization rate corresponding to the field programmable gate array module and the second resource utilization rate corresponding to the central processing unit module in real time; when the first resource utilization rate exceeds the first preset threshold, the first transferable part of the basic strategy signal calculation task is scheduled to be executed by the central processing unit module; when the second resource utilization rate exceeds the second preset threshold, the second transferable part of the complex strategy calculation task is scheduled to be executed by the graphics processing unit module.

[0043] Real-time acquisition of resource utilization enables the task priority scheduling module 104 to perceive the actual load status of each hardware module, thereby introducing dynamic migration capability based on static priority allocation. The first migrateable part refers to the calculation sub-items in the basic strategy signal calculation task that have relatively high latency tolerance and can be equivalently implemented in software on the central processing unit module 102, such as the calculation of mean-type indicators with long statistical windows.

[0044] When the resource utilization of the field-programmable gate array module 101 exceeds the first preset threshold, the first transferable part is transferred to the central processing unit module 102 for execution, which can release resources for the field-programmable gate array module 101 to ensure that the latency index of the highest priority task is not affected.

[0045] Similarly, the second transferable part refers to the computational sub-item in the complex strategy computation task that has strong data parallelism and can be efficiently executed on the graphics processor module 103. When the resource utilization of the central processing unit module 102 exceeds the second preset threshold, the second transferable part is transferred to the graphics processor module 103 for execution in order to maintain the overall processing time of the complex strategy computation task.

[0046] Preferably, in this embodiment, both the first preset threshold and the second preset threshold can be set to 80%. When the resource utilization rate of the field-programmable gate array module exceeds 80%, it indicates that it is close to full load. At this time, transferring some transferable tasks to the central processing unit module can avoid the increase in latency of the highest priority tasks due to overload of the field-programmable gate array module.

[0047] The field-programmable gate array module 101 detects the continuity of the cyclic sequence number carried in the UDP market data packet through hardware logic; in response to the detection of the sequence number gap, the field-programmable gate array module generates a retransmission request message within a preset time window and sends it to the data sender corresponding to the UDP market data packet.

[0048] The cyclic sequence number is an incrementing number field appended to the header of each UDP market data packet. The sender assigns a consecutive sequence number to each packet as it is sent. The field-programmable gate array module 101 maintains the currently expected sequence number at the receiving end, and compares the actual sequence number carried by each received data packet with the expected sequence number.

[0049] If the actual sequence number is greater than the expected sequence number, it indicates that there are undelivered data packets between the expected and actual sequence numbers, i.e., a sequence number gap has occurred. Since the above comparison logic is implemented in hardware circuitry, its processing time from receiving the data packet to completing the gap judgment is on the order of nanoseconds. Compared with the detection scheme implemented in software on the central processing unit module 102, it has lower latency, is not affected by operating system scheduling, and has stronger determinism.

[0050] The retransmission request message is encapsulated in a UDP datagram for transmission; the retransmission request message carries the range of missing sequences corresponding to the sequence number gaps; the time window is 50 microseconds.

[0051] Encapsulating retransmission request messages in UDP datagrams ensures consistency with the transmission protocol of the original market data, avoiding the overhead of connection establishment and congestion control in the Transmission Control Protocol (TCP). The missing sequence range refers to the consecutive numbered interval between the sequence number expected by the receiver and the sequence number actually received. Upon receiving this information, the sender can accurately locate the range of data packets requiring retransmission without needing to confirm each and every data packet individually.

[0052] The time window is set to 50 microseconds, which means that from the detection of the sequence number gap, the field programmable gate array module 101 must complete the generation and transmission of the retransmission request message within 50 microseconds. This time constraint ensures that the retransmission request can reach the sending end in a very short time after the data packet is lost, so that the response delay of the entire retransmission link is maintained at the microsecond level.

[0053] In the next transmission cycle after receiving the retransmission request message, the data sender prioritizes retransmitting the lost market data packets corresponding to the retransmission request message.

[0054] Under normal circumstances, the data sender sequentially transmits new data packets according to a fixed or adaptive transmission cycle. Upon receiving a retransmission request message, at the beginning of the next transmission cycle, the data sender prioritizes inserting the data packets corresponding to the missing sequence range into the head of the transmission queue for transmission, so that the lost market data packets can reach the receiver as quickly as possible, without having to wait for all the new data packets in the normal queue to be transmitted before retransmission.

[0055] The field-programmable gate array module 101 is also used to record the detection time when a sequence number gap is detected. When the difference between the current time and the detection time exceeds a preset data validity period, it stops initiating retransmission request messages for the sequence number gap. The data validity period is 500 microseconds.

[0056] The data carried by UDP market data packets is time-sensitive. Data retransmitted after the validity period expires cannot be used for current processing decisions and will consume network and sending resources. Therefore, this embodiment sets a data validity period, and stops retransmission requests after the expiration to ensure the efficiency of the system processing link.

[0057] The data validity period is set to 500 microseconds. That is, if the lost data packet cannot be obtained through retransmission within 500 microseconds from the detection of the sequence number gap, the data packet is determined to have expired. The field programmable gate array module 101 stops initiating further retransmission requests for the sequence number gap and continues to process the subsequent data packets to ensure the overall smoothness of the processing link.

[0058] like Figure 2 The image shown is a specific embodiment of a heterogeneous collaborative computing and reliable data transmission method according to this application.

[0059] In this embodiment, a heterogeneous collaborative computing and reliable data transmission method includes the following steps: Step 201: The field-programmable gate array module receives UDP market data packets from the network via the UDP protocol, performs hardware decoding on the UDP market data packets to generate decoded market data, and performs basic strategy signal calculation tasks on the decoded market data.

[0060] The Field-Programmable Gate Array (FPGA) module utilizes its hardware parallel processing capabilities to pipeline the parsing and format conversion of received UDP market data packets, generating structured decoded market data. Compared to the software-based decoding process executed on the central processing unit (CPU) module, hardware decoding requires no operating system intervention, resulting in lower processing latency and determinism. The basic strategy signal calculation task is directly based on the numerical fields in the decoded market data and is executed pipelinedly with the hardware decoding process, keeping the combined latency of the two processing stages in the nanosecond range.

[0061] Step 202: The field-programmable gate array module writes the decoded market data into the shared memory space through direct memory access. The central processing unit module reads the decoded market data from the shared memory space, performs complex strategy calculation tasks based on the decoded market data, and generates trading decision data.

[0062] Direct memory access (DMI) allows the FPGA module to write decoded market data directly into a lock-free circular buffer in shared memory without consuming CPU resources. The CPU module then reads the data from this buffer, with no data copying involved in the entire process. After obtaining the decoded market data, the CPU module executes complex strategy calculations involving multi-condition branches or cross-period state maintenance, and outputs the calculation results as trading decision data to the GPU module.

[0063] Step 203: The graphics processor module obtains transaction decision data through a unified memory access mechanism and executes strategy backtesting and data analysis tasks corresponding to the transaction decision data.

[0064] The graphics processing unit (GPU) directly accesses trading decision data through the shared physical memory address space with the central processing unit (CPU), eliminating the need for additional data transfer operations. Strategy backtesting and data analysis tasks typically involve repetitive statistical calculations on large datasets; the GPU's massively parallel computing units can efficiently complete these tasks in batch processing, achieving significantly higher throughput than the CPU's serial processing.

[0065] Step 204: The task priority scheduling module divides the basic policy signal calculation task, complex policy calculation task, and policy backtesting and data analysis task into multiple priorities according to the task delay requirements, and dynamically allocates task execution among the field programmable gate array module, central processing unit module, and graphics processing unit module according to the priority.

[0066] The task priority scheduling module allocates tasks based on their sensitivity to processing latency. Real-time message sending tasks are assigned the highest priority (with a processing latency of less than 1 microsecond); basic policy signal calculation tasks are assigned the second highest priority (with a processing latency of less than 10 microseconds); complex policy calculation tasks are assigned the third highest priority (with a processing latency of less than 100 microseconds); and policy backtesting and data analysis tasks are assigned the lowest priority (with a processing latency of less than 1 second). This priority allocation ensures that latency-sensitive tasks always receive priority access to computing resources, while batch analysis tasks are executed using remaining computing power after the resource requirements of latency-sensitive tasks have been met.

[0067] The system collects the first resource utilization rate of the field-programmable gate array module and the second resource utilization rate of the central processing unit module in real time. When the first resource utilization rate exceeds the first preset threshold, the first transferable part of the basic strategy signal calculation task is scheduled to be executed by the central processing unit module. When the second resource utilization rate exceeds the second preset threshold, the second transferable part of the complex strategy calculation task is scheduled to be executed by the graphics processing unit module.

[0068] Building upon static priority allocation, the task priority scheduling module further introduces a dynamic migration mechanism based on real-time load. When the first resource utilization of the field-programmable gate array (FPGA) module exceeds a first preset threshold, the first migrated portion of the basic policy signal calculation task with relatively high latency tolerance is transferred to the central processing unit (CPU) module for execution, thereby freeing up resources for the FPGA module to ensure the latency performance of the highest priority task.

[0069] When the second resource utilization rate of the central processing unit module exceeds the second preset threshold, the second transferable portion of the complex strategy calculation task with strong data parallelism is transferred to the graphics processing unit module for execution, maintaining the overall processing timeliness of the complex strategy calculation task. Preferably, in this embodiment, both the first preset threshold and the second preset threshold can be set to 80%.

[0070] Step 205: The field-programmable gate array (FPGA) module detects the continuity of the cyclic sequence number carried in the UDP market data packet through hardware logic; in response to the detection of the sequence number gap, the FPGA module records the detection time, generates a retransmission request message within a preset time window, and sends it to the data sender corresponding to the UDP market data packet; in the next transmission cycle after receiving the retransmission request message, the data sender prioritizes retransmitting the lost market data packet corresponding to the retransmission request message.

[0071] The field-programmable gate array (FPGA) module maintains the desired sequence number in hardware logic at the receiving end and performs a continuity comparison for each arriving data packet in real time. Because this detection logic is implemented in hardware circuitry, the processing time from the arrival of the data packet to the completion of the gap judgment is on the order of nanoseconds, and its determinism is superior to software implementation schemes.

[0072] Upon detecting a gap, the field-programmable gate array (FPGA) module immediately records the detection time as the starting point for determining the validity period of subsequent data, and generates and sends a retransmission request message within a 50-microsecond time window. After receiving the retransmission request message, the data transmitter prioritizes the retransmission task in the next transmission cycle, inserting the lost data packet at the head of the transmission queue before sending it, without waiting for new data packets in the normal queue to be sent. This ensures that the retransmitted lost market data packets reach the receiver via the shortest path.

[0073] Determine the expected sequence number corresponding to the field-programmable gate array module; when the sequence number of the received UDP market data packet is greater than the expected sequence number, it is determined that there is a sequence number gap, and the sequence number range between the expected sequence number and the data packet sequence number is recorded as the missing sequence range; the missing sequence range is carried in the retransmission request message.

[0074] The expected sequence number is dynamically maintained by the field-programmable gate array (FPGA) module at the receiving end. Its initial value is the sequence number of the first arriving UDP market data packet, and it is updated to the next expected number after each successfully received data packet. When the actual sequence number of a UDP market data packet is greater than the current expected sequence number, the interval between the two is the missing sequence range. This missing sequence range is carried in a retransmission request message and sent to the data sender, enabling the data sender to accurately locate the set of data packets that need to be retransmitted, avoiding unnecessary retransmissions of non-lost market data packets.

[0075] Step 206: When the difference between the current time and the detection time exceeds the preset data validity period, the field programmable gate array module stops initiating retransmission request messages for the sequence number gap.

[0076] The data validity period is set to 500 microseconds. If, after detecting a sequence number gap, the difference between the current time and the detection time exceeds 500 microseconds, it means that even if the lost market data packet is retransmitted, the data it carries is no longer of processing value in terms of timeliness. Continuing to initiate retransmission requests will only incur additional network and computational overhead. Therefore, after determining that the data validity period has expired, the field-programmable gate array (FPGA) module marks the corresponding sequence number gap as expired and stops further retransmission requests. It then continues to process subsequent arriving UDP market data packets, ensuring that the overall processing link is not blocked due to waiting for the retransmission of expired data.

[0077] This application also proposes a readable medium storing executable instructions. When these instructions are executed by a processor of an electronic device, the electronic device can perform a heterogeneous collaborative computing and reliable data transmission method provided in any embodiment of this application, and specifically execute methods such as... Figure 2 The method shown.

[0078] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this implementation. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0079] Although embodiments of this implementation have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this implementation, the scope of which is defined by the claims and their equivalents.

Claims

1. A heterogeneous collaborative computing and reliable data transmission system, characterized in that, include: Field-programmable gate array (FPGA) module, central processing unit (CPU) module, graphics processing unit (GPU) module, and task priority scheduling module; The field-programmable gate array (FPGA) module is used to receive UDP market data packets from the network via the UDP protocol, perform hardware decoding on the UDP market data packets to generate decoded market data, and perform basic strategy signal calculation tasks on the decoded market data; the FPGA module implements a reliable retransmission protocol through hardware logic at the corresponding receiving end. The central processing unit module is connected to the field-programmable gate array module and is used to receive the decoded market data through a shared memory space, and to perform complex strategy calculation tasks based on the decoded market data to generate trading decision data. The graphics processing unit module is connected to the central processing unit module and is used to acquire transaction decision data through a unified memory access mechanism in order to execute strategy backtesting and data analysis tasks corresponding to the transaction decision data. The task priority scheduling module is used to divide the basic policy signal calculation task, the complex policy calculation task, and the policy backtesting and data analysis task into multiple priorities according to the task delay requirements, and dynamically allocate task execution among the field programmable gate array module, the central processing unit module, and the graphics processing unit module according to the priorities. The field-programmable gate array module detects the continuity of the cyclic sequence number carried in the UDP market data packet through the hardware logic. In response to the detection of a sequence number gap, the field-programmable gate array module generates a retransmission request message within a preset time window and sends it to the data sending end corresponding to the UDP market data packet; In the next transmission cycle after receiving the retransmission request message, the data sending end shall prioritize retransmitting the lost market data packet corresponding to the retransmission request message. The field-programmable gate array module is also used to record the detection time when the sequence number gap is detected, and to stop initiating retransmission request messages for the sequence number gap when the difference between the current time and the detection time exceeds a preset data validity period.

2. The system according to claim 1, characterized in that, The shared memory space is equipped with a lock-free circular buffer. The number of slots in the lock-free circular buffer is a power of 2. The read and write operations of the lock-free circular buffer are based on compare-and-swap atomic operations to achieve concurrent access control. The field-programmable gate array module writes the decoded market data into the lock-free circular buffer through direct memory access, and the central processing unit module reads the decoded market data from the lock-free circular buffer.

3. The system according to claim 1, characterized in that, The multiple priorities include the highest priority, the second highest priority, the third highest priority, and the lowest priority; the task priority scheduling module assigns the real-time message sending task for sending transaction instructions to the highest priority, the basic strategy signal calculation task to the second highest priority, the complex strategy calculation task to the third priority, and the strategy backtesting and data analysis task to the lowest priority.

4. The system according to claim 3, characterized in that, The highest priority corresponds to a first processing delay of less than 1 microsecond, the second highest priority corresponds to a second processing delay of less than 10 microseconds, the third priority corresponds to a third processing delay of less than 100 microseconds, and the lowest priority corresponds to a fourth processing delay of less than 1 second.

5. The system according to claim 1, characterized in that, The retransmission request message is encapsulated in a UDP datagram for transmission; the retransmission request message carries the range of missing sequences corresponding to the sequence number gap; the time window is 50 microseconds; the data validity period is 500 microseconds.

6. The system according to claim 1, characterized in that, The task priority scheduling module is also used to collect the first resource utilization rate corresponding to the field programmable gate array module and the second resource utilization rate corresponding to the central processing unit module in real time; when the first resource utilization rate exceeds the first preset threshold, the first transferable part of the basic strategy signal calculation task is scheduled to be executed by the central processing unit module; when the second resource utilization rate exceeds the second preset threshold, the second transferable part of the complex strategy calculation task is scheduled to be executed by the graphics processing unit module.

7. A method for heterogeneous collaborative computing and reliable data transmission, characterized in that, The method is applied to the system according to any one of claims 1-6, and the method includes: The field-programmable gate array module receives UDP market data packets from the network via the UDP protocol, performs hardware decoding on the UDP market data packets to generate decoded market data, and performs basic strategy signal calculation tasks on the decoded market data. The field-programmable gate array module writes the decoded market data into the shared memory space via direct memory access. The central processing unit module reads the decoded market data from the shared memory space, performs complex strategy calculation tasks based on the decoded market data, and generates trading decision data. The graphics processing unit module acquires the transaction decision data through a unified memory access mechanism and executes the strategy backtesting and data analysis tasks corresponding to the transaction decision data. The task priority scheduling module divides the basic policy signal calculation task, the complex policy calculation task, and the policy backtesting and data analysis task into multiple priorities according to the task delay requirements, and dynamically allocates task execution among the field programmable gate array module, the central processing unit module, and the graphics processing unit module according to the priorities. The field-programmable gate array (FPGA) module detects the continuity of the cyclic sequence number carried in the UDP market data packet through hardware logic; in response to the detection of a sequence number gap, the FPGA module records the detection time, generates a retransmission request message within a preset time window, and sends it to the data sending end corresponding to the UDP market data packet; in the next transmission cycle after receiving the retransmission request message, the data sending end prioritizes retransmitting the lost market data packet corresponding to the retransmission request message. When the difference between the current time and the detection time exceeds the preset data validity period, the field-programmable gate array module stops initiating retransmission request messages for the sequence number gap.

8. The method according to claim 7, characterized in that, Also includes: Determine the desired serial number corresponding to the field-programmable gate array module; When the sequence number of the received UDP market data packet is greater than the expected sequence number, it is determined that there is a sequence number gap, and the sequence number range between the expected sequence number and the data packet sequence number is recorded as the missing sequence range; the retransmission request message carries the missing sequence range.

9. The method according to claim 7, characterized in that, Also includes: Real-time acquisition of the first resource utilization rate corresponding to the field-programmable gate array module and the second resource utilization rate corresponding to the central processing unit module; When the first resource utilization rate exceeds the first preset threshold, the first transferable part of the basic strategy signal calculation task will be scheduled to be executed by the central processing unit module. When the second resource utilization rate exceeds the second preset threshold, the second transferable part of the complex strategy calculation task is scheduled to be executed by the graphics processor module.

10. A computer-readable storage medium storing a computer program, characterized in that, The computer program is used to execute the heterogeneous collaborative computing and reliable data transmission method according to any one of claims 7-9.

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