Memory management method and device, verification platform and storage medium

Abstract

The application provides a memory management method and device, a verification platform and a storage medium, and relates to the field of chip verification. The memory management method is applied to a memory management unit of a verification platform, and the verification platform further comprises a memory. The method comprises the following steps: for any process of each application running on the verification platform, a memory management request of the process is received; a target memory slice corresponding to the process is determined from a preset memory management model; wherein the memory management model is preset with a memory slice corresponding to each process of each application; the memory slice is used to execute each function of memory management through a pre-allocated memory segment; and the memory management request of the process is executed through the target memory slice. The method realizes memory management isolation of different processes of different applications, and improves the reliability and security of memory management in a multi-application scenario.

Description

Technical Field

[0001] This application relates to the field of chip verification, and specifically, provides a memory management method, apparatus, verification platform, and storage medium. Background Technology

[0002] The verification platform can perform system verification on the chip. The functions of the chip being verified include those that interact with memory, such as memory access, memory protection, and address mapping. The verification platform is equipped with an MMU (Memory Management Unit) memory. The chip's software process can send a request to the verification platform to obtain the platform's memory for functional verification.

[0003] As the complexity of integrated circuits increases, it may be necessary to verify the collaboration and interaction between multiple applications working simultaneously. This requires a verification platform that runs multiple applications at the same time, each of which may include multiple processes.

[0004] Currently, when the MMU verifies a chip, different processes of the same application are managed uniformly by the MMU. For example, the MMU allocates and releases memory and maps addresses for each process. However, this approach is not suitable for memory management of multiple applications. Different applications are not isolated, and the memory segments requested by each process overlap and intersect, making effective management difficult. Memory management operations can restrict and affect each other, easily leading to memory management anomalies, such as address mapping errors. Furthermore, the memory segments (or memory spaces) requested by each process may be too fragmented, failing to be effectively made available to other processes after release, thus failing to fully utilize memory resources. Summary of the Invention

[0005] In view of this, this application aims to provide a memory management method, apparatus, verification platform, and storage medium to reduce mutual interference and address mapping conflicts between different applications when performing memory management for multiple application scenarios, thereby improving the reliability and security of memory management.

[0006] In a first aspect, embodiments of this application provide a memory management method applied to a memory management unit of a verification platform, the verification platform further comprising memory; the method comprising: receiving a memory management request from any process of each application running on the verification platform; determining a target memory slice corresponding to the process from a preset memory management model; wherein the memory management model presets a memory slice corresponding to each process of each application; the memory slice is used to perform various memory management functions through pre-allocated memory segments; and executing the memory management request of the process through the target memory slice.

[0007] In this embodiment, each process has a unique corresponding memory slice, and each memory slice is pre-allocated with memory segments. The memory segments used by the process are managed through the memory slice corresponding to the process. Thus, the memory segments used by different processes are pre-allocated and isolated from each other without overlapping. When a process uses memory, it can only use the memory segments pre-allocated by the process's memory slice. This method is easier to manage, effectively reduces the occurrence of mutual interference and address mapping conflicts between processes of different applications, and improves the reliability and security of memory management.

[0008] In one embodiment, before receiving the memory management request of the process, the method further includes: obtaining attribute information of each process of each application; the attribute information includes memory setting parameters and identification information of the process; for each process, creating an initial memory slice corresponding to the identification information of the process; configuring module components with different functions in memory management in the initial memory slice; configuring each module component based on the memory setting parameters of the process to obtain the memory slice corresponding to the process.

[0009] In this embodiment, corresponding memory slices are created using process identification information to distinguish memory slices for different processes. This facilitates accurate selection of the corresponding memory slice for a process, enabling reliable memory management. Furthermore, this application modularizes different memory management functions, breaking them down into independent components. These components work collaboratively, allowing for separate configuration and debugging of each component while implementing all memory management functions, thus reducing configuration, debugging, and maintenance costs.

[0010] In one embodiment, the identification information includes a first identifier and at least one second identifier; the first identifier is used to characterize the application to which the process belongs; the second identifier is the process identifier of the process; the step of creating an initial memory slice corresponding to the identification information of each process includes: creating an initial memory slice corresponding to the process based on the first identifier and the second identifier of the process for each process.

[0011] When multiple applications are running on the verification platform, different applications may have processes with the same identifier. This can lead to incorrect address mapping and mapping conflicts when determining the memory address corresponding to a process. Therefore, in this embodiment, a memory slice is constructed using dual identifiers. This allows for the unique identification of the corresponding memory slice through the process's identifier information, effectively reducing or avoiding anomalies caused by incorrect address mapping.

[0012] In one embodiment, before creating the initial memory slice corresponding to the process based on the first identifier and the second identifier of the process, the method further includes: determining that any memory slice in the memory management model does not simultaneously include the first identifier and the second identifier.

[0013] In this embodiment of the application, before creating a memory slice, a first identifier and a second identifier are used to determine whether a corresponding memory slice already exists, so as to avoid the situation of repeatedly creating memory slices, thereby reducing the repeated allocation of memory and reducing the possible anomalies that may occur in subsequent memory use.

[0014] In one embodiment, the memory management request includes a first target identifier and a second target identifier corresponding to the process; determining the target memory slice corresponding to the process from the preset memory management model includes: if there exists a first identifier of any memory slice that matches the first target identifier, and a second identifier of the memory slice that matches the second target identifier, then the memory slice is determined as the target memory slice.

[0015] In this embodiment of the application, by using a dual-identification method of a first identifier and a second identifier, the occurrence of mismatch between the determined memory slice and the process is effectively reduced, thereby reducing the occurrence of address mapping errors, memory management anomalies, and other situations, which helps to improve the reliability of memory management.

[0016] In one embodiment, the module components with different functions include at least: a memory manager, a page table controller, a bus converter, a page table container, and an address mapping table; the memory manager includes a virtual memory manager and a physical memory manager; the virtual memory manager is used to allocate and reclaim virtual address memory segments used by the process based on virtual addresses; the physical memory manager is used to allocate and reclaim physical address memory segments used by the process based on physical addresses; the page table controller is used to configure corresponding page tables for the process; the page table container is used to create and manage page table entries for the process; the bus converter is used to convert memory management requests of different protocols into unified format requests of the verification platform's memory, so as to execute the process's memory management requests through the unified format requests; the address mapping table is used to store the mapping relationship between virtual addresses and physical addresses of memory through memory units; configuring the module components with different functions in memory management in the initial memory slice includes: configuring the memory manager, the page table controller, the bus converter, the page table container, and the address mapping table for the initial memory slice.

[0017] In this embodiment, a memory manager, page table controller, bus converter, memory unit, page table container, and address mapping table are used to perform various functions related to memory management, including memory management, page table management, bus conversion, and page table entry management. These functions are implemented by separating them into different independent module components, which helps reduce debugging and maintenance costs. The bus converter can convert requests from different protocols into a unified format, which helps reduce the integration difficulty of the memory management model, improves its versatility, and adapts to more scenarios.

[0018] In one embodiment, configuring each module component based on the memory setting parameters of the process includes: obtaining the memory setting parameters of the process, the memory setting parameters including memory requirements and page table requirements; the virtual memory manager within the initial memory slice allocating at least one virtual address memory segment to the initial memory slice according to the memory requirements; the physical memory manager within the initial memory slice obtaining at least one physical address memory segment to the initial memory slice according to the memory requirements; and the page table controller within the initial memory slice configuring page tables according to the page table requirements; wherein the page table controller configures the size, level, bit width, and class of the page tables according to the page table requirements. At least one of the following: the page table controller within the initial memory slice divides the virtual address memory segment and the physical address memory segment according to the page table, obtaining a virtual address memory sub-segment and a physical address memory sub-segment that match each page table; an address mapping relationship is established between each pair of virtual address memory sub-segments and physical address memory sub-segments in the address mapping table of the initial memory slice; the page table container within the initial memory slice establishes page table entry information according to the address mapping relationship; the bus converter within the initial memory slice stores the page table entries into the memory, completing the creation of the memory slice corresponding to the process.

[0019] In this embodiment, the various module components collaborate with each other in the manner described above to create a complete memory slice. Furthermore, during memory slice creation, virtual and physical address memory segments of corresponding sizes can be allocated according to the actual needs of the process, adapting to the diverse memory requirements of different verification scenarios and improving the flexibility and adaptability of memory allocation. Simultaneously, corresponding page tables can be configured according to the actual needs of the process, enabling flexible switching between page table levels and page sizes. Various parameters of the page table can be adjusted according to verification requirements, adapting to the page table management needs of different chip architectures, avoiding the problem of rigid page table management, and adapting to more scenarios.

[0020] In one embodiment, the memory management request includes a target memory to be managed. If the memory management request is a memory allocation request, then executing the memory management request of the process through the target memory slice includes: allocating a target virtual address memory segment matching the target memory to the process through the virtual memory manager of the target memory slice; allocating a target physical address memory segment matching the target memory to the process through the physical memory manager of the target memory slice; establishing a target mapping relationship between the target virtual address memory segment and the target physical address memory segment in the address mapping table of the target memory slice; establishing a target page table entry in the page table container of the target memory slice based on the target mapping relationship; storing the target page table entry into the memory through the bus converter of the target memory slice; generating target memory information corresponding to the target memory, and completing the memory allocation request.

[0021] In one embodiment, the process of allocating a target virtual address memory segment matching the target memory to the process through the virtual memory manager of the target memory slice includes: the virtual memory manager of the target memory slice allocating a target virtual address memory segment matching the target memory to the process through a preset allocation strategy; the preset allocation strategy is one of the following: sparse allocation, customized allocation with a specified starting address, random allocation, and allocation with access permissions.

[0022] In this embodiment, the memory manager supports multiple memory allocation methods, which can adapt to the diverse memory requirements of different verification scenarios and improve the flexibility and adaptability of memory allocation.

[0023] In one embodiment, the memory management request includes a target memory to be managed. If the memory management request is a memory release request, then executing the memory management request of the process through the target memory slice includes: releasing the target virtual address memory segment and the target physical address memory segment corresponding to the target memory through the virtual memory manager and physical memory manager of the target memory slice; adding the target virtual address memory segment and the target physical address memory segment corresponding to the target memory to the available free memory segment; clearing the target page table entry corresponding to the target memory and the target mapping relationship in the page table container of the target memory slice; updating the target memory information of the target memory, and completing the memory release request.

[0024] In one embodiment, the memory management request further includes an address translation request, which includes a target virtual address; then, executing the memory management request of the process through the target memory slice includes: querying the address mapping relationship within the target memory slice to find the target virtual address memory segment and target mapping relationship corresponding to the target virtual address; querying the page table container within the target memory slice to find the corresponding target page table entry based on the target virtual address; and calculating the target physical address corresponding to the target virtual address based on the target page table entry, the target virtual address memory segment, and the target mapping relationship.

[0025] In this embodiment, during the allocation, release, and address translation processes of memory management, the various module components cooperate and work together. While completing the memory management function, each module component operates independently. This approach helps reduce debugging and maintenance costs and avoids integration complexity issues. Furthermore, it avoids the situation where each memory slice manages its own corresponding memory segment in multiple application scenarios, preventing interference between different applications and processes and contributing to improved memory resource utilization.

[0026] Secondly, embodiments of this application provide a memory management device applied to a memory management unit of a verification platform, the verification platform further including memory; the memory management device includes: a model top-level unit, used to receive a memory management request from any process of each application; the model top-level unit is used to determine a target memory slice corresponding to the process from a preset memory management model; wherein, the memory management model presets a memory slice corresponding to each process of each application; the memory slice is used to perform various memory management functions through pre-allocated memory segments; the memory slice unit is also used to execute the memory management request of the process through the target memory slice.

[0027] Thirdly, embodiments of this application provide a verification platform, including: a processor, a memory management unit, and a memory, wherein the memory management unit and the memory are connected, and the processor is connected to both the memory management unit and the memory; the processor is used to run at least one application process; and the memory management unit is used to execute the memory management method as described in any of the first aspects when applying and verifying the chip.

[0028] Fourthly, embodiments of this application provide a readable storage medium storing a program that, when run on a processor, causes the processor to implement the memory management method as described in any of the first aspects. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A flowchart of a memory management method provided in this application embodiment; Figure 2 This is a schematic diagram of a memory management model provided in an embodiment of this application; Figure 3 This is a schematic diagram of a memory management device provided in an embodiment of this application; Figure 4 This is a schematic diagram of a verification platform provided in an embodiment of this application.

[0031] Icons: Memory management device 300; top layer of model 310; memory slicing section 320; verification platform 400; processor 410; memory management unit 420; memory 430. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0033] First, this application provides a memory management method applied to the memory management unit of a verification platform. The verification platform includes memory, as well as processors, various functional modules, and other structures, which are not limited herein. The processor or other functional modules of the verification platform can run different applications, and each application can run different processes. The memory management unit can allocate the memory required by each process for its operation.

[0034] In the embodiments of this application, the memory management unit is equipped with an MMU model (memory management model) to manage the memory of each process of each application. The memory management model can be built based on UVM (Universal Verification Methodology) to make the memory management unit and memory management more versatile.

[0035] In the embodiments of this application, memory management includes, but is not limited to, complete memory management functions such as virtual address management, physical address management, and page table management. For example, it may include memory access, release, allocation, memory protection, address mapping, address space management, page table and page table entry management, etc., and is not limited to a single function.

[0036] Currently, verification platforms are typically built on UVM (Universal Verification Methodology). Therefore, in the embodiments of this application, the memory management model described above can be built on UVM. This allows the memory management unit and memory management model to be directly integrated into the existing UVM verification platform without large-scale modifications to the existing code, thereby improving the practicality and compatibility of the memory management method.

[0037] Next, the memory management method provided in the embodiments of this application will be described in conjunction with the memory management unit and the memory management model. Please refer to [link / reference]. Figure 1 , Figure 1 This application provides a flowchart of a memory management method, which includes: S110 receives memory management requests from any process of each application running on the verification platform.

[0038] The verification platform's processor or various functional modules are capable of running applications and processes. Processes need to request, access, and use memory while working, and release memory after use. In this embodiment, the memory management unit can receive and execute memory management requests from processes. These memory management requests include, but are not limited to, memory access, allocation, and release.

[0039] Please see Figure 2 , Figure 2 This is a schematic diagram of a memory management model provided in one embodiment of this application. In this embodiment, the memory management model includes: a top-level model, multiple memory slices (mmu_slice), and various module components configured within each memory slice. The top-level model is denoted as mmu_model, and the memory slices are denoted as mmu_slice.

[0040] The memory slice mentioned in this application is part of the memory management model and is a code module that implements memory management. The memory management model may include multiple memory slices for different processes to manage memory respectively.

[0041] Furthermore, in the embodiments of this application, in actual use, the entire runtime environment only needs to instantiate one memory management model. Different applications and their internal processes can dynamically register memory slices with the memory management model through the first identifier and the second identifier mentioned later, obtain the handle of their own memory management slice, and realize memory management isolation of different processes.

[0042] In the embodiments of this application, the top-level model serves as the entry point for the memory management model, used to manage memory slices, such as creating, searching, configuring, and globally controlling memory slices. Furthermore, the top-level model also provides interfaces for applications and processes to receive memory management requests from processes and invoke the corresponding memory slices for execution.

[0043] In the embodiments of this application, the memory management model includes multiple memory slices, each memory slice corresponding to a process. Therefore, the memory management model has a pre-defined memory slice corresponding to each process of each application.

[0044] In the embodiments of this application, each memory slice is pre-allocated with a corresponding memory segment, and the memory slice is used to perform various memory management functions through the pre-allocated memory segment. Through memory slicing, the memory used by different processes can be isolated.

[0045] In the embodiments of this application, each memory slice is configured with multiple module components. Each module component within the same memory slice can perform its own function and work collaboratively to form a complete memory management chain, realizing memory management functionality through these module components. For example, each memory slice includes, but is not limited to, core module components such as a memory manager, a page table controller (page_ctrl), an address mapping table (va_pa_mapings), a page table container (pte_container), and a bus converter (bus_access_adapter). The specific functions and working methods of each module component will be elaborated later and will not be repeated here.

[0046] In the embodiments of this application, before receiving and executing the memory management request of the process, the memory slice of the process needs to be pre-configured in the memory management model.

[0047] Therefore, in one embodiment of this application, before receiving the memory management request of the process, the method may further include: obtaining attribute information of each process of each application; for each process, creating an initial memory slice corresponding to the identification information of the process; configuring module components with different functions in memory management in the initial memory slice; configuring each module component based on the memory setting parameters of the process to obtain the memory slice corresponding to the process.

[0048] In this embodiment, the initial memory slice can be understood as a blank slice, which needs to be configured according to the needs of the process. For example, the memory segment of the appropriate size, the required page table, etc., are configured according to the needs of the process, as well as the corresponding module components and the parameters of each module component are configured to obtain a memory slice that meets the needs of the process.

[0049] In the embodiments of this application, the top-level MMU model includes multiple interfaces, including an interface for creating memory slices, which can be denoted as the setup_mmu_slice (initialization of memory slice management) interface. When a process first requests memory, it can use the setup_mmu_slice interface to feed back the process's attribute information to the memory management model, so that the memory management model can create the corresponding memory slice based on the process's attribute information.

[0050] In the embodiments of this application, different processes are distinguished by identification information. Therefore, it may be necessary to create an initial memory slice corresponding to the identification information of each process to obtain the initial memory slice corresponding to that process.

[0051] The identification information includes process identifier and application identifier. Processes with the same process identifier may belong to different applications. Therefore, in the embodiments of this application, in order to create a memory slice that uniquely corresponds to a process, a memory slice can be created simultaneously using a dual-identifier approach, that is, the same memory slice includes both process identifier and application identifier.

[0052] Therefore, in this embodiment, the identification information includes a first identifier and at least one second identifier; the first identifier is used to characterize the application to which the process belongs, the first identifier is the application identifier, and the second identifier is the process identifier of the process.

[0053] Accordingly, for each process, an initial memory slice corresponding to the process's identification information is created, including: for each process, creating an initial memory slice corresponding to the process based on the process's first and second identifiers. Simultaneously, the identifier of this initial memory slice is configured to include both the first and second identifiers. This memory slice can be created by the top-level model.

[0054] In the embodiments of this application, the first identifier can be funcid, and the second identifier can be vmid. Here, funcid is a function identifier used to distinguish different functional modules; vmid is a virtual address memory segment identifier used to distinguish different virtual address memory segments. Accordingly, since each memory slice corresponds to a process in this application, the virtual address memory segment allocated to each memory slice also has a unique correspondence with the process. Therefore, vmid can be used to represent the process identifier.

[0055] Therefore, the first and second identifiers can be combined to form an index structure, for example, represented as: m_mem_slices[funcid][vmid]. Using the first and second identifiers, a unique memory slice can be created for each process. During subsequent memory management, the unique memory slice can be found using the first and second identifiers, thus effectively avoiding memory address mapping errors between different processes.

[0056] Meanwhile, in the embodiments of this application, before creating the initial memory slice corresponding to the process based on the first identifier and the second identifier of the process, the method further includes: determining that any memory slice in the memory management model does not simultaneously include the first identifier and the second identifier.

[0057] Accordingly, if it is determined that any memory slice in the memory management model includes both the first identifier and the second identifier, it indicates that a memory slice corresponding to the process already exists, and therefore no memory slice is created.

[0058] For example, it can be expressed as: create_if_slice_not_exist=1, then the identifier does not exist and a memory slice that includes both the first identifier and the second identifier does not exist. In this case, a new memory slice can be created.

[0059] In this embodiment, the existence of the same identifier within the memory management model is determined by the first identifier and the second identifier, so as to avoid the repeated creation of memory slices, thereby avoiding the waste of memory resources caused by repeated memory allocation, and avoiding memory management anomalies such as address mapping conflicts or mismatched memory used when the unique corresponding memory slice cannot be determined during subsequent use.

[0060] In embodiments of this application, the module components with different functions include at least: a memory manager, a page table controller, a bus converter, a page table container, and an address mapping table. Accordingly, configuring the module components with different functions in memory management in the initial memory slice may include configuring the memory manager, page table controller, bus converter, page table container, and address mapping table for the initial memory slice.

[0061] Next, we will explain the functions and configurable parameters of each module component.

[0062] The memory manager is used to allocate and reclaim memory used by the process based on virtual address (VA) and physical address (PA).

[0063] In the embodiments of this application, the memory manager includes a virtual memory manager va_mgr and a physical memory manager pa_mgr. The virtual memory manager is used to allocate and reclaim virtual address memory segments used by the process based on virtual addresses, and the physical memory manager is used to allocate and reclaim physical address memory segments used by the process based on physical addresses. This is achieved through the virtual memory manager va_mgr and the physical memory manager pa_mgr.

[0064] In the embodiments of this application, the virtual memory manager va_mgr and the physical memory manager pa_mgr can configure the following memory settings parameters: segment_granule (memory segment granularity), malloc_type (memory allocation strategy), mem_space_ids (memory segment ID queue), access_key (access permission signal), free_node_q (available free memory segments), etc. Specific configuration parameters can be flexibly adjusted according to verification requirements and are not limited here. Each memory setting parameter can be obtained from the process's attribute information or provided by the process; the specific method of obtaining it is not limited here.

[0065] The available free memory segment `free_node_q` comprises multiple memory segments `mmu_mem_segment` (or the smallest unit of memory management). Each memory segment includes information such as start address, end address, size, and page table. Adjacent memory segments support process splitting and merging. Memory segments are the fundamental carriers of virtual address / physical address mapping. When memory settings are not specified, the memory segment granularity can default to 4K. If the memory allocation strategy is not specified, sparse allocation is used by default, denoted as `MALLOC_SPARSE`.

[0066] In the embodiments of this application, the memory manager is configured to support multiple memory allocation methods, such as random allocation, customized allocation (specifying the starting address), and allocation with access permissions. It can be configured accordingly based on actual needs, and the allocation method can also be set through memory setting parameters.

[0067] In embodiments of this application, the memory manager may provide the following interfaces: register_mem_space (register memory segment), online_register_mem_space (register memory segment online), rand_register_mem_space (register memory segment randomly), malloc (memory allocation interface), malloc_with_access_key (memory allocation with access permissions), and specified_malloc (customized memory allocation).

[0068] Among them, register_mem_space supports specifying the starting address, size, and memory segment ID; online_register_mem_space supports dynamically expanding memory; rand_register_mem_space allows configuration of parameters such as memory range, page size, and number of memory segments; the malloc interface can allocate memory according to a specified segment size and return the memory segment; malloc_with_access_key can bind access permissions during allocation; and the specified_malloc interface can allocate memory by specifying the starting address and segment size.

[0069] In the embodiments of this application, the memory manager is configured with a flexible memory allocation mechanism, providing multiple memory request methods such as random allocation, customized allocation, and allocation with access permissions. It supports dynamic registration and expansion of memory segments, adapts to the diverse memory needs of different verification scenarios, and improves the flexibility and adaptability of memory allocation.

[0070] In the embodiments of this application, the memory manager can also implement memory reclamation functionality. For example, it can provide a `recycle_mem_segment` interface to reclaim specified memory segments and add the reclaimed memory segments to available free memory segments, thereby achieving the recycling of memory resources. Simultaneously, it also supports the overall reclamation of memory segments, clearing the corresponding memory segment ID and free segments.

[0071] In the embodiments of this application, the memory manager can also implement other auxiliary functions. For example, it can maintain the memory resource usage status in real time, including total_free_size (free memory size) and all_space_id_free_size (global free memory size), and is also configured to support debug information display to facilitate troubleshooting memory-related problems.

[0072] The specific implementation methods of the above functions can be referred to the existing technology, and will not be repeated here. In this application, the above functions can be configured in the memory manager, and the memory manager can implement the corresponding functions to meet the memory management requirements.

[0073] The page table controller page_ctrl is used to configure the corresponding page table for a process, including but not limited to configuring and managing the page table level and page size, and obtaining the table offset of each level of page table to realize table lookup or table creation.

[0074] In the embodiments of this application, the page table controller configures the following memory settings parameters related to the page table: page_levels_bit_width (page-level bit width queue), basic_page_bit_width (basic page bit width), supported_page_types (supported page table types, a two-dimensional array), and supported_page_sizes (supported page sizes). By configuring different parameters of the page table, the created page table can be adapted to various page table types to meet the needs of different scenarios.

[0075] In some embodiments of this application, page table type configuration includes, but is not limited to, supporting multiple page table levels and page size combinations, and configuring different page table parameters through switch-case (multi-branch selection structure) logic.

[0076] For example, the following page table types can be configured: 4K level 4 page table, 16K level 4 page table, and 64K level 2 page table. A 4K level 4 page table can be represented as (basic_page_bit_width=12, page_Levels_bit_width={9,9,9,9}), supporting a maximum of 1GB of memory. A 16K level 4 page table can be represented as (basic_page_bit_width=14, page_Levels_bit_width={11,11,11,1}), supporting a maximum of 32MB of memory. A 64K level 2 page table can be represented as (basic_page_bit_width=16, page_Levels_bit_width={14,18}), supporting a maximum of 1GB of memory.

[0077] In the embodiments of this application, the page table manager also has other functions, such as: supporting the calculation of page table offset addresses and bitmasks, generating page_level_offsets (page-level offset queue) and page_level_bit_masks (page-level bitmask queue); managing all page table information, providing page table parameter support for the conversion of virtual address VA to physical address PA; and cooperating with the page table container to complete the lookup of page table entry PTE and the calculation of virtual address, etc.

[0078] In this embodiment, the page table controller enables dynamic configuration of the page table according to actual needs, allowing flexible switching between multiple page table levels and page sizes. The page table type can be adjusted according to verification requirements, thereby helping to adapt to the page table management needs of different chip architectures and solving the problem of rigid page table management.

[0079] The page table container is used to create and manage page table entries for the process. It is responsible for the storage, updating, cleanup, and management of PTE (Page Table Entry) / PDE (Page Directory Entry), and assists in completing page table-related operations in memory management. In the embodiments of this application, the page table container can be configured with the following parameters: TTBA (Translation Table Base Address), funcid, vmid, pte_entry_type (PTE entry type), pte_entry_byte_size (PTE entry byte size, default 8 bytes), etc.

[0080] In the embodiments of this application, the page table container can be configured with the following functions: PTE management, PDE management, page table cleanup, and PTE storage. PTE management includes the creation, retrieval, updating, and invalidation of PTE entries, supports batch writing of PTEs to memory, and can mark PTEs as invalid. PDE management includes the deletion and reclamation of PDE entries, releasing invalid page directory entry resources and avoiding memory waste. Page table cleanup includes cleaning up the PTE information of specified memory segments, filling the corresponding memory area with 0s to ensure the validity of page table information. PTE storage includes storing PTE entries through m_pte_sections (PTE segment queue), associating each PTE segment with a corresponding memory segment, and implementing binding management between PTEs and memory segments.

[0081] Furthermore, the page table container can work in conjunction with other module components. For example, it can work with the page table controller to calculate the PTE memory address based on page table parameters. It can also work with the bus converter to complete the bus transmission of PTE information. Finally, it can work with the memory manager to achieve dynamic allocation and reclamation of PTE memory segments.

[0082] In the embodiments of this application, the bus converter is used to abstract and isolate bus protocols, adapt to different bus protocols, and provide a unified memory access interface. That is, the bus converter can convert memory management requests from different protocols into a unified format request for the memory of the verification platform, so as to execute the memory management request of the process through the unified format request.

[0083] For example, in some embodiments of this application, the bus converter includes conversion management between access requests of different protocols and requests of the same format, which can convert access requests of different bus protocols into a unified format: {address, data}. Thus, it can adapt to verification scenarios of different bus protocols without modifying the core code, expanding the applicability of the memory management method.

[0084] In the embodiments of this application, the bus converter is also used to configure the memory access method. For example, it can configure two memory access methods: front door access and back door access. Specifically, it can be selected or configured according to memory management requests or memory configuration parameters to meet the memory access efficiency requirements in different scenarios.

[0085] In the embodiments of this application, the bus converter is also used to provide a memory access interface for receiving memory management requests, completing write and read operations of PTE information and memory data, and feeding back the memory operation results to the system. It can also work in conjunction with page table containers and memory segments to ensure the stability and accuracy of bus access.

[0086] In this embodiment, the bus converter supports multiple bus protocols and two access methods: adaptation and front / back door. It converts bus access into a unified format, which helps reduce the integration difficulty of the memory management model. It eliminates the need to configure multiple bus protocols for memory access methods, thus improving the versatility of the memory management model.

[0087] In the embodiments of this application, the address mapping table is denoted as va_pa_mappings, which is used to store the mapping relationship between virtual addresses and physical addresses in memory.

[0088] The address mapping table records the mapping relationship between virtual address memory segments and physical address memory segments. A memory segment (mmu_mem_segment) is the smallest unit of memory management, and the address mapping table implements the mapping management between VA and PA based on the memory segment (mmu_mem_segment).

[0089] In the embodiments of this application, the memory segment `mmu_mem_segment` can be configured with the following memory setting parameters: `mem_space_id` (memory segment ID), `start_addr` (start address), `end_addr` (end address), `size` (segment size), `page_info` (page table information), etc., to record a continuous virtual address memory segment or physical address memory segment. In the embodiments of this application, the memory segment can be split and merged, providing a basic carrier for the mapping between virtual addresses and physical addresses.

[0090] In the embodiments of this application, the address mapping table va_pa_mappings is used to store the mapping relationship between virtual address memory segments and physical address memory segments. It is stored in the form of mapping entries, each of which can contain src_va_segment (source virtual address segment), sub_va_segments (virtual address memory sub-segment queue), and sub_pa_segments (physical address memory sub-segment queue), and can be marked with va_pa_mapping_status (mapping status). The address mapping table can establish, query, and delete mapping relationships, and the conversion from virtual address to physical address can be achieved through the address mapping table.

[0091] For example, in one embodiment, configuring module components for different functions of memory management in the initial memory slice may include: initializing the parameters of the initial memory slice mem_slice and configuring the virtual memory manager and physical memory manager, using the default manager if not specified; initializing the page table controller and configuring parameters such as page table level and page table size based on the page table controller; initializing the bus converter and binding the bus converter to the bus access interface; initializing the memory unit and address mapping table to complete the creation and initialization of the memory slice, thus obtaining the initialization.

[0092] In the embodiments of this application, the memory attribute information of the process obtained when creating a memory slice also includes the memory setting parameters of the process. The memory setting parameters include, but are not limited to, parameters such as va_start_addr (virtual address start address), size (memory size), basic_page_bit_width (basic page bit width), page_Levels_bit_width (page level bit width queue), as well as parameters that can be configured and modified by the aforementioned module components.

[0093] In the embodiments of this application, different functions of memory management are separated, making each function modular. Functions such as memory management, page table management, bus translation, and PTE management are split into independent module components, and these components work together. This approach reduces the debugging and maintenance costs of the model and improves memory resource utilization. In addition, debug information display capabilities can be configured on the model to further reduce the debugging and maintenance costs of the model.

[0094] Accordingly, after configuring the module components for different functions of memory management in the initial memory slice, each module component is configured based on the memory setting parameters of the process to obtain the memory slice corresponding to the process. This enables each module component of the memory slice to build the relevant information for memory management required by the process, such as building memory segments, page tables, page table entries, address mapping relationships, etc.

[0095] In one embodiment of this application, configuring each module component based on the memory setting parameters of the process may include: obtaining the memory setting parameters of the process; the virtual memory manager within the initial memory slice allocating virtual address memory segments to the initial memory slice according to memory requirements; the physical memory manager within the initial memory slice obtaining physical address memory segments to the initial memory slice according to memory requirements; the page table controller within the initial memory slice configuring at least one page table according to the page table requirements; the page table controller within the initial memory slice dividing the virtual address memory segments and physical address memory segments according to the page tables to obtain virtual address memory sub-segments and physical address memory sub-segments matching each page table; establishing an address mapping relationship between each pair of virtual address memory sub-segments and physical address memory sub-segments in the address mapping table of the initial memory slice; the page table container within the initial memory slice establishing page table entry information according to the address mapping relationship; and the bus converter within the initial memory slice storing the page table entries into the memory to complete the creation of the memory slice corresponding to the process.

[0096] In the above embodiments, memory configuration parameters include memory requirements and page table requirements. Memory requirements include, but are not limited to, the virtual address start address va_start_addr, memory size size, basic page bit width basic_page_bit_width, page level bit width queue page_Levels_bit_width, etc. Page table requirements include, but are not limited to, page table size, page level bit width, page table type, etc. The virtual address memory slices may be contiguous or non-contiguous, which is not limited here. The physical address memory segment is the address segment of the verification platform's memory.

[0097] In this embodiment, the virtual memory manager can determine the end address of the virtual address from the start address based on the process's memory requirements, and use this memory segment from the start address to the end address as the virtual address memory segment. After obtaining the virtual address memory segment, the corresponding virtual memory segment can be stored in the virtual address queue for subsequent mapping establishment. Similarly, the physical memory manager can also obtain a physical address memory segment of the corresponding size from memory as the corresponding physical address memory segment.

[0098] In this embodiment, the page table controller configures the page table according to the page table requirements, and the specific parameters of the page table are configured accordingly based on the memory requirements.

[0099] When a process uses memory, it performs different tasks. Each task requires allocating a corresponding memory segment or a sub-segment of memory obtained by dividing the memory segment. The size of the memory segment or sub-segment required for each task matches the page table size, resulting in a virtual address memory segment and a physical address memory segment that match each page table, or a virtual address memory sub-segment and a physical address memory sub-segment that match each page table.

[0100] Then, a mapping relationship can be established between virtual address memory sub-segments and physical address memory sub-segments. Through this mapping relationship, after obtaining the virtual address memory segment, the corresponding physical address memory segment can be determined to realize memory access.

[0101] Finally, the page table container can establish PTE entries through mapping relationships and store them in the memory of the verification platform through the bus converter, thus completing the memory slice establishment process.

[0102] S120: Determine the target memory slice corresponding to the process from the preset memory management model.

[0103] In this embodiment, the memory slice corresponding to the process that issues the memory management request is called the target memory slice. As mentioned above, in this embodiment, the memory management model pre-sets memory slices corresponding to different processes. Each process has a unique corresponding memory slice, which pre-sets information such as the process's memory segments, page tables, and page entries. At the same time, it also pre-configures the execution of various module components. Thus, the memory management request of the process can be executed through the target memory slice.

[0104] As mentioned above, each memory slice in this application is created through a first identifier and a second identifier. Accordingly, in the embodiments of this application, the memory management request includes a target first identifier and a target second identifier corresponding to the process; and determining the target memory slice corresponding to the process from the preset memory management model may include: if there exists a memory slice whose first identifier matches the target first identifier and whose second identifier matches the target second identifier, then the memory slice is determined as the target memory slice.

[0105] Therefore, a unique target memory slice can be identified for each process, and the process's memory management requests can be executed through this target memory slice. This can effectively avoid interference between processes of different applications and address mapping conflicts, thereby improving the reliability and security of memory management.

[0106] S130, execute the process's memory management request through the target memory slice.

[0107] In the embodiments of this application, the target memory slice can work together through multiple built-in module components to jointly realize various memory management functions in order to execute memory management requests.

[0108] Taking the memory segment requested by the memory management request as the target memory as an example, the process of executing the process's memory management request on the target memory slice by memory allocation and release will be explained separately.

[0109] If the memory management request is a memory allocation request, then executing the memory management request of the process through the target memory slice may include: allocating a target virtual address memory segment matching the target memory for the process through the virtual memory manager of the target memory slice; allocating a target physical address memory segment matching the target memory for the process through the physical memory manager of the target memory slice; establishing a target mapping relationship between the target virtual address memory segment and the target physical address memory segment in the address mapping table of the target memory slice; creating a target page table entry in the page table container of the target memory slice based on the target mapping relationship; storing the target page table entry into memory through the bus converter of the target memory slice; generating target memory information corresponding to the target memory, and completing the memory allocation request. During the allocation process, it is also possible to allocate memory sub-segments obtained by cutting a memory segment.

[0110] In the embodiments of this application, memory allocation can be performed according to a preset allocation strategy within the memory manager. For example, the virtual memory manager can allocate virtual address memory segments according to the allocation strategy. Allocation can include, but is not limited to, sparse allocation, customized allocation, random allocation, and allocation with access permissions. By configuring different types of allocation methods, it is helpful to meet the diverse memory requirements of different verification scenarios and improve the flexibility and adaptability of memory allocation.

[0111] If the memory management request is a memory release request, then the memory management request of the process is executed through the target memory slice, which may include: releasing the target virtual address memory sub-segment and the target physical address memory segment corresponding to the target memory through the virtual memory manager and physical memory manager of the target memory slice; adding the target virtual address memory segment and the target physical address memory segment corresponding to the target memory to the available free memory segment; cleaning up the target page table entry and target mapping relationship corresponding to the target memory in the page table container of the target memory slice; updating the target memory information of the target memory, and completing the memory release request.

[0112] If the memory management request is an address translation request, and the address included in the address translation request is the target virtual address, then the memory management request of the process is executed through the target memory slice. This may include: querying the address mapping relationship within the target memory slice to find the target virtual address memory segment and the target mapping relationship; querying the corresponding target page table entry based on the target virtual address using the page table container within the target memory slice; and calculating the target physical address corresponding to the target virtual address based on the target page table entry, the target virtual address memory segment, and the target mapping relationship using the page table container within the target memory slice.

[0113] The principles and purposes of memory allocation, deallocation, and address translation between VA and PA can be found in existing technologies and will not be elaborated here. This explanation focuses solely on the specific execution process of the various module components within the memory slice of this application when performing their respective memory management functions.

[0114] In this embodiment of the application, by configuring a corresponding memory slice for each process, the memory management of different processes is isolated from each other. As a result, the memory segments used by different processes are pre-allocated and isolated from each other without overlapping. When a process uses memory, it can only use the memory segment pre-allocated by the memory slice of its process. This method is easier to manage and effectively reduces the occurrence of mutual interference and address mapping conflicts between processes of multiple applications, thereby improving the reliability and security of memory management.

[0115] In this embodiment, by isolating multiple memory slices, modularizing each memory management function, and making the parameters of each module component, memory, and page table parameters adjustable, memory management can be made more flexible and universal, adaptable to different scenarios, and easier to maintain.

[0116] Based on the same inventive concept, this application also provides a memory management device. Please refer to [link to relevant documentation]. Figure 3 , Figure 3 This is a schematic diagram of a memory management device provided in an embodiment of this application. The memory management device 300 includes a top-level model portion 310 and a memory slicing portion 320.

[0117] The top-level part 310 of the model is used to receive memory management requests from any process of each application.

[0118] The top-level part 310 of the model is also used to determine the target memory slice corresponding to the process from the preset memory management model; wherein, the memory management model has a preset memory slice corresponding to each process of each application; the memory slice is used to perform various functions of memory management through pre-allocated memory segments.

[0119] The memory slicing unit 320 is also used to execute the memory management request of the process through the target memory slice.

[0120] The top-level part 310 of the model is further configured to: obtain attribute information of each process of each application before receiving a memory management request from a process; the attribute information includes the memory setting parameters and identification information of the process; for each process, create an initial memory slice corresponding to the identification information of the process; configure module components with different functions in memory management in the initial memory slice; configure each module component based on the memory setting parameters of the process to obtain the memory slice corresponding to the process.

[0121] The identification information includes a first identifier and at least one second identifier; the first identifier is used to characterize the application to which the process belongs, and the second identifier is the process identifier of the process. The top-level part 310 of the model is further configured to: for each process, create an initial memory slice corresponding to the process based on the first identifier and the second identifier of the process.

[0122] The top-level part 310 of the model is further configured to: determine that any memory slice in the memory management model does not simultaneously include the first identifier and the second identifier before creating the initial memory slice corresponding to the process based on the first identifier and the second identifier of the process.

[0123] The memory management request includes a first target identifier and a second target identifier corresponding to the process. The top-level part 310 of the model is further configured to: if there exists a first identifier of any memory slice that matches the first target identifier, and a second identifier of the memory slice that matches the second target identifier, then determine the memory slice as the target memory slice.

[0124] The module components with different functions include at least: a memory manager, a page table controller, a bus converter, a page table container, and an address mapping table. The memory manager includes a virtual memory manager and a physical memory manager; the virtual memory manager allocates and reclaims virtual memory segments used by the process based on virtual addresses; the physical memory manager allocates and reclaims physical memory segments used by the process based on physical addresses; the page table controller configures the corresponding page table for the process; the page table container creates and manages page table entries for the process; the bus converter converts memory management requests from different protocols into a unified format request for the verification platform's memory, so as to execute the process's memory management requests through the unified format request; the address mapping table stores the mapping relationship between virtual addresses and physical addresses of memory through memory units.

[0125] The top-level part 310 of the model is also used to configure the memory manager, the page table controller, the bus converter, the page table container and the address mapping table for the initial memory slice.

[0126] The top-level part 310 of the model is used for: obtaining memory setting parameters of the process, the memory setting parameters including memory requirements and page table requirements; the virtual memory manager in the initial memory slice allocates at least one virtual address memory segment to the initial memory slice according to the memory requirements; the physical memory manager in the initial memory slice obtains at least one physical address memory segment for the initial memory slice according to the memory requirements; the page table controller in the initial memory slice configures the page table according to the page table requirements; wherein, the page table controller configures at least one of the following: page table size, level, bit width, and type according to the page table requirements; The page table controller within the initial memory slice segments segments the virtual address memory segment and the physical address memory segment according to the page table, obtaining a virtual address memory sub-segment and a physical address memory sub-segment that match each page table; an address mapping relationship is established between each pair of virtual address memory sub-segments and physical address memory sub-segments in the address mapping table of the initial memory slice; the page table container within the initial memory slice establishes page table entry information according to the address mapping relationship; and the bus converter within the initial memory slice stores the page table entries into the memory, completing the creation of the memory slice corresponding to this process.

[0127] The memory management request includes a target memory to be managed. If the memory management request is a memory allocation request, the memory slicing unit 320 is used to: allocate a target virtual address memory sub-segment matching the target memory to the process through the virtual memory manager of the target memory slice; allocate a target physical address memory segment matching the target memory to the process through the physical memory manager of the target memory slice; establish a target mapping relationship between the target virtual address memory segment and the target physical address memory segment in the address mapping table of the target memory slice; establish a target page table entry in the page table container of the target memory slice based on the target mapping relationship; store the target mapping relationship and the target page table entry into the memory through the bus converter of the target memory slice; generate target memory information corresponding to the target memory, and complete the memory allocation request.

[0128] The memory slicing unit 320 is used by the virtual memory manager of the target memory slice to allocate a target virtual address memory segment that matches the target memory to the process through a preset allocation strategy; the preset allocation strategy is one of the following: sparse allocation, customized allocation with a specified starting address, random allocation, and allocation with access permissions.

[0129] The memory management request includes the target memory to be managed. If the memory management request is a memory release request, the memory slicing unit 320 is used to: release the target virtual address memory sub-segment and the target physical address memory segment corresponding to the target memory through the virtual memory manager and physical memory manager of the target memory slice; add the target virtual address memory segment and the target physical address memory sub-segment corresponding to the target memory to the available free memory segment; clean up the target page table entry corresponding to the target memory and the target mapping relationship in the page table container of the target memory slice; update the target memory information of the target memory, and complete the memory release request.

[0130] The memory management request also includes an address translation request, which includes a target virtual address. The memory slicing unit 320 is used to: query the address mapping relationship within the target memory slice to find the target virtual address memory segment and the target mapping relationship corresponding to the target virtual address; query the page table container within the target memory slice to find the corresponding target page table entry based on the target virtual address; and calculate the target physical address corresponding to the target virtual address based on the target page table entry, the target virtual address memory segment, and the target mapping relationship.

[0131] Based on the same inventive concept, this application also provides a verification platform. Please refer to [link to relevant documentation]. Figure 4 , Figure 4 This is a schematic diagram of a verification platform provided in an embodiment of this application. The verification platform 400 includes: a processor 410, a memory management unit 420, and a memory 430. The memory management unit 420 and the memory 430 are connected, and the processor 410 is connected to both the memory management unit 420 and the memory 430.

[0132] In the embodiments of this application, the processor 410 is used to run the process of at least one application; the memory management unit 420 is used to execute the memory management method provided in any of the foregoing embodiments when applying and verifying the chip.

[0133] In embodiments of this application, the verification platform may be built based on UVM.

[0134] The specific structure and functions of the verification platform can be referred to the prior art. In the embodiments of this application, the verification platform can be configured with a memory management unit that executes the aforementioned memory management method, so as to manage the memory of the applications and processes running on the verification platform through the memory management method provided in this application.

[0135] Based on the same inventive concept, embodiments of this application also provide a readable storage medium storing a program thereon, wherein when the computer program runs on a processor, the processor executes the memory management method provided in the above embodiments.

[0136] The readable storage medium can be any available medium that the processor can access, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs (digital video discs)), or semiconductor media (e.g., SSDs (solid state disks)).

[0137] If the method is implemented as a software functional module and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0138] In the embodiments provided in this application, it should be understood that the disclosed methods and apparatus can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. The functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0139] The above embodiments can be freely combined without conflict, and the resulting embodiments are covered within the protection scope of this application.

[0140] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0141] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A memory management method, characterized in that, A memory management unit applied to a verification platform, the verification platform further including memory; the method includes: For any process of each application running on the verification platform, receive the memory management request of that process; The target memory slice corresponding to the process is determined from a preset memory management model; wherein, the memory management model has a preset memory slice corresponding to each process of each application; the memory slice is used to perform various memory management functions through pre-allocated memory segments; The process's memory management request is executed through the target memory slice.

2. The memory management method according to claim 1, characterized in that, Before receiving the memory management request from the process, the method further includes: Obtain the attribute information of each process of each application; the attribute information includes the memory setting parameters and identification information of the process; For each of the aforementioned processes, an initial memory slice corresponding to the process's identification information is created; Configure module components for different functions of memory management in the initial memory slice; Based on the memory settings parameters of the process, configure each module component to obtain the memory slice corresponding to the process.

3. The memory management method according to claim 2, characterized in that, The identification information includes a first identifier and at least one second identifier; the first identifier is used to characterize the application to which the process belongs. The second identifier is the process identifier of the process; The step of creating an initial memory slice corresponding to the identification information of each process includes: For each process, an initial memory slice corresponding to the process is created based on the process's first and second identifiers.

4. The memory management method according to claim 3, characterized in that, Before creating the initial memory slice corresponding to the process based on the first and second identifiers of the process, the method further includes: It is determined that any memory slice in the memory management model does not simultaneously include the first identifier and the second identifier.

5. The memory management method according to claim 3, characterized in that, The memory management request includes a first target identifier and a second target identifier corresponding to the process; Determining the target memory slice corresponding to the process from the preset memory management model includes: If any of the memory slices has a first identifier that matches the target first identifier, and a second identifier that matches the target second identifier, then the memory slice is identified as the target memory slice.

6. The memory management method according to any one of claims 2-5, characterized in that, The different functional module components include at least: a memory manager, a page table controller, a bus converter, a page table container, and an address mapping table; The memory manager includes a virtual memory manager and a physical memory manager; the virtual memory manager is used to allocate and reclaim virtual address memory segments used by the process based on virtual addresses; the physical memory manager is used to allocate and reclaim physical address memory segments used by the process based on physical addresses. The page table controller is used to configure the corresponding page table for the process; The page table container is used to create and manage page table entries for the process; The bus converter is used to convert memory management requests from different protocols into a unified format request for the memory of the verification platform, so as to execute the memory management request of the process through the unified format request; The address mapping table is used to store the mapping relationship between the virtual address and the physical address of memory through memory units; The module components for configuring different functions of memory management in the initial memory slice include: Configure the memory manager, the page table controller, the bus converter, the page table container, and the address mapping table for the initial memory slice.

7. The memory management method according to claim 6, characterized in that, The configuration of each module component based on the memory setting parameters of the process includes: Obtain the memory configuration parameters of the process, including memory requirements and page table requirements; The virtual memory manager within the initial memory slice allocates at least one virtual address memory segment to the initial memory slice according to the memory requirements; The physical memory manager within the initial memory slice obtains at least one physical address memory segment for the initial memory slice according to the memory requirements; The page table controller within the initial memory slice configures the page table according to the page table requirements; wherein, the page table controller configures at least one of the following: page table size, level, bit width, and type according to the page table requirements; The page table controller within the initial memory slice divides the virtual address memory segment and the physical address memory segment according to the page table, respectively, to obtain a virtual address memory sub-segment and a physical address memory sub-segment that match each page table; In the address mapping table of the initial memory slice, establish the address mapping relationship between each pair of virtual address memory sub-segments and physical address memory sub-segments; The page table container within the initial memory slice establishes page table entry information based on the address mapping relationship; The bus converter within the initial memory slice stores the page table entries into the memory, thus completing the creation of the memory slice corresponding to the process.

8. The memory management method according to claim 6, characterized in that, The memory management request includes the target memory to be managed. If the memory management request is a memory allocation request, then executing the memory management request of the process through the target memory slice includes: The virtual memory manager of the target memory slice allocates a target virtual address memory segment to the process that matches the target memory. The physical memory manager of the target memory slice allocates a target physical address memory segment to the process that matches the target memory. Establish a target mapping relationship between the target virtual address memory segment and the target physical address memory segment in the address mapping table of the target memory slice; The page table container of the target memory slice establishes target page table entries based on the target mapping relationship; The target page table entries are stored in the memory via the bus converter of the target memory slice; Generate the target memory information corresponding to the target memory, and complete the memory allocation request.

9. The memory management method according to claim 8, characterized in that, The step of allocating a target virtual address memory segment matching the target memory to the process through the virtual memory manager of the target memory slice includes: the virtual memory manager of the target memory slice allocating a target virtual address memory segment matching the target memory to the process through a preset allocation strategy; The preset allocation strategy is one of the following: sparse allocation, customized allocation with a specified starting address, random allocation, or allocation with access permissions.

10. The memory management method according to claim 6, characterized in that, The memory management request includes the target memory to be managed. If the memory management request is a memory release request, then executing the memory management request of the process through the target memory slice includes: The target virtual address memory segment and the target physical address memory segment corresponding to the target memory are released through the virtual memory manager and physical memory manager of the target memory segment; Add the target virtual address memory segment and the target physical address memory segment corresponding to the target memory to the available free memory segment; Clean up the target page table entries and target mapping relationships corresponding to the target memory in the page table container of the target memory slice; Update the target memory information for the target memory to complete the memory release request.

11. The memory management method according to claim 6, characterized in that, The memory management request further includes an address translation request, which includes a target virtual address; therefore, executing the memory management request of the process through the target memory slice includes: The address mapping relationship within the target memory slice is queried to find the target virtual address memory segment and the target mapping relationship corresponding to the target virtual address; The page table container within the target memory slice queries the corresponding target page table entry based on the target virtual address; The page table container within the target memory slice calculates the target physical address corresponding to the target virtual address based on the target page table entries, the target virtual address memory segment, and the target mapping relationship.

12. A memory management device, characterized in that, A memory management unit is applied to a verification platform, the verification platform further including memory; the memory management device includes: The top-level part of the model is used to receive memory management requests from any process of each application. The top-level model is also used to determine the target memory slice corresponding to the process from a preset memory management model; wherein, the memory management model has a preset memory slice corresponding to each process of each application; the memory slice is used to perform various memory management functions through pre-allocated memory segments; The memory slicing unit is also used to execute the memory management request of the process through the target memory slice.

13. A verification platform, characterized in that, include: The processor comprises a memory management unit and memory, wherein the memory management unit and memory are connected, and the processor is connected to both the memory management unit and memory; the processor is used to run the process of at least one application. The memory management unit is used to execute the memory management method as described in any one of claims 1-11 when applying and verifying the chip.

14. A readable storage medium, characterized in that, The readable storage medium stores a program that, when run on a processor, causes the processor to implement the memory management method as described in any one of claims 1-11.

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