GPU load balancing system and method based on graphics primitive broadcasting and segment partitioning

Abstract

The application provides a GPU load balancing system and method based on a primitive broadcast and segment partition, divides a primitive assembly stage into two stages of a position primitive assembly (PosPA) and a final primitive assembly (FinalPA), assembles positions of primitives in the PosPA stage, assembles attributes of the primitives in the FinalPA stage, inserts a broadcast process between the two stages, and further combines a segment area process in a rasterization stage, so that fine rendering load distribution of a Multi-Cluster GPU (multi-pipeline unit GPU) in a segment intensive task is realized.

Description

Technical Field

[0001] This invention relates to the field of image rendering technology, and more specifically, to a GPU load balancing system and method based on primitive broadcasting and fragment partitioning. Background Technology

[0002] With the continuous improvement of real-time rendering resolution of GPUs (Graphics Processing Units) and the large-scale application of rendering technologies such as real-time ray tracing and global illumination, GPU computing power is growing exponentially. In order to improve graphics rendering throughput, modern GPUs generally adopt a multi-cluster parallel architecture, which integrates multiple complete rendering pipelines inside the chip, enabling parallel processing of GPU rendering tasks.

[0003] The graphics rendering pipeline typically includes stages such as vertex shading, tessellation shading, geometry shading, primitive assembly, hidden surface removal, clipping, viewport transformation, triangle creation, rasterization, fragment shading, and fragment operations. When rendering tasks involve many fragments, rasterization and fragment operations processed fragment by fragment often become the performance bottleneck of the GPU. When the workload is not properly distributed, the advantages of the multi-cluster architecture will significantly decrease. How to achieve efficient load balancing is one of the core challenges of this architecture.

[0004] Traditional Sort-MIDdle tiled rendering architectures and reordering methods follow the design paradigm of "each primitive is assigned to only one processing unit." This means that primitives must be "cut" and distributed to different clusters at a certain point in the rendering pipeline. This process requires additional storage of intermediate primitive data, introducing sorting / remapping overhead. Distribution after rasterization requires complex depth / color merging logic. Secondly, because Sort-MIDdle uses static tile division, it cannot accurately achieve fragment-level load balancing. In extreme cases, fragment load imbalance can occur, directly affecting the overall GPU performance. Summary of the Invention

[0005] This invention addresses the technical problems existing in the prior art by providing a GPU load balancing system and method based on primitive broadcasting and fragment partitioning. This overcomes the problem of severe load imbalance during the fragment scanning and processing stages caused by uneven distribution of primitives in the screen space when multi-cluster GPUs process fragment-intensive rendering tasks.

[0006] According to a first aspect of the present invention, a GPU load balancing system based on primitive broadcasting and fragment partitioning is provided, comprising multiple rendering pipeline units (Cluster) and a broadcasting module, wherein each Cluster includes a position primitive assembly (PosPA) unit, a complete attribute primitive assembly (FinalPA) unit, and a rasterization module.

[0007] Each of the aforementioned clusters contains a vertex coloring module, which is used to color the primitive vertices and output the data for each vertex.

[0008] The PosPA unit within each Cluster is used to read the vertex position information from each vertex data and assemble it into a primitive position list;

[0009] The broadcast module is used to collect the list of primitive locations of all the clusters and distribute the collected complete list of primitive locations to the FinalPA units of all the clusters.

[0010] The FinalPA unit within each Cluster is used to read complete vertex attribute information from each vertex data according to the received complete primitive position list, perform primitive attribute assembly, and send the attribute-assembled primitives to the rasterization module within the Cluster.

[0011] The rasterization modules within each cluster are used to perform rasterization processing on the received primitives, and different rasterization modules generate fragments of different regions within the same primitive tile according to their respective configuration information.

[0012] Based on the above technical solution, the present invention can also be improved as follows.

[0013] Optionally, the vertex shading module in each of the clusters stores the shading data of each vertex in a vertex cache and sends each vertex ID to the PosPA unit in the cluster.

[0014] The PosPA unit reads the vertex position information from the vertex cache for each vertex ID, and assembles a primitive position list based on the vertex position information of each primitive.

[0015] Optionally, the broadcast module is further configured to collect and distribute the primitive position lists of each Cluster according to the original order in which primitives enter the rendering pipeline, so that rendering is performed in the original order of primitives.

[0016] Optionally, the rasterization module within each cluster performs rasterization processing using a tile-based scanning method, specifically including:

[0017] Starting from the tile containing the largest Y-coordinate vertex of the primitive, the scan proceeds row by row to obtain the valid tiles covered by the primitive. Then, a segment-by-segment scan is performed within each valid tile to generate the segment within the tile.

[0018] Optionally, each Cluster also stores a region allocation mapping table, which records the offset positions of all fragments that the Cluster is responsible for processing within a fragment tile.

[0019] The rasterization module is specifically used to generate a segment at the corresponding offset position within the Tile based on the region allocation mapping table.

[0020] Optionally, the region allocation mapping table can be dynamically configured, so that the segment regions that different clusters are responsible for within a Tile can be dynamically adjusted to adapt to different load balancing strategies.

[0021] Optionally, the load balancing strategy includes:

[0022] The tile is divided into multiple contiguous sub-blocks, with each cluster responsible for processing one of these sub-blocks; or,

[0023] A checkerboard pattern is used to ensure that the segments each cluster is responsible for within a tile are evenly distributed.

[0024] Optionally, the PosPA unit only reads and processes the screen space coordinates of the vertices as vertex position information; the FinalPA unit is used to read and process all vertex attribute information, including vertex screen space coordinates, texture coordinates, normal vectors, and vertex colors.

[0025] According to a second aspect of the present invention, a GPU load balancing method based on primitive broadcasting and fragment partitioning is provided, applied to a GPU load balancing system based on primitive broadcasting and fragment partitioning, the method comprising:

[0026] Vertex shading processing is performed in parallel within each Cluster, and data for each vertex is output.

[0027] Within each Cluster, position primitive assembly processing is performed in parallel, reading vertex position information from each vertex data and assembling it into a primitive position list;

[0028] Collect the list of primitive locations for all said clusters, and distribute the collected complete list of primitive locations to all said clusters;

[0029] Each Cluster reads complete vertex attribute information from each vertex data and performs primitive attribute assembly based on the received complete primitive position list;

[0030] Each Cluster performs rasterization processing on the primitives after attribute assembly, and different Clusters generate fragments of different regions within the same primitive tile according to their respective configuration information.

[0031] This invention provides a GPU load balancing system and method based on primitive broadcasting and fragment partitioning. Unlike the traditional graphics rendering pipeline processing flow, this invention divides the primitive assembly stage into two stages: PosPA (Position PrimitiveAssembly) and FinalPA (Final Primitive Assembly). Broadcasting processing is inserted between the two stages, and combined with fragment region processing in the rasterization stage, it realizes fine-grained rendering load distribution of Multi-Cluster GPU in fragment-intensive tasks. Attached Figure Description

[0032] Figure 1 A core processing flowchart of a GPU load balancing system based on primitive broadcasting and fragment partitioning is provided as an embodiment of the present invention;

[0033] Figure 2 A schematic diagram illustrating the overall working principle of the GPU rendering pipeline;

[0034] Figure 3 This is a flowchart illustrating the phased primitive assembly and broadcasting workflow.

[0035] Figure 4 A diagram illustrating the broadcast distribution order;

[0036] Figure 5 This is a schematic diagram of a tile-based scanning process during the rasterization stage.

[0037] Figure 6 A diagram illustrating the configuration of different regions for a Tile segment;

[0038] Figure 7 This is a flowchart of a GPU load balancing method based on primitive broadcasting and fragment partitioning, provided as an embodiment of the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In addition, the technical features of the various embodiments or individual embodiments provided by the present invention can be arbitrarily combined with each other to form feasible technical solutions. Such combinations are not constrained by the order of steps and / or structural composition patterns, but must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0040] Before describing the technical solution of the present invention, the terms and concepts involved in the present invention will be explained as follows:

[0041] Cluster: A complete rendering pipeline unit in a graphics processor, containing a complete graphics rendering pipeline, including stages such as vertex shading, primitive assembly, clipping, hidden surface removal, viewport transformation, rasterization, and fragment shading. Each cluster can independently complete the rendering process from vertex to fragment.

[0042] Primitive: The basic geometric element in graphics rendering, usually referring to a triangle, which is defined by three vertices and their connection relationships.

[0043] Primitive Assembly: The process of assembling vertex data output by the vertex shader into basic geometric primitives such as triangles, line segments, or points according to their topological structure.

[0044] PosPA (Position Primitive Assembly): A new term defined in this invention, referring to assembling only the positional information of primitives, namely the X, Y, and Z coordinates of the three vertices in screen space. This stage does not involve attribute data such as texture coordinates, normal vectors, and vertex colors.

[0045] FinalPA (Final Primitive Assembly): A new term defined in this invention, referring to the assembly of all attribute information of primitives, including position coordinates, texture coordinates, normal vectors, vertex colors, etc., outputting complete primitives for use by subsequent pipelines.

[0046] Broadcast distribution: A distribution method that sends the same data to all receivers simultaneously, unlike distribution after filtering by address or condition.

[0047] Tile: A tile that can contain multiple tiles.

[0048] Rasterization: The process of converting primitives into discrete fragments on the screen, including scan conversion, interpolation, and other operations.

[0049] Frame buffer: A storage area located in video memory (VRAM / DRAM) that stores the complete image data that will eventually be sent to the display screen.

[0050] When multi-cluster GPUs handle fragment-intensive rendering tasks, the uneven distribution of primitives within the screen space leads to a severe imbalance in the load during the fragment scanning and processing stages. This results in a "weakest link" effect, where some clusters are overloaded while others are idle, making it difficult to improve the overall rendering throughput. Most existing solutions are based on a "primitive distribution / assignment" mechanism, which requires introducing complex primitive remapping caches, distribution networks, load monitoring, or inter-chip interconnect logic modules between geometry processing and rasterization, resulting in high circuit complexity and significant verification challenges.

[0051] To address this, this invention proposes a GPU load balancing system design method based on primitive broadcasting and fragment partitioning. A phased processing mechanism is introduced during the primitive assembly stage. In the first stage, each cluster independently performs primitive position assembly (PosPA). In the second stage, the position assembly results of all clusters are broadcast to all clusters. In the third stage, each cluster performs complete primitive attribute assembly (FinalPA) based on the primitive position list, as well as operations such as clipping, backface culling, and triangle creation. Finally, in the rasterization stage, fragment region processing is performed based on the cluster configuration to achieve fragment-level load balancing.

[0052] Figure 1 The diagram illustrates the core processing flowchart of a GPU load balancing system based on primitive broadcasting and fragment partitioning according to an embodiment of the present invention. The GPU load balancing system mainly includes multiple rendering pipeline units (Cluster) and a broadcast module. Each Cluster includes a position primitive assembly module (PosPA), a complete attribute primitive assembly module (FinalPA), and a rasterization module.

[0053] The functions of each module in this GPU load balancing system are as follows:

[0054] Each of the aforementioned clusters contains a vertex coloring module, which is used to color the primitive vertices and output the data for each vertex.

[0055] The PosPA unit within each Cluster is used to read the vertex position information from each vertex data and assemble it into a primitive position list;

[0056] The broadcast module is used to collect the list of primitive locations of all the clusters and distribute the collected complete list of primitive locations to the FinalPA units of all the clusters.

[0057] The FinalPA unit within each Cluster is used to read complete vertex attribute information from each vertex data according to the received complete primitive position list, perform primitive attribute assembly, and send the attribute-assembled primitives to the rasterization module within the Cluster.

[0058] The rasterization modules within each cluster are used to perform rasterization processing on the received primitives, and different rasterization modules generate fragments of different regions within the same primitive tile according to their respective configuration information.

[0059] Among them, see Figure 1 After the vertex shading module in each cluster completes the vertex shading, the PosPA stage generates a primitive position list. Then, the PosPA primitive position list results of each cluster are collected and broadcast synchronously to all clusters. In the FinalPA stage, each cluster assembles all primitive attributes based on the primitive position list, and then performs all stages from hidden surface removal to triangle creation in the traditional pipeline. When rasterization is performed, this invention performs fragment region processing, generating only fragments within a specific region. Finally, fragment shading and subsequent pipeline stages are performed.

[0060] Figure 2 The diagram illustrates the overall working principle of the GPU rendering pipeline. The PosPA unit, FinalPA unit, broadcast module, and fragment partitioning processing within the rasterization module are all implemented using separate circuit designs. The complete data flow is as follows:

[0061] The vertex shading (vertex shading, tessellation shading, and geometry shading) outputs within each cluster are stored in a unified cache (vertex cache). Simultaneously, the corresponding vertex IDs within each cluster are sent to the PosPA unit. The PosPA unit within each cluster reads the position of each vertex after vertex shading based on the vertex ID and assembles it into a primitive position list. The broadcast module collects the primitive position lists from all clusters and aggregates these scattered lists into a complete primitive position list, broadcasting it to the FinalPA units in all clusters. At this point, all FinalPA units in all clusters receive the complete primitive position list. The FinalPA unit reads the complete vertex attributes from the vertex cache of the vertex shading results based on the complete primitive position list information and performs primitive attribute assembly. The primitive attribute assembly results are sent as a data stream to the subsequent hidden surface removal, clipping, viewport transformation, triangle creation, and rasterization modules. In the rasterization module, rasterization uses a tile-based scanning method and then processes fragments in different regions of the tile according to the configuration information.

[0062] The workflow of the phased primitive assembly and broadcast module of this invention is as follows: Figure 3 As shown, the PosPA units within each Cluster execute different primitive position assemblies in parallel and independently, while the FinalPA units execute the same primitive attribute assemblies in parallel. Each Cluster has complete primitive data when entering the rasterization stage, so that the fragment output is no longer limited by the primitive allocation method, but is independently determined by the fragment ownership judgment in the rasterization stage, which is completely unrelated to the triangle shape, size, and screen distribution.

[0063] The Position Assembly (PosPA) module only processes primitive position information (i.e., vertex position information XYZW, where XYZ is the 3D position of the vertex and W is the scaling factor), and does not involve attribute data such as texture coordinates, normals, and vertex colors. This is because when there are too many primitive vertex attributes, transmitting primitive attribute data requires a very large transmission and memory access overhead. Transmitting only primitive position attributes in the broadcast module significantly reduces the amount of data. After broadcasting, each cluster reassembles all attribute data in the FinalPA stage.

[0064] The image rendering pipeline executes strictly in the order of vertex shading, primitive assembly, triangle building, and rasterization. The order in which primitives are processed in each stage of the pipeline must be strictly maintained; this is a fundamental prerequisite for correct graphics rendering. Generally, each primitive is assigned an incrementing primitive ID (Primitive_ID) upon entering the pipeline, reflecting its order in the original rendering process. Therefore, when the broadcast module aggregates the position assembly results from each cluster, it must also maintain the original order of the primitives. During the PosPA stage, when assembling primitive positions, each cluster's primitive list needs to include this ID information, and the broadcast module must strictly distribute primitives according to their ID order, ensuring that subsequent primitive rendering also follows the original primitive order.

[0065] like Figure 4 The diagram illustrates the broadcast distribution order for four cluster scenarios. Cluster 0 is assigned primitive IDs 0, 4, and 8; Cluster 1 is assigned primitive IDs 1, 5, and 9; Cluster 2 is assigned primitive IDs 2, 6, and 10; and Cluster 3 is assigned primitive IDs 3 and 7. To ensure synchronization, the broadcast module waits until all primitive IDs of a frame have been collected before distributing the complete primitive location information list. The primitive location information lists are arranged in order.

[0066] The FinalPA unit reads complete vertex attributes from the vertex cache of the vertex class shading result based on the complete primitive position list information and performs primitive attribute assembly. The primitives after attribute assembly are then subjected to subsequent routine processing. When the rasterization stage is reached, this invention adopts a tile-based scanning method and then processes different regions within the tile according to their respective configuration information.

[0067] The detailed scanning process is as follows: Figure 5 As shown, after the rasterization modules in each cluster receive primitives, they first need to obtain the effective fragment tiles covering the primitives. The tile size during scanning can be flexibly configured, and the tile size affects the scanning granularity, mainly determined by the size of the primitives in the rendering task. Here, a 4x4 tile size is used as an example. The scan starts at the vertex with the largest y-coordinate of the triangle, using this vertex as the corner point of the first tile. After scanning left and right to obtain all effective tiles in that row, the scan moves upward from the leftmost effective tile in that row, and so on, scanning all rows. After obtaining the effective tiles, it is also necessary to scan the interior of the tiles to obtain the effective fragments, such as... Figure 5 As shown, within a Tile, the scan proceeds from the bottom left corner to the top left corner.

[0068] During the internal scanning of a tile, the rasterization modules within different clusters will also process different segment regions of the tile according to configuration information, such as... Figure 6 The image shows a valid 4x4 tile containing 16 segments, with different segment regions configured for each cluster.

[0069] Specifically, each Cluster stores a region allocation map in its configuration register. This map records the offset positions of all segments that the current Cluster is responsible for within a Tile. Taking a 4x4 Tile as an example, the offset positions are represented by (blockX, blockY), both ranging from 0 to 3, resulting in 16 configurable segment regions. For instance, Cluster0 can be configured with offset positions (0,0), (1,0), (0,1), and (1,1), representing a continuous 2x2 region in the upper left corner of the Tile; Cluster1 can be configured with offset positions (2,0), (3,0), (2,1), and (3,1), representing a continuous 2x2 region in the upper right corner of the Tile; Clusters 2 and 3 are similarly configured with continuous 2x2 regions in the lower left and lower right corners of the Tile, respectively. Under this configuration, the Tile is divided into four continuous 2x2 sub-blocks, with each Cluster responsible for one sub-block. Alternatively, a checkerboard staggered configuration can be used: Cluster 0 handles (0,0), (2,0), (0,2), (2,2); Cluster 1 handles (1,0), (3,0), (1,2), (3,2); Cluster 2 handles (0,1), (2,1), (0,3), (2,3); and Cluster 3 handles (1,1), (3,1), (1,3), (3,3). In this configuration, the fragment positions of each Cluster are evenly distributed within the tiles. Multiple configuration methods are supported, and users can configure the most suitable solution according to their target application scenario.

[0070] See Figure 7 This paper illustrates a GPU load balancing method based on primitive broadcasting and fragment partitioning according to an embodiment of the present invention, applied to the aforementioned GPU load balancing system based on primitive broadcasting and fragment partitioning. The method includes:

[0071] Step 1: Perform vertex shading processing in parallel within each Cluster and output the data for each vertex.

[0072] Step 2: Perform position primitive assembly processing in parallel within each Cluster, read the vertex position information in each vertex data, and assemble it into a primitive position list;

[0073] Step 3: Collect the list of primitive locations for all the clusters, and distribute the collected complete list of primitive locations to all the clusters;

[0074] Step 4: Each Cluster reads complete vertex attribute information from each vertex data and performs primitive attribute assembly based on the received complete primitive position list;

[0075] Step 5: Each Cluster performs rasterization processing on the primitives after attribute assembly, and different Clusters generate fragments in different areas within the same primitive tile according to their respective configuration information.

[0076] Each cluster generates fragments of different regions within a tile covered by the same primitive, based on its corresponding configuration information, including:

[0077] Each Cluster reads the region allocation mapping table stored within its own Cluster, which records the offset positions of all segments that the Cluster is responsible for processing within a Tile.

[0078] Each Cluster generates a segment at the corresponding offset position within the Tile based on the region allocation mapping table.

[0079] It is understood that the GPU load balancing method based on primitive broadcasting and fragment partitioning provided by the present invention corresponds to the GPU load balancing system based on primitive broadcasting and fragment partitioning provided in the foregoing embodiments. The relevant technical features of the GPU load balancing method based on primitive broadcasting and fragment partitioning can be referred to the relevant technical features of the GPU load balancing system based on primitive broadcasting and fragment partitioning, and will not be repeated here.

[0080] This invention provides a GPU load balancing system and method based on primitive broadcasting and fragment partitioning. It proposes a distribution processing mechanism that splits primitive assembly into two stages: PosPA and FinalPA. Furthermore, it achieves fragment load balancing across the entire GPU through regional fragment scanning output, effectively solving problems such as load imbalance and hardware complexity in fragment-intensive rendering tasks on multi-cluster GPUs. Compared to existing technologies, it has the following advantages:

[0081] First, in terms of hardware design complexity, this invention does not require the introduction of complex dynamic scheduling and real-time monitoring mechanisms. All circuit structures are clear, simple, and easy to implement. It only requires adding a broadcast module and some rasterization regional processing judgment logic to the existing rendering pipeline.

[0082] Secondly, in terms of load balancing performance, since the number of segments processed by each cluster is determined by the configuration information received during the rasterization stage and is completely independent of the screen distribution of primitives in the scene, the segment processing volume of each cluster can be approximately equal to the total number of segments divided by the number of clusters, achieving complete independence from the shape, size, and screen position of the triangle, thus achieving theoretically optimal segment-level load balancing.

[0083] Finally, regarding synchronization and communication between Multi-Clusters, this invention eliminates the need for inter-Cluster communication. Furthermore, after rasterization and regional processing, the positions of fragments in each Cluster are independent of each other. This ensures that no conflicts occur when subsequent Cluster fragments are colored and written to the frame buffer, facilitating the consistency of internal data in the GPU.

[0084] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0085] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0086] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0087] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1The function specified in one or more boxes.

[0088] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0089] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0090] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A GPU load balancing system based on primitive broadcasting and fragment partitioning, characterized in that, It includes multiple rendering pipeline units (Cluster) and broadcast modules. Each Cluster contains a Position Primitive Assembly (PosPA) unit, a Final Primitive Assembly (FinalPA) unit, and a rasterization module. Each of the aforementioned clusters contains a vertex coloring module, which is used to color the primitive vertices and output the data for each vertex. The PosPA unit within each Cluster is used to read the vertex position information from each vertex data and assemble it into a primitive position list; The broadcast module is used to collect the list of primitive locations of all the clusters and distribute the collected complete list of primitive locations to the FinalPA units of all the clusters. The FinalPA unit within each Cluster is used to read complete vertex attribute information from each vertex data according to the received complete primitive position list, perform primitive attribute assembly, and send the attribute-assembled primitives to the rasterization module within the Cluster. The rasterization modules within each cluster are used to perform rasterization processing on the received primitives, and different rasterization modules generate fragments of different regions within the same primitive tile according to their respective configuration information.

2. The system according to claim 1, characterized in that, The vertex shading modules within each cluster store the shading data of each vertex in a vertex cache and send each vertex ID to the PosPA unit within the cluster. The PosPA unit reads the vertex position information from the vertex cache for each vertex ID, and assembles a primitive position list based on the vertex position information of each primitive.

3. The system according to claim 1, characterized in that, The broadcast module is also used to collect and distribute the primitive position lists of each Cluster according to the original order in which primitives enter the rendering pipeline, so that rendering is performed according to the original order of primitives.

4. The system according to claim 1, characterized in that, The rasterization modules within each cluster perform rasterization processing using a tile-based scanning method, specifically including: Starting from the tile containing the largest Y-coordinate vertex of the primitive, the scan proceeds row by row to obtain the valid tiles covered by the primitive. Then, a segment-by-segment scan is performed within each valid tile to generate the segment within the tile.

5. The system according to claim 1, characterized in that, Each Cluster also stores a region allocation mapping table, which records the offset positions of all fragments that the Cluster is responsible for processing within a fragment tile; The rasterization module is specifically used to generate a segment at the corresponding offset position within the Tile based on the region allocation mapping table.

6. The system according to claim 5, characterized in that, The region allocation mapping table can be dynamically configured, allowing the segment regions that different clusters are responsible for within a Tile to be dynamically adjusted to adapt to different load balancing strategies.

7. The system according to claim 6, characterized in that, The load balancing strategy includes: The tile is divided into multiple contiguous sub-blocks, with each cluster responsible for processing one of these sub-blocks; or, A checkerboard pattern is used to ensure that the segments each cluster is responsible for within a tile are evenly distributed.

8. The system according to claim 1, characterized in that, The PosPA unit only reads and processes the screen space coordinates of the vertices as vertex position information; the FinalPA unit is used to read and process all vertex attribute information, including vertex screen space coordinates, texture coordinates, normal vectors, and vertex colors.

9. A GPU load balancing method based on primitive broadcasting and fragment partitioning, applied to the system as described in any one of claims 1 to 8, characterized in that, include: Vertex shading processing is performed in parallel within each Cluster, and data for each vertex is output. Within each Cluster, position primitive assembly processing is performed in parallel, reading vertex position information from each vertex data and assembling it into a primitive position list; Collect the list of primitive locations for all said clusters, and distribute the collected complete list of primitive locations to all said clusters; Each Cluster reads complete vertex attribute information from each vertex data and performs primitive attribute assembly based on the received complete primitive position list; Each Cluster performs rasterization processing on the primitives after attribute assembly, and different Clusters generate fragments in different regions within the same Tile block covered by the primitive according to their respective configuration information.

10. The method according to claim 9, characterized in that, Each cluster generates fragments of different regions within a tile covered by the same primitive, based on its corresponding configuration information, including: Each Cluster reads the region allocation mapping table stored within its own Cluster, which records the offset positions of all segments that the Cluster is responsible for processing within a Tile. Each Cluster generates a segment at the corresponding offset position within the Tile based on the region allocation mapping table.

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