A tree parallel state merging method, device and circuit based on combination law
Patent Information
- Application Number
- CN202610842080.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-11
- Publication Date
- 2026-10-13
AI Technical Summary
[0007]本发明所要解决的技术问题在于：提供一种基于结合律的树形并行状态合并方法、装置及电路，解决了大规模状态合并中效率低下、结果依赖合并顺序且难以并行化的技术问题
[0048]本发明的有益效果是：本发明将满足结合律的状态合并规则与树形数据结构相结合，通过自底向上逐层并行合并，将N个状态的合并时间复杂度从O(N)降至O(log N)，并确保合并结果与计算顺序无关、唯一确定；树形结构支持各层级内部节点并行合并，充分利用多核并行能力；增量更新仅沿祖先路径传播，动态维护开销低；动态扩缩容实时适配计算规模，保持最优效率；该方法可硬连线为查找表或组合逻辑电路，单周期完成合并，面积小、延迟低，由此，本发明为大规模并行计算、分布式系统及高可靠实时应用提供了高效、确定、可扩展的状态合并方案。
Smart Images
Figure CN122903210A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a tree-based parallel state merging method, apparatus, and circuit based on associative law, belonging to the field of computer algorithms and parallel computing technology. Background Technology
[0002] In parallel computing systems, especially in scenarios involving uncertainty state management, the local TC (Uncertainty Container) states generated by multiple computing units need to be merged into a global state to determine the overall uncertainty convergence of the system. Typical applications include uncertainty propagation analysis in large-scale scientific computing, gradient state aggregation in distributed machine learning training, and multi-source sensor data fusion in IoT edge computing. However, as the number of computing units increases to hundreds or thousands or even more, the TC state merging process faces severe performance challenges.
[0003] In existing technologies, merging TC states primarily employs a linear sequential merging method, which involves sequentially merging the local TC state of each computational unit with the currently accumulated global state until all computational units have been traversed. This method has a time complexity of O(N), where N is the number of computational units. In large-scale parallel computing scenarios, the overhead of linear merging becomes a bottleneck for system performance. More seriously, if the merging rules themselves do not satisfy the associative law, the result of linear merging will depend on the merging order of computational units, leading to different computational paths potentially resulting in different global states. This contradicts the independence and determinism requirements of parallel computing. Furthermore, the linear merging process itself is difficult to parallelize, failing to fully utilize the parallel computing capabilities of modern multi-core processors, further exacerbating the performance problem.
[0004] At the data structure level, existing technologies generally use flat arrays to manage the TC states of each computational unit. This flat organization lacks a hierarchical structure and cannot utilize the spatial locality of state access for caching optimization; at the same time, the fixed-size state array is difficult to dynamically adapt to real-time changes in the number of computational units, resulting in poor scalability. At the algorithm level, the complex state dependencies lead to high implementation complexity of the merging algorithm, and there is a lack of theoretical guarantees to ensure the convergence of the merging results.
[0005] More importantly, in engineering practices such as high-performance computing and real-time data analysis, the merging of TC states must be completed in an extremely short time to support the rapid convergence and iteration of large-scale parallel tasks. However, existing linear merging schemes suffer from linearly increasing time overhead when the number of computing units is large, making the system unable to meet real-time requirements.
[0006] Therefore, there is an urgent need for a TC state merging method that can reduce the merging time complexity to logarithmic level, support parallel execution, and be independent of the merging order. Summary of the Invention
[0007] The technical problem to be solved by the present invention is to provide a tree-based parallel state merging method, device and circuit based on the associative law, which solves the technical problems of low efficiency, result dependence on merging order and difficulty in parallelization in large-scale state merging.
[0008] The technical problem to be solved by this invention is achieved by the following technical solution:
[0009] A tree-based parallel state merging method, apparatus, and circuit based on associative law includes the following steps:
[0010] Obtain the local states generated by each of the multiple computing units, wherein the states are selected from a preset finite set of states;
[0011] The multiple local states are organized into a tree data structure, wherein each leaf node of the tree data structure corresponds to a computing unit and stores its local state, and each non-leaf node is used to store the merging result of its child node states.
[0012] According to the preset merging rules that satisfy the associative law, the tree data structure is merged layer by layer from the leaf node layer to the root node. Multiple non-leaf nodes in each layer execute the merging rules in parallel and store the merging results in the corresponding nodes.
[0013] The state stored in the root node is output as the global merge result.
[0014] The present invention is further configured such that: the tree data structure is a complete binary tree structure; the step of organizing the multiple local states into a tree data structure includes: allocating a continuous one-dimensional array in physical memory with an index starting from 0 to store all nodes, wherein for an internal node with an index of i in the one-dimensional array, the index of its left child node is 2i+1, the index of its right child node is 2i+2, and the index of its parent node is ⌊(i-1) / 2⌋.
[0015] The present invention is further configured such that: the preset merging rule satisfies the associative law, the commutative law, and idempotency, and the finite state set contains an identity element; the finite state set includes a first state representing a deterministic value, a second state representing arithmetic uncertainty, a third state representing semantic uncertainty, and a fourth state representing a mixture of the second and third states; the merging rule is configured as follows:
[0016] The first state is merged with any state, and the result is that state.
[0017] The second state is merged with the second state, and the result is the second state;
[0018] The third state is merged with the third state to obtain the third state;
[0019] The second state is combined with the third state to form the fourth state;
[0020] The fourth state is merged with any other state, and the result remains the fourth state.
[0021] The present invention is further configured such that: the step-by-step merging from the leaf node layer to the root node specifically includes: on a layer-by-layer basis, through a thread pool or parallel loop operation, multiple internal nodes in the current layer are assigned to multiple computing threads for parallel execution; each computing thread accesses non-overlapping memory address regions in the one-dimensional array in parallel.
[0022] The present invention is further configured to include an incremental update step:
[0023] When the local state of any computing unit changes, the change is only updated to the corresponding leaf node;
[0024] Starting from the leaf node, along its single ancestor path to the root node, the merging rule is re-executed layer by layer upwards to update the state of each ancestor node on the path;
[0025] During the upward recalculation process, if the recalculated state of an ancestor node is the same as its original state, the update propagation to higher-level nodes is terminated prematurely.
[0026] The present invention is further configured to include a dynamic expansion / shrinkage step:
[0027] Real-time detection of the number N of active computing units;
[0028] Calculate the minimum binary tree depth H required to fully accommodate N leaf nodes, where H is the smallest integer that satisfies 2 to the power of H greater than or equal to N;
[0029] A tree data structure with 2^H leaf nodes and 2^(H+1) minus 1 total nodes is dynamically allocated. The first N leaf nodes are assigned to active computing units, and the remaining leaf nodes are marked as idle.
[0030] The present invention is further configured to include a concurrency safety control mechanism:
[0031] Configure a global read-write lock for the tree-shaped data structure;
[0032] When concurrently updating leaf nodes, acquire the read lock of the global read-write lock;
[0033] When an update propagation is triggered and a merge operation is performed upwards to modify an internal node or the root node, a lock escalation mechanism is implemented to release the read lock and acquire the write lock of the global read-write lock.
[0034] The present invention is further configured to include a distributed cross-node extension mechanism:
[0035] The tree-like data structure is extended into a distributed merged tree covering multiple physical nodes, with each physical node maintaining a local subtree;
[0036] Each node determines its parent and child nodes based on the network topology, and receives the status of the child nodes, merges them, and sends them to the parent node.
[0037] After completing the global merge, the root node broadcasts the final state to the entire network.
[0038] A tree-structured parallel state merging device based on associative law, characterized in that it comprises:
[0039] The state acquisition module is used to acquire the local states generated by each of the multiple computing units, wherein the states are selected from a preset finite set of states.
[0040] A tree organization module is used to organize the multiple local states into a tree data structure, wherein each leaf node of the tree data structure corresponds to a computing unit and stores its local state, and each non-leaf node is used to store the merging result of its child node states.
[0041] The parallel merging module is used to merge the tree data structure layer by layer from the leaf node layer to the root node according to the preset merging rules that satisfy the associative law. In each layer, multiple non-leaf nodes execute the merging rules in parallel and store the merging results in the corresponding nodes.
[0042] The result output module is used to output the state stored in the root node as the global merge result.
[0043] A parallel state merging circuit based on associative law, characterized in that it includes:
[0044] A storage array is used to store a tree-like data structure, wherein each leaf node of the tree-like data structure corresponds to a computing unit and stores its local state, and each non-leaf node is used to store the merged result of the states of its child nodes;
[0045] The state merging logic unit includes a read-only memory lookup table or a gate-level circuit that implements bitwise OR operation. The lookup table or bitwise OR gate is hardwired to implement a preset merging rule that satisfies the associative law. It is configured to receive the states of two child nodes and output the merged state of the parent node.
[0046] The parallel control unit is configured to schedule multiple state merging logic units to process multiple internal nodes at the same level in parallel within the same clock cycle.
[0047] The output interface is used to output the global merge result stored in the root node.
[0048] The beneficial effects of this invention are as follows: This invention combines the state merging rule that satisfies the associative law with a tree data structure. By merging in parallel layer by layer from bottom to top, the time complexity of merging N states is reduced from O(N) to O(log N), and the merging result is uniquely determined and independent of the calculation order. The tree structure supports parallel merging of internal nodes at each level, making full use of multi-core parallel capabilities. Incremental updates only propagate along the ancestor path, resulting in low dynamic maintenance overhead. Dynamic scaling adapts to the computational scale in real time, maintaining optimal efficiency. This method can be hardwired into a lookup table or combinational logic circuit, completing the merging in a single cycle with small area and low latency. Therefore, this invention provides an efficient, deterministic, and scalable state merging scheme for large-scale parallel computing, distributed systems, and highly reliable real-time applications. Attached Figure Description
[0049] Figure 1 This is a schematic diagram of the main flow of the method of the present invention.
[0050] Figure 2 This is the tree structure and array mapping diagram of the present invention.
[0051] Figure 3 This is a schematic diagram of the parallel merging process of the present invention.
[0052] Figure 4 This is the incremental update and early termination diagram of the present invention.
[0053] Figure 5 This is a diagram of the dynamic expansion and contraction mechanism of the present invention.
[0054] Figure 6 This is a schematic diagram of the modules of the device of the present invention.
[0055] Figure 7 This is the overall architecture diagram of the circuit of the present invention. Detailed Implementation
[0056] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0057] In modern massively parallel computing systems, such as scientific computing clusters running climate simulations, parameter servers training deep neural networks, or IoT edge computing platforms performing real-time data fusion, it is often necessary to efficiently and deterministically merge the local states generated by hundreds or thousands of independent computing units into a global state. This state can represent the confidence level of computing reliability, the credibility of the data source, or, as in a four-state ternary computing system, the TC (uncertainty container) state.
[0058] For example, a weather model might divide a global grid into 1024 regions, which are then simulated in parallel by 1024 CPU cores or nodes. Each core generates a local state after completing the calculations for its region (e.g., TC_NONE indicates deterministic calculation, TC_CARRY indicates arithmetic carry, and TC_UNCERTAIN indicates unreliable input data). The system needs to quickly merge these 1024 local states into a single global state to determine the overall uncertainty of the entire simulation process.
[0059] Traditional linear sequential merging methods merge each local state with the accumulated global state variable in turn, resulting in a time complexity of O(N). When N=1024, this requires 1023 merging operations, which is insufficient for real-time requirements. If the state merging rules do not satisfy the associative law, the merging order will directly affect the final result, leading to uncertainty in the computational outcome, which is unacceptable for parallel systems requiring strict determinism. Furthermore, the linear merging process is inherently serial and cannot utilize the parallel computing capabilities of modern multi-core processors.
[0060] To address the aforementioned technical problems, this application provides a tree-based parallel state merging method based on associative law, such as... Figure 1 As shown, it includes:
[0061] First, the state acquisition module collects the local states generated by multiple computing units in the system.
[0062] The computing unit can be a physical core in a multi-core central processing unit, a streaming multiprocessor in a graphics processing unit, a logic block in a field-programmable gate array, or an independent node in a distributed computing cluster. Each computing unit generates a local state after executing the assigned subtask, and the state is selected from a preset finite set of states.
[0063] In a typical implementation of a four-state ternary computation system, the finite set of states includes: a first state (TC_NONE) for representing a deterministic value, a second state (TC_CARRY) for representing uncertainty arising from arithmetic operations (such as carry), a third state (TC_UNCERTAIN) for representing uncertainty arising from data semantics (such as uninitialized data), and a fourth state (TC_MIXED) for representing a mixture of the second and third states.
[0064] These four states are encoded using 2-bit binary numbers: TC_NONE is 00, TC_CARRY is 01, TC_UNCERTAIN is 10, and TC_MIXED is 11, making it easy to attach the state as metadata to the data word.
[0065] After obtaining multiple local states, the tree organization module is responsible for organizing them into a tree data structure. Each leaf node corresponds to a computation unit and directly stores the local state generated by that computation unit; each non-leaf node (including internal nodes and the root node) is used to store the merged result of its child node states.
[0066] To maximize storage efficiency and cache locality, in a preferred embodiment, the tree data structure is implemented as a complete binary tree and allocated in physical memory as a contiguous one-dimensional array.
[0067] Specifically, such as Figure 2 As shown, the system first calculates the minimum complete binary tree depth H that can accommodate N leaf nodes based on the number of computing units N. H is the smallest integer that satisfies 2^H ≥ N. Then, a contiguous memory space is allocated to store a total of (2^(H+1)-1) nodes. The root node is stored at array index 0. For any node with index i, the left child node index is 2i+1, the right child node index is 2i+2, and the parent node index is ⌊(i-1) / 2⌋.
[0068] This array-based storage avoids the additional memory overhead and indirect addressing latency caused by pointers. When accessing nodes at the same level, the access to the same level corresponds to continuous or equally spaced regions in the array, which improves the CPU cache hit rate and prefetch efficiency.
[0069] In a multi-core processor environment, to prevent cache thrashing caused by multiple cores concurrently writing to the same cache line, the tree node data structure is aligned according to the processor's cache line size during memory allocation. Specifically, a memory allocation function is used to allocate contiguous memory blocks whose size is an integer multiple of the node structure size and aligned to 64-byte boundaries. The compiler's alignment properties ensure that each node exclusively occupies one or more complete cache lines, preventing nodes accessed by different threads from being allocated to the same cache line.
[0070] In a Non-Unified Memory Access (NUMA) architecture, cross-CPU memory access latency is much higher than local memory access latency. To address this, subtree merging tasks are assigned based on the physical topology of NUMA nodes: First, leaf nodes are grouped according to the NUMA affinity of their respective computing units. Each NUMA node independently constructs its local subtree and performs local merging within the node to generate a representative state for that node. Subsequently, the representative states of all NUMA nodes are converged to the memory domain of the root node for final reduction. This strategy reduces the number of cross-node memory accesses from O(N) to O(P), where P is the number of NUMA nodes.
[0071] After constructing the tree-like data structure, the parallel merging module performs merging operations layer by layer from the leaf nodes towards the root node, based on a pre-defined state merging rule that satisfies the associative law. This merging rule satisfies the associative, commutative, and idempotent laws, and the finite set of states contains an identity element.
[0072] In an embodiment specifically designed for a four-state ternary computing system, the merging rule is configured as follows:
[0073] (1) The first state (TC_NONE, deterministic) is merged with any state, resulting in that state. The deterministic value does not introduce or change uncertainty.
[0074] (2) The second state (TC_CARRY, arithmetic uncertainty) is merged with itself, resulting in the second state. Pure arithmetic uncertainty remains arithmetic uncertainty after combination.
[0075] (3) The third state (TC_UNCERTAIN, semantic uncertainty) is merged with itself, resulting in the third state.
[0076] (4) The second state and the third state are merged to form the fourth state (TC_MIXED, mixed uncertainty). When two uncertainties with different properties meet, an uncertainty representing a "mixed" state is generated.
[0077] (5) The fourth state is merged with any state (including itself), and the result remains the fourth state. Mixed uncertainty has an absorptive property; once it occurs, it cannot be downgraded or eliminated.
[0078] The above rules, denoted by ⊕, represent the merge operator and satisfy closure, associativity ((a⊕b)⊕c = a⊕(b⊕c)), commutativity (a⊕b = b⊕a), and idempotency (a⊕a = a), forming a commutative monoid with TC_NONE as its identity element. The merge rules are summarized in the following truth table:
[0079]
[0080] Since the above merging rules satisfy the associative law, a tree structure can be safely used for parallel merging, and the final result is independent of the merging path.
[0081] During the merging process, the system starts processing from the level above the leaf nodes (the lowest level of internal nodes). Internal nodes at the same level in the tree structure are computationally independent (each node depends only on its two child nodes, and the child node sets of different nodes do not overlap), therefore, the merging operations on these nodes can be safely executed in parallel. In a software implementation based on a multi-core CPU, the parallel merging module starts a thread pool or uses a parallel programming model such as OpenMP. For the current level that needs to be merged, the system identifies all internal nodes that need to be computed at that level, allocates these nodes equally to idle threads in the thread pool, and each thread independently handles the merging computation of one or more nodes. Each thread reads the states of its two corresponding child nodes, calculates the state of the parent node according to the merging rules, and writes the result back to the array position corresponding to the parent node.
[0082] The indices of nodes at the same level in a complete binary tree form a continuous interval in a continuous one-dimensional array. For a level of depth L (root node depth is 0), the node index range is [2^L-1, 2^(L+1)-2]. This continuous index interval is evenly divided into blocks according to the number of active threads, and each thread is assigned a sub-interval. The threads address independently by adding an offset to the starting index. Since the array index sub-intervals processed by different threads do not overlap, each thread can read and write in parallel without conflict.
[0083] like Figure 3 As shown, during the layer-by-layer merging process, it is necessary to ensure that the merging of the next layer can only begin after all the next layer has been merged. In the software implementation, this is achieved by setting a multi-threaded synchronization barrier: after each layer is merged, the main thread calls a synchronization function to wait for all worker threads to reach the barrier point, then updates the current level pointer and starts the merging of the next layer. In the hardware implementation, the parallel control unit collects the ready signals output by all logic units in the lower layer, and triggers the clock tick of the next level after all are ready.
[0084] The above process starts from the level above the leaf node and proceeds upwards layer by layer. When the merging reaches the root node (level 0), the state stored in the root node is the global merging result of the local states of all computing units. The result output module reads the state of the root node and outputs it as the final result, for example, by writing it to the global state register or as the basis for conditional branches.
[0085] In addition to full merging, this method also provides an efficient incremental update mechanism to deal with scenarios where the local state of computing units changes frequently.
[0086] like Figure 4As shown, when the local state of a computing unit in the system changes from an old value to a new value, the system performs the following incremental update steps:
[0087] First, the tree organization module quickly locates the leaf node corresponding to the computing unit and updates its stored state to the new value.
[0088] Then, starting from the updated leaf node, the system re-executes the merge rule layer by layer upwards along the single ancestor path of its parent node, grandparent node and so on up to the root node.
[0089] In a contiguous one-dimensional array storage structure, for a node with index i, its sibling node index can be determined as follows: Since the left child node index is 2i+1 (always odd) and the right child node index is 2i+2 (always even), if i is odd, the node is the left child node, and its sibling (right child node) index is i+1; if i is even, the node is the right child node, and its sibling (left child node) index is i-1. The parent node index is ⌊(i-1) / 2⌋. During incremental updates, starting from the changing leaf node index i0, the following process is repeated: read the state of i and its sibling nodes, merge them, and write them to the parent node p=⌊(i-1) / 2⌋, then set i=p, until p=0.
[0090] During the upward propagation process, the system compares the new state recalculated by each ancestor node with its original old state. If the recalculated state of a certain level node is completely consistent with the state before the update, then the change of the leaf node has not affected the state of that node, and the state of its higher-level ancestor nodes must remain unchanged. At this time, the update propagation is terminated in advance. This mechanism reduces the update overhead of a single point state change from O(N) or O(log N) to O(K), where K is the number of nodes whose states have actually changed on the ancestor path, which is usually much smaller than log N.
[0091] Considering that the size of parallel computing systems may change dynamically (such as computing nodes being dynamically added or removed based on load in an elastic cloud environment), this method provides dynamic scaling steps.
[0092] like Figure 5 As shown, the system monitors the number of active computing units N in real time through a daemon process or periodic task, and performs dynamic adjustments when N increases or decreases significantly.
[0093] First, calculate the minimum complete binary tree depth H required to fully accommodate the current N active computing units as leaf nodes, where H is the smallest integer satisfying 2^H ≥ N;
[0094] Then, a new memory space is allocated to construct a new tree structure with 2^H leaf node slots and 2^(H+1)-1 total nodes. When the new tree is initialized, the first N leaf nodes are mapped to existing active computing units, and the remaining 2^HN leaf nodes are marked as "idle".
[0095] Idle nodes do not participate in computation during the merging process (they can be considered as being in the TC_NONE state, or the idle child node state can be directly used when the parent node is merged based on the idle flag). In this way, the system always runs at the optimal tree height (minimizing log N). When the number of computational units decreases, the logic for shrinking the tree is similar, releasing large blocks of memory that are no longer needed.
[0096] In complex parallel systems, multiple computing units may simultaneously complete computations and attempt to update corresponding leaf nodes and trigger ancestor node updates, resulting in concurrent access conflicts. To address this issue, this method introduces a concurrency safety control mechanism in the software implementation.
[0097] Specifically, the system configures a global read-write lock for the overall tree-like data structure and a finer-grained node-level spinlock for each node in the tree. When a computing unit needs to update its local state, it first acquires the read lock of the global read-write lock (allowing multiple updaters to enter the critical section in parallel), then acquires the node-level spinlock of the corresponding leaf node, performs the state update, and immediately releases the spinlock. After completing the leaf node update, a merge operation needs to be triggered upwards to modify the internal nodes and the root node.
[0098] At this point, lock escalation is required: the current thread first releases the global read lock it holds, and then requests to acquire the write lock (exclusive lock) of the global read-write lock. After acquiring the write lock, since the global write lock has prevented other threads from concurrently accessing the tree structure, the thread can directly update the state of each parent node sequentially along the ancestor path (without needing to acquire node-level spin locks again). After completing the root node update, the global write lock is released.
[0099] During lock upgrades, there's a time window between releasing the read lock and acquiring the write lock. The parent node's state might be updated by other threads first. Therefore, after acquiring the write lock, a second state check is performed: the current state of the parent node is reread and compared with the expected state (the new state calculated by the current thread based on the child nodes). If they match, the update proceeds normally and propagation continues upwards; if they don't match, the update is abandoned, the write lock is released, and the complete merge process restarts from the parent node (instead of starting from the leaf nodes). As an alternative, an update counter can be configured for each node. The counter is incremented during writes, and the counter value is compared during checks; if it changes, a rollback and retry are performed.
[0100] As an alternative to locking mechanisms, lock-free state updates can be achieved using the CPU's atomic compare-and-swap instructions. Since the merging rule satisfies associativity and idempotency (forming a swapping monoid with TC_NONE as the unit element), ancestor node state updates do not require strong consistency locks. The updating thread reads the parent node's current state S_old, calculates the new state S_new = merge(S_old, child_new), and then performs an atomic compare-and-swap operation: if the parent node's state is still S_old, it is updated to S_new; if it has already been updated by another thread, the latest state is read and the merge is recalculated, repeating until successful. This approach avoids thread blocking and context switching, resulting in significant performance improvements in ultra-high concurrency scenarios.
[0101] The above method describes the implementation in a single-machine multi-core environment. Furthermore, this method can also be applied to large-scale computing clusters through a distributed cross-node expansion mechanism. In this scenario, the tree data structure is expanded into a logical merged tree covering multiple physical nodes. Each physical node first maintains a local subtree to merge the local states of its internal computing units (such as CPU cores) to generate the representative state of the node.
[0102] Then, all physical nodes determine their parent and child relationships in the global merge tree based on the preset network topology (such as tree, fat tree, or hypercube) and the roles elected by the distributed coordinator (such as ZooKeeper or etcd). After completing the local merge, each node sends its representative state to its parent node.
[0103] After collecting the states from all child nodes, the parent node merges them using the same associative merging rule and continues sending the merged result to the next higher parent node until it reaches the global root node. The root node calculates the global state representing the entire cluster and then broadcasts this state backward along the merge tree to all child nodes. This distributed merging strategy reduces the communication overhead relative to cluster size from O(N^2) to O(N), and the merging rule satisfies the associative law, allowing intermediate results to be aggregated on any node, thus enhancing the flexibility and fault tolerance of the distributed system.
[0104] like Figure 6 As shown, corresponding to the above method, this application also provides a tree-structured parallel state merging device based on the associative law. The device includes: a state acquisition module for acquiring the local states generated by multiple computing units; a tree organization module for organizing the multiple local states into a tree data structure; a parallel merging module for merging in parallel layer by layer from the leaf node level to the root node according to a preset merging rule that satisfies the associative law; and a result output module for outputting the state stored in the root node as the global merging result.
[0105] like Figure 7 As shown, to achieve higher merging performance, especially in latency-sensitive or power-constrained scenarios, this application also provides an associative law-based parallel state merging circuit that can directly accelerate the above process. This circuit mainly includes a memory array, a state merging logic unit, a parallel control unit, and an output interface.
[0106] The memory array is an on-chip high-speed memory (such as a static random access memory array) used to store tree-like data structures. Its organization corresponds exactly to the continuous one-dimensional array in the aforementioned software implementation, enabling fast random read / write access to any node. The address decoder quickly locates the corresponding memory cell based on the node index provided by the parallel control unit.
[0107] To enable multiple state merging logic units to read child node states in parallel within the same clock cycle, the storage array employs a multi-bank interleaved memory. Each memory bank is equipped with an independent read / write port, allowing different banks to be accessed in parallel. Nodes at the same level in the tree structure are evenly distributed across different memory banks, enabling multiple merging units to simultaneously and conflict-free read their respective required child node data. For N parallel merging units, the number of memory banks is configured as N or 2N to ensure sufficient concurrent bandwidth.
[0108] The state merging logic unit is the core operational component of this circuit. It is a pure combinational logic circuit that directly implements the aforementioned preset merging rules that satisfy the associative law through hard-wired internal connections. This logic unit is configured with two input ports (for receiving the state codes of the left and right child nodes, for example, 2 bits each) and one output port (for outputting the merged parent node state code). The entire merging process is completed within one clock cycle, with extremely low latency.
[0109] In one specific implementation, the state merging logic unit is implemented as a lookup table circuit. Since the input consists of two 2-bit state codes, there are 16 possible combinations. The lookup table can be a 16-word × 2-bit read-only memory (ROM) that pre-stores the merging results corresponding to the truth table.
[0110] In another implementation that pursues minimal area and power consumption, the state merging logic unit can be implemented as a gate-level combinational logic, and the relationship between its output R (R[1] is the high-order bit, R[0] is the low-order bit) and the inputs A[1:0] and B[1:0] is equivalent to a bitwise OR operation:
[0111] R[1] = A[1] ∨ B[1];
[0112] R[0] = A[0] ∨ B[0];
[0113] Here, ∨ represents the logical OR. This logic can be directly implemented using two OR gates, with an area much smaller than a static random access memory unit. It should be noted that this simplified expression is completely equivalent to the truth table of the merging rule, and can be verified by exhaustive search (for example, when A=01 (TC_CARRY) and B=01, R=01; when A=01 and B=10, R=11, consistent with the truth table).
[0114] The parallel control unit is a finite state machine responsible for controlling the entire merging process. Before merging begins, it knows the depth H of the tree structure. In the first clock cycle, it generates the read address of the memory array, reads the left and right child node data corresponding to all internal nodes in the (H-1)th layer (the layer above the leaf node) in parallel, and feeds these data pairs to multiple parallel state merging logic units respectively.
[0115] In the next clock cycle, these logic units complete their calculations simultaneously. Then, the parallel control unit generates write addresses and writes the calculation results back in parallel to the corresponding parent node location in the memory array. This process is repeated layer by layer upwards until the root node is calculated. Since the merging of nodes at each level is completed within one clock cycle, the total number of clock cycles for merging N states (corresponding to a tree of depth H) is... ,Right now .
[0116] Let the depth of the complete binary tree be... The number of leaf nodes is ,satisfy .
[0117] During a full merge, starting from the first... Layer (the layer above the leaf) to the first The root node of the layer needs to be merged. layer.
[0118] The merge operation of all internal nodes within each layer can be performed in parallel, and the time cost of a single layer is constant. .
[0119] Therefore, the total time .
[0120] Compared to linear merging This method is in It has significant performance advantages when the size is large.
[0121] To further improve hardware throughput, pipeline registers are inserted between adjacent levels of the tree merging circuit.
[0122] Specifically, a register is set at the output of the internal node computing unit of each layer to latch the merging result of this layer and pass it to the next layer. This design allows the circuit to process different batches of merging tasks simultaneously in each clock cycle: the bottom layer processes the merging of child nodes of the first batch of data, the middle layer processes the merging of parent nodes of the second batch of data, and the top layer processes the merging of root nodes of the third batch of data. Thus, when the system continuously processes multiple independent state merging requests, the throughput can reach one global merging result output per clock cycle.
[0123] The output interface is a register or latch that outputs the root node to the data bus after the parallel control unit has completed the calculation of the root node. The output interface latches the root node and sends a "merge complete" signal to other parts of the system (such as the CPU's interrupt controller or status register) to indicate that the global merge result is ready.
[0124] To ensure the absolute correctness of the circuit function, especially for safety-critical systems, this parallel state merging circuit may also include a built-in verification unit. This verification unit is a small state machine that automatically traverses all 16 possible input state combinations after power-on reset, sequentially feeding them into the state merging logic unit, and comparing each output with the hard-coded known correct expected result.
[0125] Simultaneously, by constructing three states A, B, and C, and feeding them into two cascaded logic units in the order (A⊕B)⊕C and A⊕(B⊕C) respectively, the final results are compared to verify whether the associative law holds at the physical circuit level. If an inconsistency is detected, the verification unit immediately triggers an error flag, which can be connected to the system's non-maskable interrupt pin for emergency handling.
[0126] To avoid blocking ongoing merge calculations during dynamic scaling, a double-buffered pointer mechanism is employed. The system silently allocates and initializes a new, larger tree structure in background memory, without affecting the normal merging operations of the foreground tree during construction. After the new tree is built, an atomic instruction switches the root pointer, routing subsequent merge requests to the new tree. The old tree releases its memory after confirming there is no active access. This mechanism achieves zero downtime during dynamic tree structure adjustments.
[0127] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A tree-based parallel state merging method based on associative law, characterized in that, Includes the following steps: Obtain the local states generated by each of the multiple computing units, wherein the states are selected from a preset finite set of states; The multiple local states are organized into a tree data structure, wherein each leaf node of the tree data structure corresponds to a computing unit and stores its local state, and each non-leaf node is used to store the merging result of its child node states. According to the preset merging rules that satisfy the associative law, the tree data structure is merged layer by layer from the leaf node layer to the root node. Multiple non-leaf nodes in each layer execute the merging rules in parallel and store the merging results in the corresponding nodes. The state stored in the root node is output as the global merge result.
2. The method according to claim 1, characterized in that, The tree data structure is a complete binary tree structure; organizing the multiple local states into a tree data structure includes: allocating a continuous one-dimensional array in physical memory, indexed from 0, to store all nodes, wherein for an internal node with index i in the one-dimensional array, the index of its left child node is 2i+1, the index of its right child node is 2i+2, and the index of its parent node is ⌊(i-1) / 2⌋.
3. The method according to claim 1, characterized in that, The preset merging rule satisfies the associative law, commutative law, and idempotency, and the finite state set contains an identity element; the finite state set includes a first state representing a deterministic value, a second state representing arithmetic uncertainty, a third state representing semantic uncertainty, and a fourth state representing a mixture of the second and third states; the merging rule is configured as follows: The first state is merged with any state, and the result is that state. The second state is merged with the second state, and the result is the second state; The third state is merged with the third state to obtain the third state; The second state is combined with the third state to form the fourth state; The fourth state is merged with any other state, and the result remains the fourth state.
4. The method according to claim 2, characterized in that, The stepwise merging from the leaf node layer to the root node specifically includes: using a layer as a unit, through thread pools or parallel loop operations, multiple internal nodes in the current layer are assigned to multiple computing threads for parallel execution; each computing thread accesses non-overlapping memory address regions in the one-dimensional array in parallel.
5. The method according to claim 1, characterized in that, It also includes incremental update steps: When the local state of any computing unit changes, the change is only updated to the corresponding leaf node; Starting from the leaf node, along its single ancestor path to the root node, the merging rule is re-executed layer by layer upwards to update the state of each ancestor node on the path; During the upward recalculation process, if the recalculated state of an ancestor node is the same as its original state, the update propagation to higher-level nodes is terminated prematurely.
6. The method according to claim 1, characterized in that, It also includes dynamic scaling steps: Real-time detection of the number N of active computing units; Calculate the minimum binary tree depth H required to fully accommodate N leaf nodes, where H is the smallest integer that satisfies 2 to the power of H greater than or equal to N; A tree data structure with 2^H leaf nodes and 2^(H+1) minus 1 total nodes is dynamically allocated. The first N leaf nodes are assigned to active computing units, and the remaining leaf nodes are marked as idle.
7. The method according to claim 1, characterized in that, It also includes concurrency safety control mechanisms: Configure a global read-write lock for the tree-shaped data structure; When concurrently updating leaf nodes, acquire the read lock of the global read-write lock; When an update propagation is triggered and a merge operation is performed upwards to modify an internal node or the root node, a lock escalation mechanism is implemented to release the read lock and acquire the write lock of the global read-write lock.
8. The method according to claim 1, characterized in that, It also includes a distributed cross-node scaling mechanism: The tree-like data structure is extended into a distributed merged tree covering multiple physical nodes, with each physical node maintaining a local subtree; Each node determines its parent and child nodes based on the network topology, and receives the status of the child nodes, merges them, and sends them to the parent node. After completing the global merge, the root node broadcasts the final state to the entire network.
9. A tree-structured parallel state merging device based on associative law, characterized in that, include: The state acquisition module is used to acquire the local states generated by each of the multiple computing units, wherein the states are selected from a preset finite set of states. A tree organization module is used to organize the multiple local states into a tree data structure, wherein each leaf node of the tree data structure corresponds to a computing unit and stores its local state, and each non-leaf node is used to store the merging result of its child node states. The parallel merging module is used to merge the tree data structure layer by layer from the leaf node layer to the root node according to the preset merging rules that satisfy the associative law. In each layer, multiple non-leaf nodes execute the merging rules in parallel and store the merging results in the corresponding nodes. The result output module is used to output the state stored in the root node as the global merge result.
10. A parallel state merging circuit based on associative law, characterized in that, include: A storage array is used to store a tree-like data structure, wherein each leaf node of the tree-like data structure corresponds to a computing unit and stores its local state, and each non-leaf node is used to store the merged result of the states of its child nodes; The state merging logic unit includes a read-only memory lookup table or a gate-level circuit that implements bitwise OR operation. The lookup table or bitwise OR gate is hardwired to implement a preset merging rule that satisfies the associative law. It is configured to receive the states of two child nodes and output the merged state of the parent node. The parallel control unit is configured to schedule multiple state merging logic units to process multiple internal nodes at the same level in parallel within the same clock cycle. The output interface is used to output the global merge result stored in the root node.