A register fault analysis method based on hetgnn

Abstract

The application relates to the technical field of artificial intelligence, in particular to a register fault analysis method based on HetGNN (HetGNN, Heterogeneous Graph Neural Networks), which comprises the following steps: performing heterogeneous directed graph modeling on a comprehensive netlist of a target circuit, mapping register instances and logic gate instances in the circuit into different types of nodes in a heterogeneous directed graph, and mapping signal connection relationships between the instances into directed edges; performing fault injection simulation on the target circuit, generating a sensitive level label of a register node according to a comparison result of fault simulation output and golden simulation output; extracting feature information of each node in the heterogeneous directed graph; inputting the heterogeneous directed graph and the feature information of each node into a heterogeneous graph neural network for training, learning to generate an embedding representation of each node, and the heterogeneous graph neural network comprises a type-aware feature extraction module, a same-type neighbor aggregation module and a heterogeneous attention fusion module.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence technology, specifically to a register fault analysis method based on HetGNN. Background Technology

[0002] With the continuous development of microelectronics technology, the feature size of integrated circuits is constantly shrinking, and the chip integration density and operating frequency are continuously increasing. While this trend has significantly improved processor performance, it has also brought increasingly severe reliability challenges.

[0003] The space environment is filled with a large number of high-energy particles. When these particles collide with a computer, they can easily cause changes in the stored content or logical state of the computer, which is called a fault. The first type is a permanent fault, also known as a hard fault, which is characterized by the value of the memory cell always being 1 or always being 0. The second type is a transient fault, also known as a soft fault, which is characterized by the value of the memory cell flipping. The value of the memory cell can be recovered by rewriting or other methods. Although soft faults are temporary, they can propagate in the circuit and cause unpredictable results.

[0004] Traditional fault analysis methods mostly rely on simulation. This involves injecting faults into registers at different locations and times within the circuit, statistically analyzing the simulation results, and calculating the register's sensitivity level. However, this fault simulation is a very time-consuming operation because the circuit may contain a large number of registers, and performing multiple fault injection simulations for each bit requires significant computational power and time.

[0005] Therefore, this invention provides a register fault analysis method based on HetGNN. Summary of the Invention

[0006] In order to overcome the shortcomings of the prior art, at least one technical problem raised in the background art is solved.

[0007] The technical solution adopted by this invention to solve its technical problem is: a register fault analysis method based on HetGNN, comprising the following steps: Step 1: Perform heterogeneous directed graph modeling on the comprehensive netlist of the target circuit, map the register instances and logic gate instances in the circuit to different types of nodes in the heterogeneous directed graph, and map the signal connection relationships between instances to directed edges. Step 2: Perform fault injection simulation on the target circuit. Based on the comparison between the fault simulation output and the golden simulation output, generate sensitivity level labels for the register nodes according to the preset fault impact level and mapping rules. Step 3: Extract the feature information of each node in the heterogeneous directed graph; Step 4: Input the heterogeneous directed graph and the feature information of each node into the heterogeneous graph neural network for training, and learn to generate the embedding representation of each node. The heterogeneous graph neural network includes a type-aware feature extraction module, a same-type neighbor aggregation module, and a heterogeneous attention fusion module. Step 5: Train a classifier based on the embedding representations of the training set nodes and the sensitivity level labels, and use the classifier to infer the embedding representations of unlabeled register nodes to predict their fault sensitivity levels.

[0008] Preferably, the heterogeneous directed graph modeling in step S1 includes: Read each instance entry in the integrated netlist and map it to either a register type node or a logic gate type node according to the instance type; Identify input and output ports based on the port direction attribute of the instance, and establish directed edges from the output port of the source node to the input port of the target node based on the connection line name matching; The directed edges include four types: register to register, register to logic gate, logic gate to register, and logic gate to logic gate.

[0009] Preferably, the fault injection simulation in step S2 includes: Perform a fault-free gold simulation of the target circuit and record the reference output; A uniform injection strategy is adopted, in which multiple fault injection time points are selected evenly within the total simulation period, and faults are injected bit by bit into the register. The fault simulation output is compared with the baseline output, and the registers are classified as sensitive registers or non-sensitive registers according to the degree of fault impact and preset classification rules.

[0010] Preferably, the fault types include single-event upset faults and fixed-value faults, wherein the duration of a single-event upset fault is one clock cycle, and the duration of a fixed-value fault is the entire simulation cycle.

[0011] Preferably, the degree of impact of the fault is classified into the following levels based on the comparison results: The output is completely consistent with the baseline, but the internal state has been corrupted due to silent data corruption. An unrecoverable error was detected when the program's exception handling mechanism was triggered but could not be fixed. The execution time exceeds a preset multiple of the golden simulation time; A crash caused by abnormal program termination; The rules for classifying registers as sensitive or non-sensitive registers based on the degree of impact of the fault include: if the fault injection causes silent data corruption, it is marked as a non-sensitive register; if the fault injection causes any of the following to be detected: unrecoverable error, timeout, or crash, it is marked as a sensitive register.

[0012] Preferably, the node feature information includes: For register nodes, the dynamic behavior features extracted from the simulation waveform file include the maximum and minimum time intervals for signal state transitions, as well as the proportion of the logic high-level duration to the total simulation period. For each logic gate node, extract its logical function type characteristics.

[0013] Preferably, the heterogeneous graph neural network comprises five sub-neural networks: The first type of perceptual feature extraction network is used to process the dynamic behavioral features of register type nodes and generate register content embeddings. The second type of perceptual feature extraction network is used to process the type features of logic gate type nodes and generate logic gate content embeddings. The first neighbor aggregation network is used to aggregate the same type neighbors of register type nodes to generate register type-aware neighbor embeddings. The second neighbor aggregation network is used to aggregate the same type of neighbors of logic gate type nodes to generate logic gate type-aware neighbor embeddings. Heterogeneous attention fusion network is used to perform weighted fusion of embeddings of different types of nodes through attention mechanism, and output heterogeneous node embeddings.

[0014] Preferably, the training process of the heterogeneous graph neural network includes: A random walk algorithm is executed with the register node as the center to generate a random walk path; Traverse the nodes in the random walk path, take the adjacent nodes in the window as positive samples, and take the nodes of the same type as the positive samples but not adjacent as negative samples, and construct triplet training samples. By training the triples in batches, the embedding similarity of positive sample node pairs is made higher than that of negative sample node pairs, thereby learning the topological structure information of the heterogeneous directed graph and generating the embedding representation of each node.

[0015] This invention provides a register fault analysis method based on HetGNN. It has the following beneficial effects: 1. By classifying registers and logic gates in the circuit netlist into heterogeneous node types, graph neural networks can perceive the essential differences in component types, and the learned embedded representations are closer to the actual physical functions of the circuit, thus improving the accuracy of register sensitivity assessment.

[0016] 2. Through the synergistic effect of three modules—type-aware feature extraction, same-type neighbor aggregation, and heterogeneous attention fusion—the dynamic behavior attributes of registers, the Boolean function attributes of logic gates, and the interaction patterns between the two types of nodes are captured, so that the node embedding simultaneously contains individual features and structural context information.

[0017] 3. The sensitivity level labels generated by fault injection simulation can be directly used for supervised training of graph neural networks, and the trained model can perform fast inference on new circuits or registers after circuit changes without having to re-execute the full fault injection simulation. Attached Figure Description

[0018] Figure 1 This is a flowchart of the method of the present invention; Figure 2 This is a schematic diagram illustrating the transformation from a netlist to a directed graph according to the present invention; Figure 3 This is a model diagram of the HetGNN of the present invention; Figure 4 This is a simulation diagram of the fault injection of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] like Figures 1 to 4 As shown, this invention proposes a register fault analysis method based on HetGNN, comprising the following steps: Step 1: Perform heterogeneous directed graph modeling on the comprehensive netlist of the target circuit, map the register instances and logic gate instances in the circuit to different types of nodes in the heterogeneous directed graph, and map the signal connection relationships between instances to directed edges. Step 2: Perform fault injection simulation on the target circuit. Based on the comparison results between the fault simulation output and the golden simulation output, generate the sensitivity level label of the register node according to the preset fault impact level and mapping rules. Among them, the gold simulation refers to performing functional simulation on the target circuit under the condition of no fault injection, and recording its normal operation output as a benchmark reference for subsequent fault injection comparison. Step 3: Extract the feature information of each node in the heterogeneous directed graph; Step 4: Input the heterogeneous directed graph and the feature information of each node into the heterogeneous graph neural network for training, and learn to generate the embedding representation of each node. The heterogeneous graph neural network includes a type-aware feature extraction module, a same-type neighbor aggregation module, and a heterogeneous attention fusion module. Step 5: Train a classifier based on the embedding representations of the training set nodes and the sensitivity level labels. Use the classifier to infer the embedding representations of unlabeled register nodes and predict their fault sensitivity levels.

[0021] HetGNN refers to a type of neural network model that introduces a node type awareness mechanism into the graph neural network framework to learn representations of heterogeneous graphs (graphs containing multiple types of nodes and edges).

[0022] Heterogeneous directed graph modeling in step S1 includes: Read each instance entry in the integrated netlist and map it to either a register type node or a logic gate type node according to the instance type; Identify input and output ports based on the port direction attribute of the instance, and establish directed edges from the output port of the source node to the input port of the target node based on the connection line name matching; Directed edges include four types: register to register, register to logic gate, logic gate to register, and logic gate to logic gate.

[0023] Specifically, the netlist parsing tool reads the synthesized netlist file, parses each instance entry, and determines whether the instance is a sequential logic unit or a combinational logic unit based on the unit module type referenced by the instance: those belonging to D flip-flops, latches and their variants are mapped to register type nodes; those belonging to AND gates, OR gates, NOT gates, XOR gates, multiplexers and their similar combinational logic units are mapped to logic gate type nodes.

[0024] After the node mapping is completed, each port is identified as an input port or an output port based on the port direction attribute in the instance declaration; then, matching is performed based on the name of the connection line: when the output port of the first node and the input port of the second node refer to the same connection line, a directed edge is established from the first node to the second node, and the direction of the edge follows the actual transmission flow of the signal from the output port to the input port.

[0025] Based on the differences in the types of the source node and the target node, directed edges include the following four types: register to register, register to logic gate, logic gate to register, and logic gate to logic gate.

[0026] The fault injection simulation in step S2 includes: Perform a fault-free gold simulation of the target circuit and record the reference output; A uniform injection strategy is adopted, in which multiple fault injection time points are selected evenly within the total simulation period, and faults are injected bit by bit into the register. The fault simulation output is compared with the baseline output, and the registers are classified as sensitive registers or non-sensitive registers according to the degree of fault impact and preset classification rules.

[0027] Furthermore, in this embodiment of the invention: based on the register bit information listed in the register report file, a uniform injection strategy is adopted to uniformly select multiple fault injection time points within the total simulation cycle, and inject faults bit by bit into each register. The fault types include single-event upset faults and fixed-value faults: the duration of a single-event upset fault is one clock cycle, simulating the instantaneous flipping of the stored value caused by a high-energy particle impact; the duration of a fixed-value fault is the entire simulation cycle, simulating the permanent locking of the logic value of the memory cell.

[0028] After fault injection is completed, the output results of the fault simulation are collected and compared with the baseline output of the gold simulation. Based on the degree of impact of the fault on the normal function of the program, the fault results are divided into the following levels: if the output is completely consistent with the baseline, it is marked as silent data corruption; if the program exception handling is triggered during execution, it is marked as an unrecoverable error detected; if the execution time exceeds a preset multiple of the gold simulation time, it is marked as timeout; if the execution directly causes the program to crash, it is marked as crash.

[0029] Based on the aforementioned fault impact levels, registers are classified into sensitive registers or non-sensitive registers: registers that have a substantial impact on the normal operation of the program are marked as sensitive registers; registers that have no impact on the program's execution result or whose impact is below a preset threshold are marked as non-sensitive registers. The classification results serve as labels for each register node and are used for subsequent training and inference of the graph neural network.

[0030] The fault types include single-event upset faults and fixed-value faults. The duration of a single-event upset fault is one clock cycle, while the duration of a fixed-value fault is the entire simulation cycle.

[0031] The single-event upset fault simulates a momentary flip of the logic value caused by a high-energy particle impacting a memory cell. The hold time for this fault is set to one clock cycle, meaning that the register value is the flipped logic value during the first clock cycle after the fault is injected, and it returns to normal in the next cycle.

[0032] Fixed-value fault: A hard fault that simulates the permanent locking of the logic state of a memory cell. The retention time of this fault is the entire simulation cycle, that is, after the fault is injected, the register value remains constant at 0 or constant at 1 until the simulation ends.

[0033] The degree of impact of the fault is classified into the following levels based on the comparison results: The output is completely consistent with the baseline, but the internal state has been corrupted due to silent data corruption. An unrecoverable error was detected when the program's exception handling mechanism was triggered but could not be fixed. The execution time exceeds a preset multiple of the golden simulation time; A crash caused by abnormal program termination; The rules for classifying registers as sensitive or non-sensitive registers based on the degree of impact of a fault include: if a fault injection causes silent data corruption, it is marked as a non-sensitive register; if a fault injection causes any of the following to be detected: an unrecoverable error, a timeout, or a crash, it is marked as a sensitive register.

[0034] Silent data corruption occurs when the output of the fault injection simulation is completely consistent with the baseline output of the gold simulation, but an error has occurred in the internal state of the program. In this case, the fault propagates in the circuit but is not reflected in the observable output port, making it concealed.

[0035] Unrecoverable error detected: During the execution of the fault injection simulation, the program's exception handling mechanism was triggered, but the exception could not be repaired by the built-in error correction or recovery methods, and the program was forced to terminate or enter an unrecoverable state.

[0036] Timeout: The execution time of the fault injection simulation exceeds a preset multiple of the golden simulation execution time, indicating that the fault may cause program dead loops, pipeline blockages or other propagation effects that lead to execution delays. Although it has not crashed directly, it has lost its normal timing characteristics.

[0037] Crash: Fault injection directly causes the simulation program to terminate abnormally or the system to crash, indicating that the fault has caused a serious error that cannot be handled after propagating in the circuit.

[0038] Based on the aforementioned fault impact levels, registers are classified into sensitive or non-sensitive registers according to the following preset classification rules: if a fault injection into a register causes silent data corruption, it is marked as a non-sensitive register; if it causes any of the following: an unrecoverable error, timeout, or crash, it is marked as a sensitive register. The classification results serve as binary labels for each register node (sensitive = 1, non-sensitive = 0), which are used for subsequent training and inference of the graph neural network.

[0039] Node feature information includes: For register nodes, the dynamic behavior features extracted from the simulation waveform file include the maximum and minimum time intervals for signal state transitions, as well as the proportion of the logic high-level duration to the total simulation period. For each logic gate node, extract its logical function type characteristics.

[0040] Specifically, the timing behavior of each register node is analyzed from the waveform file (.vcd file) generated by the fault injection simulation, and the following dynamic behavior features are extracted: Maximum toggle interval: The maximum time interval between two consecutive state toggles of the register signal within the total simulation period. Let the time sequence of register state toggles be... Take the maximum value of the time difference between adjacent times; Minimum toggle interval: The minimum time interval between two consecutive state toggles of the register signal within the total simulation cycle.

[0041] High-level logic percentage: The ratio of the number of cycles with a register value of logic 1 to the total number of simulation cycles, i.e. ,in This represents the number of clock cycles during which the register is a logic 1. This represents the total number of simulation cycles; This represents the percentage of logic high levels, dimensionless (the ratio ranges from [0,1]).

[0042] For each logic gate node, its logic function type is extracted as a discrete category feature. The logic function type includes at least one of AND gate, OR gate, NOT gate, XOR gate, NAND gate, and NOR gate. In one implementation, each type of logic gate is represented by the following encoding: AND gate is marked as 1, OR gate as 2, NOT gate as 3, XOR gate as 4, NAND gate as 5, and NOR gate as 6.

[0043] Heterogeneous graph neural networks consist of five sub-neural networks: The first type of perceptual feature extraction network is used to process the dynamic behavioral features of register type nodes and generate register content embeddings. The second type of perceptual feature extraction network is used to process the type features of logic gate type nodes and generate logic gate content embeddings. The first neighbor aggregation network is used to aggregate the same type neighbors of register type nodes to generate register type-aware neighbor embeddings. The second neighbor aggregation network is used to aggregate the same type of neighbors of logic gate type nodes to generate logic gate type-aware neighbor embeddings. Heterogeneous attention fusion network is used to perform weighted fusion of embeddings of different types of nodes through attention mechanism, and output heterogeneous node embeddings.

[0044] Specifically, the first type of perceptual feature extraction network: This sub-network takes register-type nodes as the processing object and receives the dynamic behavior features extracted from the register nodes in step four as input, including the maximum toggle interval, the minimum toggle interval, and the proportion of logic high levels. It extracts and fuses these multi-dimensional features through mean pooling and attention mechanisms to generate the content embedding of register-type nodes, capturing the individual attributes of registers in the dynamic behavior of the circuit.

[0045] The second type of perceptual feature extraction network: This sub-network takes logic gate type nodes as its processing object and receives the logical function type features extracted from the logic gate nodes in step four as input. Through type encoding and embedding lookup, discrete category features are mapped into continuous vector representations, generating content embeddings of logic gate type nodes that represent the Boolean operation function attributes of the logic gates.

[0046] First Neighbor Aggregation Network: This sub-network processes neighbors of the same type as register-type nodes. Among the sampled neighbor nodes, those of type register are selected, grouped by node type, and then the content embeddings of each group of register neighbors are aggregated to generate register-type-aware neighbor embeddings, used to capture structural interaction information between register-type nodes.

[0047] The second neighbor aggregation network: This sub-network processes neighbors of the same type as logical gate type nodes. Among the sampled neighbor nodes, neighbors of type logical gate are selected, grouped by node type, and the content embeddings of each group of logical gate neighbors are aggregated to generate logical gate type-aware neighbor embeddings, which are used to capture the structural interaction information between logical gate type nodes.

[0048] Heterogeneous Attention Fusion Network: This sub-network receives the content embeddings generated by the above four sub-networks and the type-aware neighbor embeddings. It performs weighted fusion of the register type and logic gate type embeddings through an attention mechanism, adaptively learns the importance weights of the two types of nodes in the register fault sensitivity prediction task, and outputs the final heterogeneous node embedding.

[0049] The processing flow of heterogeneous attention fusion networks is as follows: Step a: Receive four types of embedding vectors as input, namely: the register type content embedding of the central node, the logic gate type content embedding of the central node (if the central node is a register type, the embedding is an empty vector), the register type neighbor aggregation embedding, and the logic gate type neighbor aggregation embedding.

[0050] Step b: Input each type of embedding vector into the corresponding type of multilayer perceptron (MLP), project it onto the intermediate representation space of the same dimension, and obtain the four types of intermediate vectors after projection.

[0051] Step c: Perform an inner product operation between each class of intermediate vectors and the learnable query vectors to obtain the four classes of raw attention scores.

[0052] Step d: Normalize the four types of original attention scores: take the index of each type and divide it by the sum of the four types of index values ​​to obtain the attention weight of each type. The sum of the attention weights is 1.

[0053] Step e: Multiply each type of intermediate vector by its corresponding attention weight and sum them to obtain the final node heterogeneous embedding vector.

[0054] The five sub-networks are jointly trained end-to-end: the first and second type-aware feature extraction networks generate content embeddings for the two types of nodes respectively; the first and second neighbor aggregation networks aggregate structural information for the two types of neighbors respectively; and the heterogeneous attention fusion network integrates information from different types to generate the final embedding, which is then used by the subsequent classifier for sensitivity level prediction. The aggregation operation is a mean pooling operation, that is, the arithmetic mean of the content embedding vectors of all neighbor nodes belonging to the same type is taken element by element to obtain the aggregated embedding vector of that type of neighbor.

[0055] The training process of a heterogeneous graph neural network includes: A random walk algorithm is executed with the register node as the center to generate a random walk path; Traverse the nodes in the random walk path, take the adjacent nodes in the window as positive samples, and take the nodes of the same type as the positive samples but not adjacent as negative samples, and construct triplet training samples. By training triples in batches, the embedding similarity of positive sample node pairs is made higher than that of negative sample node pairs, thus learning the topological structure information of the heterogeneous directed graph and generating the embedding representation of each node.

[0056] Specifically, the heterogeneous directed graph and the feature information of each node are input into the heterogeneous graph neural network, and the training and inference stages are performed.

[0057] Training phase: Using each register node in the heterogeneous directed graph as a central node, a random walk algorithm is executed to generate random walk paths. In one implementation, the walk length is set to L (unit: steps, positive integer), meaning each random walk path contains L nodes, including register type nodes and logic gate type nodes; Iterate through each node in each random walk path. For the current node, set a window size of W (unit: number, positive integer), and take the neighboring nodes within the window coverage as positive samples; at the same time, randomly select a node of the same type as the current node in the heterogeneous directed graph, and a node that has no directed edges connected to the center node v, as a negative sample. Thus, construct triplet training samples around each center node. ,in As the central node, For positive sample nodes, These are negative sample nodes.

[0058] All triples are batch-trained into the heterogeneous graph neural network. The training objective is to ensure that the embedding similarity between positive sample node pairs and the center node is higher than that between negative sample node pairs. The following triple loss function is used during training. : ;in The training sample set for triples is dimensionless. It is a distance metric function embedded in the space, which in one implementation is Euclidean distance and is dimensionless; is a dimensionless hyperparameter used to control the difference margin between positive and negative samples; By minimizing the loss function, the heterogeneous graph neural network learns the topological structure information of the heterogeneous directed graph. After training, it generates and saves the embedding representations of all nodes.

[0059] During the inference phase: The feature information of the register node to be predicted is input into the trained heterogeneous graph neural network to generate a corresponding embedding representation. A classifier is trained based on the embedding representations of the register nodes in the training set and their corresponding sensitivity level labels. The embedding representation of the register node to be predicted is input into the classifier, which outputs the probability distribution of whether the register belongs to a sensitive or insensitive type, thereby determining its fault sensitivity level. In one implementation, the classifier is a logistic regression classifier or a support vector machine classifier; if the output sensitivity type probability value is greater than a preset threshold (e.g., 0.5), the register is determined to be a sensitive register; otherwise, it is determined to be an insensitive register.

[0060] In summary, this invention models the circuit netlist as a heterogeneous directed graph and uses a heterogeneous graph neural network to extract and embed type-aware features of registers and logic gates, enabling node embedding to simultaneously carry individual component attributes and circuit topology information. By combining random walk and triplet loss training mechanisms, the consistency between the embedding space and the fault propagation path is ensured. Furthermore, based on a small number of labeled samples, the sensitivity level of the entire circuit registers can be rapidly inferred, providing precise guidance for chip reliability hardening.

[0061] In one implementation, the preset threshold is determined by dividing the training set into a training subset and a validation subset, training a classifier model on the training subset, evaluating the classification performance (including precision and recall) at different thresholds on the validation subset, and selecting the threshold that maximizes the F1 score as the preset threshold. In one implementation, when a logistic regression classifier is used, the preset threshold is 0.5. The classifier is a logistic regression classifier, which takes the embedded representation of the register node as input, maps the embedded vector to a scalar value through a learnable linear transformation, and then converts it into a probability value between 0 and 1 through a sigmoid function. This probability value represents the confidence that the register belongs to a sensitive type. If the probability value is greater than a preset threshold (0.5 in one embodiment), the register is determined to be a sensitive register; otherwise, it is determined to be a non-sensitive register.

[0062] The threshold is set to facilitate comparison. The size of the threshold depends on the amount of sample data and the number of bases set by those skilled in the art for each set of sample data; as long as it does not affect the ratio between the parameter and the quantized value, it is acceptable.

[0063] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A register fault analysis method based on HetGNN, characterized in that: Includes the following steps: Step 1: Perform heterogeneous directed graph modeling on the comprehensive netlist of the target circuit, map the register instances and logic gate instances in the circuit to different types of nodes in the heterogeneous directed graph, and map the signal connection relationships between instances to directed edges. Step 2: Perform fault injection simulation on the target circuit. Based on the comparison results between the fault simulation output and the golden simulation output, generate the sensitivity level label of the register node according to the preset fault impact level and mapping rules. Step 3: Extract the feature information of each node in the heterogeneous directed graph; Step 4: Input the heterogeneous directed graph and the feature information of each node into the heterogeneous graph neural network for training, and learn to generate the embedding representation of each node. The heterogeneous graph neural network includes a type-aware feature extraction module, a same-type neighbor aggregation module, and a heterogeneous attention fusion module. Step 5: Train a classifier based on the embedding representations of the training set nodes and the sensitivity level labels, and use the classifier to infer the embedding representations of unlabeled register nodes to predict their fault sensitivity levels.

2. The register fault analysis method based on HetGNN according to claim 1, characterized in that: The heterogeneous directed graph modeling in step S1 includes: Read each instance entry in the integrated netlist and map it to either a register type node or a logic gate type node according to the instance type; Identify input and output ports based on the port direction attribute of the instance, and establish directed edges from the source node's output port to the target node's input port based on the connection line name matching; The directed edges include four types: register to register, register to logic gate, logic gate to register, and logic gate to logic gate.

3. The register fault analysis method based on HetGNN according to claim 2, characterized in that: The fault injection simulation in step S2 includes: Perform a fault-free gold simulation of the target circuit and record the reference output; A uniform injection strategy is adopted, in which multiple fault injection time points are selected evenly within the total simulation period, and faults are injected bit by bit into the register. The fault simulation output is compared with the baseline output, and the registers are classified as sensitive registers or non-sensitive registers according to the degree of fault impact and preset classification rules.

4. The register fault analysis method based on HetGNN according to claim 3, characterized in that: The fault types include single-event upset faults and fixed-value faults, wherein the duration of a single-event upset fault is one clock cycle, and the duration of a fixed-value fault is the entire simulation cycle.

5. The register fault analysis method based on HetGNN according to claim 3, characterized in that: The degree of impact of the fault is classified into the following levels based on the comparison results: The output is completely consistent with the baseline, but the internal state has been corrupted due to silent data corruption. An unrecoverable error was detected when the program's exception handling mechanism was triggered but could not be fixed. Timeout due to execution time exceeding a preset multiple of the golden simulation time; A crash caused by abnormal program termination; The rules for classifying registers as sensitive or non-sensitive registers based on the degree of impact of the fault include: if the fault injection causes silent data corruption, it is marked as a non-sensitive register; if the fault injection causes any of the following to be detected: unrecoverable error, timeout, or crash, it is marked as a sensitive register.

6. The register fault analysis method based on HetGNN according to claim 5, characterized in that: The node feature information includes: For register nodes, the dynamic behavior features extracted from the simulation waveform file include the maximum and minimum time intervals for signal state transitions, as well as the proportion of the logic high-level duration to the total simulation period. For each logic gate node, extract its logical function type characteristics.

7. The register fault analysis method based on HetGNN according to claim 6, characterized in that: The heterogeneous graph neural network comprises five sub-neural networks: The first type of perceptual feature extraction network is used to process the dynamic behavioral features of register type nodes and generate register content embeddings. The second type of perceptual feature extraction network is used to process the type features of logic gate type nodes and generate logic gate content embeddings. The first neighbor aggregation network is used to aggregate the same type neighbors of register type nodes to generate register type-aware neighbor embeddings. The second neighbor aggregation network is used to aggregate the same type of neighbors of logic gate type nodes to generate logic gate type-aware neighbor embeddings. Heterogeneous attention fusion network is used to perform weighted fusion of embeddings of different types of nodes through attention mechanism, and output heterogeneous node embeddings.

8. The register fault analysis method based on HetGNN according to claim 7, characterized in that: The training process of the heterogeneous graph neural network includes: A random walk algorithm is executed with the register node as the center to generate a random walk path; Traverse the nodes in the random walk path, take the adjacent nodes in the window as positive samples, and take the nodes of the same type as the positive samples but not adjacent as negative samples, and construct triplet training samples. By training the triples in batches, the embedding similarity of positive sample node pairs is made higher than that of negative sample node pairs, thereby learning the topological structure information of the heterogeneous directed graph and generating the embedding representation of each node.

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