A detection method and electronic device

Abstract

The application provides a detection method and an electronic device; the method comprises the following steps: in response to a hardware system entering a first target state, a target adapter card is controlled to be in a first signal state based on a first detection signal; wherein the target adapter card is connected with one mainboard port in a plurality of mainboard ports of the hardware system; the first detection signal can detect the in-place state of the adapter card in the plurality of mainboard ports in response to the hardware system entering a second target state; a first connection relationship between the target adapter card in the first signal state and the connected mainboard port is determined; and the first connection relationship is matched with a first preset connection relationship to determine a first detection result for the first connection relationship.

Description

Technical Field

[0001] This application relates to the field of testing technology, and more particularly to a testing method and electronic device. Background Technology

[0002] A server's motherboard can house multiple adapter cards and graphics cards to handle various tasks. Each adapter card may perform different tasks, and incorrect insertion can cause the server to become unusable and crash. Therefore, it's necessary to check the adapter card's insertion position. Currently, this check is performed after the server hardware system boots into the operating system. Since operating system boots very slowly, if an incorrect insertion position is detected, the server must be shut down for proactive repair. This results in a very long detection cycle and low efficiency. Summary of the Invention

[0003] This application provides a detection method, apparatus, electronic device, computer-readable storage medium, and computer program product.

[0004] The technical solution of this application embodiment is implemented as follows: In a first aspect, embodiments of this application provide a detection method, the method comprising: In response to the hardware system entering the first target state, the target adapter card is controlled to enter the first signal state based on the first detection signal; wherein, the target adapter card is connected to one of the multiple motherboard ports of the hardware system; the first detection signal can detect the presence status of the adapter card among the multiple motherboard ports in response to the hardware system entering the second target state. Determine the first connection relationship between the target adapter card in the first signal state and the connected motherboard port; The first connection relationship is matched with the first preset connection relationship to determine the first detection result for the first connection relationship.

[0005] Secondly, embodiments of this application provide a detection device, the device comprising: The first control module is used to control the target adapter card to a first signal state based on a first detection signal in response to the hardware system entering a first target state; wherein the target adapter card is connected to one of the multiple motherboard ports of the hardware system; the first detection signal can detect the presence status of the adapter card among the multiple motherboard ports in response to the hardware system entering a second target state. The first determining module is used to determine the first connection relationship between the target adapter card in the first signal state and the connected motherboard port; The second determining module is used to match the first connection relationship with the first preset connection relationship and determine the first detection result for the first connection relationship.

[0006] Thirdly, embodiments of this application provide an electronic device, including a motherboard and a detection unit; the motherboard is provided with multiple adapter cards; wherein... The detection unit is used to control the target adapter card to a first signal state based on a first detection signal when the hardware system enters a first target state; wherein the target adapter card is connected to one of the multiple motherboard ports of the hardware system; the first detection signal can detect the presence status of the adapter card among the multiple motherboard ports when the hardware system enters a second target state. Determine the first connection relationship between the target adapter card in the first signal state and the connected motherboard port; The first connection relationship is matched with the first preset connection relationship to determine the first detection result for the first connection relationship.

[0007] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program or computer-executable instructions for implementing the detection method provided in embodiments of this application when executed by a processor.

[0008] Fifthly, embodiments of this application provide a computer program product, including a computer program or computer executable instructions, which, when executed by a processor, implement the detection method provided in embodiments of this application. Attached Figure Description

[0009] Figure 1 This is a flowchart illustrating a detection method provided in an embodiment of this application. Figure 1 ; Figure 2 A flowchart illustrating a detection method provided in this application embodiment. Figure 2 ; Figure 3 A flowchart illustrating a detection method provided in this application embodiment. Figure 3 ; Figure 4 A flowchart illustrating a detection method provided in this application embodiment. Figure 4 ; Figure 5 A flowchart illustrating a detection method provided in this application embodiment. Figure 5 ; Figure 6 A flowchart illustrating a detection method provided in this application embodiment. Figure 6 ; Figure 7 A flowchart illustrating a detection method provided in this application embodiment. Figure 7 ; Figure 8 A flowchart illustrating a detection method provided in this application embodiment. Figure 8 ; Figure 9 A flowchart illustrating a detection method provided in this application embodiment. Figure 9 ; Figure 10 A schematic diagram of a cable connection provided in an embodiment of this application; Figure 11 A schematic diagram of a current signal provided in an embodiment of this application; Figure 12 This is a schematic diagram of the signal topology of a motherboard interface provided in an embodiment of this application; Figure 13 An execution topology diagram of the overall working process provided in this application embodiment; Figure 14 This application provides a schematic diagram of the signal flow in the first stage according to an embodiment of the present application. Figure 15 This application provides a schematic diagram of a second-stage signal flow in an embodiment. Figure 16 This is a logic block diagram of a detection device provided in an embodiment of this application; Figure 17 This is a schematic diagram of the hardware entity of an electronic device provided in an embodiment of this application. Detailed Implementation

[0010] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0011] Before providing a further detailed description of the embodiments of this application, the nouns and terms used in the embodiments of this application are explained, and the nouns and terms used in the embodiments of this application shall be interpreted as follows: 1) S5 State: This refers to the server hardware system being in a soft-off state, meaning the operating system or UEFI is off, but the server is still connected to AC power and maintains basic power supply; management modules such as the BMC can still run. This state is an important stage before system startup and can be used to perform early detection tasks without waiting for the full operating system to load, thus significantly improving detection efficiency.

[0012] 2) PRSNT_N signal: This stands for Presence Detect Signal, a signal line in the PCIe interface used to detect whether a device is inserted. When a device is inserted, this signal is pulled low (active low), notifying the motherboard or controller that a device is present, thereby triggering clock enable, asset identification, and other operations. In this application, this signal is time-division multiplexed and used in the system's S5 state to establish a detection path, achieving automatic identification of connection relationships.

[0013] 3) BMC (Baseboard Management Controller): The BMC is the core module in the server used for remote monitoring, management, and control of hardware status. The BMC has an independent processor, memory, and network interface, and can run even when the system is not powered on or is powered off. It is responsible for power management, temperature monitoring, fault alarms, and logging. In this application, the BMC acts as the initiator and control center of the testing process, communicating with modules such as the FPGA and I / O expanders (IOEXP) via buses such as I2C to drive the testing process.

[0014] 4) FPGA (Field-Programmable Gate Array): A field-programmable gate array is a configurable hardware logic device that can dynamically change its internal circuit structure during system operation. In this application, the FPGA is deployed on the power delivery board (PDB) to implement functions such as signal switching, PERESET_N (the reset pin signal of the graphics card), and current sampling. It is the key execution unit for completing the auxiliary power cable misconnection detection.

[0015] 5) Riser Card: A hardware device used to expand the number of PCIe slots in a server. It is typically mounted on the motherboard and connects to the motherboard via the MCIO (Mezzanine Card I / O) interface. It provides multiple CEM (Computer Express Module) slots for expansion cards such as graphics cards (also known as Graphics Processing Units, or GPUs; this application uses "GPU" to refer to graphics cards). The MCIO port on the Riser card connects to the motherboard's MCIO port via a cable. Incorrect connection can lead to device recognition failure or abnormal bandwidth.

[0016] 6) MCIO (Mezzanine Card I / O): The intermediate layer card input / output interface, which is the physical connection point between the Riser card and the motherboard for signal transmission. Each MCIO port has a unique number and corresponds to a specific Riser card and motherboard location. This application determines whether the connection is correct by detecting the mapping relationship between the Riser card MCIO and the motherboard MCIO.

[0017] 7) PERESET_N signal: PCIe reset signal, used to initialize and restart PCIe devices or slots. When this signal is pulled low, the device in the corresponding slot enters a reset state, internal high-speed I / O and logic circuits stop working, and the current drops significantly. This application utilizes this characteristic to infer the connection relationship between the auxiliary power cable and the GPU slot by detecting current changes during the DC Reboot phase.

[0018] 8) AUX Power Cable: A cable that provides additional power to high-power expansion cards such as GPUs. It is typically powered by a PDB and connects to the power supply port on the Riser card. Due to its complex connection, incorrect insertion is prone to occur, leading to abnormal power supply or even damage to the device. This application achieves accurate identification of the AUX Power Cable connection by detecting changes in current.

[0019] 9) S0 State: System operating state S0 (i.e., system power state S0) is the state in which the computer is fully powered on and running. The system hardware context is fully preserved, software does not need to be restored, and hardware latency is extremely low. In this state, the processor, memory, and peripherals are all active, and the system is fully usable. Simultaneously, to save energy (especially for mobile devices), the system supports fine-grained power management: each device independently saves energy, and unused hardware components can be shut down and started as needed, or enter a lower power state. The S0 state is the basic environment for the operating system to perform task scheduling and process user-mode (application) threads, and it is also the primary scenario for the initial installation and testing of new devices. In this state, the device's power policy owner can enable the device's wake-up function so that when the system subsequently enters sleep mode, it can respond to external signals to wake up the system or itself.

[0020] To address the issues of long detection cycles and low detection efficiency in detecting the insertion position of the adapter card, this application provides a detection method. Figure 1 A flowchart illustrating a detection method provided in this application embodiment. Figure 1It can be applied to control devices in servers (such as Baseboard Management Controllers (BMCs) or Programmable Logic Devices (PLDs)). Figure 1 As shown, this method can be implemented through steps S101 to S103: Step S101: In response to the hardware system entering the first target state, the target adapter card is controlled to the first signal state based on the first detection signal; wherein, the target adapter card is connected to one of the multiple motherboard ports of the hardware system; the first detection signal can detect the presence status of the adapter card among the multiple motherboard ports in response to the hardware system entering the second target state.

[0021] In the embodiments of this application, the hardware system refers to a server hardware system. The server hardware system may include a motherboard, which has multiple high-speed data transmission interfaces (peripheral component interconnect express, PCIe) as motherboard ports. Adapter cards can be inserted into the PCIe interfaces, and the adapter cards also have PCIe interfaces for connecting devices such as graphics cards and computing cards that can perform corresponding tasks.

[0022] An adapter card is a hardware device used to expand the number of PCIe slots in a server. It is typically mounted on the motherboard and connects to the motherboard via the mezzanine card I / O (MCIO) interface. It also provides multiple Computer Express Module (CEM) slots for expansion cards such as GPUs. The I / O interfaces on the adapter card are connected to the motherboard ports via connecting cables, forming a physical connection path. Each adapter card has a pre-defined connection relationship with a specific motherboard port; incorrect connections may result in the target adapter card not being recognized or experiencing abnormal bandwidth.

[0023] In some embodiments, the first target state refers to the state after the hardware system is powered on but before it has entered the operating system, also known as the soft-off state or S5 state. In the first target state, the server hardware system is in a soft-off state, meaning the operating system or Unified Extensible Firmware Interface (UEFI) is off, but the server is still connected to AC power and maintains basic power supply; management modules such as the baseboard management controller can still operate. This state is an important stage before system startup and can be used to perform early detection tasks without waiting for the full operating system to load, thus significantly improving detection efficiency.

[0024] In this state, the presence detection pin (PRSNT_N) on the adapter card will not be used for actual presence detection needs. Therefore, in the first target state, the presence detection signal of the presence detection pin can be used as a detection signal to detect the connection relationship between the adapter card and the motherboard interface.

[0025] The first detection signal is the presence detection signal of the adapter card in the first target state. The first detection signal includes two states: a first signal state and a second signal state. In this application's technical solution, the first signal state can be set to a low level and the second signal state to a high level. It should be noted that setting the first signal state to a high level and the second signal state to a low level is still feasible.

[0026] For example, when the first signal state is set to low and the second signal state is set to high, during connection detection, the first detection signal of one of the target adapter cards can be pulled low. In this case, it can be assumed that there is a connection between the target motherboard port (which is at a low level) and the target adapter card. Conversely, when the first signal state is set to low and the second signal state is set to high, during connection detection, the first detection signal of one of the target adapter cards can be pulled high. In this case, it can be assumed that there is a connection between the target motherboard port (which is at a high level) and the target adapter card.

[0027] It is easy to understand that the number of target adapter cards in the first signal state is usually 1, so that the connection between the motherboard port and the target adapter card can be confirmed by the actual motherboard port where the level changes.

[0028] In some embodiments, the second target state refers to the operating state of the hardware system, also known as the S0 state. In the second target state, the hardware system can operate normally to provide corresponding services. It is easy to understand that in the second target state, the presence detection pin can perform a presence detection function to ensure that the hardware card on this interface can operate normally.

[0029] Step S102: Determine the first connection relationship between the target adapter card in the first signal state and the connected motherboard port.

[0030] In the embodiments of this application, the first connection relationship refers to the actual physical connection mapping relationship between the target adapter card and the motherboard port. The first connection relationship is determined by detecting the signal response of the motherboard port on the motherboard side: when the first detection signal of the target adapter card is pulled low, if the first detection signal of a certain motherboard port on the motherboard also becomes low, it indicates that the target adapter card is connected to that motherboard port via a connecting cable. The above detection process essentially establishes a mapping relationship between the port of the target adapter card and the motherboard port; that is, it is considered that the motherboard port connected to the target adapter card is the motherboard port that simultaneously changes to the first signal state when the target adapter card changes to the first signal state. Therefore, it can be considered that there is a first connection relationship between the target adapter card and the motherboard port.

[0031] For example, in a system with four adapter cards and four motherboard ports, the BMC sequentially controls the first detection signal of the target adapter card to go low, and detects which motherboard port's signal goes low simultaneously. Assuming that after the first target adapter card's first detection signal is pulled low, the first detection signal of the third motherboard port goes low, the first connection relationship is recorded as "first target adapter card → third motherboard port". Repeating this operation yields the set of actual connection relationships between all adapter cards and motherboard ports.

[0032] It's easy to understand that during a single test, the number of target adapter cards is 1, and the number of first connection relationships is also 1. When the motherboard contains only one adapter card as the target adapter card, the actual set of connection relationships contains only one first connection relationship.

[0033] Step S103: Match the first connection relationship with the first preset connection relationship to determine the first detection result for the first connection relationship.

[0034] In the embodiments of this application, the first preset connection relationship refers to the correct correspondence between the target adapter card and the motherboard port, pre-defined according to the system configuration file or hardware design specifications. The first preset connection relationship is typically stored in the firmware of the baseboard management controller or loaded by upper-layer software during system initialization. For example, in a standard configuration, the first target adapter card should be connected to the first motherboard port, the second target adapter card should be connected to the second motherboard port, and so on. The first preset connection relationship serves as the benchmark for determining whether the connection is correct.

[0035] The first connection relationship and the first preset connection relationship may contain the same target adapter card. During matching, it can be determined whether the motherboard ports contained in the first connection relationship and the first preset connection relationship are the same. If they are the same, the matching result is a successful match, and the first detection result can be either a successful detection or a successful match; if they are different, the matching result is a failed match, and the first detection result can be either a failed detection or a failed match.

[0036] Based on the embodiments disclosed in this application, a hardware detection path is established by multiplexing the in-situ detection signal of the adapter card as the first detection signal in the first target state. The baseboard management controller controls the first detection signal of the target adapter card to go low, detects the signal response of the corresponding motherboard port on the motherboard side, determines the actual connection relationship, and matches it with the preset correct connection relationship, thereby realizing automatic and accurate detection of the insertion position of the target adapter card. This method does not require modification of the hardware structure and does not require waiting for the upper-layer software to start, significantly improving detection efficiency and maintenance convenience.

[0037] In some embodiments, such as Figure 2 As shown, Figure 2 A flowchart illustrating a detection method provided in this application embodiment. Figure 2 The step S101 of "controlling the target adapter card to the first signal state" can be achieved through steps S201 and S202: Step S201: Determine at least one adapter card connected to multiple motherboard ports, and control at least one adapter card to the second signal state.

[0038] In the embodiments of this application, after the adapter card is connected to the motherboard of the server, regardless of whether the motherboard port it is connected to is correct, the presence detection signal will definitely be pulled low after the adapter card is connected. Therefore, the server's control device can read that a card is connected. In this way, the control device can identify at least one adapter card connected to multiple motherboard ports.

[0039] Meanwhile, since the server hardware system is currently in the first target state, the in-situ detection signal is not yet performing actual in-situ detection. Therefore, the control device can uniformly set all adapter cards to the second signal state during the detection phase, i.e., enter the connectivity detection mode. In this mode, the control device pulls the PRSNT_N signal high on all adapter cards, so that these signals no longer reflect the device insertion status, but are used as detection channels. This operation ensures that subsequent independent detection of individual adapter cards will not be interfered with by signals from other adapter cards.

[0040] Taking a control device composed of BMC and FPGA as an example, when the server is in S5 state (soft shutdown state, AC power is still on), the BMC can first establish a connection with the FPGA on the power supply board through the Inter-Integrated Circuit (I2C) communication protocol, and send control commands to start the detection process (for example, by using a custom connection detection function to assign the value of the in-situ detection signal to the value of the connection detection signal to disable the regular device in-situ detection function), so that the entire system enters a dedicated topology detection mode.

[0041] Step S202: Determine the target adapter card in at least one adapter card and control the target adapter card to the first signal state.

[0042] In the embodiments of this application, based on the fact that the plurality of adapter cards have been placed in the second signal state, a specific target adapter card can be selected one by one and controlled to the first signal state, while other unselected adapter cards continue to maintain a high level state.

[0043] Using the example above, the BMC can send instructions to the FPGA via the I2C bus, and the FPGA can control the I / O Expander (IOEXP) corresponding to the target adapter card to pull the PRSNT_N signal of the target adapter card low, thereby causing the target adapter card to enter the first signal state.

[0044] Based on the above embodiments disclosed in this application, all adapter cards can be pulled high to the second signal state first, and then the target adapter card can be pulled low to the first signal state. By successively pulling the target adapter cards low to the first signal state, the target adapter cards can be activated one by one for connection relationship detection, which can improve the control accuracy of the target adapter cards in connection detection, and thus improve the accuracy of connection relationship detection.

[0045] In some embodiments, such as Figure 3 As shown, Figure 3 A flowchart illustrating a detection method provided in this application embodiment. Figure 3 Step S102 can be achieved through steps S301 and S302: Step S301: Determine the target motherboard port that is in the first signal state among multiple motherboard ports.

[0046] In the embodiments of this application, the first signal state here refers to the state where, after the system enters the first target state, the IOEXP on the BMC-controlled adapter card pulls the PRSNT_N signal of a specific pin low (i.e., sets it to a low level), and at this time, the PRSNT_L signal of the corresponding motherboard port on the motherboard side is also synchronously pulled low. The first signal state is used to indicate whether the motherboard port channel connected to the target adapter card currently being detected is correct.

[0047] The target motherboard port refers to the motherboard port that is confirmed to be physically connected to the target adapter card during the current detection process. The target motherboard port is determined by the BMC through scanning the IOEXP on the motherboard, reading the PRSNT_L signal status of each motherboard port, and identifying the only port that is at a low level. For example, in a dual adapter card configuration, if the PRSNT_N signal of the target adapter card is pulled low, and only the PRSNT_L signal of port 1 becomes low, then port 1 is the target motherboard port.

[0048] Using the example above, BMC can scan the I / O Expander (IOEXP) on the motherboard side to read the PRSNT_L signal status of each motherboard port, determine which motherboard port's PRSNT_L signal also goes low, and thus determine the actual motherboard port location where the target adapter card is connected.

[0049] Step S302: The target motherboard port is determined as the motherboard port connected to the target adapter card, thus obtaining the first connection relationship between the target motherboard port and the target adapter card.

[0050] In the embodiments of this application, the first connection relationship refers to the topological mapping relationship formed between the target adapter card and the target motherboard port that is actually physically connected to it on the motherboard. When the BMC identifies a unique target motherboard port that is in the first signal state (i.e., low level), it considers that the target motherboard port to be the port that the current target adapter card is actually connected to, and the connection relationship between the target adapter card and the target motherboard port is the first connection relationship.

[0051] It is easy to understand that steps S301 and S302 can be repeated multiple times to traverse all the adapter cards connected to the server motherboard, thereby obtaining the first connection relationship between each adapter card and the motherboard port.

[0052] Based on the above embodiments disclosed in this application, a first connection relationship can be actively established between the target adapter card and the motherboard port in the first signal state, thereby improving the accuracy of connection relationship detection.

[0053] In some embodiments, such as Figure 4 As shown, Figure 4 A flowchart illustrating a detection method provided in this application embodiment. Figure 4 Step S103 can be achieved through steps S401 and S402: Step S401: If the first connection relationship matches the first preset connection relationship successfully, determine that the first detection result for the first connection relationship is a correct connection.

[0054] In the embodiments of this application, a successful match means that the current first connection relationship is completely consistent with the first preset connection relationship, that is, the adapter card is correctly paired with the corresponding motherboard port on the motherboard. When the match is successful, the system determines that the first connection relationship is correct and records the normal state without further intervention.

[0055] In one possible embodiment, after each first connection relationship is acquired, it can be determined whether the first connection relationship can be successfully matched with a first preset connection relationship. If the match is successful, the first connection relationship between the next adapter card and the motherboard port can be acquired. If a match fails, the detection process can be interrupted immediately. This can avoid acquiring too many erroneous first connection relationships and improve the identifiability of the failed first connection relationships.

[0056] Alternatively, all first connection relationships can be obtained and matched at once. This way, all first connection relationships that fail to match the first preset connection relationship can be obtained at once. During subsequent maintenance, the operation and maintenance personnel can use logical analysis to determine the motherboard port that each adapter card should be connected to at once, which can greatly improve the efficiency of correcting incorrect connection relationships.

[0057] Step S402: If the first connection relationship fails to match the first preset connection relationship, the first detection result is determined to be a connection anomaly.

[0058] In the embodiments of this application, a matching failure indicates that the current first connection relationship does not match the first preset connection relationship, i.e., there is a case where the cable is plugged in incorrectly. For example, if the adapter card 1 should be connected to motherboard port 1, but is actually connected to motherboard port 2, the BMC will find during the scanning process that after pulling down the PRSNT_L signal of the adapter card 1, motherboard port 1 is not pulled down, while motherboard port 2 is pulled down, thus determining that the matching has failed.

[0059] In actual execution, "connection error" can be used as an identifier to trigger operations such as detecting interruption or termination and generating error reports.

[0060] Based on the above embodiments disclosed in this application, the baseboard management controller can actively initiate connection relationship matching detection in the first target state, compare the first connection relationship with the first preset connection relationship, and determine that the connection is correct when the match is successful and that the connection is abnormal when the match fails. Through the two judgment logics of the first detection result, the accuracy and reliability of the first detection result can be improved.

[0061] In some embodiments, such as Figure 5 As shown, Figure 5 A flowchart illustrating a detection method provided in this application embodiment. Figure 5 The above detection method may further include step S501: Step S501: If the first connection relationship fails to match the first preset connection relationship, an error report containing the first connection relationship is generated.

[0062] In the embodiments of this application, an error report refers to a system log or structured data file automatically generated and recorded by the baseboard management controller when an abnormal connection is detected. This file describes the connection error status, location, and suggested repair solutions. The error report includes not only the current actual connection status information but also the expected correct connection configuration, facilitating quick problem location by maintenance personnel. Error reports are typically stored locally on the baseboard management controller in text format (such as JSON or XML) or uploaded to a remote management system via a network as system log entries.

[0063] For example, in a server motherboard system, when the input / output cable of an adapter card is incorrectly inserted into a non-corresponding motherboard port, the baseboard management controller will generate an error report that includes: the input / output port of adapter card 1 is connected to motherboard port 2, but should be connected to motherboard port 1, and may include an indication of the incorrect and correct insertion positions.

[0064] Based on the embodiments disclosed in this application, an error report containing the first connection relationship can be generated when the first connection relationship fails to match the first preset connection relationship. This clearly records the physical connection status, providing maintenance personnel with accurate fault location information. Maintenance personnel can quickly resolve the problem of incorrect adapter card insertion position based on the error report. Generating error reports significantly improves the ease of maintenance for adapter card insertion position detection.

[0065] In some embodiments, such as Figure 6 As shown, Figure 6 A flowchart illustrating a detection method provided in this application embodiment. Figure 6 The above detection method may further include steps S104 to S108: Step S104: If the first detection result is a pass, based on the second detection signal, obtain the first electrical parameters of at least one power supply port connected to at least one graphics card.

[0066] In the embodiments of this application, if the first detection result is a pass, it indicates that all adapter cards are connected to the correct motherboard ports. However, since the rated power of the graphics cards on the adapter cards may differ, to ensure that the graphics cards on each adapter card can operate normally and achieve their respective functions, it is also necessary to ensure that the input power of each graphics card matches its rated power. In the server's auxiliary power supply, multiple ports can be pre-configured to output various power levels, thus, there is a possibility of incorrect insertion of the auxiliary power supply interface of the graphics card. Therefore, it is also necessary to perform insertion detection on the individual power supply ports of the graphics cards to ensure that they are connected correctly.

[0067] To achieve this, the connection between the graphics card and the power supply port can be detected by utilizing the correspondence between the graphics card's reset signal and the power supply parameters (such as voltage and current).

[0068] The aforementioned correspondence refers to the fact that when the graphics card's reset signal is pulled low, it triggers a graphics card reset, at which point the graphics card's power supply current decreases. Using this principle, the connection between the graphics card and its power supply port can be detected.

[0069] In some embodiments, the second detection signal is the graphics card reset signal, which can be used to trigger the graphics card reset. At this time, the first electrical parameters (such as current or voltage) of the power supply port can be obtained by an external ammeter or the ammeter built into the auxiliary power supply.

[0070] It should be noted that after the adapter card completes the first connection relationship detection, the connection detection signal can be restored to the in-situ detection signal, and the clock buffer of the reference clock on the adapter card with the graphics card plugged in can be activated at the same time, thereby preparing the server to enter the second target state.

[0071] Step S105: Control the target slot of the target adapter card to the first signal state; the target slot is connected to the target graphics card in at least one graphics card.

[0072] In the embodiments of this application, controlling the target slot of the target adapter card to be in a first signal state is actually achieved by using the reset pin of the target slot to put the target slot into the first signal state. Since the graphics card is inserted into the target slot of the adapter card, the target graphics card can enter a reset state after the target slot enters the first signal state.

[0073] Step S106: In response to the target slot being in a first signal state, obtain the second electrical parameters of at least one power supply port.

[0074] In the embodiments of this application, when the target graphics card enters the reset state, there will be a port in the auxiliary power supply whose electrical parameters change significantly. Therefore, when the target slot is in the first signal state, the second electrical parameters of each power supply port can be obtained. If only one power supply port participates in power supply, the second electrical parameters of that power supply port are obtained.

[0075] The second electrical parameter refers to the current or voltage value of the power supply port that is sampled again after the target slot is set to the first signal state. Since the graphics card shuts down its internal high-speed I / O and logic circuits after entering the reset state, power consumption decreases significantly, and the current decreases accordingly (e.g., a measured decrease of approximately 1.2A).

[0076] In actual execution, after the FPGA sets the target slot to the first signal state, it can immediately reread the current of all auxiliary power supply ports via the ADC_I2C bus to obtain the second electrical parameter. The difference between the second electrical parameter and the first electrical parameter directly reflects which power supply port the target slot is electrically connected to. For example, if only the current of the power supply port numbered P1 decreases after the target slot is set to the first signal state, it indicates that P1 is connected to the target slot.

[0077] Step S107: Based on the first electrical parameters and the second electrical parameters, determine the second connection relationship between the target graphics card and the connected power supply port.

[0078] In the embodiments of this application, the electrical parameter can be the output current or output power of the power supply port. This application uses output current as an example for illustration, but since changes in output current also cause changes in output power, it is also feasible to determine the second connection relationship using output power as an electrical parameter.

[0079] The second connection relationship refers to the mapping relationship established between the target graphics card (through its target slot) and the power supply port by comparing the first and second electrical parameters. The specific establishment process can include at least the following two methods: 1) Calculate the current difference between two measurements for each power supply port. If the difference exceeds a preset threshold (e.g., 0.8A), it is determined that the power supply port has a physical connection with the current target slot. For example, when the target slot is set to the first signal state, if only the current of P1 decreases, it is determined that the target slot is connected to P1. By performing the above operation on each target slot in sequence, a complete slot-power supply port mapping table is finally constructed, i.e., the second connection relationship.

[0080] 2) Based on the power supply port, compare the second electrical parameter with the first electrical parameter, find the target power supply port where the electrical parameter changes significantly, and determine that the target power supply port has a physical connection with the current target slot.

[0081] Step S108: Match the second connection relationship with the second preset connection relationship to determine the second detection result for the second connection relationship.

[0082] In the embodiments of this application, the second preset connection relationship refers to the correct connection scheme predefined according to the hardware design specifications, such as the correspondence between the rated operating power of the graphics card and the output power of each port of the auxiliary power supply, which may include the target slot 1 being connected to power supply port 1, the target slot 2 being connected to power supply port 2, etc.

[0083] In actual execution, the BMC in the control device can compare the actual detected second connection relationship with the second preset connection relationship. If they are completely consistent, the second detection result is a pass; otherwise, the detection fails, and the specific error location is reported. For example, if the detection finds that target slot 1 is actually connected to power supply port 2, the BMC can terminate the detection process and generate an error log "Target slot 1 is incorrectly inserted into power supply port 2; it should be connected to power supply port 1," so that maintenance personnel can quickly locate the problem.

[0084] Based on the embodiments disclosed in this application, after the first detection result is a pass, the first electrical parameters of the power supply port are sequentially acquired, the target slot of the target adapter card is controlled to a first signal state to acquire the second electrical parameters, and the second connection relationship between the target graphics card and the connected power supply port is determined based on the two sets of electrical parameters. The second connection relationship is then matched with a second preset connection relationship to determine the second detection result. Since a change in the reset signal state of the graphics card's reset pin will cause a change in the graphics card's power supply current, the reset pin can be used to detect the second connection relationship between the graphics card and the power supply port based on this principle, without the need to build an additional connection link. This greatly increases the convenience of detecting the second connection relationship and improves its accuracy. At the same time, the second detection result can reflect whether the second connection relationship meets expectations. When the second detection result is a pass, it can ensure that each graphics card operates at an appropriate power after officially entering the working state, which can improve the operating stability of the graphics card. When the second detection result is a fail, it can detect the insertion error in time before the graphics card enters the working state, avoiding damage to the costly graphics card equipment, reducing the damage rate of the graphics card equipment, and extending the service life of the graphics card equipment.

[0085] In some embodiments, such as Figure 7 As shown, Figure 7 A flowchart illustrating a detection method provided in this application embodiment. Figure 7 The step S105, "controlling the target slot of the target adapter card to the first signal state", can be achieved through steps S601 and S602: Step S601: Determine at least one slot on the target adapter card that is connected to at least one graphics card, and control at least one slot to the second signal state.

[0086] In embodiments of this application, at least one graphics card refers to one or more graphics card devices installed in a server hardware system, which are inserted into slots provided by the target adapter card. Here, a slot refers to the physical interface location on the target adapter card used to install the graphics card, and each slot corresponds to a specific PCIe channel and electrical connection path.

[0087] The second signal state refers to the high-level state that pulls the reset signal of the slot high, that is, keeping all graphics cards in the non-reset state first.

[0088] It's easy to understand that when only one slot in the adapter card has a graphics card, the reset signal of that slot can be pulled high to put it into the second signal state, thus ensuring the standardization of the entire process.

[0089] Step S602: Determine at least one target slot connected to the target graphics card and control the target slot to the first signal state.

[0090] In the embodiments of this application, the target graphics card refers to a specific graphics card device in the system that requires connection verification, typically configured by the system or specified by the user. The target slot refers to the specific slot physically connected to the target graphics card. The first signal state refers to pulling the PRSNT_N signal of the target slot low, thereby enabling the target graphics card to enter a reset state.

[0091] For example, in a system with four graphics card slots, if the slot to be tested is SLOT1, the reset signals of the other three slots (SLOT2, SLOT3, and SLOT4) will all remain high, and the BMC can pull the reset signal of SLOT1 low alone.

[0092] It is easy to understand that steps S601 and S602 can be executed repeatedly. That is, after obtaining a second connection relationship between a target slot and the power supply port or detecting that connection relationship, steps S601 and S602 can be executed again. When step S601 is executed for the second time, it is only necessary to pull the reset signal of the previous target slot high; when step S602 is executed for the second time, it is only necessary to pull the reset signal of one of the other target slots that is different from the previous target slot low. Following the above logic, the high / low pulling of all target slots can be completed.

[0093] Based on the embodiments disclosed in this application, a reset signal can be used to control the slots connected to the graphics card to sequentially enter the second signal state, and the slots connected to the target graphics card to enter the first signal state. This allows for a standardized process of sequentially lowering the reset signal of each target slot, significantly improving the efficiency of detecting the second connection relationship between the graphics card and the power supply port.

[0094] In some embodiments, such as Figure 8 As shown, Figure 8 A flowchart illustrating a detection method provided in this application embodiment. Figure 8 Step S107 can be achieved through steps S701 and S702: Step S701: Based on the first electrical parameter and the second electrical parameter, determine at least one target power supply port in which the change value of electrical parameter satisfies the target threshold.

[0095] In the embodiments of this application, the electrical parameter change value refers to the amount of change in electrical parameters such as current or voltage at the power supply port before and after a specific operation (such as pulling the PERESET_N signal low). The electrical parameter change value is used to determine the target power supply port among the power supply ports. The target threshold is a preset standard value used to determine whether the change in electrical parameters is significant, and is usually set according to hardware characteristics. For example, the measured current drop on the NV RTX4000 is about 1.2A, so 1.0A or 0.8A can be used as the target threshold.

[0096] Therefore, the target power supply port can be determined by calculating the changes in the first and second electrical parameters and by comparing the changes in the electrical parameters with the target threshold.

[0097] For example, the current difference between two measurements for each power supply port can be calculated. If the difference exceeds a preset threshold (e.g., 0.8A), the source power supply port for calculating the first and second electrical parameters of that difference is the target power supply port, and it can be determined that this power supply port has a physical connection with the current target slot. For example, when the target slot is set to the first signal state, if only the current of P1 drops by more than 0.8A, then P1 is determined to be the target power supply port.

[0098] Step S702: The target power supply port is determined as the power supply port connected to the target graphics card, thus obtaining the second connection relationship between the target power supply port and the target graphics card.

[0099] In the embodiments of this application, the second connection relationship refers to the physical connection mapping relationship between the target graphics card and the target power supply port. In this application, it is assumed that a second connection relationship exists between the slot that pulls down the reset signal and the target port whose actual electrical parameters are reduced. After obtaining the target port, the system actively binds the target power supply port to the target graphics card and records the second connection relationship between the target power supply port and the target graphics card, facilitating subsequent fault diagnosis and maintenance.

[0100] In practical applications, when the system detects a significant change in the current of the power supply port corresponding to a certain SLOT, it can confirm that the power supply port is the target power supply port. For example, in a quad-GPU server, if the current of the power supply port numbered CON3 drops by 1.5A (exceeding the target threshold of 1.0A) after SLOT1 pulls PERESET_N low, then the system will identify CON3 as the target power supply port of SLOT1 and establish a second connection relationship between SLOT1 and CON3.

[0101] By performing the above operations on each target slot in sequence, a complete slot-power port mapping table can eventually be constructed, which contains all the secondary connection relationships.

[0102] Based on the embodiments disclosed in this application, the change value of electrical parameters can be calculated based on the first electrical parameter and the second electrical parameter, and the change value of electrical parameters can be compared with a target threshold to identify the target power supply port connected to the target graphics card. In this way, the physical connection relationship between the target power supply port and the target graphics card can be accurately determined, thereby avoiding graphics card failure or service interruption caused by incorrect connection of the target power supply port, and thus improving the accuracy of the second connection relationship.

[0103] In some embodiments, such as Figure 9 As shown, Figure 9 A flowchart illustrating a detection method provided in this application embodiment. Figure 9 After step S108, the above detection method may further include steps S109 and S110: In step S109, in response to the completion of detection of each graphics card in at least one graphics card, at least one slot connected to at least one graphics card is controlled to a second signal state, and a restart command is sent; the restart command is used to instruct the hardware system to perform a DC restart.

[0104] In the embodiments of this application, after the connection relationship between the graphics card and the power supply port is detected, if the detection process ends normally, it can be considered that the first connection relationship between the adapter card and the motherboard port and the second connection relationship between the graphics card and the power supply port are both correctly connected. At this time, the server hardware device can initiate a DC reboot process to provide DC power to the central processing unit (CPU) of the server hardware device. During this process, to avoid the graphics card repeatedly performing reset operations, the slots with graphics cards can be uniformly adjusted to the second signal state.

[0105] DC restart refers to the process of cutting off the DC power supply to a server device during operation (such as unplugging the adapter, battery, or disconnecting the 12V / 5V power supply to the motherboard) and then powering it back on. In this application, DC restart is used to supply DC power to the server's CPU.

[0106] Step S110: In response to the completion of the hardware system restart, control the hardware system to enter the second target state.

[0107] In the embodiments of this application, hardware system reboot completion means that the hardware system has completed the entire process from power failure to power restoration, CPU initialization, firmware loading, and enumeration of each of the at least one graphics card, and has reached a runnable state. The hardware system reboot completion event is determined by the BMC by monitoring the hardware system power status, CPU health signals, and the ready status returned by UEFI. Once the hardware system reboot completion is confirmed, the BMC will perform preset subsequent operations, such as updating system logs, clearing temporary caches, and restoring network services.

[0108] The second target state refers to the operating state that the hardware system enters after completing a DC restart, typically the normal operating state (S0) or a preparatory state for entering the S0 state. The second target state may include specific Basic Input Output System (BIOS) / UEFI settings, PCIe topology, power management strategies, etc.

[0109] For example, when the Baseboard Management Controller (BMC) receives a hardware system boot completion signal from the Unified Extensible Firmware Interface (UEFI), it considers the hardware system to have successfully restarted. At this point, the BMC will control the hardware system to enter a second target state, such as loading the default BIOS configuration, enabling each of the at least one verified graphics card, and enabling remote management functions. If a connection error is detected during the detection process, the BMC will also record the error details in the log to facilitate quick problem localization by maintenance personnel.

[0110] Based on the embodiments disclosed in this application, after the detection is completed, at least one slot in the hardware system is controlled to a second signal state and a restart command is sent. Then, after the hardware system restarts, the hardware system is controlled to enter a second target state. In this way, an automated process from detection to recovery can be realized, thereby reducing manual intervention and troubleshooting time, and thus improving the efficiency and reliability of server deployment and maintenance.

[0111] This application provides an electronic device, including a motherboard and a detection unit; the motherboard is equipped with multiple adapter cards; wherein... The detection unit is configured to, in response to the hardware system entering a first target state, control the target adapter card to a first signal state based on a first detection signal; wherein the target adapter card is connected to one of a plurality of motherboard ports of the hardware system; the first detection signal is capable of detecting the presence status of the adapter card among the plurality of motherboard ports in response to the hardware system entering a second target state; determining a first connection relationship between the target adapter card in the first signal state and the connected motherboard port; matching the first connection relationship with a first preset connection relationship, and determining a first detection result for the first connection relationship.

[0112] The detection unit may include a baseboard management controller and a field-programmable gate array (FPGA). The FPGA is mounted on a power supply board that powers the motherboard and is used to control the power supply to the hardware on the motherboard. During the pull-down and pull-up operations of the first and second detection signals, the baseboard management controller can be the main control unit, and the FPGA can be the execution unit. That is, the baseboard management controller sends control signals to the FPGA, and the FPGA executes the pull-down and / or pull-up operations of the first and / or second detection signals based on the control signals.

[0113] The following describes the application of the detection method provided in the embodiments of this application in a real-world scenario.

[0114] Current server motherboard designs for Artificial Intelligence (AI) servers require specific connectors for the cable riser's motherboard port (MCIO). Figure 10 The issue of misplaced (blue lines in the diagram) requires waiting until the system (server hardware system) boots into the operating system to check which I / O operations are not recognized or have incorrect bandwidth to determine if the problem exists. Because the operating system boots very slowly, this results in very low efficiency.

[0115] When the cable adapter is connected to the GPU card, the GPU card's auxiliary power cable ( Figure 10 The red line in the diagram also indicates a risk of incorrect connection. If the AUX power cable is connected incorrectly and a power fault occurs, the baseboard management controller will be unable to report the corresponding fault SLOT information to the system, making it difficult for service personnel to accurately locate the fault and affecting maintenance efficiency.

[0116] To address the aforementioned issues, this solution proposes an automatic detection method for the MCIO topology by time-division multiplexing the PRSNT_N signal (i.e., the presence detection signal) without modifying the system hardware. The detection is completed as soon as the system enters the S5 phase, eliminating the need to wait for the system to enter S0, thus significantly improving detection efficiency and maintenance convenience. This solution utilizes the BMC, FPGA, UEFI, and hardware in collaborative operation to further perform AUX power cable mis-insertion detection during the DC reboot phase.

[0117] The specific implementation method is as follows: During system startup, the MCIO connectivity is first checked. This check is based on the existing hardware design of the server motherboard. A hardware path is constructed by time-division multiplexing single-function signals into multi-function signals, starting from the BMC, passing through the RISER adapter card, cable, to the motherboard MCIO, and then back to the BMC: BMC => RISER => RISER_MCIO => cable => MB_MCIO => MB_CKT => BMC. After the system enters the S5 phase, the BMC scans this path and establishes...<RISER_MCIO : MB_MCIO> The mapping relationship between them is as follows: A RISE card has one MCIO, and the motherboard also has one MCIO; these two MCIO connectors are connected by a cable. Multiple RISE cards can be installed on the same motherboard, and a specific RISE card has a fixed correspondence with a specific MCIO on the motherboard. The BMC compares the actual established mapping with the current system configuration information.<RISER_MCIO : MB_MCIO> If the mapping relationship is inconsistent, the BMC will report the incorrect MCIO location and clearly indicate the actual MCIO serial number connected to the current MCIO cable and the target MCIO serial number that should be connected, so as to quickly locate and correct the error.

[0118] In addition, to detect incorrect AUX power cable insertion, the system sequentially pulls down the PERESET_N signal of each SLOT before DC reboot. When the Compute Extension Module (CEM) card enters the RESET state from the L0 state, all high-speed I / O and internal logic enter the reset state, and the current will drop significantly (in actual testing on the graphics card (NV RTX) 4000, the current drops by about 1.2A, which is easy to detect). Figure 11 The fluctuations in the medium current signal. By monitoring this current change, the correspondence with PERESET_N can be detected.

[0119] To achieve the above functions, signal topology analysis of the MCIO interface on the server motherboard is required. Its topology is as follows: Figure 12As shown. The PRSNT_N signal is originally used to indicate whether a device is inserted into the MCIO connector. When a device is inserted, the PRSNT_N signal is pulled low, thereby enabling the corresponding MCIO reference clock ref clock 1202, and notifying BMC1201 that the device has been inserted through IOEXP1203.

[0120] In this scheme, the path of the PRSNT_N signal is used as the core link of the detection path. That is, in the path BMC=>RISER=>RISER_MCIO =>cable=>MB_MCIO =>MB_CKT=>BMC, the system highlights the PRSNT_N signal.

[0121] In conventional designs, the PRSNT signal of the CEM slot is typically connected to the PRSNT1_L pin of the MCIO. When a card is inserted, PRSNT1_L is pulled low to activate the clock buffer on the motherboard and notify the BMC for asset management. At this time, the PRSNT1_L signal on the motherboard's MCIO is pulled to GND by the PRSNTB_N signal on the slot card, making it difficult to flexibly control the state of the PRSNT1_L signal. To solve this problem, this solution connects the CEM_PRSNT signal to the PDB_FPGA (each CEM has four PRSNT signals, which are short-circuited into a single signal before being connected to the FPGA). Even with a card inserted, the PDB_FPGA can still control the signal state by manipulating the IOEXP on the RISER, allowing it to be used for other functions in S5 state.

[0122] After the system completes the detection in S5 state, PDB_FPGA sets MCIO_PRSNT1_L to be equal to CEM_PRSNT. The FPGA acts as a signal switcher with two inputs: 1. CEM_PRSNT of the RISER card; 2. A control signal from the BMC; and one output: MCIO_PRSNT1_L. In detection mode, the FPGA sets MCIO_PRSNT1_L to the control signal from the BMC, which is used for misinsertion detection. After detection, the FPGA sets MCIO_PRSNT1_L to CEM_PRSNT, restoring MCIO_PRSNT1_L to its function as an indicator signal to indicate whether a PCIe card is inserted on the RISER card. If so, MCIO_PRSNT1_L is pulled low, thereby enabling the corresponding MCIO's CLOCK.

[0123] The system operation is divided into three stages, and its overall execution topology is as follows: Figure 13 As shown. The specific steps are as follows: Phase 1: In the first stage, its signal flow is as follows Figure 14 The first dashed line 1401 in the diagram is used to execute steps S01 to S07.

[0124] Step S01: Before the system enters state S0, BMC1301 communicates with FPGA1302 to control PDB to enter connectivity detection mode. In this mode, FPGA1302 pulls all PRSNT_N signals high through the FPGA_I2C bus and uses the PRSNT_N signals to perform connectivity detection.

[0125] Step S02: BMC1301 controls IOEXP on the RISER via FPGA_I2C to pull the PRSNT_N signal of the first RISER_MCIO low, while keeping the PRSNT_N signals of the other RISER_MCIOs high.

[0126] Step S03: The BMC1301 scans the IOEXP on the motherboard via the I2C_BMC_MGMT0 bus, reads the PRSNT_L status of each MB_MCIO, and confirms which MB_MCIO's PRSNT_L is pulled low at the same time.

[0127] Step S04: If the detected MB_MCIO PRSNT_L state is LOW and is consistent with the expected MB_MCIO state corresponding to the current RISER, then the connection is correct; otherwise, BMC1301 generates an error report indicating that the MCIO connection of the RISER is incorrect.

[0128] Step S05: BMC1301 reports an error message, which includes the MB_MCIO serial number that the RISER_MCIO is actually connected to and the target MB_MCIO serial number that should be connected, so that maintenance personnel can quickly locate and correct the connection error between the RISER_MCIO and MB_MCIO.

[0129] Step S06: BMC1301 executes steps S02 to S05 sequentially to check each RISER_MCIO and confirm that the connection relationship between all RISERs and MB_MCIOs is correct.

[0130] Step S07: After completing all RISER_MCIO connection detections, FPGA1302 exits the connectivity detection mode.

[0131] Phase Two: In the second stage, its signal flow is as follows Figure 15The second dashed line 1501 in the figure is used to execute steps S08 and S09.

[0132] Step S08: FPGA1302 controls IOEXP on RISER via FPGA_I2C to make MCIO_PRSNT1_L equal to CEM_PRSNT (i.e., MCIO_PRSNT1_L = CEM_PRSNT2A&CEM_PRSNT2B&CEM_PRSNT2C&PRSNT2D), restoring the original function of MCIO_PRSNT1_L.

[0133] Step S09: When a graphics card 1303 is inserted into the RISER, MCIO_PRSNT1_L is pulled low, and the clock buffer on the motherboard will turn on the reference clock of the corresponding MCIO.

[0134] During the initial AC boot, UEFI requires a DC reboot operation before the full boot process is complete.

[0135] Phase Three: Step S11: By default, FPGA1302 pulls the PERESET_N signal high for all SLOTs, which does not affect the timing of the CPU starting training.

[0136] Step S12: Before preparing for DC reboot, UEFI first disables the error logging function of PCIe ports such as IEH and sends a notification to BMC1301, waiting for BMC1301 to return an instruction to allow DC reboot.

[0137] Step S13: After receiving the first DC reboot preparation notification sent by UEFI, BMC1301 sends an instruction to FPGA1302 to start the detection process of the connection relationship between graphics card 1303 and auxiliary power supply.

[0138] Step S14: The FPGA1302 reads the initial current value of each power supply port through the ADC_I2C bus and stores the read current value in a preset register.

[0139] Taking a device with 4 GPU slots as an example, the FPGA1302 controller first pulls the PERESET_N signal of SLOT1 low, and then reads the current value on the power supply port of the auxiliary power supply corresponding to each of the four GPU slots through the ADC_I2C bus.

[0140] Step S15: FPGA1302 compares the currently read current value with the initial current value. If a certain current drops significantly, it determines that the power supply port corresponds to the current SLOT1.

[0141] Step S16: The FPGA1302 updates the current values ​​of all power supply ports to new initial values ​​to support the subsequent detection process.

[0142] Step S17: Repeat steps S15 to S17 to sequentially check the connection relationship of the auxiliary power cables of the remaining three SLOTs.

[0143] Step S18: When the detection task of all SLOTs is completed, FPGA1302 pulls the PERESET_N signal of all SLOTs high and sends a notification to BMC1301 to indicate that the detection of all SLOTs has been completed.

[0144] Step S19: BMC1301 notifies the UEFI system that it can perform a DC Reboot operation.

[0145] In this way, the BMC, FPGA, UEFI and other hardware can work together to identify the cable connection status of the motherboard port and auxiliary power supply, ensuring accurate detection in the early stages of the system and improving the efficiency of system deployment and maintenance.

[0146] The advantages of this solution are: no modification to the existing hardware design is required, and MCIO topology identification and error reporting can be achieved simply by time-division multiplexing the PRSNT_N signal; detection can be completed in the S5 stage without waiting for the system to enter S0, which greatly saves time and costs; at the same time, combined with the FPGA current detection mechanism, the misconnection detection of auxiliary power cables can be realized in the DC reboot stage, which improves the reliability and service friendliness of the system.

[0147] Figure 16 A logic block diagram of a detection device provided in an embodiment of this application is shown below. Figure 16 As shown, the detection device 1600 may include: The first control module 1601 is used to control the target adapter card to a first signal state based on a first detection signal in response to the hardware system entering a first target state; wherein the target adapter card is connected to one of the multiple motherboard ports of the hardware system; the first detection signal can detect the presence status of the adapter card among the multiple motherboard ports in response to the hardware system entering a second target state. The first determining module 1602 is used to determine the first connection relationship between the target adapter card in the first signal state and the connected motherboard port; The second determining module 1603 is used to match the first connection relationship with the first preset connection relationship and determine the first detection result for the first connection relationship.

[0148] In some embodiments, the first control module 1601 includes: The first determining submodule is used to determine at least one adapter card connected to multiple motherboard ports and control at least one adapter card to the second signal state; The second determining submodule is used to determine the target adapter card in at least one adapter card and control the target adapter card to the first signal state.

[0149] In some embodiments, the first determining module 1602 includes: The third determination submodule is used to determine the target motherboard port that is in the first signal state among multiple motherboard ports; The fourth determination submodule is used to determine the target motherboard port as the motherboard port connected to the target adapter card, thereby obtaining the first connection relationship between the target motherboard port and the target adapter card.

[0150] In some embodiments, the second determining submodule 1603 includes: The fifth determining submodule is used to determine that the first detection result for the first connection relationship is correct if the first connection relationship matches the first preset connection relationship. The sixth determination submodule is used to determine the first detection result as a connection abnormality if the first connection relationship fails to match the first preset connection relationship.

[0151] In some embodiments, the detection device 1600 further includes: The generation module is used to generate an error report containing the first connection relationship if the first connection relationship fails to match the first preset connection relationship.

[0152] In some embodiments, the detection device 1600 further includes: The first acquisition module is used to obtain, based on the second detection signal, a first electrical parameter of at least one power supply port connected to at least one graphics card if the first detection result is a successful detection. The second control module is used to control the target slot of the target adapter card to the first signal state; the target slot is connected to the target graphics card in at least one graphics card. The second acquisition module is used to obtain the second electrical parameters of at least one power supply port in response to the target slot being in a first signal state. The third determining module is used to determine the second connection relationship between the target graphics card and the connected power supply port based on the first electrical parameters and the second electrical parameters. The fourth determining module is used to match the second connection relationship with the second preset connection relationship and determine the second detection result for the second connection relationship.

[0153] In some embodiments, the second control module includes: The first control submodule is used to determine at least one slot on the target adapter card that is connected to at least one graphics card, and control at least one slot to be in the second signal state; The second control submodule is used to determine the target slot connected to the target graphics card in at least one slot and control the target slot to the first signal state.

[0154] In some embodiments, the third determining module includes: The seventh determination submodule is used to determine, based on the first electrical parameter and the second electrical parameter, at least one target power supply port whose electrical parameter change value meets the target threshold. The eighth determination submodule is used to determine the target power supply port as the power supply port connected to the target graphics card, and obtain the second connection relationship between the target power supply port and the target graphics card.

[0155] In some embodiments, after the fourth determining module, the detection device 1600 further includes: The third control module is used to respond to the completion of detection of each graphics card in at least one graphics card, control at least one slot connected to at least one graphics card to the second signal state, and send a restart command; the restart command is used to instruct the hardware system to perform a DC restart; The fourth control module is used to control the hardware system to enter the second target state in response to the completion of the hardware system restart.

[0156] It should be noted that, in the embodiments of this application, if the above-described detection method is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to the related technology, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, and firmware.

[0157] This application provides another electronic device, including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements some or all of the steps in the above-described method.

[0158] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements some or all of the steps in the above-described method. The computer-readable storage medium can be transient or non-transient.

[0159] This application provides a computer program including computer-readable code. When the computer-readable code runs in an electronic device, the processor in the electronic device executes some or all of the steps in the above-described method.

[0160] This application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium; in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0161] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referred to interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0162] Figure 17 This is a hardware entity diagram of an electronic device provided in an embodiment of this application, such as... Figure 17 As shown, the hardware entity of the electronic device 1700 includes a processor 1701 and a memory 1702, wherein the memory 1702 stores a computer program that can run on the processor 1701, and the processor 1701 executes the program to implement the steps in the method of any of the above embodiments.

[0163] The memory 1702 stores computer programs that can run on the processor. The memory 1702 is configured to store instructions and applications that can be executed by the processor 1701. It can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) in the processor 1701 and various modules in the electronic device 1700. It can be implemented by flash memory or random access memory (RAM).

[0164] When the processor 1701 executes the program, it implements the steps of any of the above-mentioned detection methods. The processor 1701 typically controls the overall operation of the electronic device 1700.

[0165] This application provides a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement the steps of the detection method as described in any of the above embodiments.

[0166] It should be noted that the descriptions of the storage medium and device embodiments above are similar to the descriptions of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0167] The aforementioned processor can be at least one of the following: Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), Digital Signal Processing Device (DSPD), Programmable Logic Device (PLD), Field Programmable Gate Array (FPGA), Central Processing Unit (CPU), Controller, Microcontroller, and Microprocessor. It is understood that other electronic devices can also implement the functions of the aforementioned processor, and this application does not specifically limit the specific implementation.

[0168] The aforementioned computer storage media / memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM), etc.; or it can be various terminals that include one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0169] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0170] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0171] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0172] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0173] Furthermore, in the various embodiments of this application, all functional units can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units. Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0174] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0175] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A detection method, the method comprising: In response to the hardware system entering a first target state, the target adapter card is controlled to a first signal state based on a first detection signal; wherein the target adapter card is connected to one of the multiple motherboard ports of the hardware system; the first detection signal can detect the presence status of the adapter card among the multiple motherboard ports in response to the hardware system entering a second target state; Determine the first connection relationship between the target adapter card in the first signal state and the connected motherboard port; The first connection relationship is matched with the first preset connection relationship to determine the first detection result for the first connection relationship.

2. The method according to claim 1, wherein the control target adapter card is in a first signal state, comprising: Identify at least one adapter card connected to the plurality of motherboard ports, and control the at least one adapter card to a second signal state; The target adapter card among the at least one adapter card is identified, and the target adapter card is controlled to be in the first signal state.

3. The method according to claim 2, wherein determining the first connection relationship between the target adapter card in the first signal state and the connected motherboard port includes: Determine the target motherboard port among the plurality of motherboard ports that is in the first signal state; The target motherboard port is determined as the motherboard port connected to the target adapter card, thus obtaining the first connection relationship between the target motherboard port and the target adapter card.

4. The method according to claim 1, wherein matching the first connection relationship with a first preset connection relationship to determine a first detection result for the first connection relationship includes: If the first connection relationship successfully matches the first preset connection relationship, the first detection result for the first connection relationship is determined to be a correct connection. If the first connection relationship fails to match the first preset connection relationship, the first detection result is determined to be a connection anomaly.

5. The method according to claim 4, further comprising: If the first connection relationship fails to match the first preset connection relationship, an error report containing the first connection relationship is generated.

6. The method according to claim 1, further comprising: If the first detection result is a pass, based on the second detection signal, the first electrical parameters of at least one power supply port connected to at least one graphics card are obtained; The target slot of the target adapter card is controlled to the first signal state; the target slot is connected to the target graphics card in the at least one graphics card. In response to the target slot being in the first signal state, the second electrical parameters of the at least one power supply port are obtained; Based on the first electrical parameter and the second electrical parameter, a second connection relationship between the target graphics card and the connected power supply port is determined; The second connection relationship is matched with the second preset connection relationship to determine the second detection result for the second connection relationship.

7. The method according to claim 6, wherein controlling the target slot of the target adapter card to the first signal state includes: Identify at least one slot on the target adapter card that is connected to at least one graphics card, and control the at least one slot to a second signal state; Identify the target slot that is connected to the target graphics card in the at least one slot, and control the target slot to the first signal state.

8. The method according to claim 7, wherein determining the second connection relationship between the target graphics card and the connected power supply port based on the first electrical parameters and the second electrical parameters comprises: Based on the first electrical parameter and the second electrical parameter, determine the target power supply port in the at least one power supply port whose electrical parameter change value meets the target threshold. The target power supply port is determined as the power supply port connected to the target graphics card, thus obtaining the second connection relationship between the target power supply port and the target graphics card.

9. The method according to claim 6, after matching the second connection relationship with the second preset connection relationship and determining the second detection result for the second connection relationship, the method further includes: In response to the completion of detection for each of the at least one graphics card, the at least one slot connected to the at least one graphics card is controlled to be in the second signal state, and a restart command is sent; the restart command is used to instruct the hardware system to perform a DC restart; In response to the completion of the hardware system restart, the hardware system is controlled to enter the second target state.

10. An electronic device, comprising a motherboard and a detection unit; wherein the motherboard is provided with a plurality of adapter cards; wherein, The detection unit is configured to control the target adapter card to a first signal state based on a first detection signal in response to the hardware system entering a first target state; wherein the target adapter card is connected to one of the multiple motherboard ports of the hardware system; the first detection signal can detect the presence status of the adapter card among the multiple motherboard ports in response to the hardware system entering a second target state; Determine the first connection relationship between the target adapter card in the first signal state and the connected motherboard port; The first connection relationship is matched with the first preset connection relationship to determine the first detection result for the first connection relationship.

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