A solid state disk regulation method, device and equipment

Abstract

The application provides a solid state disk regulation method, device and equipment, the method comprises the following steps: obtaining the first attribute information of the current input and output task, and predicting the second attribute information of the next input and output task according to the first attribute information; determining the time period type according to the first attribute information and the second attribute information, the time period type comprises idle and non-idle; obtaining the running state information of the flash memory grain of the solid state disk according to the time period type; determining the health state level of the flash memory grain according to the running state information; obtaining the load state of the solid state disk, determining the regulation strategy of the flash memory grain according to the load state and the health state level, and executing the regulation strategy. The application realizes the balance of the power consumption and performance of the solid state disk.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a solid-state drive control method, apparatus, and device. Background Technology

[0002] Solid-state drives (SSDs) have gradually replaced traditional hard disk drives (HDDs) as the mainstream storage device due to their advantages such as fast read / write speeds and strong shock resistance. However, due to the physical characteristics of NAND flash memory, SSDs generally face a trade-off between read / write performance and power consumption during use. Under high load, to meet the requirements of write accuracy and speed, the controller needs to process multiple tasks simultaneously, leading to a significant increase in power consumption and a surge in SSD temperature. Prolonged high temperatures accelerate NAND aging, exacerbate threshold voltage deviation, and affect its lifespan. Under low load, SSDs reduce power consumption by lowering the threshold voltage of the NAND chips, but this directly affects data storage accuracy and processing efficiency. To balance power consumption and performance, current SSDs mostly use fixed strategies or simple threshold switching. For example, some SSDs are preset to performance mode or power mode at the factory, or the mode is switched based on whether the IO (Input / Output) queue depth is greater than a threshold. These methods do not consider real-time load changes and the actual state of the NAND chips, which can easily lead to insufficient performance under high load or wasted power under low load, affecting user experience and accelerating SSD aging. Summary of the Invention

[0003] This application provides a solid-state drive control method, apparatus, and device to at least solve the above-mentioned technical problems existing in the prior art.

[0004] According to a first aspect of this application, a solid-state drive (SSD) control method is provided, the method comprising: Obtain the first attribute information of the current input / output task, and predict the second attribute information of the next input / output task based on the first attribute information; Based on the first attribute information and the second attribute information, the time period type is determined, and the time period type includes idle and non-idle; Based on the time period type, obtain the operating status information of the flash memory chips of the solid-state drive; Based on the operating status information, the health status level of the flash memory chip is determined; The load status of the solid-state drive is obtained, and the control strategy for the flash memory chips is determined based on the load status and the health status level, and the control strategy is executed.

[0005] In one possible implementation, predicting the second attribute information for the next input / output task based on the first attribute information includes: The first attribute information is input into the prediction model to obtain the second attribute information of the next input-output task output by the prediction model.

[0006] In one possible implementation, the prediction model is trained through the following operations: Acquire multiple consecutive task sequences, each of which includes multiple consecutive historical input / output tasks; Extract attribute information for each historical input-output task in each consecutive task sequence, and combine all attribute information of each consecutive task sequence into an input sequence in order; The input sequence is shifted forward by a preset number to obtain the target sequence; The prediction model to be trained is trained by using the input sequence as input and the target sequence as output, and the trained prediction model is obtained.

[0007] In one possible implementation, the first attribute information includes the end time of the current input / output task, and the second attribute information includes the start time of the next input / output task; Based on the first attribute information and the second attribute information, the time period type is determined, including: The idle period is determined based on the end time of the current input / output task and the start time of the next input / output task; In response to the fact that the current time is in an idle period, the period type is determined to be idle; In response to the fact that the current time is a non-idle period, the period type is determined to be non-idle.

[0008] In one possible implementation, obtaining the operating status information of the flash memory chips of the solid-state drive according to the time period type includes: In response to the time period being idle, the first operating status information of the flash memory chip is obtained; the first operating status information includes temperature, operating voltage, read / write latency, number of error bits, data write volume, number of erase / write cycles, and bad block percentage; In response to the time period being non-idle, the second operating status information of the flash memory chip is obtained. The second operating status information includes temperature, operating voltage, read / write latency, number of error bits, data write volume, number of erase / write cycles, bad block percentage, and programming voltage.

[0009] In one possible implementation, before obtaining the operating status information of the flash memory chips of the solid-state drive, the method further includes: The operating status information of the flash memory chip is collected according to a preset collection cycle; Each piece of data in the collected running status information is compared with its corresponding preset threshold. If any data exceeds the corresponding preset threshold, the collected running status information is identified as abnormal data, and the abnormal data is reported to the abnormal data receiving buffer through interrupt request and direct memory access. In response to the fact that all data does not exceed the corresponding preset threshold, the running status information collected this time is determined as normal data, until the number of collections reaches the preset number, and then all normal data collected within the preset number of collections is transferred to the normal data buffer.

[0010] In one possible implementation, obtaining the operating status information of the flash memory chips in the solid-state drive includes: Extract all runtime status information from the abnormal data receiving buffer and the normal data buffer; Based on the operational status information, the health status level of the flash memory chip is determined, including: All operational status information is input into the classification model in chronological order to obtain the health status level of the flash memory chip output by the classification model. The health status level includes healthy, normal, and abnormal.

[0011] In one possible implementation, the classification model is trained through the following operations: Obtain sample operating status information of multiple flash memory chips; The health status level of each group of samples is labeled with the sample operation status information. The sample health status level includes healthy, normal and abnormal. Using the running status information of each group of samples as input and the health status level of the samples as output, the classification model to be trained is trained to obtain the trained classification model.

[0012] In one possible implementation, determining the control strategy for the flash memory chip based on the load state and the health status level includes: In response to the health status level being healthy and the load status being high, the control strategy is determined to be: maintaining the current operating parameters of the flash memory chip, triggering a trimming operation, and reducing the wear leveling trigger frequency; In response to the health status level being healthy and the load status being low load, the control strategy is determined to be: reducing the operating voltage of the flash memory chip, triggering incremental inspection, moving data of storage blocks with more than a preset threshold of errors, increasing the garbage collection trigger frequency, and increasing the wear leveling trigger frequency.

[0013] In one possible implementation, the method further includes: In response to the health status level being normal and the load status being high load, the regulation strategy is determined as follows: in response to the temperature being less than a first threshold, the operating voltage of the flash memory chip is increased, a trimming operation is triggered, and the wear leveling trigger frequency is reduced; in response to the temperature being greater than a second threshold, the clock frequency of the flash memory chip is reduced. In response to the health status level being normal and the load status being low, the control strategy is determined to be: reducing the operating voltage of the flash memory chip, triggering a global inspection, moving data from storage blocks with an error count exceeding a preset threshold, increasing the garbage collection trigger frequency, and increasing the wear leveling trigger frequency.

[0014] In one possible implementation, the method further includes: In response to the abnormal health status level and the high load status, the control strategy is determined as follows: in response to the temperature being less than a first threshold, the operating voltage of the flash memory chip is increased while the clock frequency remains unchanged; in response to the temperature being greater than a second threshold, the clock frequency of the flash memory chip is decreased, the data to be written is migrated to the cache until the load decreases and then written back to the flash memory chip; and during load intervals, the operating voltage, garbage collection trigger frequency, and wear leveling trigger frequency of the flash memory chip are decreased. In response to the abnormal health status level and the low load status, the control strategy is determined to be: reducing the operating voltage and clock frequency of the flash memory chip, triggering key area inspection, moving data of storage blocks with more than a preset threshold of errors, increasing the garbage collection trigger frequency, and increasing the wear leveling trigger frequency.

[0015] In one possible implementation, the first attribute information or the second attribute information may further include at least one of the following: task type, logical block address, read / write size, and read / write type.

[0016] According to a second aspect of this application, a solid-state drive control device is provided, the device comprising: The prediction module is used to obtain the first attribute information of the current input-output task and predict the second attribute information of the next input-output task based on the first attribute information. The first determining module is used to determine the time period type based on the first attribute information and the second attribute information, wherein the time period type includes idle and non-idle; The acquisition module is used to acquire the operating status information of the flash memory chips of the solid-state drive according to the time period type; The second determining module is used to determine the health status level of the flash memory chip based on the operating status information. The control module is used to acquire the load status of the solid-state drive, determine the control strategy of the flash memory chips based on the load status and the health status level, and execute the control strategy.

[0017] According to a third aspect of this application, an electronic device is provided, comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in this application.

[0018] According to a fourth aspect of this application, a non-transitory computer-readable storage medium is provided storing computer instructions for causing the computer to perform the methods described in this application.

[0019] The solid-state drive (SSD) control method, apparatus, and device of this application acquire first attribute information of the current input / output task and predict second attribute information of the next input / output task based on the first attribute information; determine a time period type based on the first and second attribute information, the time period type including idle and non-idle; acquire the operating status information of the flash memory chips of the SSD based on the time period type; determine the health status level of the flash memory chips based on the operating status information; acquire the load status of the SSD; determine a control strategy for the flash memory chips based on the load status and the health status level; and execute the control strategy. By determining the health status level through operating status information and formulating and executing the control strategy in conjunction with the load status, the control strategy simultaneously considers the actual health status of the flash memory chips and the real-time load requirements of the SSD, achieving a balance between SSD power consumption and performance.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0021] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, in which: In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0022] Figure 1A schematic diagram illustrating the implementation flow of the solid-state drive control method provided in an embodiment of this application is shown; Figure 2 This paper illustrates a schematic diagram of the implementation process of the cache operation in the solid-state drive control method provided in an embodiment of this application; Figure 3 A schematic diagram of the composition structure of the solid-state drive control device according to an embodiment of this application is shown; Figure 4 A schematic diagram of the composition structure of an electronic device according to an embodiment of this application is shown. Detailed Implementation

[0023] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] The solid-state drive (SSD) control method provided in this application embodiment is described in detail below with reference to the accompanying drawings. This method can be executed by an electronic device, including the SSD and the computer device on which it is mounted or connected. The computer device can be a personal computer, server, laptop, tablet, smartphone, etc. The SSD includes a controller chip, a flash memory array, a cache (such as DRAM cache), and a communication interface. The controller chip is the core processing unit inside the SSD, responsible for managing data read / write, error checking, garbage collection, wear leveling, and other operations of the flash memory chips. It can also balance the performance and power consumption of the SSD by monitoring and adjusting parameters such as the operating voltage and clock frequency of the flash memory chips. In this application embodiment, the SSD controller chip is mainly used as the execution subject for description. However, those skilled in the art will understand that all or part of the steps of this method can also be executed by a processor (such as a CPU) or a separate monitoring chip that is communicatively connected to the SSD. This application does not specifically limit this.

[0025] Figure 1 A schematic diagram illustrating the implementation flow of the solid-state drive control method provided in this application embodiment is shown.

[0026] refer to Figure 1 This application provides a solid-state drive (SSD) control method, the method comprising: Operation 101: Obtain the first attribute information of the current input / output task, and predict the second attribute information of the next input / output task based on the first attribute information.

[0027] During the operation of a solid-state drive (SSD), the host continuously sends input / output (I / O) tasks to the SSD, such as data read requests or data write requests. Each I / O task carries its own attribute information, including but not limited to task type, logical block address, read / write size, read / write type, start time, and end time. This attribute information reflects the characteristics of the current I / O task and also implies the temporal regularity of the I / O task sequence. For example, in a file copy scenario, there is usually a certain interval between the end time of multiple consecutive I / O tasks and the start time of the next I / O task. The start and end times can be considered as the reception / completion time of the I / O request.

[0028] First, the first attribute information of the current I / O task is obtained. Then, the second attribute information of the next I / O task is predicted based on this first attribute information. The first attribute information refers to all the attribute information involved in the current input / output task throughout its entire lifecycle (from start to completion). Since the attribute information of I / O tasks is correlated over time, the attributes of subsequent I / O tasks can be inferred based on the attributes of the current I / O task; for example, the start time of the next I / O task can be predicted based on the end time of the current I / O task.

[0029] Operation 102: Determine the time period type based on the first attribute information and the second attribute information. The time period type includes idle and non-idle.

[0030] In one embodiment of this application, the first attribute information includes the end time of the current input / output task, and the second attribute information includes the start time of the next input / output task. Determining the time period type based on the first attribute information and the second attribute information includes: determining an idle time period based on the end time of the current input / output task and the start time of the next input / output task; determining the time period type as idle in response to the current time being an idle time period; and determining the time period type as non-idle in response to the current time being a non-idle time period.

[0031] After obtaining the first attribute information of the current I / O task and the predicted second attribute information of the next I / O task, the time period type to which the current moment belongs is determined based on these two sets of information. The time period type includes idle and non-idle.

[0032] Specifically, the time period between the end time of the current I / O task and the start time of the next I / O task is the idle period. During this period, no I / O tasks are being executed, and the SSD is in a relatively idle state. During the execution of the current I / O task and the next I / O task, the SSD is in a non-idle state. By comparing the predicted start time of the next I / O task with the end time of the current I / O task, it can be determined whether the current moment is in an idle or non-idle period.

[0033] Operation 103: Based on the time period type, obtain the operating status information of the flash memory chips in the solid-state drive.

[0034] Flash memory chips are the core physical medium used for data storage in solid-state drives (SSDs), also known as NAND (Not AND) flash memory. Flash memory chips include, but are not limited to, SLC (Single-Level Cell), MLC (Multi-Level Cell), and TLC (Triple-Level Cell). The operational status information of flash memory chips is fundamental data for assessing their current health. The range of operational status information available varies depending on the time period. During non-idle periods (i.e., during write operations), the flash memory chips are in a programming operation state, at which time parameters reflecting the stability of the write process, such as programming voltage, can be collected. During idle periods, however, there is no write operation, and parameters related to write operations cannot be obtained. Therefore, it is necessary to acquire operational status information using corresponding acquisition methods based on the time period type. More comprehensive operational status information should be acquired during non-idle periods, while basic operational status information should be acquired during idle periods. By acquiring differentiated operational status information based on the time period type, sufficient operational status information for subsequent health assessments can be obtained without affecting normal I / O performance.

[0035] Operation 104: Determine the health status level of the flash memory chip based on the operating status information.

[0036] After obtaining the operational status information of the flash memory chips, the health status level of the flash memory chips is determined based on this information. The health status level is used to characterize the current health level of the flash memory chips, and can be divided into different levels such as healthy, normal, and abnormal.

[0037] The various data points in the operational status information (such as temperature, voltage, read / write latency, and error rate) each reflect a specific aspect of the flash memory chip's health. Excessively high temperature may indicate that the flash memory chip is overheating; abnormally high read / write latency may indicate that the flash memory chip's performance is declining; and an elevated error rate may indicate that the flash memory chip's storage cells are aging. By comprehensively analyzing these data points, the current health status level of the flash memory chip can be determined.

[0038] Operation 105: Obtain the load status of the solid-state drive, determine the control strategy for the flash memory chips based on the load status and health status level, and execute the control strategy.

[0039] After determining the health status level of the flash memory chips, it's also necessary to obtain the current load status of the solid-state drive (SSD). The load status reflects the I / O workload the SSD is currently under. For example, high load indicates the SSD is processing a large number of I / O tasks, demanding high performance; low load indicates fewer I / O tasks, requiring more power optimization. Then, based on the combination of load status and health status level, a control strategy suitable for the current flash memory chips is determined and executed. This control strategy balances SSD performance and power consumption while ensuring data reliability. When the flash memory chips are in good health and under high load, the focus can be on maintaining performance; when the flash memory chips are in poor health and under low load, the focus can be on reducing power consumption and extending lifespan. By combining load status and health status level for comprehensive decision-making, a control scheme more suited to the current scenario can be developed, avoiding insufficient performance or wasted power due to decisions based on a single factor.

[0040] Thus, this embodiment of the application predicts the second attribute information of the next I / O task by obtaining the first attribute information of the current I / O task, thereby distinguishing between idle and non-idle periods, and obtaining the operating status information of the flash memory chips in a differentiated manner according to the time period type. Sufficient operating status data is obtained without affecting normal I / O performance. The health status level is determined by the operating status information, and a control strategy is formulated and executed in combination with the load status. This ensures that the control strategy considers both the actual health status of the flash memory chips and the real-time load requirements of the solid-state drive, avoiding the performance insufficiency or power waste caused by traditional fixed strategies or simple threshold switching methods that do not consider the real-time load and flash memory chip status, and achieving a balance between power consumption and performance.

[0041] In one embodiment of this application, predicting the second attribute information of the next input-output task based on the first attribute information includes: inputting the first attribute information into the prediction model to obtain the second attribute information of the next input-output task output by the prediction model.

[0042] Each I / O task carries a set of recordable attribute information during execution. For the current input / output task, its first attribute information can be represented as a feature vector as follows: .in, For I / O task type, For logical block address, For read / write size, For read / write type, For the start time, This is the end time.

[0043] The aforementioned feature vectors are preprocessed and used as input to the prediction model. The prediction model infers based on the attribute information of the current task and outputs the second attribute information of the next I / O task, including the task type, start time, end time, logical block address, read / write size, and read / write type. Thus, the attributes of the next task can be known in advance during the execution of the current task, providing a data foundation for subsequently determining the time period type.

[0044] In one embodiment of this application, the prediction model is trained through the following operations: acquiring multiple consecutive task sequences, each consecutive task sequence including multiple consecutive historical input-output tasks; extracting attribute information for each historical input-output task in each consecutive task sequence, and combining all attribute information of each consecutive task sequence in sequence into an input sequence; shifting the input sequence forward by a preset number to obtain a target sequence; training the prediction model to be trained with the input sequence as input and the target sequence as output to obtain a trained prediction model.

[0045] The training of the prediction model relies on I / O behavior log data recorded during SSD operation. Before training, multiple consecutive task sequences are first selected from the I / O logs. Each consecutive task sequence includes multiple historical I / O tasks that are consecutive in time, arranged in execution order, preserving the temporal dependencies between I / O tasks. For each historical I / O task in each consecutive task sequence, its attribute information is extracted. The attribute information of each task can be represented in the form of the following feature vector: The above feature extraction operation is performed on all tasks in each consecutive task sequence. All extracted feature vectors are arranged in chronological order of the tasks and combined into an input sequence. Each element in the input sequence corresponds to a feature vector of a historical I / O task, which as a whole reflects the evolution trajectory of I / O tasks in the time dimension.

[0046] When constructing the target sequence, the input sequence is shifted forward by a predetermined number of positions (e.g., one position forward) to obtain the target sequence. Specifically, if the input sequence contains feature vectors from task 1 to task n, then the target sequence contains feature vectors from task 2 to task n+1. Each element in the target sequence is shifted forward by one task position relative to the input sequence, representing the expected value of the input sequence at the next time step. The overlap length between the input and target sequences can be set according to actual training needs; a longer overlap length helps retain more temporal features.

[0047] After obtaining the input and target sequences, the input sequence is used as the input to the training samples, and the target sequence is used as the output label for the training samples to train the prediction model. Through iterative training with a large number of sample pairs, the model gradually learns and masters the evolutionary pattern of I / O task sequences in the time dimension, that is, it predicts the corresponding attribute features of future tasks based on the attribute features of several consecutive past tasks. After multiple iterations of training until the model converges, the trained prediction model is obtained, which can then be deployed for online prediction.

[0048] Furthermore, as various workloads run, SSD I / O log data accumulates continuously. A model update can be triggered when any of the following conditions are met: the span of the I / O data is an integer multiple of period T (period T can be set to one week, half a month, or one month, etc.), or there is a significant difference between the predicted read / write tasks and the actual read / write tasks in key attributes such as start time, read / write size, and read / write type. In this case, the training sample set can be expanded, the prediction model retrained, and the model parameters updated to ensure that the model's prediction accuracy can adapt to changes in the actual workload.

[0049] In one embodiment of this application, the above operation 103, which obtains the operating status information of the flash memory chip of the solid-state drive according to the time period type, includes: in response to the time period type being idle, obtaining the first operating status information of the flash memory chip; the first operating status information includes temperature, operating voltage, read / write latency, number of error bits, data write volume, number of erase / write cycles, and bad block percentage; in response to the time period type being non-idle, obtaining the second operating status information of the flash memory chip, the second operating status information includes temperature, operating voltage, read / write latency, number of error bits, data write volume, number of erase / write cycles, bad block percentage, and programming voltage.

[0050] Specifically, the time period determines which operational status information can be collected. During idle periods, the SSD is not performing write operations, and the flash memory chips are in a relatively static state. At this time, basic operational status information of the flash memory chips can be collected, including temperature, operating voltage, read / write latency, number of error bits, Error Correcting Code (ECC), data write volume, number of program / erase (PE) operations, and bad block percentage. During non-idle periods, the SSD is processing I / O tasks, especially during write operations, and the flash memory chips are in a programming state. At this time, in addition to collecting all operational status information from the idle period, the programming voltage can also be collected. The programming voltage is a key electrical parameter of NAND flash memory during write operations, and its value directly reflects the voltage stability of the flash memory chips during the programming process. The programming voltage can only be collected during write operations; during idle periods, the flash memory chips are not performing write operations, so this parameter cannot be obtained. Therefore, the second operational status information collected during non-idle periods includes an additional dimension of programming voltage compared to the first operational status information collected during idle periods.

[0051] Figure 2 This paper illustrates a schematic diagram of the implementation process of the cache operation in the solid-state drive control method provided in an embodiment of this application.

[0052] In one embodiment of this application, before operation 103, which obtains the operating status information of the flash memory chips of the solid-state drive, the following operations are also performed: Operation 201: Collect the operating status information of the flash memory chip according to the preset collection cycle.

[0053] During operation, the flash memory chip's operational status information is continuously collected at a preset acquisition cycle. Since the various data points in the operational status information change at different rates—for example, operating voltage and temperature change relatively quickly, requiring a higher acquisition frequency; while parameters such as read / write latency, error bits, data write volume, and erase / write cycles change relatively slowly, allowing for a lower acquisition frequency. The acquisition cycle for each of these data points can be configured independently; for example, the acquisition cycle for operating voltage and temperature can be set to 1ms, and the acquisition cycle for the other parameters can be set to 100ms. This application does not limit the specific value of the acquisition cycle.

[0054] Operation 202 compares each data point in the collected running status information with the corresponding preset threshold.

[0055] After each data acquisition, each piece of data in the acquired operational status information is compared with its corresponding preset threshold. The preset thresholds for each data point can be independently set based on the flash memory chip specifications and operating environment, and are used to determine whether the acquired data is within the normal range. For example, the thresholds are: temperature 60℃, operating voltage fluctuation 10%, NAND programming voltage peak 11V, average read / write latency 200µs, 5 consecutive page errors (10 pages), and PE (expiration / delay) threshold 8000.

[0056] Operation 203: In response to any data exceeding the corresponding preset threshold, the collected running status information is identified as abnormal data, and the abnormal data is reported to the abnormal data receiving buffer through interrupt request and direct memory access.

[0057] If any data point in a collected operational status update exceeds its corresponding preset threshold, it indicates a potential anomaly in the flash memory chip. In this case, all collected operational status information is identified as anomalous data, and the anomalous data is rapidly reported to the anomalous data receiving buffer via Interrupt Request (IRQ) and Direct Memory Access (DMA) methods, where it is processed in real-time by the anomaly interrupt service routine. The preset thresholds for each data point are independently set based on the flash memory chip's specifications and the operating environment.

[0058] Reporting abnormal data via interrupt requests and direct memory access offers high priority and fast response. Interrupt requests can interrupt currently executing low-priority tasks, enabling the SSD controller to respond immediately to abnormal conditions. Direct memory access, on the other hand, can quickly transfer data to the designated cache without CPU intervention, reducing data transfer latency and ensuring that abnormal data is processed in a timely manner, thus preventing data reliability from being affected by the failure to detect abnormal conditions in a timely manner.

[0059] Operation 204: In response to the fact that all data have not exceeded the corresponding preset threshold, the running status information collected this time is determined as normal data, until the number of collections reaches the preset number, and then all normal data collected within the preset number of collections is transferred to the normal data buffer.

[0060] When all data in a collected operational status report does not exceed the corresponding preset threshold, it indicates that the flash memory chip is currently in a normal state. This collected operational status information is then classified as normal data, and collection continues. Unlike interrupt reporting of abnormal data, normal data is reported in batches. Once the number of normal data collections reaches a preset number (e.g., 10 times), all normal data collected within that preset number is packaged and transmitted via the bus to the normal data buffer for subsequent health status assessment. Batch transmission reduces bus usage and CPU intervention, thereby lowering the transmission overhead of normal data.

[0061] Thus, this embodiment of the application achieves differentiated processing of abnormal and normal data by rapidly reporting abnormal data using interrupt requests and direct memory access, and transferring normal data in batches to the normal data buffer. Real-time reporting of abnormal data ensures timely response, while batch transmission of normal data reduces bus overhead. This ensures that abnormal situations can be detected in a timely manner, while avoiding the impact of frequent interrupts on normal I / O performance.

[0062] In one embodiment of this application, operation 103, which acquires the operating status information of the flash memory chips in the solid-state drive, includes: extracting all operating status information from the abnormal data receive buffer and the normal data buffer. Correspondingly, operation 104, which determines the health status level of the flash memory chips based on the operating status information, includes: inputting all operating status information sequentially into a classification model to obtain the health status level of the flash memory chips output by the classification model. The health status level includes healthy, normal, and abnormal.

[0063] After completing the hierarchical caching of runtime status information, all runtime status information is extracted from the abnormal data receiving buffer and the normal data buffer. The extracted runtime status information is normalized, and individual outliers are filtered to remove transient noise before being used as input to the classification model.

[0064] The classification model uses a Support Vector Machine (SVM) model. The input feature vector of the SVM model is:

[0065] in, For the temperature of the flash memory chip, Operating voltage For read / write latency, For the number of erroneous bits, For data write volume, The number of erase / write cycles, This represents the percentage of bad blocks (the ratio of the number of bad blocks to the total number of blocks).

[0066] The SVM classification model can be represented as:

[0067] in, For the feature weight vector, For bias terms, and The model is trained using a training set. After training, the real-time collected runtime status information is input into the classification model for calculation, based on... Output the corresponding health status level based on the given value: This indicates that the flash memory chip is in a healthy state. This indicates a normal state. This indicates an abnormal status.

[0068] In one embodiment of this application, the classification model is trained through the following operations: acquiring sample operating status information of multiple groups of flash memory chips; labeling the sample operating status information of each group of samples with a sample health status level, including healthy, normal and abnormal; using the sample operating status information of each group of samples as input and the sample health status level as output, training the classification model to be trained to obtain the trained classification model.

[0069] First, we obtained sample operational status information for multiple sets of flash memory chips. This sample data comes from the operational status records of flash memory chips accumulated during actual SSD operation or testing, covering the status of flash memory chips at different health levels. Each sample includes temperature (…). ), working voltage ( ), read / write latency ( ), number of error bits ( ), data write volume ( ), number of erase / write cycles ( ) and the percentage of bad blocks ( Features such as health status and generalization ability are considered. To ensure the generalization ability of the model, each health status level in the sample set should contain at least 10,000 samples, and the number of samples in each category should be relatively balanced to avoid the model being biased towards the majority class due to class imbalance.

[0070] Then, the health status level of each group of samples is labeled. The labeled health status levels include three categories: healthy, normal, and abnormal. Labeling is based on the specifications of the flash memory chips, historical performance, or expert experience. For example, samples with near-limited erase / write cycles, significantly increased error bits, or a bad block percentage exceeding a threshold can be labeled as abnormal; samples with parameters within the normal range but some indicators showing a deviation trend can be labeled as normal; and samples with all parameters in good condition can be labeled as healthy. The labeled sample set is then divided into a training set and a validation set. The training set is used for learning model parameters, and the validation set is used to evaluate the model's generalization performance.

[0071] Finally, using the operational status information of each group of samples as input and the health status level of the samples as output, the classification model to be trained is trained to obtain the trained classification model. The classification model adopts the SVM model. The goal of the SVM model is to find an optimal classification hyperplane that maximizes the margin between samples of different classes on both sides of the hyperplane. During training, the model learns the mapping relationship between input features and health status levels by minimizing structured risk. The SVM classification model can be represented as: By training the model using a training set, the optimal [model / model] can be obtained. and Parameter values. After training, the validation set is input into the model for evaluation. Once the model's classification accuracy meets the requirements, the trained SVM classification model can be deployed to the SSD controller for online inference. The trained classification model can be used to determine the health status level of real-time collected operational status information.

[0072] Furthermore, as various loads operate, NAND state-related data accumulates. When the accumulated data spans a period of time... When the period is an integer multiple of the period (The timeframe can be one week, half a month, or one month, etc.), or when the inferred NAND state differs significantly from the actual NAND state, the sample set can be expanded, the classification model retrained, and the classification model parameters updated.

[0073] In one embodiment of this application, the above operation 105 determines the control strategy of the flash memory chip based on the load status and health status level, including: in response to the health status level being healthy and the load status being high load, the control strategy is determined to be: maintaining the current operating parameters of the flash memory chip, triggering a trimming operation, and reducing the wear leveling trigger frequency; in response to the health status level being healthy and the load status being low load, the control strategy is determined to be: reducing the operating voltage of the flash memory chip, triggering incremental inspection, moving data for storage blocks with an error count exceeding a preset threshold, increasing the garbage collection trigger frequency, and increasing the wear leveling trigger frequency.

[0074] Specifically, when the classification model outputs a health status level of "healthy," it indicates that all operating parameters of the flash memory chips are within the normal range, and the flash memory chips have a good working foundation. At this point, the choice of control strategy mainly depends on the load status. If the current load is high, the SSD is processing a large number of I / O tasks, placing high demands on performance. Therefore, the control strategy focuses on maintaining the current performance level, maintaining the current operating parameters of the flash memory chips (including operating voltage, clock frequency, etc.), and not making active adjustments to avoid introducing performance fluctuations; at the same time, it triggers trimming operations to optimize data management and appropriately reduces the trigger frequency of wear leveling (WL) to reduce additional overhead under high load, ensuring that I / O performance is not affected by background maintenance tasks.

[0075] If the current load is low with few I / O tasks, the SSD has ample time for background maintenance. In this case, the control strategy focuses on optimizing the flash memory chip's state during the low-load window, reducing the chip's operating voltage to lower power consumption; triggering incremental inspections (i.e., inspecting only newly written blocks with a high write / erase count since the last inspection), reducing inspection overhead while ensuring data reliability in critical areas; migrating data from blocks with errors exceeding a preset threshold, moving data from unreliable blocks to healthy blocks; and increasing the frequency of garbage collection (GC) and wear leveling to proactively improve the flash memory chip's storage state, preparing for subsequent high-load tasks.

[0076] In one embodiment of this application, the above-mentioned operation 105, which determines the control strategy of the flash memory chip based on the load state and health state level, further includes: in response to the health state level being normal and the load state being high load, determining the control strategy as follows: in response to the temperature being less than a first threshold, increasing the operating voltage of the flash memory chip, triggering a trimming operation, and reducing the wear leveling trigger frequency; in response to the temperature being greater than a second threshold, reducing the clock frequency of the flash memory chip; in response to the health state level being normal and the load state being low load, determining the control strategy as follows: reducing the operating voltage of the flash memory chip, triggering a global inspection, performing data migration on storage blocks with an error count exceeding a preset threshold, increasing the garbage collection trigger frequency, and increasing the wear leveling trigger frequency.

[0077] Specifically, when the health status level is "normal," it indicates that some operating parameters of the flash memory chips have deviated from the normal range, requiring appropriate control measures to slow down aging. In this case, the control strategy needs to consider both load conditions and temperature factors.

[0078] If the current load is high and the health status is average, it's necessary to prevent further temperature increases and accelerated flash memory chip aging while ensuring performance. In this case, the temperature control strategy is implemented in stages: when the temperature is below a first threshold... At this point, the flash memory chip still has a temperature margin, which can temporarily increase the operating voltage to enhance write reliability, while triggering the Trim operation and reducing the wear leveling trigger frequency to reduce additional overhead under high load; when the temperature exceeds the second threshold... When the temperature rises to a certain level, it indicates that the flash memory chip is already at a high temperature. Continuing to heat up will accelerate bit flipping and NAND aging. At this point, the control strategy is to reduce the clock frequency of the flash memory chip to suppress the temperature rise and avoid further impact on data reliability due to high temperature.

[0079] If the current load is low and the health status is average, the SSD has ample time for comprehensive maintenance. At this time, the control strategy focuses on proactively improving the overall condition of the flash memory chips during the low-load window, reducing the operating voltage of the flash memory chips to lower power consumption; triggering a global inspection (inspecting all storage blocks) to comprehensively identify potential data reliability risks; migrating data from storage blocks with error counts exceeding a preset threshold; and simultaneously increasing the trigger frequency of garbage collection and wear leveling to free up more free blocks, reserving sufficient available resources for subsequent high-load tasks.

[0080] In one embodiment of this application, the above-mentioned operation 105, which determines the control strategy of the flash memory chip based on the load status and health status level, further includes: in response to an abnormal health status level and a high load status, determining the control strategy as follows: in response to a temperature lower than a first threshold, increasing the operating voltage of the flash memory chip while maintaining the clock frequency unchanged; in response to a temperature higher than a second threshold, decreasing the clock frequency of the flash memory chip, migrating the data to be written to the cache until the load decreases and then writing it back to the flash memory chip; and decreasing the operating voltage, garbage collection trigger frequency, and wear leveling trigger frequency of the flash memory chip during load intervals; in response to an abnormal health status level and a low load status, determining the control strategy as follows: decreasing the operating voltage and clock frequency of the flash memory chip, triggering key area inspection, moving data from storage blocks with an error count exceeding a preset threshold, increasing the garbage collection trigger frequency, and increasing the wear leveling trigger frequency.

[0081] Specifically, when the health status level is abnormal, it indicates that the operating state of the flash memory chips has significantly deviated from the normal range, requiring a more aggressive control strategy to ensure data reliability. If the current load is high and the health status is abnormal, the control strategy needs to maintain I / O service as much as possible while ensuring data reliability. In this case, the control strategy is graded based on temperature: when the temperature is below a first threshold... When the temperature exceeds the second threshold, the operating voltage can be temporarily increased to enhance write reliability while maintaining the clock frequency to preserve the current performance level; At the same time, the clock frequency of the flash memory chip is reduced to suppress temperature rise, and the data to be written is temporarily migrated to the DRAM cache. It is then written back to the flash memory chip after the load decreases, so as to avoid writing data to the flash memory chip that is already in an abnormal state under high load and high temperature conditions. At the same time, the operating voltage, garbage collection trigger frequency and wear leveling trigger frequency of the flash memory chip are reduced during load gaps to reduce additional power consumption and heat generation.

[0082] If the current load is low and the health status is abnormal, the flash memory chips are in a relatively vulnerable state and require comprehensive protection measures. The control strategy at this time is as follows: reduce the operating voltage and clock frequency of the flash memory chips to reduce power consumption and heat; trigger key area inspections (targeted inspections of key areas with high error rates or numerous erase / write cycles); move data from storage blocks with error counts exceeding a preset threshold; and simultaneously increase the trigger frequency of garbage collection and wear leveling to replace more free blocks, thereby reducing the risk of data loss under abnormal conditions.

[0083] Based on the above-described solid-state drive (SSD) control method, this application also provides an SSD control system. The system includes a host and an SSD, with the host issuing input / output tasks to the SSD. The SSD includes: flash memory chips for storing data, including NAND flash memory; a cache area, including an abnormal data reception cache area and a normal data cache area; and an SSD controller connected to the host and the flash memory chips for executing the SSD control method of this application.

[0084] Figure 3 A schematic diagram of the composition structure of the solid-state drive control device provided in the embodiments of this application is shown.

[0085] refer to Figure 3 This application also provides a solid-state drive control device, which includes: The prediction module 301 is used to obtain the first attribute information of the current input-output task and predict the second attribute information of the next input-output task based on the first attribute information. The first determining module 302 is used to determine the time period type based on the first attribute information and the second attribute information. The time period type includes idle and non-idle. The acquisition module 303 is used to acquire the operating status information of the flash memory chips of the solid-state drive according to the time period type; The second determining module 304 is used to determine the health status level of the flash memory chip based on the operating status information. The control module 305 is used to obtain the load status of the solid-state drive, determine the control strategy of the flash memory chips based on the load status and health status level, and execute the control strategy.

[0086] In one embodiment of this application, the prediction module 301 is used for: The first attribute information is input into the prediction model to obtain the second attribute information of the next input-output task from the prediction model.

[0087] In one embodiment of this application, the first determining module 302 is used for: Determine the idle period based on the end time of the current input / output task and the start time of the next input / output task; In response to the fact that the current time is in an idle period, the period type is determined to be idle; In response to the fact that the current time is a non-idle period, the period type is determined to be non-idle.

[0088] In one embodiment of this application, the acquisition module 303 is used for: In response to the time period being idle, the first operating status information of the flash memory chip is obtained; the first operating status information includes temperature, operating voltage, read / write latency, number of error bits, data write volume, number of erase / write cycles, and percentage of bad blocks; In response to a non-idle time period, the second operating status information of the flash memory chip is obtained. The second operating status information includes temperature, operating voltage, read / write latency, number of error bits, data write volume, number of erase / write cycles, bad block percentage, and programming voltage.

[0089] In one embodiment of this application, the device is further configured to: Collect the operating status information of the flash memory chips according to the preset collection cycle; Each piece of data in the collected running status information is compared with its corresponding preset threshold. If any data exceeds the corresponding preset threshold, the collected running status information is identified as abnormal data, and the abnormal data is reported to the abnormal data receiving buffer through interrupt request and direct memory access. In response to the fact that all data does not exceed the corresponding preset threshold, the running status information collected this time is determined as normal data, until the number of collections reaches the preset number, and then all normal data collected within the preset number of collections is transferred to the normal data buffer.

[0090] In one embodiment of this application, the acquisition module 303 is used for: Extract all runtime status information from the abnormal data receiving buffer and the normal data buffer; The second determining module 304 is used for: All operational status information is input into the classification model in a time sequence to obtain the health status level of the flash memory chip output by the classification model. The health status level includes healthy, normal, and abnormal.

[0091] In one embodiment of this application, the control module 305 is used for: In response to a healthy health status and a high load status, the control strategy is determined as follows: maintain the current operating parameters of the flash memory chips, trigger a trimming operation, and reduce the wear leveling trigger frequency. In response to a healthy health status and a low load status, the control strategy is determined as follows: reduce the operating voltage of the flash memory chips, trigger incremental inspection, move data for storage blocks with more than a preset threshold of errors, increase the frequency of garbage collection and increase the frequency of wear leveling.

[0092] In one embodiment of this application, the control module 305 is further configured to: In response to a normal health status and a high load status, the control strategy is determined as follows: in response to a temperature below the first threshold, increase the operating voltage of the flash memory chip, trigger a trimming operation, and reduce the wear leveling trigger frequency; in response to a temperature above the second threshold, reduce the clock frequency of the flash memory chip. In response to a normal health status and a low load status, the control strategy is determined as follows: reduce the operating voltage of the flash memory chips, trigger a global inspection, move data for storage blocks with more than a preset threshold of errors, increase the frequency of garbage collection and increase the frequency of wear leveling.

[0093] In one embodiment of this application, the control module 305 is further configured to: In response to an abnormal health status and a high load, the following control strategies are determined: In response to a temperature below the first threshold, increase the operating voltage of the flash memory chip while keeping the clock frequency constant; In response to a temperature above the second threshold, decrease the clock frequency of the flash memory chip, migrate the data to be written to the cache until the load decreases and then write it back to the flash memory chip; Also, during load intervals, decrease the operating voltage of the flash memory chip, the garbage collection trigger frequency, and the wear leveling trigger frequency. In response to an abnormal health status and a low load status, the control strategy is determined as follows: reduce the operating voltage and clock frequency of the flash memory chips, trigger key area inspections, move data for storage blocks with more than a preset threshold of errors, increase the frequency of garbage collection and wear leveling.

[0094] It should be noted that the description of the device in this application embodiment is similar to the description of the method embodiment above, and has similar beneficial effects as the method embodiment, therefore, it will not be repeated. For any technical details not covered in the solid-state drive control device provided in this application embodiment, please refer to... Figures 1 to 2The meaning is understood in accordance with the description of any of the accompanying drawings.

[0095] According to an embodiment of this application, this application also provides a solid-state drive (SSD) for executing the SSD control method of this application.

[0096] According to embodiments of this application, this application also provides an electronic device and a readable storage medium, the electronic device including a solid-state drive.

[0097] Figure 4 A schematic block diagram of an example electronic device 400 that can be used to implement embodiments of this application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the application described and / or claimed herein.

[0098] like Figure 4 As shown, the electronic device 400 includes a computing unit 401, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 402 or a computer program loaded from a storage unit 408 into a random access memory (RAM) 403. The RAM 403 may also store various programs and data required for the operation of the electronic device 400. The computing unit 401, ROM 402, and RAM 403 are interconnected via a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0099] Multiple components in electronic device 400 are connected to I / O interface 405, including: input unit 406, such as keyboard, mouse, etc.; output unit 407, such as various types of displays, speakers, etc.; storage unit 408, such as disk, optical disk, etc.; and communication unit 409, such as network card, modem, wireless transceiver, etc. Communication unit 409 allows electronic device 400 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0100] The computing unit 401 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 401 performs the various methods and processes described above, such as solid-state drive (SSD) control methods. For example, in some embodiments, the SSD control method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 408. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 400 via ROM 402 and / or communication unit 409. When the computer program is loaded into RAM 403 and executed by the computing unit 401, one or more steps of the SSD control method described above may be performed. Alternatively, in other embodiments, the computing unit 401 may be configured to perform the SSD control method by any other suitable means (e.g., by means of firmware).

[0101] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transferring data and instructions to the storage system, the at least one input device, and the at least one output device.

[0102] The program code used to implement the methods of this application may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0103] In the context of this application, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0104] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0105] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0106] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0107] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0108] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0109] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A solid-state drive (SSD) control method, characterized in that, The method includes: Obtain the first attribute information of the current input / output task, and predict the second attribute information of the next input / output task based on the first attribute information; Based on the first attribute information and the second attribute information, the time period type is determined, and the time period type includes idle and non-idle; Based on the time period type, obtain the operating status information of the flash memory chips of the solid-state drive; Based on the operating status information, the health status level of the flash memory chip is determined; The load status of the solid-state drive is obtained, and the control strategy for the flash memory chips is determined based on the load status and the health status level, and the control strategy is executed.

2. The method according to claim 1, characterized in that, The step of predicting the second attribute information for the next input / output task based on the first attribute information includes: The first attribute information is input into the prediction model to obtain the second attribute information of the next input-output task output by the prediction model.

3. The method according to claim 1, characterized in that, The first attribute information includes the end time of the current input / output task, and the second attribute information includes the start time of the next input / output task; Based on the first attribute information and the second attribute information, the time period type is determined, including: The idle period is determined based on the end time of the current input / output task and the start time of the next input / output task; In response to the fact that the current time is in an idle period, the period type is determined to be idle; In response to the fact that the current time is a non-idle period, the period type is determined to be non-idle.

4. The method according to claim 1, characterized in that, Before obtaining the operating status information of the flash memory chips of the solid-state drive, the method further includes: The operating status information of the flash memory chip is collected according to a preset collection cycle; Each piece of data in the collected running status information is compared with its corresponding preset threshold. If any data exceeds the corresponding preset threshold, the collected running status information is identified as abnormal data, and the abnormal data is reported to the abnormal data receiving buffer through interrupt request and direct memory access. In response to the fact that all data does not exceed the corresponding preset threshold, the running status information collected this time is determined as normal data, until the number of collections reaches the preset number, and then all normal data collected within the preset number of collections is transferred to the normal data buffer.

5. The method according to claim 4, characterized in that, The step of obtaining the operating status information of the flash memory chips of the solid-state drive includes: Extract all runtime status information from the abnormal data receiving buffer and the normal data buffer; Based on the operational status information, the health status level of the flash memory chip is determined, including: All operational status information is input into the classification model in chronological order to obtain the health status level of the flash memory chip output by the classification model. The health status level includes healthy, normal, and abnormal.

6. The method according to claim 1, characterized in that, The step of determining the control strategy for the flash memory chip based on the load state and the health status level includes: In response to the health status level being healthy and the load status being high, the control strategy is determined to be: maintaining the current operating parameters of the flash memory chip, triggering a trimming operation, and reducing the wear leveling trigger frequency; In response to the health status level being healthy and the load status being low load, the control strategy is determined to be: reducing the operating voltage of the flash memory chip, triggering incremental inspection, moving data of storage blocks with more than a preset threshold of errors, increasing the garbage collection trigger frequency, and increasing the wear leveling trigger frequency.

7. The method according to claim 6, characterized in that, The method further includes: In response to the health status level being normal and the load status being high load, the regulation strategy is determined as follows: in response to the temperature being less than a first threshold, the operating voltage of the flash memory chip is increased, a trimming operation is triggered, and the wear leveling trigger frequency is reduced; in response to the temperature being greater than a second threshold, the clock frequency of the flash memory chip is reduced. In response to the health status level being normal and the load status being low, the control strategy is determined to be: reducing the operating voltage of the flash memory chip, triggering a global inspection, moving data from storage blocks with an error count exceeding a preset threshold, increasing the garbage collection trigger frequency, and increasing the wear leveling trigger frequency.

8. The method according to claim 6, characterized in that, The method further includes: In response to the abnormal health status level and the high load status, the control strategy is determined as follows: in response to the temperature being less than a first threshold, the operating voltage of the flash memory chip is increased while the clock frequency remains unchanged; in response to the temperature being greater than a second threshold, the clock frequency of the flash memory chip is decreased, the data to be written is migrated to the cache until the load decreases and then written back to the flash memory chip; and during load intervals, the operating voltage, garbage collection trigger frequency, and wear leveling trigger frequency of the flash memory chip are decreased. In response to the abnormal health status level and the low load status, the control strategy is determined to be: reducing the operating voltage and clock frequency of the flash memory chip, triggering key area inspection, moving data of storage blocks with more than a preset threshold of errors, increasing the garbage collection trigger frequency, and increasing the wear leveling trigger frequency.

9. A solid-state drive control device, characterized in that, The device includes: The prediction module is used to obtain the first attribute information of the current input-output task and predict the second attribute information of the next input-output task based on the first attribute information. The first determining module is used to determine the time period type based on the first attribute information and the second attribute information, wherein the time period type includes idle and non-idle; The acquisition module is used to acquire the operating status information of the flash memory chips of the solid-state drive according to the time period type; The second determining module is used to determine the health status level of the flash memory chip based on the operating status information. The control module is used to acquire the load status of the solid-state drive, determine the control strategy of the flash memory chips based on the load status and the health status level, and execute the control strategy.

10. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.

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