Method for automatically constructing white-box verification environment with assertion and related device

Abstract

The application discloses a white-box verification environment construction method for automatically generating assertions and related equipment. The white-box verification environment construction method for automatically generating assertions comprises the following steps: inserting an event keyword at all nodes requiring signal checking in firmware or algorithm code, binding the event keyword with the program counter address of the code line where the event keyword is located after compiling through a compiler, and generating event triggering code; defining an assertion library containing a plurality of assertion attribute templates in advance; filling a signal to be checked and its expected behavior under each event into an Excel table; parsing the Excel table through an automatic script, calling the assertion attribute templates in the assertion library, generating assertion code, combining the event triggering code, the assertion library and the generated assertion code, and forming a complete white-box verification environment. The application realizes the beneficial technical effects of improving development efficiency, reducing maintenance cost and error risk, and intuitive and efficient inspection.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design and verification technology, and in particular to a method, apparatus, computer device, and computer-readable storage medium for constructing a white-box verification environment for fully automated assertion generation based on events in a chip-wide verification scenario. Background Technology

[0002] In integrated circuit design, full-chip verification is a complex and critical step. Especially in firmware or algorithm flow verification, it's typically necessary to check whether the values ​​of various signals in the RTL (Register Transfer Level) circuitry meet expectations at each node of the flow. This white-box verification method relies on a large amount of assertion code to monitor signal behavior in real time.

[0003] As chip size and complexity increase, the assertions required for white-box verification environments typically reach the order of millions of lines. The traditional method of having verification personnel manually write and maintain assertion code has the following significant drawbacks: (1) Writing millions of lines of assertion code by hand is a huge workload, has a long development cycle, and is extremely inefficient. (2) Once the firmware process, algorithm logic or expected value of the signal changes, the verification personnel need to manually locate and modify a large number of assertion codes, which is costly to maintain and can easily introduce new errors. (3) Designers and verifiers face significant inspection difficulties when reviewing code, not only due to the large workload, but also because it is difficult to quickly locate problems. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method, apparatus, computer device and computer-readable storage medium for building a white-box verification environment for fully automatic generation of assertions, aiming to solve the technical problems of low development efficiency, high maintenance cost and difficulty in inspection caused by manually writing and maintaining a large amount of assertion code in the prior art.

[0005] Firstly, a method for constructing a white-box verification environment that automatically generates assertions is provided, comprising the following steps: inserting event keywords at all nodes in the firmware or algorithm code that require signal inspection; binding the event keywords to the program counter address of the code line containing the compiled event keywords using a compiler, and generating event triggering code; pre-defining an assertion library containing multiple assertion attribute templates; filling the signals to be inspected and their expected behaviors under each event into an Excel spreadsheet; parsing the Excel spreadsheet using an automated script, calling the assertion attribute templates in the assertion library, generating assertion code; and combining the event triggering code, the assertion library, and the generated assertion code to form a complete white-box verification environment.

[0006] Secondly, a fully automated assertion generation white-box verification environment construction device is provided, comprising: an event trigger code generation module, used to insert event keywords at all nodes in firmware or algorithm code that require signal inspection, bind the event keywords to the program counter address of the code line containing the compiled event keywords through a compiler, and generate event trigger code; an assertion library definition module, used to predefine an assertion library containing multiple assertion attribute templates; an Excel spreadsheet editing module, used to fill the signals to be inspected and their expected behaviors under each event into an Excel spreadsheet; and a white-box verification environment construction module, used to parse the Excel spreadsheet through an automated script, call the assertion attribute templates in the assertion library, generate assertion code, and combine the event trigger code, assertion library, and generated assertion code to form a complete white-box verification environment.

[0007] Thirdly, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described method for constructing a white-box verification environment for fully automated assertion generation.

[0008] Fourthly, a computer-readable storage medium is provided, wherein a computer program is stored therein, and when the computer program is executed by a processor, the steps of the above-described method for constructing a white-box verification environment for fully automatic assertion generation are implemented.

[0009] The aforementioned fully automated assertion generation white-box verification environment construction method, apparatus, computer equipment, and storage medium convert Excel spreadsheets into assertion code through automated scripts, avoiding the enormous workload of manually writing millions of lines of code. This reduces the workload from weeks or even months to hours, significantly improving development efficiency. When the expected value of a process or signal changes, only the Excel file needs to be modified and the automated script rerun to update the entire verification environment, without the need to manually modify any assertion code, significantly reducing maintenance costs and error risks. When designers and verification personnel conduct code reviews, they no longer need to directly examine complex SV assertion code, but can confirm the correctness of verification points by examining logically clear and structured Excel spreadsheets, making the review process more intuitive and efficient. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart illustrating a method for constructing a white-box verification environment for fully automated assertion generation according to an embodiment of the present invention. Figure 2 This is a schematic diagram of a white-box verification environment construction device for fully automated assertion generation according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] This invention provides a method, apparatus, computer device, and storage medium for constructing a white-box verification environment that automatically generates assertions. It embeds SV (System Verilog) event keywords into firmware or algorithm code, which are then converted into event-triggered SV language after customized processing by a compiler. The design presents the behavior of verification signals in the process as an Excel spreadsheet, automatically generating the white-box verification environment, facilitating development and maintenance by verification personnel. Subsequent inspection can be performed using the Excel spreadsheet, which is clearer and more efficient than directly inspecting the SV code.

[0014] Figure 1 A flowchart illustrating the method for constructing a white-box verification environment for fully automated assertion generation provided in this embodiment of the invention is shown below. Figure 1 As shown, the method for constructing a white-box verification environment for fully automated assertion generation includes steps S10 to S40: S10: Insert event keywords at all nodes in the firmware or algorithm code that require signal checking, bind the event keywords to the program counter address of the code line where the compiled event keywords are located through the compiler, and generate event trigger code.

[0015] Specifically, based on business requirements and the key challenges of the firmware / algorithm flow, designers identify all nodes in the firmware or algorithm code that require RTL (Register Transfer Level) signal expected behavior checks and insert the `event` keyword. In response to user actions, the system inserts the pre-defined `event` keyword after the code line corresponding to the checked node. Then, the firmware or algorithm code is compiled by the compiler.

[0016] The compiler used for code compilation needs to be customized so that it can identify the line of code containing the event keyword while converting firmware or algorithm code into binary machine code, and bind the event keyword to the PC (program counter) address of the line of code containing the event keyword after compilation, and generate SV (system Verilog) event trigger code.

[0017] The specific process for firmware or algorithm code is as follows: The compiler converts the firmware or algorithm code into binary machine code, and simultaneously identifies the code line containing the event keyword (each line of code after compilation will have a corresponding PC address), and establishes a mapping relationship between the event keyword and the program counter address of the code line containing the event keyword after compilation; the compiler automatically generates SV event triggering code based on the mapping relationship between the event keyword and the program counter address of the code line containing the event keyword. This SV event triggering code triggers the corresponding event by monitoring the CPU's program counter bus during verification simulation. When the RTL CPU executes to the corresponding PC, it triggers the assertion event.

[0018] The programming language of the firmware or algorithm code can be a known language such as C or C++, or it can be a scripting language designed specifically for a particular hardware platform.

[0019] S20: Predefine an assertion library containing multiple assertion property templates.

[0020] Verification personnel categorize the RTL signals to be inspected based on their behavior, and manually write a parameterized assert property template for each category, forming an assertion library. Subsequent assertion code generated by scripts can directly call the assert property templates in the assertion library. For example, 1000 RTL signals are divided into 50 categories, and an assertion library containing 50 assert property templates is manually written based on the categories.

[0021] S30: Fill the signal to be checked and its expected behavior under each event into an Excel spreadsheet.

[0022] Based on the design scheme, the designers listed all RTL signals to be checked and the nodes that need to be checked, and filled in an Excel spreadsheet, as shown in Table 1. In the first column of the Excel spreadsheet, the signal names of different signals to be checked were entered sequentially; in the first row of the Excel spreadsheet, the event names of different events were entered sequentially; and in the cells at the intersection of the row and column, the expected values ​​of the corresponding signals to be checked under the corresponding events were entered.

[0023] Table 1: S40: The Excel spreadsheet is parsed using an automated script, the assertion attribute templates in the assertion library are called to generate assertion code, and the event triggering code, the assertion library and the generated assertion code are combined to form a complete white-box verification environment.

[0024] The Excel spreadsheet is parsed using Perl or Python scripts to identify each non-empty cell and obtain the expected values ​​of the RTL signals to be checked under the corresponding events. Based on the RTL signal name and expected value, the required assertion type is determined, and the corresponding assertion attribute template is instantiated and parameters are populated from the assertion library according to the assertion type, generating SV assertion code that the verification environment can recognize. Finally, the SV assertion code, event triggering code, and assertion library are combined into a white-box assertion environment, enabling the automated generation and maintenance of massive amounts of assertion code.

[0025] The fully automated assertion generation white-box verification environment construction method provided in this embodiment of the invention has the following advantages compared with the prior art: (1) By converting Excel spreadsheets into assertion code through automated scripts, the huge workload of manually writing millions of lines of code is avoided, reducing the work of weeks or even months to hours, and greatly improving development efficiency; (2) When the expected value of the process or signal changes, you only need to modify the EXCEL file and then rerun the automation script to update the entire verification environment. No manual modification of any assertion code is required, which significantly reduces maintenance costs and error risks. (3) When designers and verifiers conduct code reviews, they no longer need to directly examine complex SV assertion code. Instead, they can confirm the correctness of verification points by examining logically clear and structured Excel spreadsheets, making the review process more intuitive and efficient.

[0026] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0027] In one embodiment, a fully automated assertion generation white-box verification environment construction apparatus is provided, which corresponds one-to-one with the fully automated assertion generation white-box verification environment construction method described in the above embodiments. For example... Figure 2 As shown, this fully automated assertion generation white-box verification environment construction device includes an event trigger code generation module 10, an assertion library definition module 20, an Excel spreadsheet editing module 30, and a white-box verification environment construction module 40. Detailed descriptions of each functional module are as follows: The event trigger code generation module 10 is used to insert event keywords at all nodes in the firmware or algorithm code that require signal checking, bind the event keywords to the program counter address of the code line where the compiled event keywords are located through the compiler, and generate event trigger code. Assertion library definition module 20 is used to predefine an assertion library containing multiple assertion attribute templates; Excel spreadsheet editing module 30 is used to fill in the signals to be checked and their expected behavior under each event into an Excel spreadsheet; The white-box verification environment construction module 40 is used to parse the Excel table through an automated script, call the assertion attribute template in the assertion library, generate assertion code, and combine the event triggering code, the assertion library and the generated assertion code to form a complete white-box verification environment.

[0028] The fully automated assertion generation white-box verification environment construction device provided in this embodiment of the invention has the following advantages compared with the prior art: (1) By converting Excel spreadsheets into assertion code through automated scripts, the huge workload of manually writing millions of lines of code is avoided, reducing the work of weeks or even months to hours, and greatly improving development efficiency; (2) When the expected value of the process or signal changes, you only need to modify the EXCEL file and then rerun the automation script to update the entire verification environment. No manual modification of any assertion code is required, which significantly reduces maintenance costs and error risks. (3) When designers and verifiers conduct code reviews, they no longer need to directly examine complex SV assertion code. Instead, they can confirm the correctness of verification points by examining logically clear and structured Excel spreadsheets, making the review process more intuitive and efficient.

[0029] Specific limitations regarding the apparatus for building a white-box verification environment with fully automated assertion generation can be found in the limitations of the method for building a white-box verification environment with fully automated assertion generation described above, and will not be repeated here. Each module in the aforementioned apparatus for building a white-box verification environment with fully automated assertion generation can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0030] In one embodiment, a computer device is provided, the internal structure of which can be shown as follows: Figure 3As shown, the computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile and / or volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface is used to communicate with other external electronic devices via a network connection. When the computer program is executed by the processor, it implements the functions or steps of the aforementioned fully automated assertion generation white-box verification environment construction method.

[0031] In one embodiment, a computer-readable storage medium is provided, wherein a computer program is stored therein, and when executed by a processor, the computer program implements the functions or steps of the above-described method for constructing a white-box verification environment for fully automated assertion generation.

[0032] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0033] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0034] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for constructing a white-box verification environment that automatically generates assertions, characterized in that, Includes the following steps: Insert event keywords at all nodes in the firmware or algorithm code that require signal checking. The compiler binds the event keywords to the program counter address of the code line containing the compiled event keywords and generates event triggering code. A predefined assertion library containing multiple assertion property templates; Enter the signals to be checked and their expected behavior under each event into an Excel spreadsheet; The Excel spreadsheet is parsed by an automated script, the assertion attribute templates in the assertion library are called to generate assertion code, and the event triggering code, the assertion library and the generated assertion code are combined to form a complete white-box verification environment.

2. The method for constructing a white-box verification environment for fully automated assertion generation according to claim 1, characterized in that, The process of binding the event keyword to the program counter address of the code line containing the compiled event keyword specifically includes: The compiler converts firmware or algorithm code into binary machine code, identifies the code line where the event keyword is located, and establishes a mapping relationship between the event keyword and the program counter address of the code line where the event keyword is located after compilation.

3. The method for constructing a white-box verification environment for fully automated assertion generation according to claim 2, characterized in that, The steps for generating the event trigger code specifically include: The compiler automatically generates event triggering code based on the mapping relationship between event keywords and the program counter address of the code line containing the event keywords. This event triggering code triggers the corresponding event by monitoring the CPU program counter bus during verification simulation.

4. The method for constructing a white-box verification environment for fully automated assertion generation according to claim 1, characterized in that, The step of predefining an assertion library containing multiple assertion attribute templates specifically includes: classifying the signals to be checked according to their behavior, and manually writing a parameterized assertion attribute template for each type of signal.

5. The method for constructing a white-box verification environment for fully automated assertion generation according to claim 1, characterized in that, The step of filling the signal to be inspected and its expected behavior under each event into an Excel spreadsheet specifically includes: Enter the names of the different signals to be checked into the first column of the Excel spreadsheet; Enter the event names of different events sequentially into the first row of cells in the Excel spreadsheet; Enter the expected value of the corresponding signal under the corresponding event in the cell at the intersection of the row and column.

6. The method for constructing a white-box verification environment for fully automated assertion generation according to claim 1, characterized in that, The steps of parsing the Excel table using an automated script, calling assertion attribute templates from the assertion library, and generating assertion code specifically include: The Excel spreadsheet is parsed using an automated script to identify each non-empty cell and obtain the expected value of the signal to be checked under the corresponding event. The required assertion type is determined based on the signal name and expected value, and the corresponding assertion attribute template is instantiated and parameters are populated from the assertion library according to the assertion type.

7. The method for constructing a white-box verification environment for fully automated assertion generation according to claim 1, characterized in that, The firmware or algorithm code is programmed in C or C++; the automation script is a Perl or Python script.

8. A fully automated white-box verification environment construction device for generating assertions, characterized in that, include: The event trigger code generation module is used to insert event keywords at all nodes in the firmware or algorithm code that require signal checking. The compiler binds the event keywords to the program counter address of the code line where the event keywords are located after compilation and generates event trigger code. The assertion library definition module is used to predefine an assertion library containing multiple assertion attribute templates; The Excel spreadsheet editing module is used to fill in the signals to be checked and their expected behavior under various events into an Excel spreadsheet; The white-box verification environment building module is used to parse the Excel table through an automated script, call the assertion attribute templates in the assertion library, generate assertion code, and combine the event triggering code, the assertion library and the generated assertion code to form a complete white-box verification environment.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method for constructing a white-box verification environment for fully automated assertion generation as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method for constructing a white-box verification environment for fully automated assertion generation as described in any one of claims 1 to 7.

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