A memory management system, method, device and medium

Abstract

The present disclosure relates to the technical field of memory management, and particularly relates to a memory management system, method, device and medium. The present disclosure comprises: a logical address mapping module configured to provide a unified continuous logical address space to shield underlying physical differences; an address conversion module configured to maintain a dynamic logical-physical address mapping table to realize real-time address conversion; a power-on initialization module configured to poll Sector status, calculate address information and manage bad blocks; a synchronous reading module configured to synchronously read data according to the mapping table; and an asynchronous writing module configured to perform asynchronous writing in a periodic task according to the Sector status. Through the logical-physical dynamic mapping and asynchronous writing mechanism, the present disclosure realizes dynamic allocation similar to memory, greatly improves storage flexibility, system real-time performance and data security, and perfectly supports complex scenarios such as variable-length data and OTA upgrading.

Description

Technical Field

[0001] This disclosure relates to the field of memory management technology, and in particular to a memory management system, method, device and medium. Background Technology

[0002] In embedded systems such as automotive electronics and industrial control based on the Tricore architecture, program code is typically stored in on-chip PFlash memory. Fixed data is traditionally stored in DFlash. Generally, using Dflash to store fixed data based on the Tricore architecture requires configuring a Fee abstract FLASH to simulate an EEPROM and using the NVM storage service layer for management. The memory management of Dflash presents the following technical challenges: 1. Erase before writing: Flash memory must be erased (set to all 1s) in units of "sectors" or "pages" before it can be written in units of "words" or "bytes". This erase-before-write characteristic makes data update operations cumbersome.

[0003] 2. Fixed partitioning is inflexible: When using Fee to simulate DFLASH as EEPROM, data needs to be managed in pages or sectors, simulating byte or word operations in EEPROM, and divided into fixed program areas, configuration parameter areas, data record areas, etc. This static partitioning model cannot adapt to dynamically changing storage needs when facing OTA upgrades requiring storage of multiple image versions, or when the data record area needs dynamic expansion.

[0004] 3. The operation process is prone to causing system lag: Flash erase and write operations take a long time. During this period, the CPU usually needs to wait or is in a busy state, which affects the response of real-time tasks.

[0005] 4. Special characteristics of storage service management: When using NVM to manage DFLASH, additional data space is required for NVM management, which increases the overhead of DFLASH space.

[0006] In summary, there is an urgent need in this field for a Flash memory management solution that can overcome the above-mentioned shortcomings and provide a flexible, efficient, and long-lifespan solution. Summary of the Invention

[0007] To address the aforementioned problems, this disclosure provides a memory management system, method, device, and medium to solve the issues of poor flexibility and low efficiency in traditional Flash management.

[0008] Firstly, a memory management system includes: The logical address mapping module is used to provide a unified and continuous logical address space to upper-layer applications, shielding the differences in the size, location, and status of physical sectors. The address translation module, connected to the logical address mapping module, is used to maintain a dynamic logical-physical address mapping table and convert logical address access requests initiated by applications into valid physical addresses for the corresponding physical sectors in real time. The power-on initialization module is used to poll all physical sectors allocated by the memory management system during system initialization, calculate written addresses, writable addresses, and readable addresses, and detect and handle bad blocks. The synchronous read module is used to receive read requests from upper-layer applications, query the logical-physical address mapping table through the address translation module to obtain the valid physical address of the corresponding physical sector, and synchronously read the data at that physical address into the target cache. The asynchronous write module is used to receive write requests initiated by upper-layer applications based on logical addresses, determine the valid physical address of the corresponding physical sector through the address translation module, and asynchronously complete the data writing in a periodic task. The data erasure module is used to receive erasure requests from upper-layer applications and erase all data in the selected sector.

[0009] Furthermore, the asynchronous write module includes a write request caching unit and a background polling unit: Write to the request cache unit to temporarily store the logical address, source data address, and data length submitted by the upper-layer application; The background polling unit is invoked during the system's periodic tasks to perform the actual physical write operation based on the request from the cache unit, and polls the status register after the write to confirm that the write is complete.

[0010] Furthermore, the asynchronous write module is specifically used for: When the valid physical address of the corresponding physical sector is in the erase state and the sector block state is initialized, the valid information flag is written to the physical address corresponding to the sector in an aligned format, and then the asynchronous writing of the source data is triggered. When the corresponding physical sector is in a used state and the sector block status is in a verified state, a new writable physical address is allocated within the sector. The valid information in the source address is written into the new writable physical address in an aligned format. The written data is compared with the data in the source address. If they are completely consistent, the logical-physical address mapping table is updated to point to the new writable physical address. At the same time, the data in the original physical address is marked as invalid and submitted to the background polling unit for asynchronous writing.

[0011] Specifically, after an address is erased in Dflash, a flag indicating valid information is written to the beginning of the erased address. Confirming the flag confirms that the address block is in an initialized state.

[0012] During writing, the data to be written is compared with the data in the source address. Two consecutive sets of 0x55667788 are written to the 8-byte physical area of ​​the DFLASH region of the allocated physical address. After the writing is completed, the physical area is read out.

[0013] Furthermore, the specific method by which the power-on initialization module detects and handles bad blocks is as follows: The system reads the Marker value at the fixed address of the Sector to determine if the Sector is corrupted. If it is corrupted, an erasure operation is performed. After erasure, the system verifies the validity of the block. If the verification passes, the Sector is set as a valid block and allowed to be written to. If the verification fails, the Sector is set as a permanent bad block and isolated.

[0014] Secondly, a memory management method, based on the aforementioned memory management system, includes: During power-on initialization, the system polls all physical sectors allocated by the memory management system during system initialization, calculates written addresses, writable addresses, and readable addresses, and detects and handles bad blocks. When a read request is received from an upper-layer application, the address translation module queries the logical-physical address mapping table to obtain the valid physical address of the corresponding physical sector, and synchronously reads the data at that physical address into the target cache. When a write request is received from an upper-layer application based on a logical address, the address translation module determines the valid physical address of the corresponding physical sector and asynchronously completes the data writing in a periodic task. When a wipe request is received from the upper-layer application, all data in the selected sector is wiped.

[0015] Furthermore, data writing is performed asynchronously within periodic tasks, including: When the valid physical address of the corresponding physical sector is in the erase state and the block state is initialized, the valid information flag is written to the physical address corresponding to the sector in an aligned format, and then the asynchronous writing of the source data is triggered. When the corresponding physical sector is in a used state and the block status is in a verified state, a new writable physical address is allocated within the sector. The valid information in the source address is written into the new writable physical address in an aligned format. The written data is compared with the data in the source address. If they are completely consistent, the logical-physical address mapping table is updated to point to the new writable physical address. At the same time, the data in the original physical address is marked as invalid and submitted to the background polling unit for asynchronous writing.

[0016] Furthermore, during system initialization, all physical sectors allocated by the memory management system are polled, including rebuilding the logical-physical address mapping table: Traverse the written areas of all valid sectors, read the valid information flags of data blocks, filter out the latest valid data blocks based on the logical address information and data status recorded in the valid information flags, and restore and construct the mapping relationship between logical addresses and the latest physical addresses.

[0017] Furthermore, it erases all data in the selected sector, and then includes: The erased Sector is marked as free and available, and its space is reintegrated into the available physical space pool of the logical address mapping module for space allocation during subsequent writes.

[0018] Thirdly, an electronic device includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, which stores computer programs; The processor implements one of the memory management methods described above when executing computer programs stored in memory.

[0019] Fourthly, a computer-readable storage medium stores a computer program that, when executed by a processor, implements the aforementioned memory management method.

[0020] This disclosure includes at least the following beneficial effects: This disclosure achieves dynamic allocation similar to memory through logical-physical dynamic mapping and asynchronous writing mechanism, which greatly improves storage flexibility, system real-time performance and data security, and perfectly supports complex scenarios such as variable-length data and OTA upgrades.

[0021] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures pointed out in the description and the accompanying drawings. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1This is a schematic diagram of the memory management system architecture according to an embodiment of the present disclosure; Figure 2 This is a schematic diagram of the initialization process according to an embodiment of the present disclosure; Figure 3 This is a schematic diagram of the data reading process according to an embodiment of the present disclosure; Figure 4 This is a schematic diagram of the data writing process in an embodiment of this disclosure; Figure 5 This is a schematic diagram of the asynchronous write process according to an embodiment of the present disclosure; Figure 6 This is a schematic diagram of the data erasure process according to an embodiment of the present disclosure; Figure 7 This is a schematic diagram of the electronic device structure according to an embodiment of the present disclosure. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0025] like Figure 1 As shown, a memory management system includes: Logical address mapping module, address translation module, power-on initialization module, synchronous read module, asynchronous write module, and data erase module; The logical address mapping module is used to provide a unified and continuous logical address space to upper-layer applications, shielding the differences in the size, location, and status of physical sectors. The address translation module, connected to the logical address mapping module, is used to maintain a dynamic logical-physical address mapping table and convert logical address access requests initiated by applications into valid physical addresses for the corresponding physical sectors in real time. The power-on initialization module is used to poll all physical sectors allocated by the memory management system during system initialization, calculate written addresses, writable addresses, and readable addresses, and detect and handle bad blocks. The synchronous read module is used to receive read requests from upper-layer applications, query the logical-physical address mapping table through the address translation module to obtain the valid physical address of the corresponding physical sector, and synchronously read the data at that physical address into the target cache. The asynchronous write module is used to receive write requests initiated by upper-layer applications based on logical addresses, determine the valid physical address of the corresponding physical sector through the address translation module, and asynchronously complete the data writing in a periodic task. The data erasure module is used to receive erasure requests from upper-layer applications and erase all data in the selected sector.

[0026] In practice: Logical address mapping module: used to provide a unified and continuous logical address space to upper-layer applications, shielding the differences in size, location and status of the underlying Flash physical sectors.

[0027] Address translation module: Connected to the logical address mapping module, it maintains a dynamic "logical-physical" address mapping table. This module is responsible for converting logical address access requests initiated by applications into currently valid physical addresses in real time.

[0028] Power-on initialization module: During system initialization, it checks the status of the sectors allocated by the memory management system, polls all sectors, and calculates information such as the currently written addresses, writable addresses, and readable addresses of each sector. It can detect problematic sectors and mark them as bad blocks, performing an erase operation on the block's address. After erasure, the block address is marked as a valid block, allowing writing. When a sector is found to be valid, a validity check is performed on that sector.

[0029] Synchronous Read Module: Provides standard functions to the upper layer, which can synchronously read data from Dflash to the target address using the sector number, target address, and data length.

[0030] Asynchronous write module: Provides standard functions to the upper layer, which can call these functions to enable writing data from the source address to the target address of the corresponding sector; and completes the write asynchronously in periodic tasks.

[0031] Data erasure module: Provides standard functions to the upper layer, which can be called to erase all data in the selected sector.

[0032] TricoreFlash Controller Driver Layer: Encapsulates all operations for the Tricore architecture-specific Flash controller, including unlocking PFlash / DFlash, writing standard command sequences, checking operation status, and handling access errors, providing a unified hardware operation interface for upper-layer modules.

[0033] This disclosure provides a memory management method, based on the aforementioned memory management system, comprising: During power-on initialization, the system polls all physical sectors allocated by the memory management system during system initialization, calculates written addresses, writable addresses, and readable addresses, and detects and handles bad blocks. When a read request is received from an upper-layer application, the address translation module queries the logical-physical address mapping table to obtain the valid physical address of the corresponding physical sector, and synchronously reads the data at that physical address into the target cache. When a write request is received from an upper-layer application based on a logical address, the address translation module determines the valid physical address of the corresponding physical sector and asynchronously completes the data writing in a periodic task. When a wipe request is received from the upper-layer application, all data in the selected sector is wiped.

[0034] In practice: Initialization steps are as follows Figure 2 As shown: During system initialization, the status of the sectors allocated by the memory management system is checked. All sectors are polled, and information such as the currently written addresses, writable addresses, and readable addresses of each sector is calculated. Problematic sectors can be detected, and those blocks are marked as bad blocks, with their addresses being erased. After erasure, the block address is marked as a valid block, allowing writing. When a sector is found to be valid, a validity check is performed on that sector.

[0035] Data reading steps are as follows Figure 3 As shown: The upper-layer application initiates a request to read data from a pre-allocated sector (which contains information about the target address) of the memory management system.

[0036] Calculate the effective length of the data to be read.

[0037] Data from the selected sector will be synchronously read into the target address.

[0038] Data writing steps are as follows Figure 4 and Figure 5 As shown: The upper-layer application initiates a request to write data to a pre-divided Sector (which contains information about the target address) of the memory management system.

[0039] The logical address mapping module is used to map the Sector to the upper-layer application, and to look up relevant information about the pre-divided Sector, such as the target address and the validity of the target address. If the current Sector address is in the erase state and the Sector block state is initialized, the valid information flag bit, which occupies 8 bytes, is written to the physical address corresponding to the Sector block in a 4-byte aligned format, and is written asynchronously in the periodic task.

[0040] Based on the current Sector's used status and the Sector block status being verified, the Sector write module will be called again. The valid information from the source address, which occupies 8 bytes, will be written in a format aligned to 4 bytes to the physical address corresponding to the Sector block. The written data will be compared with the data in the source address. If they are completely consistent, asynchronous writing is allowed in the periodic task.

[0041] Data from the source address is asynchronously written to the target address of the selected sector in a periodic task, and the FLS address is polled in the periodic task to determine whether the data writing is complete.

[0042] Data erasure steps are as follows Figure 6 As shown: The upper-layer application initiates a request to erase data in a pre-divided Sector (which contains information about the target address) of the memory management system.

[0043] Call the Flash Status API to get the status of the previous memory task, if it is not in a pending state.

[0044] The API for wiping FLS can erase the target address by selecting the start address and region size. Compared with the prior art, this disclosure has the following significant advantages: 1. Extremely high flexibility: Through logical address mapping, upper-layer applications do not need to care about the physical storage location of data, realizing dynamic allocation similar to memory, perfectly supporting complex scenarios such as variable-length data, multiple updates, and dynamic partitioning.

[0045] 2. Improve system performance and real-time performance: Write operations are performed asynchronously, and the flexible write mechanism also reduces unnecessary erase operations.

[0046] 3. Hardware architecture optimization: Deep optimization of Tricore's Flash controller to fully utilize its hardware performance and ensure operational efficiency and security.

[0047] like Figure 7 As shown, this disclosure provides an electronic device, including a processor 701, a communication interface 702, a memory 703, and a communication bus 704, wherein the processor 701, the communication interface 702, and the memory 703 communicate with each other through the communication bus 704; Memory 703 stores computer programs; The processor 701 implements the above method when executing a computer program stored in the memory 703.

[0048] This disclosure provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0049] The computer-readable storage medium may be included in the device / apparatus described in the above embodiments; or it may exist independently and not assembled into the device / apparatus. The computer-readable storage medium carries one or more programs that, when executed, implement the method according to the embodiments of this disclosure.

[0050] According to embodiments of this disclosure, the computer-readable storage medium can be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this disclosure, the computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0051] To enable those skilled in the art to better understand this disclosure, the principles of this disclosure are explained as follows: The sectors are divided into sectors based on their numbering and memory size as needed.

[0052] 1. The TricoreFlash controller driver layer encapsulates all operations for the Tricore architecture-specific Flash controller, including unlocking PFlash / DFlash, writing standard command sequences, checking operation status, and handling access errors, providing a unified hardware operation interface for upper-layer modules.

[0053] 2. Logical Address Mapping Module: This module provides a unified and continuous logical address space to upper-layer applications, shielding them from differences in the size, location, and status of the underlying Flash physical sectors. When the upper layer calls functions to write data, it does not need to consider the specific location distribution of the address; it only needs to check whether the data being written conforms to the byte alignment rules and length.

[0054] 3. Address Translation Module: Connected to the logical address mapping module, this module maintains a dynamic logical-physical address mapping table. It is responsible for converting application-initiated logical address access requests into currently valid physical addresses in real time.

[0055] 4. Power-on initialization module: such as Figure 2 As shown, The system checks the status of the sectors allocated by the memory management system during initialization.

[0056] Poll all sectors and calculate information such as the current written address, writable address, and readable address for each sector.

[0057] By reading the Marker value at the fixed address of the Sector, it can be determined whether the Sector is a corrupted block. If the block address is corrupted, an erasure operation is performed on the block address to clear all data. After erasure is complete, the block address will be set as a valid block, allowing writing.

[0058] Once the current sector is found to be a valid sector, a validity check will be performed on that sector.

[0059] 5. Synchronous reading module, such as Figure 3 As shown: It provides standard functions to the upper layer, which can synchronously read data from Dflash to the target address by using the sector number, the target address, and the data length.

[0060] The upper-layer application initiates a request to read data from a pre-allocated sector (which contains information about the target address) of the memory management system.

[0061] Solve the block status and effective block length of the Sector that needs to read data.

[0062] Data from the selected sector will be synchronously read into the target address.

[0063] 6. Asynchronous write module: such as Figure 4 and Figure 5 As shown, a standard function is provided to the upper layer, which can call the function to enable writing data from the source address to the target address of the corresponding sector; and the writing is completed asynchronously in a periodic task.

[0064] The upper-layer application initiates a request to write data to a pre-divided Sector (which contains information about the target address) of the memory management system.

[0065] The logical address mapping module is used to map the Sector to the upper-layer application, and to look up relevant information about the pre-divided Sector, such as the target address and the validity of the target address. If the current Sector address is in the erase state and the Sector block state is initialized, the valid information flag bit, which occupies 8 bytes, is written to the physical address corresponding to the Sector block in a 4-byte aligned format, and is written asynchronously in the periodic task.

[0066] Based on the current Sector's used status and the Sector block status being verified, the Sector write module will be called again. The valid information from the source address, which occupies 8 bytes, will be written in a format aligned to 4 bytes to the physical address corresponding to the Sector block. The written data will be compared with the data in the source address. If they are completely consistent, asynchronous writing is allowed in the periodic task.

[0067] Data from the source address is asynchronously written to the target address of the selected sector in a periodic task, and the FLS address is polled in the periodic task to determine whether the data writing is complete.

[0068] Data erasure module, such as Figure 6 As shown, a standard function is provided to the upper layer, which can call the function to erase all data in the selected sector.

[0069] This disclosure provides a unified, contiguous logical address space for upper-layer applications, shielding the differences in size, location, and status of the underlying Flash physical sectors.

[0070] Connected to the logical address mapping module, it maintains a dynamic "logical-physical" address mapping table. This module is responsible for converting logical address access requests initiated by applications into currently valid physical addresses in real time.

[0071] During system initialization, the status of the sectors allocated by the memory management system is checked. All sectors are polled, and information such as the currently written addresses, writable addresses, and readable addresses of each sector is calculated. Problematic sectors are detected, and the blocks are marked as bad blocks, with their addresses being erased. After erasure, the block addresses are marked as valid blocks, allowing writing. Once a valid sector is detected, a validity check is performed on it.

[0072] It provides standard functions to the upper layer, which can synchronously read data from Dflash to the target address by using the sector number, the target address, and the data length.

[0073] It provides standard functions to the upper layer, which can call these functions to enable writing data from the source address to the target address of the corresponding sector; and complete the writing asynchronously in a periodic task.

[0074] It provides a standard function to the upper layer, which can be called to erase all data in the selected sector.

[0075] The TricoreFlash controller driver layer encapsulates all operations for the Tricore architecture-specific Flash controller, including unlocking PFlash / DFlash, writing standard command sequences, checking operation status, and handling access errors, providing a unified hardware operation interface for upper-layer modules.

[0076] Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A memory management system, characterized in that, include: The logical address mapping module is used to provide a unified and continuous logical address space to upper-layer applications, shielding the differences in the size, location, and status of physical sectors. The address translation module, connected to the logical address mapping module, is used to maintain a dynamic logical-physical address mapping table and convert logical address access requests initiated by applications into valid physical addresses for the corresponding physical sectors in real time. The power-on initialization module is used to poll all physical sectors allocated by the memory management system during system initialization, calculate written addresses, writable addresses, and readable addresses, and detect and handle bad blocks. The synchronous read module is used to receive read requests from upper-layer applications, query the logical-physical address mapping table through the address translation module to obtain the valid physical address of the corresponding physical sector, and synchronously read the data at that physical address into the target cache. The asynchronous write module is used to receive write requests initiated by upper-layer applications based on logical addresses, determine the valid physical address of the corresponding physical sector through the address translation module, and asynchronously complete the data writing in a periodic task. The data erasure module is used to receive erasure requests from upper-layer applications and erase all data in the selected sector.

2. A memory management system according to claim 1, characterized in that, The asynchronous write module includes a write request caching unit and a background polling unit: Write to the request cache unit to temporarily store the logical address, source data address, and data length submitted by the upper-layer application; The background polling unit is invoked during the system's periodic tasks to perform the actual physical write operation based on the request from the cache unit, and polls the status register after the write to confirm that the write is complete.

3. A memory management system according to claim 2, characterized in that, The asynchronous write module is specifically used for: When the valid physical address of the corresponding physical sector is in the erase state and the sector block state is initialized, the valid information flag is written to the physical address corresponding to the sector in an aligned format, and then the asynchronous writing of the source data is triggered. When the corresponding physical sector is in a used state and the sector block status is in a verified state, a new writable physical address is allocated within the sector. The valid information in the source address is written into the new writable physical address in an aligned format. The written data is compared with the data in the source address. If they are completely consistent, the logical-physical address mapping table is updated to point to the new writable physical address. At the same time, the data in the original physical address is marked as invalid and submitted to the background polling unit for asynchronous writing.

4. A memory management system according to claim 1, characterized in that, The specific method by which the power-on initialization module detects and handles bad blocks is as follows: The system reads the Marker value at the fixed address of the Sector to determine if the Sector is corrupted. If it is corrupted, an erasure operation is performed. After erasure, the system verifies the validity of the block. If the verification passes, the Sector is set as a valid block and allowed to be written to. If the verification fails, the Sector is set as a permanent bad block and isolated.

5. A memory management method, characterized in that, A memory management system according to any one of claims 1-4, comprising: During power-on initialization, the system polls all physical sectors allocated by the memory management system during system initialization, calculates written addresses, writable addresses, and readable addresses, and detects and handles bad blocks. When a read request is received from an upper-layer application, the address translation module queries the logical-physical address mapping table to obtain the valid physical address of the corresponding physical sector, and synchronously reads the data at that physical address into the target cache. When a write request is received from an upper-layer application based on a logical address, the address translation module determines the valid physical address of the corresponding physical sector and asynchronously completes the data writing in a periodic task. When a wipe request is received from the upper-layer application, all data in the selected sector is wiped.

6. A memory management method according to claim 5, characterized in that, Data writing is performed asynchronously in periodic tasks, including: When the valid physical address of the corresponding physical sector is in the erase state and the block state is initialized, the valid information flag is written to the physical address corresponding to the sector in an aligned format, and then the asynchronous writing of the source data is triggered. When the corresponding physical sector is in a used state and the block status is in a verified state, a new writable physical address is allocated within the sector. The valid information in the source address is written into the new writable physical address in an aligned format. The written data is compared with the data in the source address. If they are completely consistent, the logical-physical address mapping table is updated to point to the new writable physical address. At the same time, the data in the original physical address is marked as invalid and submitted to the background polling unit for asynchronous writing.

7. A memory management method according to claim 5, characterized in that, During system initialization, all physical sectors allocated by the memory management system are polled, including rebuilding the logical-physical address mapping table: Traverse the written areas of all valid sectors, read the valid information flags of data blocks, filter out the latest valid data blocks based on the logical address information and data status recorded in the valid information flags, and restore and construct the mapping relationship between logical addresses and the latest physical addresses.

8. A memory management method according to claim 5, characterized in that, Erase all data in the selected sector, followed by: The erased Sector is marked as free and available, and its space is reintegrated into the available physical space pool of the logical address mapping module for space allocation during subsequent writes.

9. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, which stores computer programs; A processor, when executing a computer program stored in memory, implements a memory management method according to any one of claims 5-8.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements a memory management method according to any one of claims 5-8.

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