Data caching method and storage device

Abstract

The application relates to a data caching method and a storage device, and belongs to the technical field of storage. The method comprises the following steps: when a firmware programs a flash memory page, detecting the proportion of read and write commands in host IO commands; according to the proportion of the read and write commands, adjusting the release time of the buffer, and completing data caching. Through dynamic adjustment of the release time of the buffer, in combination with dynamic management of the number of high-performance buffers and low-performance buffers in the buffer pool, long-time waiting of the read command is avoided, the read service quality is optimized, and the maximum write performance is maintained.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a data caching method and storage device. Background Technology

[0002] Solid State Drive (SSD) firmware programming flash memory pages can be divided into two stages: transferring data into the flash memory cache (i.e., transfer complete); and writing data into the medium (i.e., programming complete). The controller can be configured to send corresponding transfer complete and programming complete signals to the firmware after these two stages are completed. To achieve extremely high sequential write performance in SSDs, the firmware needs to utilize high-performance buffers (e.g., Static Random-Access Memory, SRAM) to carry user data from the host. However, due to the high cost of high-performance buffers, they are rarely used in SSD controllers. To improve the throughput of high-performance buffers, the firmware typically releases the buffer immediately after data is transferred into the flash memory buffer (i.e., transfer complete).

[0003] However, while this buffer release timing significantly improves buffer turnover and write performance, it also introduces problems. When a host read command hits this released buffer, the read command must wait until the flash memory is fully programmed before it can read the correct data from the flash memory. This significantly worsens the latency of some read commands, resulting in unsatisfactory Quality of Service (QoS). Summary of the Invention

[0004] Therefore, in response to the above-mentioned technical problems, this application provides a data caching method and storage device to solve the problem of unsatisfactory read service quality when programming flash memory pages in firmware.

[0005] In a first aspect, embodiments of this application provide a data caching method, the data caching method comprising: in response to receiving an IO command from a host, detecting the ratio of read and write commands in the IO command; dynamically determining the timing of buffer release based on the ratio of read and write commands, and caching the data included in the IO command.

[0006] In some embodiments of this application, the step of dynamically determining the release timing of the buffer based on the ratio of the read and write commands includes: when the ratio of the read and write commands is identified as a pure write state, determining the release timing of the buffer as the transmission is complete; when the ratio of the read and write commands is identified as a mixed read and write state, determining the release timing of the buffer as the programming is complete.

[0007] In some embodiments of this application, when the ratio of the read / write command is identified as a pure write state, the data caching method further includes: requesting a first buffer from a buffer pool to receive the data included in the IO command; after the data is received, transferring the data from the first buffer to the cache of the flash memory; and releasing the first buffer after the data is transferred into the cache of the flash memory; wherein the first buffer is of the type of low-performance buffer or high-performance buffer.

[0008] In some embodiments of this application, when the ratio of read and write commands is identified as a mixed read and write state, the data caching method further includes: switching the software mode from transmission completion to programming completion, selecting a low-performance buffer in the software pool, and releasing it into the buffer pool.

[0009] In some embodiments of this application, the data caching method further includes: in response to the completion of flash programming, releasing all low-performance buffers and / or high-performance buffers into a buffer pool.

[0010] In some embodiments of this application, before requesting the first buffer from the buffer pool, the data caching method further includes: adding the low-performance buffer to the empty buffer pool to form a buffer pool.

[0011] In some embodiments of this application, the data caching method further includes: determining the type of a first buffer to be released, and determining the location to release the first buffer based on the type of the first buffer.

[0012] In some embodiments of this application, determining the location for releasing the first buffer based on its type includes: when the first buffer is a low-performance buffer, releasing the first buffer to a firmware-managed software pool.

[0013] In some embodiments of this application, determining the release location of the first buffer based on its type includes: when the first buffer is a high-performance buffer, releasing the first buffer back to the buffer pool.

[0014] Secondly, embodiments of this application also provide a storage device, including: a memory and a processor, wherein the processor includes multiple cores, and the memory stores a computer program, which, when executed by the processor, implements the above-described data caching method.

[0015] Through the above technical solution, the data caching method provided in this application embodiment detects the ratio of read and write commands from host I / O commands during firmware programming of flash memory pages; adjusts the release timing of the buffer according to the ratio of read and write commands, and completes data caching. This application embodiment avoids long wait times for read commands by dynamically adjusting the release timing of the buffer, combined with dynamic management of the number of high-performance and low-performance buffers in the buffer pool, thus optimizing read service quality (QoS) while maintaining maximum write performance. Furthermore, by managing different types of buffers, it optimizes the read service quality of the storage device and maintains the maximum write performance of the storage device.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating the data caching method provided in an embodiment of this application.

[0019] Figure 2 This is a schematic diagram of the data caching and buffer management process provided in the embodiments of this application.

[0020] Figure 3 This is a schematic diagram of the data buffer flow state in pure write mode provided in an embodiment of this application.

[0021] Figure 4 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0023] Please refer to Figure 1 This application provides a data caching method, which may include the following steps: Step S110: In response to receiving an IO command from the host, detect the ratio of read and write commands in the IO commands.

[0024] The firmware detection frequency is, for example, once per second, meaning the detection cycle is one second. The firmware can detect the number of read or write commands from the host within one second. Firmware can be understood as a low-level software program running on the device's main control chip, such as the firmware in a solid-state drive (SSD), USB flash drive, or embedded storage device.

[0025] Step S120: Dynamically determine the timing of buffer release based on the ratio of read and write commands, and complete the caching of data included in the IO commands.

[0026] In a preferred embodiment of this application, dynamically determining the timing of buffer release based on the ratio of read and write commands may include: identifying whether the current state is a pure write state or a mixed read and write state based on the ratio of read and write commands, and then dynamically determining the timing of buffer release. When the ratio of read and write commands is identified as a pure write state, the timing of buffer release is determined to be the completion of transmission; when the ratio of read and write commands is identified as a mixed read and write state, the timing of buffer release is determined to be the completion of programming.

[0027] In the embodiments of this application, the pure write state can be understood as only a write command is detected within the detection period (e.g., 1 second), with no or almost no read commands; the mixed read-write state can be understood as read commands and write commands detected within 1 second coexisting, and the read command has a certain probability of reading the logical address that has just been written or is about to be written.

[0028] Please refer to Figure 2 For example, when the firmware detects that it is currently in a pure write state (also known as a pure write scenario), the buffer is released during the transfer completion stage; that is, the buffer is released immediately after the data is transferred into the non-volatile flash memory (e.g., NAND cache). When the firmware detects that it is currently in a mixed read / write state (also known as a mixed read / write scenario), the buffer is released during the programming completion stage. The NAND cache is a device located inside the NAND flash memory and is not managed by the firmware. All data is transferred into the NAND flash memory for caching before programming.

[0029] This application embodiment can dynamically determine the timing of buffer release based on the read / write status. In a pure write scenario where reading is not affected, the buffer is still released after the transmission is completed. Only in a mixed read / write scenario is the buffer released after programming is completed, thus avoiding long wait times for reads (commands) and ensuring the Quality of Service (QoS) for read operations.

[0030] In a preferred embodiment of this application, when the ratio of read / write commands is identified as a pure write state, the data caching method may further include: requesting a first buffer from a buffer pool to receive the data included in the IO command; after the data is received, transferring the data from the first buffer to the flash memory cache; and releasing the first buffer after the data is transferred into the flash memory cache. The first buffer may be a low-performance buffer or a high-performance buffer.

[0031] High-performance buffers, such as SRAM, have fast read / write speeds, short access times, and low latency, but are difficult to implement for large-capacity storage. Low-performance buffers, such as DRAM, have read / write speeds that are an order of magnitude slower than SRAM, longer access times, and higher latency for random access, but can achieve large-capacity storage.

[0032] Please refer to Figure 3 For example, in a pure write state, the flow of data buffer in an SSD can include: issuing a write command; the SSD requesting a buffer (i.e., the first buffer) from the buffer pool to receive data; after the data is received, it is transferred to the cache of the flash memory (e.g., NAND); after the data enters the cache of the flash memory, the buffer can be immediately released back to the buffer pool.

[0033] In a preferred embodiment of this application, when the ratio of read and write commands is identified as a mixed read and write state, the data caching method may further include: switching the software mode from transmission completion to programming completion, selecting a low-performance buffer in the software pool, and releasing it into the buffer pool.

[0034] In a preferred embodiment of this application, the data caching method may further include: in response to the completion of flash programming, releasing all low-performance buffers and / or high-performance buffers into a buffer pool.

[0035] Please refer to Figure 2 For example, in a mixed read / write state, the release timing of the buffer is determined to be the programming completion stage. Switching the software mode from transfer completion to programming completion releases low-performance buffers in the software pool to the buffer pool; in response to flash programming completion, they are released back to the buffer pool (all types of buffers).

[0036] In this embodiment, since there are no read commands waiting for write commands to complete during a pure write IO command, and the data storage area (in NAND) is in a defined state when data is written, an early release strategy can be adopted for buffer release. That is, as soon as the data of the write command is transmitted to the NAND buffer, the occupied buffer can be released; and by selecting a high-performance buffer for release, it can be transferred back to the buffer pool for use in the processing of subsequent commands.

[0037] The difference lies in the fact that in mixed read / write mode, IO commands include both read and write commands; the timing of buffer release cannot be too early, but must wait until programming is complete before all low-performance buffers in the software pool can be released to the buffer pool. First, in software mode, the switching timing needs to be adjusted to release buffers only after programming is complete. Then, all low-performance buffers in the software pool are released back to the buffer pool. After flash programming is complete, all buffers (including low-performance buffers and high-performance buffers) need to be released to the buffer pool. In some controllers, it may not be possible to specify the type of buffer acquired in the buffer pool. To avoid acquiring low-performance buffers affecting write performance, in a preferred embodiment of this application, only high-performance buffers are added to the buffer pool.

[0038] In a preferred embodiment of this application, the read service quality of the storage device can be optimized and the maximum write performance of the storage device can be maintained by managing different types of buffers.

[0039] In a preferred embodiment of this application, before requesting the first buffer from the buffer pool, the data caching method may further include: adding a low-performance buffer to an empty buffer pool to form a buffer pool.

[0040] For example, a buffer pool can be configured to add a sufficient amount of low-performance buffers.

[0041] In a preferred embodiment of this application, the data caching method may further include: determining the type of the first buffer to be released, and determining the location to release the first buffer based on the type of the first buffer.

[0042] Please refer to Figure 2 As mentioned earlier, when the firmware detects that it is currently in a pure write scenario, the buffer is released as soon as the data is transferred into the NAND flash memory. However, only the high-performance buffer is released into the buffer pool, while the low-performance buffer is placed into the software pool managed by the firmware and will not be transferred again. In a pure write scenario, the firmware excludes the low-performance buffer from the buffer pool and restores the buffer release timing to when the flash memory transfer is complete, thus maintaining the maximum write performance in a pure write scenario.

[0043] In a preferred embodiment of this application, determining the location for releasing the first buffer based on its type may include: when the first buffer is a low-performance buffer, releasing the first buffer to a firmware-managed software pool.

[0044] In this embodiment, the NAND cache is managed internally within the NAND flash memory. Before data is programmed and written to the NAND medium, it must first be transferred to the NAND cache. The software pool is initially empty. During a pure write command, the firmware only places low-performance buffers into the software pool. When releasing buffer resources, a buffer resource is randomly selected for release.

[0045] In a preferred embodiment of this application, determining the release location of the first buffer based on its type may include: when the first buffer is a high-performance buffer, releasing the first buffer back to the buffer pool.

[0046] Please refer to Figure 2 For example, when the firmware detects a mixed read / write scenario, it immediately releases the low-performance buffer from the software pool to the buffer pool, allowing it to join the flow. The release timing of the buffer is switched to after flash programming is complete. This way, when a read operation hits data that has been transferred, it can directly read from the buffer without waiting for flash programming to finish. In mixed read / write scenarios, by delaying the buffer release timing until programming is complete, long wait times for reads are avoided. Furthermore, by adding a low-performance buffer, the performance degradation caused by insufficient buffer quantity after slow buffer flow is avoided. This embodiment of the application can optimize read QoS performance in mixed read / write scenarios while ensuring that performance in pure write scenarios remains unaffected.

[0047] Accordingly, the data caching method provided in this application embodiment detects the ratio of read and write commands from host I / O commands during firmware programming of flash memory pages; adjusts the release timing of the buffer based on the ratio of read and write commands, and completes data caching. This application embodiment avoids long wait times for read commands by dynamically adjusting the release timing of the buffer, combined with dynamic management of the number of high-performance and low-performance buffers in the buffer pool, thus optimizing read service quality (QoS) while maintaining maximum write performance. Furthermore, by managing different types of buffers, it optimizes the read service quality of the storage device and maintains the maximum write performance of the storage device.

[0048] Furthermore, this application embodiment differentiates between pure write scenarios and mixed read / write scenarios. In mixed read / write scenarios, by delaying the buffer release timing until after programming is complete, long wait times for read commands in IO commands are avoided; by adding low-performance buffers, performance degradation caused by insufficient buffer quantity after slow buffer stream transitions is prevented. In pure write scenarios, low-performance buffers are excluded from the buffer pool through firmware, and the buffer re-addition timing is restored to after flash transfer is complete, maintaining maximum performance in pure write scenarios. Based on this, this application embodiment can optimize the read service quality of storage devices and maintain the maximum write performance of storage devices.

[0049] It should be understood that, Figure 1-3 The steps in the flowchart are not necessarily executed in the indicated order. Unless otherwise explicitly stated herein, there is no strict order in which these steps are performed; they can be executed in other orders. Figure 1-3At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0050] It is understood that the same / similar parts between the various embodiments of the methods described above in this specification can be referred to each other. Each embodiment focuses on the differences from other embodiments, and relevant parts can be referred to the description of other method embodiments.

[0051] This application also provides a storage device, which includes a processor and a memory. The processor contains multiple cores, and the memory stores a computer program. When the computer program is executed by the processor, it can implement the data caching method of any of the above embodiments. The execution method and beneficial effects are similar, and will not be described again here.

[0052] Figure 4 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application, such as... Figure 4 As shown, the storage device may include a processor 410 and a memory 420. The memory 420 stores a computer program. When the computer program is executed by the processor 410, it can implement the data caching method provided in any of the above embodiments. Its execution method and beneficial effects are similar and will not be described again here.

[0053] Of course, for the sake of simplicity, Figure 4 Only some of the components of the storage device relevant to the present invention are shown, omitting components such as buses, input / output interfaces, input devices, and output devices. In addition, the storage device may include any other suitable components depending on the specific application.

[0054] This application provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement the data caching method of any of the above embodiments. The execution method and beneficial effects are similar, and will not be described again here.

[0055] The aforementioned computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0056] The computer program described above can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer device, partially on the user's device, as a standalone software package, partially on the user's computer device and partially on a remote computer device, or entirely on a remote computer device or server.

[0057] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. Multitasking and parallel processing may be advantageous in certain environments. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this application. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0058] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data caching method, characterized in that, The data caching method includes: In response to receiving I / O commands from the host, detect the ratio of read to write commands in the I / O commands; Based on the ratio of read and write commands, the timing of buffer release is dynamically determined, and the data included in the IO commands is cached.

2. The data caching method according to claim 1, characterized in that, The step of dynamically determining the timing of buffer release based on the ratio of read and write commands includes: When the ratio of the read / write command is identified as a pure write state, the release timing of the buffer is determined to be when the transmission is completed; When the ratio of the read and write commands is identified as a mixed read and write state, the release timing of the buffer is determined to be when the programming is completed.

3. The data caching method according to claim 2, characterized in that, When the ratio of the read / write command is identified as a pure write state, the data caching method further includes: Allocate the first buffer from the buffer pool to receive the data included in the I / O command; After the data is received, the data is transferred from the first buffer to the flash memory cache; After the data is transferred into the cache of the flash memory, the first buffer is released; The first buffer is either a low-performance buffer or a high-performance buffer.

4. The data caching method according to claim 3, characterized in that, When the ratio of the read / write commands is identified as a mixed read / write state, the data caching method further includes: Switch the software mode from transport-complete to program-complete, select low-performance buffers in the software pool, and release them into the buffer pool.

5. The data caching method according to claim 4, characterized in that, The data caching method further includes: In response to the completion of flash programming, all low-performance buffers and / or high-performance buffers are released into the buffer pool.

6. The data caching method according to claim 3, characterized in that, Before requesting the first buffer from the buffer pool, the data caching method further includes: Add low-performance buffers to an empty buffer pool to form a buffer pool.

7. The data caching method according to claim 3, characterized in that, The data caching method further includes: Determine the type of the first buffer to be released, and determine the location to release the first buffer based on its type.

8. The data caching method according to claim 7, characterized in that, Determining the release location of the first buffer based on its type includes: When the first buffer is of type low-performance buffer, the first buffer is released to the firmware-managed software pool.

9. The data caching method according to claim 7, characterized in that, Determining the release location of the first buffer based on its type includes: When the first buffer is of type high-performance buffer, the first buffer is released back to the buffer pool.

10. A storage device, characterized in that, include: A memory and a processor, the processor comprising multiple cores, wherein the memory stores a computer program that, when executed by the processor, implements the data caching method according to any one of claims 1-9.

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