Method, apparatus, system, and medium for accelerating memory management unit to page table

Abstract

The application discloses a method, device, system and medium for accelerating a page table of a memory management unit; the method is applied to a computing unit on a memory side; the method comprises the following steps: receiving a page table acquisition command sent by a memory management unit; wherein the page table acquisition command comprises a virtual address and page table access control information; the page table access control information is used for indicating a page table level which needs to be accessed in a memory this time and a physical base address corresponding to a starting level in a current access process; analyzing the page table acquisition command, obtaining the physical base address corresponding to the starting level, and reading target page table items corresponding to each page table level from the memory step by step according to a level index in the virtual address, so as to supplement a mapping link between the virtual address and the physical address; and returning all the read target page table items to the memory management unit. The application can reduce bus round-trip transmission time consumption and improve address conversion efficiency.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus, system, and computer-readable storage medium for accelerating the fetching of page tables by a memory management unit. Background Technology

[0002] The Memory Management Unit (MMU) is responsible for translating virtual addresses from the processor into physical addresses. Upon receiving a virtual address, the MMU first checks its internal Translation Lookaside Buffer (TLB) to see if a corresponding physical page frame number exists. If the TLB matches, the MMU can immediately synthesize the physical address. If the TLB misses, the MMU needs to access multiple levels of page tables in memory, performing a step-by-step search to complete the address translation.

[0003] Taking a 48-bit virtual address and a 4KB page size as an example, in the event of a TLB miss, the MMU needs to initiate four consecutive memory read operations to sequentially read four levels of page table entries to complete the virtual-to-physical address mapping. Memory access latency is much higher than on-chip cache latency, and multiple serial memory accesses significantly increase address translation time, thereby reducing processor efficiency. Therefore, shortening the MMU's address translation latency is a problem that urgently needs to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a method, apparatus, system, and computer-readable storage medium for accelerating page table fetching by a memory management unit. By using a computing unit located inside or outside the memory, the page table reading task is completed, reducing the bus round-trip transmission time caused by the memory management unit directly accessing multi-level page tables serially, thereby improving address translation efficiency.

[0005] A first aspect of the present invention provides a method for accelerating page table fetching by a memory management unit, applied to a computing unit; the computing unit is located inside or outside a memory storing multi-level page tables; the method includes: The system receives a page table retrieval command sent by the memory management unit; wherein the page table retrieval command includes: a virtual address and page table access control information; the page table access control information is used to indicate the page table level that needs to be accessed in the memory this time, and the physical base address corresponding to the starting level during this access process; The page table retrieval command is parsed to obtain the physical base address corresponding to the starting level. Based on the level index in the virtual address, the target page table entry corresponding to each page table level is read from the memory level by level to complete the mapping link between the virtual address and the physical address. All read target page table entries are sent back to the memory management unit.

[0006] Optionally, the page table access control information includes: base address information and missing physical page frame number values ​​corresponding to each level of page table; each base address information is either the physical base address of the corresponding page table or a missing physical base address value.

[0007] Optionally, parsing the page table retrieval command to obtain the physical base address corresponding to the starting level, and reading the target page table entry corresponding to each page table level from the memory according to the level index in the virtual address, includes: Based on the missing identifier value in the page table access control information, determine the physical base address corresponding to the page table level and the starting level; Starting from the physical base address corresponding to the starting level, and combining the corresponding level index, read operations are performed level by level in the memory to obtain the target page table entry corresponding to each page table level.

[0008] Optionally, the target page table entry is obtained through the following steps: Based on the level index and physical base address corresponding to the current page table level, read a preset number of consecutive data blocks from the current page table; wherein, the consecutive data blocks include: the base page table entry pointed to by the corresponding level index, and the adjacent page table entries of the base page table entry; Each adjacent page table entry is evaluated for validity, and all valid adjacent page table entries, along with the reference page table entry, are used as the target page table entry for the current page table level.

[0009] Optionally, the page table fetch command is generated when the memory management unit detects that the mapping link in the translation back cache is incomplete.

[0010] A second aspect of the present invention provides a system for accelerating page table fetching by a memory management unit, the system comprising: a memory management unit and a computing unit; wherein the computing unit is located inside or outside a memory storing multi-level page tables; The memory management unit is used to check whether the mapping link between the received virtual address and the physical address is complete in the translation back cache. If the mapping link is incomplete, it generates a page table retrieval command and sends it to the computing unit through the bus. The computing unit is used to execute the method of fetching the page table for the accelerated memory management unit as described in any one of claims 1 to 5.

[0011] Optionally, the memory management unit includes: a command generation subunit; The command generation subunit is used to generate the page table retrieval command based on the physical base address of the first-level page table cached in the page table base address register and the physical base addresses of N cached page tables in the translation backing cache when the mapping link is incomplete; wherein, N≥0.

[0012] Optionally, the memory management unit is further configured to write all target page table entries returned by the computing unit into the translation back cache through the control unit corresponding to the translation back cache.

[0013] A third aspect of the present invention provides an apparatus for accelerating page table fetching by a memory management unit, applied to a computing unit; the computing unit is located inside or outside a memory storing multi-level page tables; the apparatus includes: The command acquisition module is used to receive page table acquisition commands sent by the memory management unit; wherein, the page table acquisition command includes: virtual address and page table access control information; the page table access control information is used to indicate the page table level that needs to be accessed in the memory this time, and the physical base address corresponding to the starting level in this access process; The page table reading module is used to parse the page table acquisition command, obtain the physical base address corresponding to the starting level, and read the target page table entry corresponding to each page table level from the memory level by level according to the level index in the virtual address, so as to complete the mapping link between the virtual address and the physical address. The result return module is used to uniformly return all read target page table entries to the memory management unit.

[0014] A fourth aspect of the present invention provides a computer-readable storage medium comprising a stored computer program; wherein, when the computer program is executed, it controls the device in which the computer-readable storage medium is located to perform the method for fetching page tables of an accelerated memory management unit as described in any embodiment of the first aspect.

[0015] Compared with the prior art, the embodiments of the present invention provide a method, apparatus, system, and computer-readable storage medium for accelerating page table fetching by a memory management unit. By integrating a dedicated computing unit inside or outside the memory to execute the page table reading task delegated by the memory management unit, the multiple serial table lookup interactions between the memory management unit and the memory are transformed into a single command issuance and result return interaction, which can effectively reduce the bus round-trip transmission time and improve address translation efficiency. In addition, the page table access control information carried in the page table retrieval command can limit the page table level to be accessed and the physical base address of the starting level, eliminating the need to traverse level by level from the first-level page table each time, thereby reducing redundant memory access operations. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of an embodiment of a memory management unit page table system provided by related technologies; Figure 2 This is a flowchart illustrating an embodiment of the method for accelerating the page table fetching of a memory management unit provided by the present invention; Figure 3 This is a schematic diagram of a structure of an embodiment of the system for accelerating the page table fetching of the memory management unit provided by the present invention; Figure 4 This is a schematic diagram of another embodiment of the system for accelerating the page table fetching of the memory management unit provided by the present invention; Figure 5 This is a schematic diagram of one embodiment of the apparatus for fetching the page table of the accelerated memory management unit provided in this invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] like Figure 1 The diagram shown is a structural schematic of an embodiment of a page table fetching system for a memory management unit provided by related technologies. The processor sends a virtual address to port 0 of the memory management unit (MMU). After receiving the virtual address, the MMU first checks whether the virtual address hits its internal Translation Lookaside Buffer (TLB). If the TLB hits, the MMU directly generates the corresponding physical address and outputs it to the bus via port 1 for subsequent processing. If the TLB misses, the MMU accesses the memory (such as Double Data Rate Synchronous Dynamic Random Access Memory, DDR) via the bus through port 2 to read the multi-level page table and stores the returned page table entries (i.e., page table entries) into the TLB for subsequent address translation.

[0019] The number of page table levels configured in the MMU is determined by the virtual address width and the page size; for example, a four-level page table is typically used when a 48-bit virtual address is paired with a 4KB page. This embodiment of the invention does not limit the specific number of page table levels.

[0020] Taking a four-level page table as an example, the page table fetching process of the memory management unit in related technologies is as follows: The MMU initiates its first read operation to memory (such as DDR) via port2 and receives the returned first-level page table entry (which stores the physical base address of the second-level page table). Based on the physical base address of the second-level page table, the MMU initiates its second read operation to memory via port2 and receives the returned second-level page table entry (which stores the physical base address of the third-level page table). Based on the physical base address of the third-level page table, the MMU continues to initiate its third read operation to memory via port2 and receives the returned third-level page table entry (which stores the physical base address of the fourth-level page table). Based on the physical base address of the fourth-level page table, the MMU initiates its fourth read operation to memory via port2 and receives the returned fourth-level page table entry (which stores the physical page frame number ultimately pointed to by the virtual address).

[0021] Currently, in the case of a TLB miss, the MMU needs to initiate four serial read operations to the memory to complete the virtual-to-physical address translation. The multiple bus interactions accumulate a large access delay, resulting in reduced address translation efficiency and system performance.

[0022] See Figure 2 This is a flowchart illustrating an embodiment of the method for accelerating the page table fetching of a memory management unit provided by the present invention.

[0023] To address the aforementioned technical problems, a first aspect of the present invention provides a method for accelerating page table fetching by a memory management unit, applied to a computing unit; the computing unit is located inside or outside a memory storing multi-level page tables; the method includes steps S1 to S3, as follows: Step S1: Receive a page table retrieval command sent by the memory management unit; wherein, the page table retrieval command includes: virtual address and page table access control information; the page table access control information is used to indicate the page table level that needs to be accessed in the memory this time, and the physical base address corresponding to the starting level in this access process; Step S2: Parse the page table retrieval command to obtain the physical base address corresponding to the starting level, and read the target page table entry corresponding to each page table level from the memory level by level according to the level index in the virtual address, so as to complete the mapping link between the virtual address and the physical address; Step S3: Send all read target page table entries back to the memory management unit.

[0024] It should be noted that, in the embodiments of the present invention, a dedicated computing unit (such as a small CPU) is provided inside the memory storing multi-level page tables (such as integrated inside the DDR chip) or on the periphery (such as close to the DDR chip). This computing unit is used to execute the page table reading task delegated by the MMU and optimize the number of bus interactions.

[0025] The MMU receives the virtual address from the processor and checks if the virtual address hits its internal TLB. If the TLB is not hit, the MMU no longer initiates multiple serial read operations to the memory (such as DDR) via the bus. Instead, it integrates the cache information within the MMU, generates a page table fetch command, and sends it to the memory-side computing unit. The page table fetch command includes at least two parts: the virtual address to be translated and page table access control information. The page table access control information is generated by the MMU based on the valid physical base address of the internally cached page tables. It is used to explicitly indicate the page table level that needs to be read this time, as well as the physical base address corresponding to the starting level of this read. This allows the memory-side computing unit to directly start the query from the page table above the first page table level with a missing physical base address, instead of traversing level by level starting from the first-level page table each time, thereby reducing redundant memory access operations.

[0026] For example, in a scenario involving a four-level page table traversal, if the TLB only caches the first-level page table entry for the virtual address, then the second, third, and fourth-level page table entries need to be retrieved. This means the page table levels that need to be read are from the second to the fourth level (performing three read operations). The physical base address corresponding to the starting level is the physical base address of the second-level page table where the first-level page table entry is stored. If the TLB only caches the first and second-level page table entries for the virtual address, then the third and fourth-level page table entries need to be retrieved. This means additional read operations are required. If the page table hierarchy is from level 3 to level 4 (two read operations are performed), the physical base address corresponding to the starting level is the physical base address of the level 3 page table stored in the level 2 page table entry. If the TLB only caches the level 1, level 2, and level 3 page table entries for the virtual address, then the level 4 page table entry (physical page frame number) needs to be retrieved. That is, the page table hierarchy that needs to be read is level 4 (one read operation is performed), and the physical base address corresponding to the starting level is the physical base address of the level 4 page table stored in the level 3 page table entry.

[0027] After receiving the page table retrieval command, the computing unit first segments the virtual address carried in the command, extracting the hierarchical indexes matching each level of the page table and extracting the physical base address of the starting level from the page table access control information. Then, leveraging its proximity to the memory (such as DDR), the computing unit calculates the physical address of the page table entry at that level based on the physical base address and the corresponding hierarchical index, and reads the entry from memory via port 5. If the currently read page table entry is not the last level (not a physical page frame number), the physical base address of the next-level page table is extracted from it, and the next-level page table entry is read again using the corresponding hierarchical index. Missing page table entries are read level by level in memory until the last-level page table entry is reached, thus completing the mapping link from virtual address to physical address (i.e., all relevant levels of page table entries). During this process, the computing unit can utilize its internal processing capabilities (such as running firmware programs) to perform address calculations and validity checks, completing the page table reading task delegated by the MMU.

[0028] The computing unit packages all the target page table entries it reads and sends them to the bus all at once via port 4, eventually sending them back to the MMU. After receiving all the target page table entries via port 3, the MMU writes them into the translation back buffer via the corresponding control unit (denoted as TLB_ctrl). The MMU can then immediately use this complete mapping link to complete the current virtual address translation, or it can use the page table data cached in the TLB to handle subsequent address translation requests related to the virtual address.

[0029] As can be seen from the above, the method for accelerating the page table fetching of the memory management unit provided by the present invention decentralizes the page table reading task, which originally required the MMU to access the memory serially multiple times, to the computing unit on the memory side. This reduces the number of bus round trips to one command issuance and one result return, which can significantly reduce the time overhead caused by bus round trip transmission. In conjunction with page table access control information to skip the cached effective page table level, it further reduces the number of redundant memory accesses and improves address translation efficiency.

[0030] In an optional embodiment, the page table fetch command is generated when the memory management unit detects that the mapping link in the translation back cache is incomplete.

[0031] Specifically, when the MMU receives a virtual address from the processor, it first checks the mapping in the TLB to determine if the mapping link corresponding to the virtual address has been completely cached. A complete mapping link refers to the link from the first-level page table entry to the last-level page table entry. If the TLB has been completely cached, the MMU directly completes the address translation without generating a page table fetch command. If the TLB is missing the corresponding page table entry, a page table fetch command is generated and sent to the memory-side computing unit to request the computing unit to read the missing page table entries from memory, thereby completing the mapping link of the virtual address.

[0032] In an optional embodiment, the page table access control information includes: base address information and missing physical page frame number values ​​corresponding to each level of page table; each base address information is either the physical base address of the corresponding page table or a missing physical base address value.

[0033] It should be noted that in a scenario involving four-level page table traversal, the format of the page table retrieval command can be {va, lv1_addr, lv2_addr, lv3_addr, lv4_addr,} lv4_pte}; where the va field represents the virtual address to be translated by the MMU; the page table access control information consists of the lv1_addr, lv2_addr, lv3_addr, lv4_addr and lv4_pte fields; the lv1_addr, lv2_addr, lv3_addr and lv4_addr fields correspond to the base address information of the first to fourth level page tables respectively; the value rules for these base address information are uniformly as follows: if the MMU has cached the physical base address of the corresponding level, then the base address information of that level is set to that physical base address; otherwise, the base address information of that level is set to a missing flag value (such as 0) to indicate that the base address of that level is missing and the calculation unit needs to obtain it from the previous level page table entry; the value of the lv4_pte field is the missing flag value corresponding to the physical page frame number. For example, if the lv4_pte field is set to 0, it means that the physical page frame number stored in the fourth level page table is missing and the calculation unit needs to read the last level page table to supplement the physical page frame number.

[0034] Based on the differences in the caching of the four-level page table entries in the MMU, the page table fetch command generated by the MMU has four types: When only the physical base address of the first-level page table is valid, the MMU sets the lv1_addr field to lv1_PA and sends {va, lv1_PA, 0,0, 0, 0}, indicating that the compute unit needs to read the target page table entries from the first-level page table to the fourth-level page table sequentially; when only the physical base addresses of the first-level and second-level page tables are valid, the MMU sends {va, lv1_PA, lv2_PA, 0, 0, 0}, indicating that the compute unit needs to read the target page table entries from the second-level page table to the fourth-level page table sequentially; when the physical base addresses from the first-level page table to the third-level page table are valid, the MMU sends {va, lv1_PA, lv2_PA, lv3_PA, 0, 0} indicates that the computation unit needs to read the target page table entries from the third-level page table to the fourth-level page table sequentially; when the physical base addresses of the first-level page table to the fourth-level page table are all valid, the MMU sends {va, lv1_PA, lv2_PA, lv3_PA, lv4_PA, 0}, indicating that the computation unit needs to read the target page table entry (i.e., the final physical page frame number) from the fourth-level page table; where lvn_PA is the physical base address of the nth-level page table; n≥1.

[0035] The MMU only sends a page table fetch command when the mapping link between the virtual address and physical address within the TLB is incomplete (TLB miss). Obviously, the physical page frame number corresponding to the last-level page table will be missing, and the lv4_pte field will always have a missing flag value of 0 in all the command types mentioned above. Therefore, the command format of the page table fetch command {va,lv1_addr, lv2_addr, lv3_addr, lv4_addr, lv4_pte} can be simplified to {va, lv1_addr, lv2_addr, lv3_addr, lv4_addr}. When the computing unit receives the simplified page table fetch command, it will by default need to read up to the last-level page table entry (i.e., the physical page frame number), without needing to explicitly indicate this in the lv4_pte field.

[0036] Furthermore, the page table fetch command is not limited to the two formats mentioned above: {va, lv1_addr, lv2_addr, lv3_addr, lv4_addr, lv4_pte} and {va, lv1_addr, lv2_addr, lv3_addr, lv4_addr}. It can also carry only the page table base address of the starting level and the total number of page table levels to be accessed, or only the page table base address of the starting level and the sequence number of that starting level, etc. This embodiment of the invention does not specifically limit the format of the page table fetch command, as long as the command can indicate the page table level to be accessed in the memory (e.g., DDR) and the physical base address corresponding to the starting level during this access.

[0037] In an optional embodiment, parsing the page table retrieval command to obtain the physical base address corresponding to the starting level, and reading the target page table entry corresponding to each page table level from the memory according to the level index in the virtual address, includes: Based on the missing identifier value in the page table access control information, determine the physical base address corresponding to the page table level and the starting level; Starting from the physical base address corresponding to the starting level, and combining the corresponding level index, read operations are performed level by level in the memory to obtain the target page table entry corresponding to each page table level.

[0038] It should be noted that when the page table retrieval command is in the format {va, lv1_addr, lv2_addr, lv3_addr, lv4_addr, lv4_pte}, the calculation unit checks whether the values ​​of certain fields are missing flags of 0. Based on these missing flag values, the page table level to be accessed is determined. For example, if the first field with a value of 0 is lv3_addr (i.e., the physical base address of the third-level page table is missing), the calculation unit determines that the page table level to be accessed is the second to fourth level, and the physical base address corresponding to the starting level is lv2_PA (i.e., the physical base address of the second-level page table) filled in the lv2_addr field.

[0039] The computing unit starts from the physical base address corresponding to the starting level, and reads the target page table entry of the current level from the memory in combination with the split level index. The intermediate level page table entry stores the physical base address of the next level page table. The computing unit uses the newly acquired physical base address and the corresponding level index to continue to initiate read operations to the memory, and retrieves the target page table entries of all levels to be supplemented / accessed in sequence, until the target page table entries (i.e., physical page frame numbers) of the last level are read.

[0040] Finally, the computing unit packages all the target page table entries it has read and sends them back to the MMU via the bus.

[0041] In an optional embodiment, the target page table entry is obtained through the following steps: Based on the level index and physical base address corresponding to the current page table level, read a preset number of consecutive data blocks from the current page table; wherein, the consecutive data blocks include: the base page table entry pointed to by the corresponding level index, and the adjacent page table entries of the base page table entry; Each adjacent page table entry is evaluated for validity, and all valid adjacent page table entries, along with the reference page table entry, are used as the target page table entry for the current page table level.

[0042] It should be noted that, to improve the TLB hit rate, the computing unit, based on the level index and physical base address corresponding to the current page table level, does not simply read the single page table entry pointed to by the current level index when accessing memory. Instead, it reads a continuous block of data of a preset number of page table entries. That is, it not only reads the base page table entry necessary for this address translation, but also reads multiple adjacent page table entries surrounding the base page table entry. This preset number of page table entries can be matched with the memory's batch transfer granularity without increasing read latency.

[0043] After reading a contiguous block of data, the computation unit uses its built-in processing capabilities to perform validity checks on each adjacent page table entry within that block (e.g., checking the "valid bit" or "presence bit" in the page table entry). Following these validity checks, the computation unit combines all valid adjacent page table entries with the base page table entry as the target page table entry for the current page table level. These pre-read valid adjacent page table entries represent pre-loaded potential available page table resources, and their subsequent storage in the TLB can significantly improve the cache hit rate for subsequent address accesses.

[0044] In this embodiment of the invention, the page table entry validity screening is automatically completed by the memory-side computing unit, so that the MMU does not need to process a large amount of invalid or useless data, thereby reducing the amount of data backhaul, reducing the bus bandwidth occupation and the overhead of internal MMU screening.

[0045] See Figure 3 This is a schematic diagram of an embodiment of the system for accelerating the page table fetching of the memory management unit provided by the present invention.

[0046] A second aspect of the present invention provides a system for accelerating page table fetching by a memory management unit, the system comprising: a memory management unit 100 and a computing unit 200; wherein the computing unit 200 is located inside or outside a memory storing multi-level page tables; The memory management unit 100 is used to check whether the mapping link between the received virtual address and the physical address is complete in the translation back cache. If the mapping link is incomplete, it generates a page table retrieval command and sends it to the computing unit 200 through the bus. The computing unit 200 is used to execute the method for fetching the page table of the accelerated memory management unit as described in any of the embodiments of the first aspect above.

[0047] Furthermore, the memory management unit 100 is also used to write all target page table entries returned by the computing unit 200 into the translation back cache through the control unit corresponding to the translation back cache.

[0048] It should be noted that, as Figure 4 The diagram shown is a structural schematic of another embodiment of the system for accelerating the page table fetching of the memory management unit provided by the present invention. Figure 4 In the process, the MMU receives the virtual address sent by the processor through port 0. When a TLB hit occurs, the MMU directly synthesizes the physical address corresponding to the virtual address and transmits it to the bus for further processing through port 1. When a TLB miss occurs, the MMU generates a page table fetch command and sends it to the bus through port 2 to be transmitted to the memory-side computing unit 200. The memory-side computing unit 200 receives the page table fetch command transmitted via the bus through port 6, and after parsing, initiates a read operation to the memory through port 5 to obtain the target page table entry of the page table level to be accessed. The computing unit 200 packages all target page table entries and sends them back to the MMU through port 4. The MMU receives all target page table entries through port 3 and writes the received target page table entries into the TLB through the control unit corresponding to the TLB (denoted as TLB_ctrl).

[0049] In this embodiment of the invention, a computing unit 200 is set up inside or outside the memory. The page table reading task, which originally required the MMU to access the memory multiple times serially, is offloaded to the computing unit 200, which can effectively reduce the bus round-trip transmission time and improve the address translation efficiency.

[0050] In an optional embodiment, the memory management unit 100 includes: a command generation subunit; The command generation subunit is used to generate the page table retrieval command based on the physical base address of the first-level page table cached in the page table base address register and the physical base addresses of N cached page tables in the translation backing cache when the mapping link is incomplete; wherein, N≥0.

[0051] It should be noted that N represents the number of levels of the physical base address that the current virtual address has been cached in the TLB. For example, when N=0, it means that the TLB has not cached the physical base address of any level of page table corresponding to the current virtual address (only the page table base address register caches the physical base address of the first-level page table); when N=1, it means that the TLB has cached the physical base address of the second-level page table corresponding to the current virtual address (i.e., the first-level page table entry); when N=2, it means that the TLB has cached the physical base addresses of the second to third-level page tables corresponding to the current virtual address. The physical base address of the first-level page table is usually cached in the MMU's page table base address register, which is updated with process switching.

[0052] The command generation subunit determines the page table level to be accessed and the page table base address of the starting level in this access process based on all physical base addresses known to the current MMU (located in the page table base address register and TLB), and generates the page table retrieval command accordingly.

[0053] See Figure 5 This is a schematic diagram of one embodiment of the apparatus for fetching the page table of the accelerated memory management unit provided in this invention.

[0054] A third aspect of the present invention provides an apparatus for accelerating page table fetching by a memory management unit, applied to a computing unit 200; the computing unit 200 is located inside or outside a memory storing multi-level page tables; the apparatus includes: Command acquisition module 210 is used to receive page table acquisition command sent by memory management unit 100; wherein, the page table acquisition command includes: virtual address and page table access control information; the page table access control information is used to indicate the page table level that needs to be accessed in the memory this time, and the physical base address corresponding to the starting level in this access process; Page table reading module 220 is used to parse the page table acquisition command, obtain the physical base address corresponding to the starting level, and read the target page table entry corresponding to each page table level from the memory level by level according to the level index in the virtual address, so as to complete the mapping link between the virtual address and the physical address. The result return module 230 is used to uniformly return all read target page table entries to the memory management unit 100.

[0055] It should be noted that the apparatus for accelerating the page table fetching of the memory management unit provided in this embodiment of the invention can implement all the processing flows of the method for accelerating the page table fetching of the memory management unit described in any of the embodiments of the first aspect. The specific implementation schemes and technical effects of the apparatus for accelerating the page table fetching of the memory management unit correspond to the specific implementation schemes and technical effects of the method for accelerating the page table fetching of the memory management unit described in any of the embodiments of the first aspect, and will not be repeated here.

[0056] A fourth aspect of the present invention provides a computer-readable storage medium comprising a stored computer program; wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to perform the method for fetching page tables of an accelerated memory management unit as described in any of the first aspects of the present invention.

[0057] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, or it may be an electrical, mechanical, or other form of connection.

[0058] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected according to actual needs to achieve the technical effects of the solutions provided in the embodiments of this application.

[0059] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0060] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0061] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for accelerating page table fetching by a memory management unit, characterized in that, Applied to computing units; The computing unit is located inside or outside a memory that stores multi-level page tables; the method includes: The system receives a page table retrieval command sent by the memory management unit; wherein the page table retrieval command includes: a virtual address and page table access control information; the page table access control information is used to indicate the page table level that needs to be accessed in the memory this time, and the physical base address corresponding to the starting level during this access process; The page table retrieval command is parsed to obtain the physical base address corresponding to the starting level. Based on the level index in the virtual address, the target page table entry corresponding to each page table level is read from the memory level by level to complete the mapping link between the virtual address and the physical address. All read target page table entries are sent back to the memory management unit.

2. The method for accelerating page table fetching in a memory management unit as described in claim 1, characterized in that, The page table access control information includes: base address information and missing physical page frame number values ​​corresponding to each level of page table; each base address information is either the physical base address of the corresponding page table or a missing physical base address value.

3. The method for accelerating page table fetching in the memory management unit as described in claim 2, characterized in that, The step of parsing the page table retrieval command to obtain the physical base address corresponding to the starting level, and reading the target page table entry corresponding to each page table level from the memory according to the level index in the virtual address, includes: Based on the missing identifier value in the page table access control information, determine the physical base address corresponding to the page table level and the starting level; Starting from the physical base address corresponding to the starting level, and combining the corresponding level index, read operations are performed level by level in the memory to obtain the target page table entry corresponding to each page table level.

4. The method for accelerating page table fetching of the memory management unit as described in claim 1, characterized in that, The target page table entry is obtained through the following steps: Based on the level index and physical base address corresponding to the current page table level, read a preset number of consecutive data blocks from the current page table; wherein, the consecutive data blocks include: the base page table entry pointed to by the corresponding level index, and the adjacent page table entries of the base page table entry; Each adjacent page table entry is evaluated for validity, and all valid adjacent page table entries, along with the reference page table entry, are used as the target page table entry for the current page table level.

5. The method for accelerating page table fetching in a memory management unit as described in claim 1, characterized in that, The page table fetch command is generated when the memory management unit detects that the mapping link in the translation back cache is incomplete.

6. A system for accelerating page table fetching by a memory management unit, characterized in that, The system includes a memory management unit and a computing unit; wherein the computing unit is located inside or outside a memory storing multi-level page tables; The memory management unit is used to check whether the mapping link between the received virtual address and the physical address is complete in the translation back cache. If the mapping link is incomplete, it generates a page table retrieval command and sends it to the computing unit through the bus. The computing unit is used to execute the method of fetching the page table for the accelerated memory management unit as described in any one of claims 1 to 5.

7. The system for accelerating page table fetching of the memory management unit as described in claim 6, characterized in that, The memory management unit includes: a command generation subunit; The command generation subunit is used to generate the page table retrieval command based on the physical base address of the first-level page table cached in the page table base address register and the physical base addresses of N cached page tables in the translation backing cache when the mapping link is incomplete; wherein, N≥0.

8. The accelerated memory management unit page table fetch system as described in claim 6, characterized in that, The memory management unit is also used to write all target page table entries returned by the computing unit into the translation back cache through the control unit corresponding to the translation back cache.

9. An apparatus for accelerating page table fetching by a memory management unit, characterized in that, The device is applied to a computing unit; the computing unit is located inside or outside a memory storing multi-level page tables; the device includes: The command acquisition module is used to receive page table acquisition commands sent by the memory management unit; wherein, the page table acquisition command includes: virtual address and page table access control information; the page table access control information is used to indicate the page table level that needs to be accessed in the memory this time, and the physical base address corresponding to the starting level in this access process; The page table reading module is used to parse the page table acquisition command, obtain the physical base address corresponding to the starting level, and read the target page table entry corresponding to each page table level from the memory level by level according to the level index in the virtual address, so as to complete the mapping link between the virtual address and the physical address. The result return module is used to uniformly return all read target page table entries to the memory management unit.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored computer program; wherein, when the computer program is executed, it controls the device on which the computer-readable storage medium is located to perform the method of fetching the page table of the accelerated memory management unit as described in any one of claims 1 to 5.

Images