Processor access control method and system

Abstract

The present disclosure relates to the technical field of processor, in particular to a processor memory access control method and system, the method comprising: receiving a fetch read request from an instruction prefetch buffer unit and starting a preset number of merging waiting windows; within the merging waiting window, if a data read request from a data buffer unit is received and the addresses of the two requests are in the same aligned address block, a single serial burst read operation is initiated through a shared main memory channel to obtain complete data in the aligned address block; the complete data is provided to the instruction prefetch buffer unit, and corresponding data words are selected from the complete data according to the low bits of the address of the data read request and provided to the data buffer unit; and the arbitration count state is updated, which is equivalent to obtaining service authorization on both sides once. The technical scheme can combine two types of different read requests into the same serial burst, effectively improving the serial bandwidth utilization.

Description

Technical Field

[0001] This disclosure relates to the field of processor technology, specifically to a processor memory access control method and system. Background Technology

[0002] In embedded processor systems, with the rapid development of the Internet of Things, edge computing, and smart terminal devices, the requirements for system power consumption, cost, and reliability are increasing. Traditional embedded systems typically employ a dual-memory architecture, using on-chip static random access memory (SRAM) as the main operating memory and off-chip non-volatile memory (such as NOR Flash) as the program memory. While this architecture is mature, it requires copying the program from the non-volatile memory to the SRAM during startup, increasing startup time and system power consumption. Furthermore, running data is lost after power failure, failing to meet the needs of low-power persistent applications.

[0003] In recent years, the development of non-volatile memory technologies such as magnetoresistive random access memory (MRAM) has provided new approaches to solving the aforementioned problems. MRAM has advantages such as non-volatility, high-speed read and write, and unlimited erase and write cycles, making it possible to build processor systems with external serial non-volatile memory devices as unified main memory—that is, program code and runtime data coexist in the same external serial non-volatile memory device, and the program is executed in-situ on the unified main memory without needing to be copied to another type of main memory for execution.

[0004] However, this unified main memory architecture faces a series of new technical challenges. Due to the significant clock frequency and bit width differences between the processor core and the external serial non-volatile memory device, the original single-port bandwidth ratio can be hundreds of times. The shared main memory path becomes the performance bottleneck of the entire system. Simultaneously, three types of requests—instruction fetch requests from the processor core, data read / write requests, and recovery access requests during system power-down recovery—compete for the shared main memory path. How to coordinate different types of access requests on the single-port serial path to efficiently utilize the limited serial bandwidth is a core engineering problem that urgently needs to be solved. Summary of the Invention

[0005] To address the problems in the related technologies, this disclosure provides a processor memory access control method and system.

[0006] In a first aspect, this disclosure provides a processor memory access control method applied to a processor system using an external serial non-volatile memory as a unified main memory. The processor system includes a shared main memory path connected to the external serial non-volatile memory via a serial interface. The method includes: Receive fetch / read requests from the instruction prefetch buffer unit and open a merge wait window for a preset number of cycles; Within the merge waiting window, if a data read request is received from the data buffer unit, and the address targeted by the data read request and the fetch read request are located in the same aligned address block, then a single serial burst read operation is initiated to the external serial non-volatile memory through the shared main memory path to obtain the complete data in the aligned address block. The complete data is provided to the instruction prefetch buffer unit, and the corresponding data word is selected from the complete data according to the low address of the data read request and provided to the data buffer unit. In response to the single serial burst read operation, the count state used for arbitrating the fetch read request and the data read request is updated to be equivalent to both the fetch read request and the data read request receiving a service authorization once.

[0007] In one embodiment of this disclosure, the fetch read request is a row mode request initiated by the instruction prefetch buffer unit when neither the sequential prefetch queue nor the reserved entry array is hit. The row mode request is used to read a data line containing multiple consecutive instruction words from the external serial non-volatile memory.

[0008] In one embodiment of this disclosure, the data read request is a single-word request initiated by the data buffer unit within the write completion protection window when it is determined that the read request to be processed does not overlap with the bytes to be written in the incomplete write request.

[0009] In one embodiment of this disclosure, determining that the data read request and the instruction fetch read request meet the merging conditions within the merge waiting window further includes: The merge waiting window is enabled. The memory access type corresponding to the data read request is a read operation; The addresses of both the fetch request and the data read request are within the preset legal address range; Furthermore, neither the fetch request nor the data read request was shielded by their respective duplicate authorization protection signals.

[0010] In one embodiment of this disclosure, providing the complete data to the instruction prefetch buffer unit, and simultaneously selecting a corresponding data word from the complete data according to the low-order address of the data read request and providing it to the data buffer unit, includes: When the instruction read request and the data read request point to the same data word in the complete data, the data word is fanned out to both the instruction prefetch buffer unit and the data buffer unit. When they point to different data words, the instruction prefetch buffer unit obtains all the data words in the complete data, and the data buffer unit obtains the corresponding single data word based on the low-order bits of the address.

[0011] In one embodiment of this disclosure, if no data read request meeting the merging conditions is received within the merge waiting window, or if the merge waiting window times out, the process reverts to the normal arbitration mode, and initiates independent read operations serving the fetch read request and the data read request to the external serial non-volatile memory respectively, and requests the update of the count state only to the party that actually obtains authorization.

[0012] In one embodiment of this disclosure, the counting state includes a service count counter on the instruction side and a service count counter on the data side, which are maintained separately; the update, which is equivalent to both the fetch read request and the data read request receiving a service authorization once, includes: incrementing the service count counter on the instruction side and the service count counter on the data side by one count unit.

[0013] In one embodiment of this disclosure, the counting state includes maintaining a single service difference; the update, which is equivalent to both the fetch read request and the data read request receiving a service authorization once, includes keeping the single service difference unchanged.

[0014] In one embodiment of this disclosure, it further includes: The instruction prefetch buffer unit is equipped with a reserved entry array, which does not clear entries that have passed address verification when a branch refresh event occurs; When the cumulative number of repeated hits of the same entry address in the reserved entry array reaches a preset cyclic hit threshold, and the hit count of the corresponding entry reaches a preset stable threshold, the instruction prefetch buffer unit enters the cyclic yield mode. In the circular transfer mode, the instruction prefetch buffer unit suspends the submission of background prefetch requests to the shared main memory path, thereby transferring the right to occupy the shared main memory path to data read requests.

[0015] In one embodiment of this disclosure, it further includes: In the cyclical transfer mode, the number of consecutive finger fetch misses is monitored; When the number of consecutive missed fetches reaches a preset missed callback threshold, a progressive forced callback is executed. The progressive forced callback includes: first, opening a callback window of a preset length, and allowing a limited number of background prefetch requests within the callback window; if the number of consecutive missed fetches does not decrease within the callback window, then conditional hit count aging is performed on the old loop entry that triggered loop yielding to reduce its priority for triggering loop yielding again; if the number of consecutive missed fetches reaches the missed callback threshold again after the callback window ends, then the loop signature state is finally cleared and the loop yielding mode is exited.

[0016] In one embodiment of this disclosure, it further includes: The data buffer unit stores and updates the byte channel mask for incomplete write requests; Upon receiving a data read request, the read byte mask of the data read request is decoded, and the overlap between the read byte mask and the byte channel mask of the incomplete write request is determined. If it is determined that there is no overlap, the blocking of the data read request caused by data correlation is lifted in advance, and the data read request is sent to the main memory access arbitration unit as a normal read request. If it is determined to be overlapping and the byte channel mask of the incomplete write request completely covers the read byte mask, then the data buffer unit will combine the complete read data from the local write buffer and return it, without initiating an access to the external serial non-volatile memory. If the data is determined to be overlapping and the byte channel mask of the incomplete write request fails to completely cover the read byte mask, the data read request will continue to be blocked until the physical completion confirmation of the incomplete write request is returned.

[0017] In one embodiment of this disclosure, it further includes: When a silence signal is received from the associated recovery control unit, the main memory access arbitration unit suspends authorization for the fetch read request and the data read request, and freezes the update of the count state; In response to the silence signal, the instruction prefetch buffer unit freezes its internal entry hit count aging operation, continuous fetch miss count update, and cyclic transfer decision triggering. When the silence signal is removed, the counting state and the various counts and checks of the frozen instruction prefetch buffer unit continue to evolve from the values ​​at the time of freezing.

[0018] In one embodiment of this disclosure, the preset number of frames for the merge waiting window, the granularity of the aligned address block, and the data width read in a single serial burst read operation are all configurable system parameters.

[0019] Secondly, this disclosure provides a processor memory access control system applied to a processor system using an external serial non-volatile memory as the unified main memory, the system comprising: The processor core is configured to execute program instructions and issue instruction fetch requests and data access requests. The instruction prefetch buffer unit is configured to initiate an instruction fetch read request to the main memory access arbitration unit in response to the instruction fetch request when the instruction is not found in the local storage structure. The data buffer unit is configured to initiate a data read request to the main memory access arbitration unit in response to a data read request from the processor core. The main memory access arbitration unit is configured to receive the fetch read request and open a merge wait window with a preset number of clock cycles. Within the merge wait window, if a data read request is received, and the addresses targeted by the data read request and the fetch read request are located within the same aligned address block, a single serial burst read operation is initiated to the serial non-volatile memory control unit via the shared main memory path to obtain the complete data within the aligned address block. The complete data is provided to the instruction prefetch buffer unit, and simultaneously, a corresponding data word is selected from the complete data based on the low-order address of the data read request and provided to the data buffer unit. Furthermore, in response to the single serial burst read operation, an update is performed on the count state used for arbitrating the fetch read request and the data read request, equivalent to both the fetch read request and the data read request receiving a service authorization.

[0020] Thirdly, embodiments of this disclosure provide an electronic device including a memory and a processor, wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method as described in any of the first aspects.

[0021] Fourthly, this disclosure provides a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the method as described in any of the first aspects.

[0022] The technical effects provided by the embodiments of this disclosure may include the following beneficial effects: The processor memory access control method and system provided in this disclosure perform a single serial burst merging of instruction-side line-mode fetch read requests and data-side single-word read requests that hit the same aligned address block. Each successful merge saves approximately one serial transaction's fixed overhead (the time required for command, address, and chip select transmission), effectively reducing redundant command, address, and chip select transmissions. Since the fixed overhead of the serial interface is much greater than the incremental overhead of word-by-word data transmission, this merging mechanism significantly improves serial bandwidth utilization under extreme bandwidth ratio conditions. Simultaneously, the merge grant effectively presents a result where both sides receive service, ensuring that the merge grant does not disrupt service fairness between the instruction and data sides. This avoids the problem of continuous merging causing a monotonically accumulating service difference on one side, triggering forced bias, and in turn interrupting subsequent merges.

[0023] The processor memory access control method and system provided in this disclosure, through the setting of a reserved entry array in the instruction prefetch buffer unit, ensures that entries that have passed address verification are not cleared when a branch refresh event occurs. This allows loop body instruction fetching to repeatedly hit locally across branch refreshes, enabling the accumulation and identification of loop signatures. When the loop signature identification is successful, the instruction prefetch buffer unit actively suspends background prefetch request submissions, prioritizing the data-side request with the only shared main memory path, effectively reducing the waiting time for data access within the loop body. This concession is bottom-up and complete, unlike the top-down service quality quota schemes or client-internal address range control schemes in the prior art.

[0024] The processor memory access control method and system provided in this disclosure have a saturation adjustment mechanism that releases the transfer through a progressive three-stage callback when there are consecutive instruction fetch misses. This includes limited release through the callback window, conditional aging of old loop entries, and clearing of loop signatures. This avoids loop misjudgment or transfer jitter near the loop boundary and effectively prevents long-term starvation on the instruction side.

[0025] The processor memory access control method and system provided in this disclosure, including the byte channel mask-driven write-complete protection early release method, allow read requests that do not overlap with the bytes to be written to be unblocked early, and read requests whose read bytes are completely covered by the write bytes to be written are directly combined and returned locally via the write-before-read path, without waiting for the entire request-level write-complete window to end. This mechanism refines the granularity of write-complete protection from the request level to the byte level, and does not introduce physical read-write concurrency throughout the process, effectively reclaiming the available bandwidth within the write-complete waiting window.

[0026] The processor memory access control method and system provided in this disclosure, in conjunction with the silent signal of the associated recovery control unit, freezes runtime count states such as anti-starvation count, reserved entry hit count, instruction fetch miss count, and merge window detection during the recovery period. After recovery, the counts continue to evolve from the frozen point, avoiding secondary starvation and circular signature errors caused by sudden changes in client service counts after recovery.

[0027] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0028] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. The following is a description of the accompanying drawings.

[0029] Figure 1 A schematic diagram of the structure of a processor system according to an embodiment of the present disclosure is shown.

[0030] Figure 2 A flowchart illustrating a processor memory access control method according to an embodiment of the present disclosure is shown.

[0031] Figure 3 A memory access control timing diagram of a processor memory access control method according to an embodiment of the present disclosure is shown.

[0032] Figure 4 A schematic diagram illustrating the conceptual state transition of a cyclic transfer step according to an embodiment of the present disclosure is shown.

[0033] Figure 5 A structural block diagram of an instruction prefetch buffer unit according to an embodiment of the present disclosure is shown.

[0034] Figure 6 A structural block diagram of a data buffer unit according to an embodiment of the present disclosure is shown.

[0035] Figure 7 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0036] Figure 8 A schematic diagram of the structure of a computer system suitable for implementing the method according to embodiments of the present disclosure is shown. Detailed Implementation

[0037] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings to enable those skilled in the art to readily implement them. Furthermore, for clarity, portions unrelated to the description of exemplary embodiments have been omitted from the drawings.

[0038] In this disclosure, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of features, figures, steps, behaviors, components, parts or combinations thereof disclosed in this specification, and are not intended to exclude the possibility of the presence or addition of one or more other features, figures, steps, behaviors, components, parts or combinations thereof.

[0039] It should also be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0040] Figure 1 A schematic diagram of the structure of a processor system according to an embodiment of the present disclosure is shown.

[0041] like Figure 1 As shown, the processor system includes a processor core 100, an instruction prefetch buffer unit 101, a data buffer unit 102, a main memory access arbitration unit 103, a serial non-volatile memory control unit 104, a boot execution unit 105, an external serial non-volatile memory device 106, and a recovery control unit 107. The processor core 100 is connected to the instruction prefetch buffer unit 101 via an instruction-side interface and to the data buffer unit 102 via a data-side interface. The instruction prefetch buffer unit 101 and the data buffer unit 102 are both connected downwards to the main memory access arbitration unit 103. The main memory access arbitration unit 103 is connected to the serial non-volatile memory control unit 104 via a shared main memory path. The serial non-volatile memory control unit 104 is connected to the external serial non-volatile memory device 106 via a serial interface. The external serial non-volatile memory device 106 serves as a unified main memory, storing both program code and runtime data. The boot execution unit 105 is connected to the main memory access arbitration unit 103 and is used to complete the boot process in configuration mode after power-on and jump to the program entry point in the unified main memory. If the system is configured with associated power-off recovery function, the recovery control unit 107 is connected to the main memory access arbitration unit 103 and the instruction prefetch buffer unit 101 via a silence signal. In this disclosure, the processor core 100 accesses instructions and data in the external serial non-volatile memory device 106 through the instruction prefetch buffer unit 101 and the data buffer unit 102, respectively. The main memory access arbitration unit 103 arbitrates the instruction fetch read request and the data read request to determine the right to occupy the shared main memory path.

[0042] Figure 2 A flowchart illustrating a processor memory access control method according to an embodiment of the present disclosure is shown.

[0043] like Figure 2 As shown, the processor memory access control method includes the following steps S201-S204.

[0044] In step S201, a fetch request is received from the instruction prefetch buffer unit, and a merging wait window with a preset number of ticks is opened.

[0045] In this embodiment, the processor core issues an instruction fetch request, which includes the instruction fetch address. The instruction fetch request is sent to the instruction prefetch buffer unit via the processor core's instruction-side interface. In response to the instruction fetch request, the instruction prefetch buffer unit first queries its internal local memory structure, including a sequential prefetch queue and a reserved entry array. If the instruction fetch address is matched in either the sequential prefetch queue or the reserved entry array, the instruction prefetch buffer unit directly reads the corresponding instruction word from its local memory structure and returns it to the processor core, without occupying the shared main memory path, thereby avoiding contention for serial bandwidth with data-side requests.

[0046] If the fetch address is not found in either the sequential prefetch queue or the reserved entry array, the instruction prefetch buffer unit initiates a fetch read request to the main memory access arbitration unit. This fetch read request is a row-mode request, containing a request address and a row-mode indication signal. The row-mode indication signal informs the main memory access arbitration unit that the requested data volume is a data row, i.e., an aligned data block containing multiple consecutive instruction words. In one embodiment, the size of this data row is 8 bytes (i.e., two consecutive 32-bit instruction words), and its address is aligned to an 8-byte boundary.

[0047] Upon receiving a fetch request, the main memory access arbitration unit does not immediately authorize the transmission but instead opens a merge wait window with a preset number of clock cycles. The width of the merge wait window is determined by configurable system parameters. In one embodiment, the width of the merge wait window is two clock cycles. Simultaneously with the window opening, the main memory access arbitration unit captures the row base address of the fetch request for subsequent merge determination.

[0048] In step S202, if a data read request is received from the data buffer unit within the merge waiting window, and the address targeted by the data read request and the fetch read request are located in the same aligned address block, then a single serial burst read operation is initiated to the external serial non-volatile memory through the shared main memory path to obtain the complete data in the aligned address block.

[0049] In this embodiment, during the merge wait window, the main memory access arbitration unit monitors data-side requests from the data buffer unit. In response to a data read request (e.g., a load instruction) from the processor core, the data buffer unit initiates a data read request to the main memory access arbitration unit. This data read request is a single-word request, used to read one data word from the external serial non-volatile memory device, the size of which corresponds to the data path width of the processor core. In one embodiment, it is 4 bytes (32 bits).

[0050] After receiving the data read request within the merge waiting window, the main memory access arbitration unit performs a merge admission determination. The merge admission determination includes comparing whether the address of the data read request and the address of the fetch read request are located within the same aligned address block. The size of the aligned address block corresponds to the row-mode read width of the fetch read request. In one embodiment, the aligned address block is an 8-byte aligned address block, and the main memory access arbitration unit compares whether the high-order bits (e.g., address bits [31:3]) of the address of the fetch read request are consistent with the high-order bits (e.g., address bits [31:3]) of the address of the data read request. If they are consistent, it is determined that the two requests hit the same aligned address block.

[0051] Furthermore, determining that the data read request and the instruction fetch read request meet the merging conditions within the merge waiting window also includes: first, the merge waiting window is currently enabled, meaning the arbitration status register is in a waiting-to-merge state and the window has not yet timed out; second, the memory access type corresponding to the data read request is a read operation, and data write operations do not participate in the merging because read operations and write operations cannot share the same read burst; third, the addresses of both the instruction fetch read request and the data read request are within a preset legal address range, which corresponds to the addressable memory space of the external serial non-volatile memory device; fourth, neither the instruction fetch read request nor the data read request is shielded by their respective duplicate grant protection signals, which are used to prevent the same request from being granted repeatedly.

[0052] When all the above-mentioned merge admission conditions are met, the main memory access arbitration unit determines that the two requests can be merged and enters the merge authorization path. Under the merge authorization path, the main memory access arbitration unit initiates a single serial burst read operation to the serial non-volatile memory control unit through the shared main memory path. The read width of this single serial burst read operation is the size of the aligned address block. In one embodiment, it is 8 bytes, that is, two consecutive 32-bit data words are read. The serial non-volatile memory control unit converts the single serial burst read operation into a serial command sequence conforming to the serial interface protocol, including chip select signal pull-low, command byte transmission, address byte transmission, virtual wait period, and continuous data bit transmission, and sends it to the external serial non-volatile memory device.

[0053] It should be noted that if no data read request meeting the merging conditions is received within the merge waiting window, or if the merge waiting window times out, the main memory access arbitration unit reverts to the normal arbitration mode. In normal arbitration mode, the main memory access arbitration unit initiates independent read operations serving the fetch read request and independent read operations serving the data read request (if the data read request exists and is waiting) to the serial non-volatile memory control unit, respectively. That is, each request independently occupies the shared main memory path, and each pays the fixed overhead of a complete serial transaction. For the fetch read request, the independent read operation is still a row-mode read (8 bytes); for the data read request, the independent read operation is a single-word read (4 bytes).

[0054] In step S203, the complete data is provided to the instruction prefetch buffer unit, and at the same time, the corresponding data word is selected from the complete data according to the low address of the data read request and provided to the data buffer unit.

[0055] In this embodiment, the external serial non-volatile memory device, in response to the serial burst read operation, serially shifts out the complete data bit by bit from the aligned address block. The serial non-volatile memory control unit receives the serial input bit stream, converts it to parallel, and obtains the complete data. In one embodiment, the complete data is 8 bytes of row data. The serial non-volatile memory control unit returns the complete data along with a completion acknowledgment signal to the main memory access arbitration unit.

[0056] After receiving the complete data, the main memory access arbitration unit distributes the complete data simultaneously to the instruction prefetch buffer unit and the data buffer unit via its internal return data splitting logic. The specific splitting method is as follows: For the instruction prefetch buffer unit, the main memory access arbitration unit provides the complete data, i.e., all 8-byte lines of data, to the instruction prefetch buffer unit. After receiving the complete data, the instruction prefetch buffer unit performs the following processing: returns the instruction word corresponding to the current fetch address in the complete data to the processor core; registers all instruction words in the complete data (including the current instruction word and adjacent instruction words) into the reserved entry array and the sequential prefetch queue for local hits by subsequent fetch requests.

[0057] For the data buffer unit, the main memory access arbitration unit selects the corresponding data word from the complete data according to the low address bits of the data read request. In one embodiment, the data read request is a 4-byte single-word request, and the complete data is 8-byte row data (including two 32-bit data words, word 0 and word 1). The main memory access arbitration unit selects according to the address bits [2] of the data read request: if the address bit [2] is 0, word 0 is selected and provided to the data buffer unit; if the address bit [2] is 1, word 1 is selected and provided to the data buffer unit.

[0058] Specifically, when the fetch request and the data read request point to the same data word in the complete data, for example, when the address of the fetch request and the address of the data read request fall within the same 4-byte word, i.e., their address bits [2] are the same, then the data word is fanned out to both the instruction prefetch buffer unit and the data buffer unit. When pointing to different data words (e.g., the fetch request points to word 0, the data read request points to word 1, or vice versa), the instruction prefetch buffer unit obtains all the data words in the complete data, while the data buffer unit only obtains a single data word selected according to its low address bits.

[0059] This mechanism of sorting data to two different consumers based on the least significant byte of the address differs from existing client burst merging schemes. Existing burst merging schemes merge data from similar clients, such as requests from multiple parallel threads on the same master device. The merged data is routed within the same consumer and does not require sorting based on the least significant byte of the address. However, this disclosure merges data from two types of clients with different semantics and burst lengths (instruction-side line-mode requests and data-side single-word requests). The merged data must be sorted based on the least significant byte of the address and distributed to two different consumers.

[0060] In step S204, in response to the single serial burst read operation, an update is performed on the count state used to arbitrate the fetch read request and the data read request, which is equivalent to both the fetch read request and the data read request receiving a service authorization once.

[0061] In this embodiment, the main memory access arbitration unit maintains a count state for arbitrating instruction fetch and data read requests. This count state tracks the number of authorized services each instruction-side and data-side request receives, preventing a particular request from being denied authorization for an extended period, thus preventing starvation.

[0062] When a merge authorization is completed, the aforementioned single serial burst read operation is successfully completed. The main memory access arbitration unit must ensure that the count state is equivalent to "the instruction side and the data side each obtaining one service authorization". This operation is necessary because of the correctness constraint of the anti-starvation mechanism: if a merge authorization is only regarded as a one-sided request for service, multiple consecutive merges will cause the service difference on the other side to monotonically accumulate, quickly exceeding the anti-starvation threshold and triggering forced bias, which in turn blocks the subsequent merge and reduces the bandwidth benefits of shared bursts.

[0063] In one embodiment, the counting status includes separately maintained instruction-side service count counters and data-side service count counters. After the single serial burst read operation is completed, the main memory access arbitration unit increments both the instruction-side and data-side service count counters by one unit. That is, merging an authorization counts one service on each side, equivalent to each side receiving an independent serial transaction service. In this implementation, if a subsequent merge authorization is completed, both counters increment by another unit, ensuring synchronized growth of service counts on both sides, and the service difference remains unchanged due to the merge authorization.

[0064] In another embodiment, the counting state includes maintaining a single service difference register, which stores the difference between the number of services provided by the data side and the number of services provided by the instruction side. The main memory access arbitration unit maintains this single service difference unchanged after the single serial burst read operation is completed. That is, merging the grant does not change the service difference, which is equivalent to merging the grant so that both sides receive one service. This implementation has the advantage of lower hardware overhead. In one embodiment, the service difference is a signed integer, saturated between plus and minus 7. When the difference is positive and exceeds a positive threshold (e.g., +3), it indicates that the data side receives significantly more services than the instruction side, and the main memory access arbitration unit will force a bias towards the instruction side, i.e., prioritize granting the instruction side's request; conversely, when the difference is negative and below a negative threshold (e.g., -3), it indicates that the instruction side receives significantly more services than the data side, and the main memory access arbitration unit will force a bias towards the data side.

[0065] It should be noted that, regardless of the implementation method used, the update rules for the count status in merged authorization differ from those in ordinary authorization. In ordinary arbitration mode, where a single independent read request is authorized, the main memory access arbitration unit only requests an update to the count status from the party actually authorized: if it's an independent instruction-side authorization, only the instruction-side service count counter is incremented or the single service difference is adjusted by one unit towards the data-side skew; if it's an independent data-side authorization, only the data-side service count counter is incremented or the single service difference is adjusted by one unit towards the instruction-side skew. However, under merged authorization, both sides are considered to have received service, and the count status update is equivalent to each side counting once, thus ensuring that merged authorization does not disrupt service fairness between the instruction and data sides.

[0066] The above solution effectively reduces redundant command, address, and chip select overhead by merging heterogeneous requests, specifically combining instruction-side line reads and data-side single-word reads into a single serial burst operation. Due to the fixed overhead of serial bursts ( It is far greater than the incremental overhead of adding one more data word. Each successful merge can save approximately one In systems with extreme bandwidth ratios (such as a processor core frequency of 100MHz and a serial interface of 10MHz), it can significantly reduce the occupancy time of the shared main memory path and improve the effective bandwidth utilization.

[0067] The processor memory access control method and system provided in this disclosure perform a single serial burst merging of instruction-side line-mode fetch read requests and data-side single-word read requests that hit the same aligned address block. Each successful merge saves approximately one serial transaction's fixed overhead (the time required for command, address, and chip select transmission), effectively reducing redundant command, address, and chip select transmissions. Since the fixed overhead of the serial interface is much greater than the incremental overhead of word-by-word data transmission, this merging mechanism significantly improves serial bandwidth utilization under extreme bandwidth ratio conditions. Simultaneously, the merge grant effectively presents a result where both sides receive service, ensuring that the merge grant does not disrupt service fairness between the instruction and data sides. This avoids the problem of continuous merging causing a monotonically accumulating service difference on one side, triggering forced bias, and in turn interrupting subsequent merges.

[0068] According to an embodiment of this disclosure, the fetch read request is a line mode request initiated by the instruction prefetch buffer unit when neither the local sequential prefetch queue nor the reserved entry array is hit.

[0069] Specifically, the instruction prefetch buffer maintains a sequential prefetch queue to cache consecutive instruction words prefetched from external memory; it also maintains a reserved entry array to store instruction words that have been verified during previous fetch operations. When the processor core issues a fetch request, the instruction prefetch buffer searches these two structures in parallel, or searches the sequential prefetch queue first and then the reserved entry array: if the fetch address matches either queue, the corresponding instruction word is returned directly without initiating an access to external memory; only when neither queue is matched is it considered a fetch miss, and a row-mode request is constructed to fully utilize the efficiency of serial bursts.

[0070] According to an embodiment of this disclosure, the data read request is a single-word request initiated by the data buffer unit within the write completion protection window when it is determined that the read request to be processed does not overlap with the bytes to be written in the incomplete write request.

[0071] Specifically, the data buffer unit has an internal write buffer used to record the address, data, and byte enable (write mask) of the most recent incomplete write operation. When the write operation has been sent to the serial control unit through the main memory access arbitration unit but has not yet received physical completion confirmation (i.e., it is within the write completion protection window), if a new load instruction arrives, the data buffer unit first decodes the loaded byte enable (generating a read byte mask based on the memory access width and the low-order address bits), and then performs a bitwise AND operation between the read byte mask and the write mask recorded in the write buffer. If the result is 0 (i.e., the two bytes do not overlap), it is determined that the new read request has no data dependency on the in-transit write operation. The data buffer unit immediately releases the blocking state of the new read request and sends it to the main memory access arbitration unit as a normal single-word read request to participate in subsequent arbitration and possible merging processes. This early release does not affect the physical seriality of the shared main memory path, but only eliminates the additional waiting caused by data dependencies, thus enabling timely processing of non-conflicting read requests within the write protection window and reducing processor pauses.

[0072] According to embodiments of this disclosure, the method further includes a cyclic transfer step: The instruction prefetch buffer unit is equipped with a reserved entry array, which does not clear entries that have passed address verification when a branch refresh event occurs; When the cumulative number of repeated hits of the same entry address in the reserved entry array reaches a preset cyclic hit threshold, and the hit count of the corresponding entry reaches a preset stable threshold, the instruction prefetch buffer unit enters the cyclic yield mode. In the circular transfer mode, the instruction prefetch buffer unit suspends the submission of background prefetch requests to the shared main memory path, thereby transferring the right to occupy the shared main memory path to data read requests.

[0073] The circular transfer step provided in this embodiment is based on the same shared main memory path shared by the aforementioned heterogeneous request merging methods, further optimizing the occupancy of the shared main memory path for mixed loads with intensive circular requests and accompanying data access. Its core lies in the fact that the instruction prefetch buffer unit identifies the existence of circular signatures through a reserved entry array, and after confirming that the circular body has been completely overwritten locally, actively suspends the submission of background prefetch requests to the shared main memory path, completely transferring the occupancy of the shared main memory path to data-side requests.

[0074] In this embodiment, the instruction prefetch buffer unit is provided with a sequential prefetch queue and a reserved entry array. The sequential prefetch queue is used to cache adjacent instruction words prefetched from the external serial non-volatile memory device in the order of instruction fetching. In one embodiment, the sequential prefetch queue is a first-in-first-out queue with a depth of 8. The reserved entry array is used to retain instruction words that have passed address verification. Its essential difference from the general instruction cache (I-Cache) is that the reserved entry array does not clear entries that have passed address verification when a branch refresh event occurs, while the general instruction cache clears the affected cache lines when branch prediction fails or a branch refresh occurs. The reserved entry array is only completely cleared when the reset signal or the restore refresh signal is valid. This characteristic allows the loop body to repeatedly hit the same batch of verified entries in the reserved entry array during execution, especially when the loop body branch repeatedly jumps back to the entry point. This continuous hit across branch refreshes is the signal source for loop signature recognition.

[0075] In one embodiment, the reserved entry array is a direct mapping array containing 16 entries. Each entry is indexed by the low-order bits of the word address (e.g., address bits [5:2]), reserving a 32-bit instruction word and its corresponding complete word address to avoid direct mapping alias conflicts. Therefore, the reserved entry array covers a maximum of 64 bytes of instruction area, corresponding to approximately 16 32-bit instructions. When the instruction in the loop body does not exceed this capacity, loop yielding can be triggered; if the loop body exceeds this capacity, loop yielding is not triggered, the system reverts to normal prefetching, correctness is not affected, only the yielding benefit is not obtained. It should be noted that the number of entries and the number of words per entry are scalable implementation parameters, which can be extended to 32 or 64 entries in other embodiments, and each entry can also reserve multiple instruction words; this disclosure does not limit this.

[0076] Each reserved entry is accompanied by a hit count register. In one embodiment, the hit count register is a 2-bit counter with a saturation value of 3. The hit count increments as the corresponding reserved entry is fetched, until it reaches the saturation value. All non-zero hit counts are aged down every fixed period, in one embodiment every 8 clock cycles, i.e., each non-zero hit count is decremented by one. The aging operation prevents long-unaccessed entries from continuously affecting circular signature detection with excessively high hit counts.

[0077] The instruction prefetch buffer also maintains a circular entry address register and a circular hit counter. The circular entry address register records the entry address of the most recently repeatedly hit reserved entries. The circular hit counter is used to accumulate the number of times the same entry address is repeatedly hit; in one embodiment, it is a saturation counter with a threshold K=4.

[0078] The instruction prefetch buffer unit's processing flow in response to an instruction fetch request is as follows: The processor core issues an instruction fetch request, which includes an instruction fetch address and an instruction fetch valid indication signal. The instruction prefetch buffer unit simultaneously queries the sequential prefetch queue and the reserved entry array using the instruction fetch address. If a hit is found in the sequential prefetch queue (i.e., the instruction fetch address matches the address of an entry in the sequential prefetch queue), the instruction prefetch buffer unit reads the corresponding instruction word from the sequential prefetch queue and returns it to the processor core, marking the entry as consumed. If a hit is found in the reserved entry array (i.e., the reserved entry indexed by the instruction fetch address is valid and the address matches), the instruction prefetch buffer unit reads the corresponding instruction word from the reserved entry array and returns it to the processor core, incrementing the hit count of that entry.

[0079] If the fetch address is not found in either the sequential prefetch queue or the reserved entry array, the instruction prefetch buffer unit initiates a fetch read request to the main memory access arbitration unit, i.e., the row mode request in step S201 above, to read the complete data row containing the fetch address from the external serial non-volatile memory device.

[0080] The instruction prefetch buffer unit employs a lazy prefetch strategy. After a system reset, the instruction prefetch buffer unit is inactive and does not initiate any background prefetch requests. Only after receiving the first valid instruction fetch request (i.e., when the processor core begins actual program execution) does the instruction prefetch buffer unit set its active flag to valid, initiating subsequent background prefetches. Thereafter, during idle periods when the processor core does not actively fetch instructions, the instruction prefetch buffer unit initiates background prefetch requests to the main memory access arbitration unit in line-mode requests, supplementing adjacent instruction lines into the sequential prefetch queue. This lazy activation strategy avoids unnecessary prefetch access immediately after a reset, reducing unnecessary occupation of the shared main memory path.

[0081] When the cumulative number of repeated hits at the same entry address in the reserved entry array reaches a preset cyclic hit threshold, and the hit count of the corresponding entry reaches a preset stable threshold, the instruction prefetch buffer unit enters the cyclic yield mode.

[0082] Specifically, in one embodiment, the circular signature detection logic of the instruction prefetch buffer unit continuously monitors the hit behavior of each entry in the reserved entry array. When an entry is hit repeatedly, the circular entry address register records the entry address of the entry, and the circular hit counter accumulates the number of repeated hits at that entry address. When the circular hit counter reaches a threshold K (K=4 in one embodiment), it indicates that the same entry address has been hit repeatedly multiple times. At this time, the detection logic further checks whether the hit count corresponding to the entry has reached the entry threshold (in one embodiment, the hit count ≥ 2). If the hit count also meets the condition, the circular signature is confirmed to be valid—that is, the loop body instruction fetch has been locally overwritten by the reserved entry array, and the loop body no longer relies on fetching instructions from the external serial non-volatile memory device during operation. At this time, the instruction prefetch buffer unit sets the circular yield flag to valid and enters the circular yield mode.

[0083] In the circular yielding mode, the instruction prefetch buffer unit suspends the submission of background prefetch requests to the shared main memory path. Specifically, the enable condition for the instruction prefetch buffer unit to submit a new request to the main memory access arbitration unit includes the inverse condition of the circular yielding flag. When the circular yielding flag is valid, even if there are free entries in the sequential prefetch queue, the instruction prefetch buffer unit will no longer initiate new background prefetch requests. Therefore, the shared main memory path is no longer occupied by instruction-side background prefetch requests within this window and can be preferentially occupied by data-side requests. This yielding direction is bottom-up, initiated proactively by the instruction prefetch buffer unit itself after identifying the circularity, rather than being issued from top to bottom by external policies; the yielding method is to completely suspend request submission, that is, to completely relinquish the shared main memory path, rather than through weight adjustment or quota reduction.

[0084] In the circular passover mode, the processor core's instruction fetch request is still served locally by the reserved entry array. Since the loop body has been confirmed to be locally overwritten, the processor core's instruction fetch request is hit in the reserved entry array and returns the instruction word, without occupying the shared main memory path.

[0085] According to embodiments of this disclosure, the method further includes a saturation adjustment mechanism: In the cyclical transfer mode, the number of consecutive finger fetch misses is monitored; When the number of consecutive missed fetches reaches a preset missed callback threshold, a progressive forced callback is executed. The progressive forced callback includes: first, opening a callback window of a preset length, and allowing a limited number of background prefetch requests within the callback window; if the number of consecutive missed fetches does not decrease within the callback window, then conditional hit count aging is performed on the old loop entry that triggered loop yielding to reduce its priority for triggering loop yielding again; if the number of consecutive missed fetches reaches the missed callback threshold again after the callback window ends, then the loop signature state is finally cleared and the loop yielding mode is exited.

[0086] To prevent long-term starvation on the instruction side due to loop misjudgment or accidental exit of the loop body, the loop handover method also includes a saturation adjustment mechanism.

[0087] Specifically, in the circular delivery mode, the instruction prefetch buffer unit maintains a consecutive fetch miss counter. Each time an instruction fetch request misses both the sequential prefetch queue and the reserved entry array, the consecutive fetch miss counter is incremented. When the number of consecutive fetch misses reaches a preset miss callback threshold, the instruction prefetch buffer unit performs a progressive forced callback. In one embodiment, the miss callback threshold N=4.

[0088] The progressive forced callback includes three progressive phases: In the first stage, the instruction prefetch buffer unit clears the loop yielding flag, opens a callback window of a preset length, and allows a limited number of background prefetch requests within the callback window. In one embodiment, the length of the callback window is 16 frames, and the budgeted number of background prefetch requests allowed within the callback window is 2. That is, during the callback window, the instruction prefetch buffer unit allows a maximum of 2 background prefetch requests to be submitted to the main memory access arbitration unit, and continuously observes whether the fetch miss falls back. If the fetch request can hit the sequential prefetch queue or the reserved entry array within the callback window, the consecutive fetch miss counter is cleared, indicating that the loop is still within the local coverage range, and the loop yielding mode can be re-entered.

[0089] In the second stage, if the number of consecutive instruction fetch misses does not decrease within the callback window, i.e., the instruction fetch request continues to miss, the instruction prefetch buffer unit performs a conditional aging operation on the old loop entry that triggers loop yielding: the hit count corresponding to the entry is decremented by one (stopping after reaching a preset minimum value), thereby reducing its priority for triggering loop yielding again. This operation avoids old loop signatures from remaining with a high hit count after the loop has exited, thus frequently triggering yielding and reducing the risk of the system repeatedly and jerkily switching yielding on and off near the loop boundary.

[0090] In the third stage, if the number of consecutive instruction fetch misses reaches the miss callback threshold again after the callback window ends, the instruction prefetch buffer unit determines that the loop hypothesis has been permanently invalidated, clears the loop entry address register and the loop hit counter, exits the loop yield mode, and returns to the normal prefetch mode to re-detect the loop signature.

[0091] The four conceptual states of the above-mentioned cyclical transfer steps are as follows: Figure 4 As shown. Under normal conditions, the instruction prefetch buffer unit operates according to the normal prefetch strategy. When the loop hit counter starts accumulating and the loop entry address register is recorded, the instruction prefetch buffer unit enters the loop detection state. When the loop hit counter reaches threshold K and the hit count of the corresponding entry reaches the entry threshold, the instruction prefetch buffer unit enters the loop yielding state, and the loop yielding flag is set to valid. In the loop yielding state, if the number of consecutive instruction fetch misses reaches the miss callback threshold N, the instruction prefetch buffer unit enters the forced callback state. In the forced callback state, the instruction prefetch buffer unit first performs a limited release of the callback window, and then performs conditional aging or clears the loop signature as needed, finally returning to the normal state. It should be noted that the above four states are expressed by a combination of flags and count values ​​such as the loop yielding flag, callback window counter, loop hit counter, and consecutive instruction fetch miss counter, and do not require a separate four-state register.

[0092] According to embodiments of this disclosure, the method further includes write-after-read-before delivery and write-complete protection steps: The data buffer unit stores and updates the byte channel mask for incomplete write requests; Upon receiving a data read request, the read byte mask of the data read request is decoded, and the overlap between the read byte mask and the byte channel mask of the incomplete write request is determined. If it is determined that there is no overlap, the blocking of the data read request caused by data correlation is lifted in advance, and the data read request is sent to the main memory access arbitration unit as a normal read request. If it is determined to be overlapping and the byte channel mask of the incomplete write request completely covers the read byte mask, then the data buffer unit will combine the complete read data from the local write buffer and return it, without initiating an access to the external serial non-volatile memory. If the data is determined to be overlapping and the byte channel mask of the incomplete write request fails to completely cover the read byte mask, the data read request will continue to be blocked until the physical completion confirmation of the incomplete write request is returned.

[0093] The write-after-read-before delivery and write-complete protection early release method provided in this disclosure addresses the read blocking problem caused by data write operations. Under the constraint of a single-port shared main memory path that physically does not support concurrent read and write operations, a write-complete protection window exists from the time a write operation is initiated until the write-complete confirmation is returned. Within this window, conventional methods block all subsequent read operations. However, this disclosure refines the blocking granularity from the request level to the byte level through a byte channel mask, allowing read requests that do not overlap with the bytes to be written and read requests that can be fully delivered to the front of the read window to not wait for the entire write-complete window to end.

[0094] In this embodiment, the data buffer unit includes a write buffer and byte mask comparison logic. The write buffer is used to store the address, data, and byte channel mask of the most recent incomplete write request. When the processor core issues a store instruction, the address, write data, and byte enable signal of the store instruction are sent to the data buffer unit via the data-side interface of the processor core. The data buffer unit registers the information of the store instruction in the write buffer, recording it as the address, data, and byte channel mask of the incomplete write request. Each bit of the byte channel mask corresponds to a byte channel, indicating whether the byte needs to be written. In one embodiment, the byte channel mask is 4 bits, each corresponding to one of the 4 bytes of a 32-bit data word. For example, the byte channel mask "1111" indicates that all 4 bytes need to be written, and the byte channel mask "0011" indicates that the lower two bytes need to be written, and the higher two bytes do not need to be written.

[0095] After registering the incomplete write request, the data buffer unit immediately initiates a write transaction request to the main memory access arbitration unit. The main memory access arbitration unit sends the write transaction request to the serial non-volatile memory control unit via the shared main memory path. The serial non-volatile memory control unit converts the write transaction into a serial command sequence and sends it to the external serial non-volatile memory device. The processor core can retire the memory instruction before the physical write of the write transaction is completed.

[0096] Before the physical completion confirmation of the incomplete write request is returned, the write buffer holds the address, data, and byte channel mask of the incomplete write request. This period corresponds to the write completion protection window. Within the write completion protection window, if the processor core issues a load instruction, the data buffer unit, upon receiving the data read request of the load instruction, does not immediately block but first decodes the read byte mask of the data read request. The read byte mask is obtained by decoding based on the memory access width and low-order address bits of the load instruction: in one embodiment, the read byte mask for a word read (32-bit) is "1111"; for a half-word read (16-bit), it is selected as "0011" or "1100" according to the address bits; and for a byte read (8-bit), it is "0001" shifted left by the low-order address bits.

[0097] The byte mask comparison logic determines the overlap between the read byte mask and the byte channel mask of the incomplete write request, and handles the overlap in the following three ways: Scenario 1: Determined as non-overlapping, meaning the bitwise AND of the read byte mask and the byte channel mask of the incomplete write request results in zero. This indicates that the byte requested by the data read request and the byte to be written in the incomplete write request have no overlap, and their data are unrelated. In this case, the data buffer unit prematurely releases the blocking caused by data dependency of the data read request and sends the data read request as a normal read request to the main memory access arbitration unit. The data read request is subsequently authorized to access the external serial non-volatile memory device by the main memory access arbitration unit according to the single-port serial arbitration rules. It should be emphasized that "prematurely releasing" here only releases the waiting caused by data dependency, and does not release the single-port serial arbitration constraint. The data read request still needs to wait for the serial transmission phase of the write transaction to end (i.e., the write frame is sent) on the shared main memory path before it can be authorized to access, but it does not need to wait for a complete write completion confirmation to return. Its physical essence is that the serial transmission phase of the write transaction (write frame transmission) and the serial transmission phase of the read transaction are still serial on the single-port path, but the read transaction does not need to wait for the write cycle to be completely finished before entering the arbitration queue to wait for transmission, thus gaining an advance in time.

[0098] Scenario 2: If the data is determined to be overlapping and the byte channel mask of the incomplete write request completely covers the read byte mask, i.e., (byte channel mask of incomplete write request & read byte mask) == read byte mask, this indicates that all bytes required for the data read request have been covered by the incomplete write request, and the complete read data can be assembled from the write buffer. In this case, the data buffer unit controls the read data selector to read the corresponding bytes from the write buffer, assemble them into complete read data, and return them directly to the processor core without initiating any access to the external serial non-volatile memory device. This path is the write-after-read-before delivery path.

[0099] Scenario 3: The scenario is determined to be overlapping, and the byte channel mask of the incomplete write request fails to completely cover the read byte mask, i.e., (byte channel mask of incomplete write request & read byte mask) != 0 and (byte channel mask of incomplete write request & read byte mask) != read byte mask. This indicates that some bytes required by the data read request are available in the write buffer, but at least one required byte is not covered, making it impossible to assemble complete read data locally. In this case, the data buffer unit continues to block the data read request until the physical completion acknowledgment of the incomplete write request is returned. After the physical completion acknowledgment is returned, the incomplete write request in the write buffer is cleared or marked as completed, and the data read request is unblocked and sent to the main memory access arbitration unit as a normal read request.

[0100] It should be noted that the three processing paths described above are different: In scenario one, the read request enters an arbitration waiting state after being prematurely released, and whether it actually accesses the external device is still determined serially by the main memory access arbitration unit; in scenario two, the read request is returned locally without accessing the external device at all; in scenario three, the read request continues to wait. No physical read / write concurrency is introduced throughout the process.

[0101] According to embodiments of this disclosure, the method further includes a recovery period coordination step: When a silence signal is received from the associated recovery control unit, the main memory access arbitration unit suspends authorization for the fetch read request and the data read request, and freezes the update of the count state; In response to the silence signal, the instruction prefetch buffer unit freezes its internal entry hit count aging operation, continuous fetch miss count update, and cyclic transfer decision triggering. When the silence signal is removed, the counting state and the various counts and checks of the frozen instruction prefetch buffer unit continue to evolve from the values ​​at the time of freezing.

[0102] The recovery period arbitration service count freezing method provided in this embodiment is used to avoid secondary starvation caused by sudden changes in the count state when the system is configured with associated power failure recovery function.

[0103] In this embodiment, when the system is configured with associated power-loss recovery functionality, the system further includes an associated recovery control unit. During recovery or save operations, the associated recovery control unit sends a silence signal to the main memory access arbitration unit and the instruction prefetch buffer unit. In one embodiment, the silence signal is active high.

[0104] In response to the silence signal being valid, the main memory access arbitration unit performs the following freeze operations: First, it suspends authorization for instruction-side fetch read requests and data-side read requests. Specifically, the main memory access arbitration unit disables the instruction-side request eligibility signal and the data-side request eligibility signal, retaining only the eligibility to allow recovery-side requests; Second, it freezes the update of the anti-starvation counter. Under the single service difference implementation mode, the service difference stops increasing or decreasing and remains unchanged at its current value; under the separate maintenance of service counts on both sides implementation mode, the service count counters on both sides stop increasing and remain unchanged at their current values; Third, it freezes the merge wait window detection. If there is an open merge wait window, the remaining ticks of the merge wait window are frozen and retained, continuing according to the remaining ticks or returning after timeout once the silence signal is withdrawn.

[0105] In response to the valid silence signal, the instruction prefetch buffer unit performs the following freeze operations: First, freeze the hit count aging operation of each entry in the reserved entry array, that is, pause the aging cycle and keep each hit count unchanged; Second, freeze the update of the consecutive fetch miss counter, that is, keep the number of consecutive fetch misses unchanged; Third, freeze the triggering of the round-trip decision, that is, keep the round-trip flag at its current value and do not enter or exit the round-trip mode due to new hit events; Fourth, disable the background prefetch request submission enable.

[0106] When the silence signal is removed, the frozen counts and checks of the main memory access arbitration unit and the instruction prefetch buffer unit continue to evolve from the values ​​at the time of freezing, rather than being reset to zero. This "freeze-continue from the freeze point" design makes the evolution of the runtime count state during the recovery period "transparent," meaning that the recovery period leaves no trace of abrupt changes in the runtime count. If a zeroing method is used, the anti-starvation count will start from zero after recovery, the circular signature will be lost, and the previously accumulated service difference may lead to one side continuously obtaining authorization, dragging the other side into secondary starvation. The process of re-accumulating the circular signature will also lose the bandwidth concession benefits of the steady-state phase.

[0107] According to embodiments of this disclosure, the preset number of frames for the merge waiting window, the granularity of the aligned address block, and the data width read in a single serial burst read operation are all configurable system parameters.

[0108] Specifically, in this system, the above parameters can be configured via software-programmable registers. For example, the number of merge wait window cycles W can be adjusted between 1 and 8 cycles to adapt to different processor pipeline depths and serial interface speeds; the granularity of the aligned address block can be set to 4 bytes, 8 bytes, or 16 bytes to match the internal row size of the external memory; the data width of a single burst read operation can be set to 4 bytes, 8 bytes, or 16 bytes to balance command overhead and bus occupancy time. These parameters can be dynamically configured by the system firmware during initialization according to the actual application load, or they can be adaptively adjusted by the hardware, enabling this disclosure to flexibly adapt to various application scenarios.

[0109] Figure 3 A memory access control timing diagram of a processor memory access control method according to an embodiment of the present disclosure is shown. (See attached diagram.) Figure 3 As shown on the timeline (t0 to t7), the processor memory access control method of this disclosure specifically includes the following processing stages: During the time window t0 to t1, the instruction fetch signal remains in a high-level active state, indicating that the instruction prefetch buffer unit 101 responds to the current instruction fetch request and initiates the first round of instruction fetch operation.

[0110] Within the time window t1 to t2, the fetch signal drops and remains at a low level, forming a low-level branch extending to time t5. This low-level branch indicates that the hardware determination of the local hit status of the first round of instruction fetch operation has been completed. At this time, the instruction fetch request determined to be a miss has been handed over to the main memory access arbitration unit 103. The instruction fetch unit itself suspends submitting new requests and is in a silent waiting phase to release timing resources for subsequent arbitration processing.

[0111] Within time windows t2 to t4, in response to the initial instruction fetch failure, the merge / splitter signal synchronously jumps to a high level, triggering the system to enter an instruction fetch read request (row mode request), which remains valid. The main memory access arbitration unit 103, in response to the row mode instruction fetch read request, opens a merge wait window; within this window, if a data-side read request arriving at the same aligned address block is detected, the instruction fetch read request and the data-side read request are merged into a single burst read operation. Specifically, at time node t3, the main memory access arbitration unit 103 completes the data return from the external memory burst read operation at time t3 or immediately following time t3. Subsequently, the system synchronously performs a byte-level splitting operation at time t3, responding to the low-order address information of the returned data, and hard-wires the merged burst data, outputting it to the instruction-side consumer and the data-side consumer respectively. The merge / splitter signal only drops to an invalid low level state after the splitting and distribution operations are completely completed at time t4.

[0112] Within the time window t4 to t5, the merge / splitter signal drops to an invalid low level. Simultaneously, the data side write protection signal generates a brief valid high-level pulse. This pulse indicates that the data side has received the split data and begins to briefly occupy the shared main memory path to pre-set subsequent write operations.

[0113] Within the time window t5 to t6, the instruction fetch control signal, the cycle yield control signal, and the data write protection control signal simultaneously transition to a high-level active state. This concurrency logic specifically includes: the cycle yield control signal being set high indicates that the instruction prefetch buffer unit 101, in response to the accumulation of cycle signatures reaching a preset threshold, determines that the current state is a local hit in the cycle body and completely yields the bus usage rights of the shared main memory path to the data side; the instruction fetch control signal being simultaneously set high indicates that during the cycle yield, the local hit instruction fetch operation within the instruction pipeline continues to execute (forming a non-conflicting concurrency between local operation and path right yield); and the data write protection control signal being set high indicates that the data side has officially taken over the path, and its write request protection arbitration logic has been activated and locked.

[0114] Within the time window t6 to t7, the write-protection completion window signal transitions to a valid high level. It should be noted that the high signal at t6 has a one-beat phase delay compared to the high signal of the data-side write-protection signal at t5. This delay indicates that the data side has completed pre-processing operations such as address alignment, byte mask calculation, and internal state establishment during t5 to t6; at this point, the write-protection window officially takes effect. During the window's validity period, the system executes the following branch control: if the access address of the read request does not overlap with the byte to be written, the data-related blocking of the read request is released early; if the read request overlaps with the byte to be written but data forwarding is allowed, the write buffer directly returns the forwarded data to the read request; if the read request overlaps with the byte to be written and forwarding is not allowed, the read request must wait for the write request to complete completely before performing the access operation.

[0115] Effect Example In one embodiment (using a 5-stage RISC-V RV32I processor core, a core frequency of 100MHz, a serial interface frequency of 10MHz, and a serial clock divider parameter MRAM_CLK_DIV=5), a custom mixed workload (including four types of tasks: sequential arithmetic operations, access loops, function calls, and branch jumps) was used as the test caliber. The phased comparative measurement results are as follows: Configuration Effective execution cycle Estimating CPI Serial read count illustrate No optimized baseline 4,957,153 2266 4,574 Refers to unreserved entries, no prefetch hits Add reserved entry array 569,665 238 256 The success rate of retaining entries across branches and refreshing them significantly increases the loop hit rate. Add byte-level routing and other optimizations 190,129 79 128 Based on the retained entries, merging and routing coordination are superimposed. BRAM can be installed on the same processor core (upper limit reference). 2,584 1.049 0 Upper limit of the same core without serial interface bottleneck As shown in the table above, the reserved entry array (core of the circular transfer implementation) reduces the effective execution cycle time from approximately 4.96M to approximately 0.57M, resulting in a performance improvement of approximately 8.7 times. On this basis, the addition of byte-level demultiplexing and merging windows (core of the heterogeneous request merging implementation) further reduces the cycle time from approximately 0.57M to approximately 0.19M, resulting in a performance improvement of approximately 3.0 times. Here, BRAM stands for Block Random Access Memory.

[0116] This disclosure also provides a processor memory access control system applied to a processor system that uses an external serial non-volatile memory as the unified main memory. The system includes: The processor core is configured to execute program instructions and issue instruction fetch requests and data access requests. The instruction prefetch buffer unit is configured to initiate an instruction fetch read request to the main memory access arbitration unit in response to the instruction fetch request when the instruction is not found in the local storage structure. The data buffer unit is configured to initiate a data read request to the main memory access arbitration unit in response to a data read request from the processor core. The main memory access arbitration unit is configured to receive the fetch read request and open a merge wait window with a preset number of clock cycles. Within the merge wait window, if a data read request is received, and the addresses targeted by the data read request and the fetch read request are located within the same aligned address block, a single serial burst read operation is initiated to the serial non-volatile memory control unit via the shared main memory path to obtain the complete data within the aligned address block. The complete data is provided to the instruction prefetch buffer unit, and simultaneously, a corresponding data word is selected from the complete data based on the low-order address of the data read request and provided to the data buffer unit. Furthermore, in response to the single serial burst read operation, an update is performed on the count state used for arbitrating the fetch read request and the data read request, equivalent to both the fetch read request and the data read request receiving a service authorization.

[0117] According to an embodiment of this disclosure, the fetch read request is a row mode request initiated by the instruction prefetch buffer unit when neither the sequential prefetch queue nor the reserved entry array is hit. The row mode request is used to read a data line containing a consecutive plurality of instruction words from the external serial nonvolatile memory.

[0118] According to an embodiment of this disclosure, the data read request is a single-word request initiated by the data buffer unit within the write completion protection window when it is determined that the read request to be processed does not overlap with the bytes to be written in the incomplete write request.

[0119] According to an embodiment of this disclosure, the main memory access arbitration unit includes: a merge admission determination logic, which is configured to determine whether the data read request and the fetch read request meet a merge condition, wherein the merge condition further includes: The merge waiting window is enabled. The memory access type corresponding to the data read request is a read operation; The addresses of both the fetch request and the data read request are within the preset legal address range; Neither the instruction fetch request nor the data read request was shielded by their respective duplicate authorization protection signals. According to an embodiment of this disclosure, the main memory access arbitration unit further includes: a return data decoupling logic, configured to fan out the data word simultaneously to the instruction prefetch buffer unit and the data buffer unit when the instruction fetch read request and the data read request point to the same data word in the complete data; and to provide all data words in the complete data to the instruction prefetch buffer unit when they point to different data words, and to select a corresponding single data word from the complete data according to the low-order address bits and provide it to the data buffer unit.

[0120] According to an embodiment of this disclosure, the main memory access arbitration unit is further configured to, if no data read request meeting the merging conditions is received within the merge waiting window, or if the merge waiting window times out, return to the normal arbitration mode, initiate independent read operations serving the fetch read request and independent read operations serving the data read request to the serial non-volatile memory control unit respectively, and request the update of the count state only for the party that actually obtains authorization.

[0121] According to embodiments of this disclosure, the main memory access arbitration unit includes: instruction-side service count counters and data-side service count counters maintained separately; The main memory access arbitration unit is also configured to increment the instruction-side service count counter and the data-side service count counter by one count unit after the single serial burst read operation is completed.

[0122] According to an embodiment of this disclosure, the main memory access arbitration unit includes: a single service difference register for maintaining the service difference between the fetch read request and the data read request; The main memory access arbitration unit is also configured to keep the single service difference unchanged after the single serial burst read operation is completed.

[0123] According to embodiments of this disclosure, such as Figure 5 As shown, the instruction prefetch buffer unit includes: a reserved entry array, a circular signature detection logic, and a transfer control logic; The reserved entry array is configured not to clear entries that have passed address verification when a branch refresh event occurs; The circular signature detection logic is configured to detect the cumulative number of repeated hits of the same entry address in the reserved entry array and monitor the hit count of the corresponding entry. The transfer control logic is configured to cause the instruction prefetch buffer unit to enter a circular transfer mode when the cumulative number of repeated hits reaches a preset circular hit threshold and the hit count reaches a preset stable threshold; in the circular transfer mode, the submission of background prefetch requests to the shared main memory path is suspended, so as to transfer the right to occupy the shared main memory path to the data read request.

[0124] Furthermore, the instruction prefetch buffer unit also includes a consecutive miss counter and callback control logic; The consecutive miss counter is configured to monitor the number of consecutive fetch misses in the cyclic yield mode; The callback control logic is configured to execute a progressive forced callback when the number of consecutive missed fetches reaches a preset missed callback threshold. The progressive forced callback includes: opening a callback window of a preset length, allowing a limited number of background prefetch requests within the callback window; if the number of consecutive missed fetches does not decrease within the callback window, conditional hit count aging is performed on the old loop entry that triggered loop yielding to reduce its priority for triggering loop yielding again; if the number of consecutive missed fetches reaches the missed callback threshold again after the callback window ends, the loop signature state is cleared and the loop yielding mode is exited.

[0125] According to embodiments of this disclosure, such as Figure 6 As shown, the data buffer unit includes a write buffer, byte mask comparison logic, forwarding decision logic, and a read data selector; The write buffer is configured to store and update the address, data, and byte channel mask of incomplete write requests; The byte mask comparison logic is configured to, upon receiving a data read request, decode the read byte mask of the data read request and perform an overlap determination between the read byte mask and the byte channel mask of the incomplete write request; The forwarding decision logic is configured such that if it is determined that there is no overlap, the blocking of the data read request caused by data correlation is released in advance, and the data read request is sent to the main memory access arbitration unit as a normal read request; if it is determined that there is overlap and the byte channel mask of the incomplete write request completely covers the read byte mask, the read data selector is controlled to combine the complete read data from the write buffer and return, without initiating access to the external serial non-volatile memory; if it is determined that there is overlap and the byte channel mask of the incomplete write request does not completely cover the read byte mask, the data read request continues to be blocked until the physical completion confirmation of the incomplete write request is returned.

[0126] According to embodiments of this disclosure, the processor memory access control further includes a boot execution unit configured to select a boot loading mode or a direct execution mode based on a configuration signal.

[0127] In the boot loading mode, the processor core first executes the on-chip boot code to copy program segments from the external serial non-volatile memory before jumping to execution. Specifically, after reset, the processor core executes the on-chip boot code, which reads the necessary program segments from the external serial non-volatile memory via the main memory access arbitration unit and the serial non-volatile memory control unit, and then writes them back to the running location (still located in the same external serial non-volatile memory, or written to another area within its address space) via the main memory access arbitration unit. After completion, a boot handover register is written to generate a handover pulse, and the process jumps to the unified main memory program entry point.

[0128] In the direct execution mode, the processor core fetches instructions from the external serial non-volatile memory in situ. Specifically, after reset, the processor core directly fetches instructions from the preset entry address of the unified main memory. The fetch request is initiated by the instruction prefetch buffer unit and the main memory access arbitration unit, without the need for prior copying.

[0129] Both modes ultimately jump to the program entry point in the unified main memory and execute in place on the same unified main memory, using the exact same byte-level demultiplexing and circular passover mechanism during runtime.

[0130] According to embodiments of this disclosure, the external serial non-volatile memory is any one of magnetoresistive random access memory (MRAM), serial ferroelectric random access memory (serial FRAM), or serial NOR flash memory.

[0131] The specific technical details of the embodiments disclosed herein can be found in the above method embodiments, and will not be repeated here.

[0132] This disclosure also discloses an electronic device, Figure 7 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0133] like Figure 7 As shown, the electronic device includes a memory and a processor, wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method according to embodiments of the present disclosure.

[0134] The processor memory access control method is applied to a processor system that uses an external serial non-volatile memory as a unified main memory. The processor system includes a shared main memory path connected to the external serial non-volatile memory via a serial interface. The method includes: Receive fetch / read requests from the instruction prefetch buffer unit and open a merge wait window for a preset number of cycles; Within the merge waiting window, if a data read request is received from the data buffer unit, and the address targeted by the data read request and the fetch read request are located in the same aligned address block, then a single serial burst read operation is initiated to the external serial non-volatile memory through the shared main memory path to obtain the complete data in the aligned address block. The complete data is provided to the instruction prefetch buffer unit, and the corresponding data word is selected from the complete data according to the low address of the data read request and provided to the data buffer unit. In response to the single serial burst read operation, the count state used for arbitrating the fetch read request and the data read request is updated to be equivalent to both the fetch read request and the data read request receiving a service authorization once.

[0135] In one embodiment of this disclosure, the fetch read request is a row mode request initiated by the instruction prefetch buffer unit when neither the sequential prefetch queue nor the reserved entry array is hit. The row mode request is used to read a data line containing multiple consecutive instruction words from the external serial non-volatile memory.

[0136] In one embodiment of this disclosure, the data read request is a single-word request initiated by the data buffer unit within the write completion protection window when it is determined that the read request to be processed does not overlap with the bytes to be written in the incomplete write request.

[0137] In one embodiment of this disclosure, determining that the data read request and the instruction fetch read request meet the merging conditions within the merge waiting window further includes: The merge waiting window is enabled. The memory access type corresponding to the data read request is a read operation; The addresses of both the fetch request and the data read request are within the preset legal address range; Furthermore, neither the fetch request nor the data read request was shielded by their respective duplicate authorization protection signals.

[0138] In one embodiment of this disclosure, providing the complete data to the instruction prefetch buffer unit, and simultaneously selecting a corresponding data word from the complete data according to the low-order address of the data read request and providing it to the data buffer unit, includes: When the instruction read request and the data read request point to the same data word in the complete data, the data word is fanned out to both the instruction prefetch buffer unit and the data buffer unit. When they point to different data words, the instruction prefetch buffer unit obtains all the data words in the complete data, and the data buffer unit obtains the corresponding single data word based on the low-order bits of the address.

[0139] In one embodiment of this disclosure, if no data read request meeting the merging conditions is received within the merge waiting window, or if the merge waiting window times out, the process reverts to the normal arbitration mode, and initiates independent read operations serving the fetch read request and the data read request to the external serial non-volatile memory respectively, and requests the update of the count state only to the party that actually obtains authorization.

[0140] In one embodiment of this disclosure, the counting state includes a service count counter on the instruction side and a service count counter on the data side, which are maintained separately; the update, which is equivalent to both the fetch read request and the data read request receiving a service authorization once, includes: incrementing the service count counter on the instruction side and the service count counter on the data side by one count unit.

[0141] In one embodiment of this disclosure, the counting state includes maintaining a single service difference; the update, which is equivalent to both the fetch read request and the data read request receiving a service authorization once, includes keeping the single service difference unchanged.

[0142] In one embodiment of this disclosure, it further includes: The instruction prefetch buffer unit is equipped with a reserved entry array, which does not clear entries that have passed address verification when a branch refresh event occurs; When the cumulative number of repeated hits of the same entry address in the reserved entry array reaches a preset cyclic hit threshold, and the hit count of the corresponding entry reaches a preset stable threshold, the instruction prefetch buffer unit enters the cyclic yield mode. In the circular transfer mode, the instruction prefetch buffer unit suspends the submission of background prefetch requests to the shared main memory path, thereby transferring the right to occupy the shared main memory path to data read requests.

[0143] In one embodiment of this disclosure, it further includes: In the cyclical transfer mode, the number of consecutive finger fetch misses is monitored; When the number of consecutive missed fetches reaches a preset missed callback threshold, a progressive forced callback is executed. The progressive forced callback includes: first, opening a callback window of a preset length, and allowing a limited number of background prefetch requests within the callback window; if the number of consecutive missed fetches does not decrease within the callback window, then conditional hit count aging is performed on the old loop entry that triggered loop yielding to reduce its priority for triggering loop yielding again; if the number of consecutive missed fetches reaches the missed callback threshold again after the callback window ends, then the loop signature state is finally cleared and the loop yielding mode is exited.

[0144] In one embodiment of this disclosure, it further includes: The data buffer unit stores and updates the byte channel mask for incomplete write requests; Upon receiving a data read request, the read byte mask of the data read request is decoded, and the overlap between the read byte mask and the byte channel mask of the incomplete write request is determined. If it is determined that there is no overlap, the blocking of the data read request caused by data correlation is lifted in advance, and the data read request is sent to the main memory access arbitration unit as a normal read request. If it is determined to be overlapping and the byte channel mask of the incomplete write request completely covers the read byte mask, then the data buffer unit will combine the complete read data from the local write buffer and return it, without initiating an access to the external serial non-volatile memory. If the data is determined to be overlapping and the byte channel mask of the incomplete write request fails to completely cover the read byte mask, the data read request will continue to be blocked until the physical completion confirmation of the incomplete write request is returned.

[0145] In one embodiment of this disclosure, it further includes: When a silence signal is received from the associated recovery control unit, the main memory access arbitration unit suspends authorization for the fetch read request and the data read request, and freezes the update of the count state; In response to the silence signal, the instruction prefetch buffer unit freezes its internal entry hit count aging operation, continuous fetch miss count update, and cyclic transfer decision triggering. When the silence signal is removed, the counting state and the various counts and checks of the frozen instruction prefetch buffer unit continue to evolve from the values ​​at the time of freezing.

[0146] In one embodiment of this disclosure, the preset number of frames for the merge waiting window, the granularity of the aligned address block, and the data width read in a single serial burst read operation are all configurable system parameters.

[0147] Figure 8 A schematic diagram of the structure of a computer system suitable for implementing the method according to embodiments of the present disclosure is shown.

[0148] like Figure 8 As shown, the computer system includes a processing unit that can execute various methods described above based on a program stored in a read-only memory (ROM) or a program loaded from a storage portion into a random access memory (RAM). The RAM also stores various programs and data required for the operation of the computer system. The processing unit, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0149] The following components are connected to the I / O interface: input sections including keyboards, mice, etc.; output sections including cathode ray tubes (CRTs), liquid crystal displays (LCDs), and speakers; storage sections including hard disks; and communication sections including network interface cards such as LAN cards and modems. The communication section performs communication processes via a network such as the Internet. Drives are also connected to the I / O interface as needed. Removable media, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive as needed so that computer programs read from them can be installed into the storage section as required. The processing unit can be implemented as a CPU, GPU, TPU, FPGA, NPU, etc.

[0150] In particular, according to embodiments of this disclosure, the methods described above can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program tangibly embodied on a machine-readable medium, the computer program containing program code for performing the methods described above. In such embodiments, the computer program can be downloaded and installed from a network via a communication component, and / or installed from a removable medium.

[0151] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0152] The units or modules described in the embodiments of this disclosure can be implemented in software or programmable hardware. The described units or modules can also be located in a processor, and the names of these units or modules do not necessarily constitute a limitation on the unit or module itself.

[0153] In another aspect, this disclosure also provides a chip including at least one processor that can be used to implement the methods involved in the above system embodiments.

[0154] In one possible design, the chip also includes a memory for storing program instructions and data, which may be located inside or outside the processor.

[0155] In another aspect, this disclosure also provides a computer-readable storage medium, which may be a computer-readable storage medium included in the electronic device or computer system described above; or it may be a standalone computer-readable storage medium not assembled into a device. The computer-readable storage medium stores one or more programs, which are used by one or more processors to perform the methods described in this disclosure.

[0156] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

Claims

1. A processor memory access control method, applied to a processor system using an external serial non-volatile memory as a unified main memory, the processor system including a shared main memory path connected to the external serial non-volatile memory via a serial interface, characterized in that, The method includes: Receive fetch / read requests from the instruction prefetch buffer unit and open a merge wait window for a preset number of cycles; Within the merge waiting window, if a data read request is received from the data buffer unit, and the address targeted by the data read request and the fetch read request are located in the same aligned address block, then a single serial burst read operation is initiated to the external serial non-volatile memory through the shared main memory path to obtain the complete data in the aligned address block. The complete data is provided to the instruction prefetch buffer unit, and the corresponding data word is selected from the complete data according to the low address of the data read request and provided to the data buffer unit. In response to the single serial burst read operation, the count state used for arbitrating the fetch read request and the data read request is updated to be equivalent to both the fetch read request and the data read request receiving a service authorization once.

2. The method according to claim 1, characterized in that, Within the merge waiting window, determining that the data read request and the fetch read request meet the merge conditions further includes: The merge waiting window is enabled. The memory access type corresponding to the data read request is a read operation; The addresses of both the fetch request and the data read request are within the preset legal address range; Furthermore, neither the fetch request nor the data read request was shielded by their respective duplicate authorization protection signals.

3. The method according to claim 1, characterized in that, The step of providing the complete data to the instruction prefetch buffer unit, and simultaneously selecting the corresponding data word from the complete data according to the low-order address of the data read request and providing it to the data buffer unit, includes: When the instruction read request and the data read request point to the same data word in the complete data, the data word is fanned out to both the instruction prefetch buffer unit and the data buffer unit. When they point to different data words, the instruction prefetch buffer unit obtains all the data words in the complete data, and the data buffer unit obtains the corresponding single data word based on the low-order bits of the address.

4. The method according to claim 1, characterized in that, The counting status includes a service count counter on the instruction side and a service count counter on the data side, which are maintained separately; the update that is equivalent to both the instruction fetch request and the data read request receiving a service authorization once includes: incrementing the service count counter on the instruction side and the service count counter on the data side by one count unit.

5. The method according to claim 1, characterized in that, The counting state includes maintaining a single service difference; the update, which is equivalent to both the fetch read request and the data read request receiving a service authorization once, includes keeping the single service difference unchanged.

6. The method according to claim 1, characterized in that, Also includes: The instruction prefetch buffer unit is equipped with a reserved entry array, which does not clear entries that have passed address verification when a branch refresh event occurs; When the cumulative number of repeated hits of the same entry address in the reserved entry array reaches a preset cyclic hit threshold, and the hit count of the corresponding entry reaches a preset stable threshold, the instruction prefetch buffer unit enters the cyclic yield mode. In the circular transfer mode, the instruction prefetch buffer unit suspends the submission of background prefetch requests to the shared main memory path, thereby transferring the right to occupy the shared main memory path to data read requests.

7. The method according to claim 6, characterized in that, Also includes: In the cyclical transfer mode, the number of consecutive finger fetch misses is monitored; When the number of consecutive missed fetches reaches a preset missed callback threshold, a progressive forced callback is executed. The progressive forced callback includes: first, opening a callback window of a preset length, and allowing a limited number of background prefetch requests within the callback window; if the number of consecutive missed fetches does not decrease within the callback window, then conditional hit count aging is performed on the old loop entry that triggered loop yielding to reduce its priority for triggering loop yielding again; if the number of consecutive missed fetches reaches the missed callback threshold again after the callback window ends, then the loop signature state is finally cleared and the loop yielding mode is exited.

8. The method according to claim 1, characterized in that, Also includes: The data buffer unit stores and updates the byte channel mask for incomplete write requests; Upon receiving a data read request, the read byte mask of the data read request is decoded, and the overlap between the read byte mask and the byte channel mask of the incomplete write request is determined. If it is determined that the data read request is not overlapping, the blocking caused by data correlation will be lifted in advance, and the data read request will be sent to the main memory access arbitration unit as a normal read request. If it is determined to be overlapping and the byte channel mask of the incomplete write request completely covers the read byte mask, then the data buffer unit will combine the complete read data from the local write buffer and return it, without initiating an access to the external serial non-volatile memory. If the data is determined to be overlapping and the byte channel mask of the incomplete write request fails to completely cover the read byte mask, the data read request will continue to be blocked until the physical completion confirmation of the incomplete write request is returned.

9. The method according to claim 1, characterized in that, Also includes: When a silence signal is received from the associated recovery control unit, the main memory access arbitration unit suspends authorization for the fetch read request and the data read request, and freezes the update of the count state; In response to the silence signal, the instruction prefetch buffer unit freezes its internal entry hit count aging operation, continuous fetch miss count update, and cyclic transfer decision triggering. When the silence signal is removed, the counting state and the various counts and checks of the frozen instruction prefetch buffer unit continue to evolve from the values ​​at the time of freezing.

10. A processor memory access control system, applied in a processor system using an external serial non-volatile memory as the unified main memory, characterized in that, The system includes: The processor core is configured to execute program instructions and issue instruction fetch requests and data access requests. The instruction prefetch buffer unit is configured to initiate an instruction fetch read request to the main memory access arbitration unit in response to the instruction fetch request when the instruction is not found in the local storage structure. The data buffer unit is configured to initiate a data read request to the main memory access arbitration unit in response to a data read request from the processor core. The main memory access arbitration unit is configured to receive the fetch read request and open a merge wait window with a preset number of clock cycles. Within the merge wait window, if a data read request is received, and the addresses targeted by the data read request and the fetch read request are located within the same aligned address block, a single serial burst read operation is initiated to the serial non-volatile memory control unit via the shared main memory path to obtain the complete data within the aligned address block. The complete data is provided to the instruction prefetch buffer unit, and simultaneously, a corresponding data word is selected from the complete data based on the low-order address of the data read request and provided to the data buffer unit. Furthermore, in response to the single serial burst read operation, an update is performed on the count state used for arbitrating the fetch read request and the data read request, equivalent to both the fetch read request and the data read request receiving a service authorization.

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