Power management system and digital-analog hybrid chip

Abstract

The application relates to the technical field of power supply chips, and discloses a power management system and a digital-analog hybrid chip, wherein the digital-analog hybrid chip comprises: a first wafer; a high-voltage circuit prepared on the first wafer, the high-voltage circuit being built based on components of a first voltage level and components of a second voltage level, the first voltage level being greater than the second voltage level; a second wafer; a control circuit prepared on the second wafer, the control circuit being built based on components of the second voltage level and components of a third voltage level, the second voltage level being greater than the third voltage level; and interconnection wire preparation between the first wafer and the second wafer to combine and package the first wafer and the second wafer. According to the application, the high-voltage circuit and the control circuit during chip design are prepared by using two wafers, and the two wafers are combined and packaged by interconnection wire preparation, so that the two wafers can each omit a part of MASK layers corresponding to the components, and the manufacturing cost is reduced.

Description

Technical Field

[0001] This application relates to the field of power chip technology, and in particular to a mixed-signal chip and a power management system. Background Technology

[0002] High-voltage mixed-signal chips are increasingly used in power management applications, such as digital power supplies, USB fast charging protocols, PoE (Power over Ethernet), and analog front-end (AFE) for battery management. These applications typically require chips to withstand high voltages while also integrating an MCU (Microcontroller Unit) controller. This necessitates considering both the high-voltage and low-voltage circuitry, as well as the interaction between these two circuits, when designing mixed-signal chips.

[0003] In related technologies, mixed-signal chip design generally adopts a single-wafer solution, which is based on the same process platform. This design can ensure that the low-voltage circuit and the high-voltage circuit are on the same wafer, and the interconnection between the two circuits is relatively convenient. There is no need to worry about the problem of too many interconnect lines. However, the number of mask layers during wafer manufacturing is too large, usually exceeding 30 layers, which increases the manufacturing difficulty and cost. Summary of the Invention

[0004] The purpose of this application is to provide a mixed-signal chip and a power management system having the mixed-signal chip. By using two different wafers to fabricate the high-voltage circuit and control circuit during chip design, and by interconnecting the two wafers to package them together, the number of mask layers corresponding to some components can be eliminated for each wafer. This greatly reduces the number of mask layers in the manufacturing of each circuit without increasing the wafer area significantly, thereby reducing manufacturing costs.

[0005] To achieve the above objectives, the main technical solutions adopted in this application include:

[0006] In a first aspect, embodiments of this application provide a mixed-signal chip, comprising: a first wafer; a high-voltage circuit fabricated on the first wafer, the high-voltage circuit being constructed based on components of a first voltage level, or based on components of the first voltage level and components of a second voltage level, wherein the first voltage level is greater than the second voltage level; a second wafer; a control circuit fabricated on the second wafer, the control circuit being constructed based on components of a third voltage level, or based on components of the second voltage level and components of the third voltage level, wherein the second voltage level is greater than the third voltage level; and interconnection wire bonding is performed between the first wafer and the second wafer to merge and package the first wafer and the second wafer.

[0007] According to the embodiments of this application, a mixed-signal chip fabricates a high-voltage circuit including components of a first voltage level on a first wafer, and a control circuit including components of a third voltage level on a second wafer. This allows the high-voltage circuit and the control circuit to be fabricated on two different wafers, thereby eliminating the need for a third voltage level component layer on the first wafer and a first voltage level component layer on the second wafer. This significantly reduces the number of mask layers required for each circuit. Furthermore, interconnect wire bonding is performed between the first and second wafers to achieve integrated packaging. This process is simple and does not require a significant increase in wafer area, thus reducing chip manufacturing costs.

[0008] Optionally, in some embodiments of this application, when the high-voltage circuit is constructed based on components of the first voltage level and components of the second voltage level, and the control circuit is constructed based on components of the second voltage level and components of the third voltage level, the high-voltage circuit includes a first interface control unit, which is constructed based on components of the second voltage level in the high-voltage circuit; the control circuit includes a second interface control unit, at least a portion of which is constructed based on components of the second voltage level in the control circuit; wherein, interconnect wire bonding is performed between the first wafer and the second wafer to enable signal interaction between the first interface control unit and the second interface control unit.

[0009] Optionally, in some embodiments of this application, when the high-voltage circuit is constructed based on components of the first voltage level and the control circuit is constructed based on components of the third voltage level, the high-voltage circuit includes a third interface control unit and the control circuit includes a fourth interface control unit, wherein the first wafer and the second wafer are interconnected by wire bonding to enable signal interaction between the third interface control unit and the fourth interface control unit.

[0010] Optionally, in some embodiments of this application, when the high-voltage circuit is constructed based on components of the first voltage level and components of the second voltage level, and the control circuit is constructed based on components of the third voltage level, the high-voltage circuit includes a fifth interface control unit, which is constructed based on components of the second voltage level in the high-voltage circuit; the control circuit includes a sixth interface control unit, which is constructed based on components of the third voltage level in the control circuit; wherein, the first wafer and the second wafer are interconnected by wire bonding to enable signal interaction between the fifth interface control unit and the sixth interface control unit.

[0011] Optionally, in some embodiments of this application, when the high-voltage circuit is constructed based on components of the first voltage level and the control circuit is constructed based on components of the second voltage level and the third voltage level, the high-voltage circuit includes a seventh interface control unit, which is constructed based on components of the first voltage level in the high-voltage circuit; the control circuit includes an eighth interface control unit, at least a portion of which is constructed based on components of the second voltage level in the control circuit; wherein, the first wafer and the second wafer are interconnected by wire bonding to enable signal interaction between the seventh interface control unit and the eighth interface control unit.

[0012] Optionally, in some embodiments of this application, the first interface control unit is fabricated on a first wafer adjacent to the second wafer, and the second interface control unit is fabricated on a second wafer adjacent to the first wafer.

[0013] Optionally, in some embodiments of this application, the unit built based on the components of the first voltage level in the high voltage circuit is fabricated on one side of the first wafer, and one side of the first wafer is far away from the second wafer.

[0014] Optionally, in some embodiments of this application, when the mixed-signal chip is a PSE chip, the unit built based on the components of the first voltage level in the high-voltage circuit includes a high-voltage ESD unit and a high-voltage power device, and the unit built based on the components of the second voltage level in the high-voltage circuit includes a first DAC control unit, a first ADC control unit, and a first register, wherein the first DAC control unit, the first ADC control unit, and the first register are located between the first interface control unit and the unit built based on the components of the first voltage level; the control circuit further includes a PSE protocol control unit, a second register, a first MCU core, and a first storage control unit, wherein the PSE protocol control unit, the second register, the first MCU core, and the first storage control unit are fabricated on one side of the second wafer, and one side of the second wafer is away from the first wafer.

[0015] Optionally, in some embodiments of this application, at least one of the second interface control unit, the PSE protocol control unit, the second register, the first MCU core, and the first storage control unit includes components of the third voltage level.

[0016] Optionally, in some other embodiments of this application, when the mixed-signal chip is a fast charging protocol chip, the unit built based on the components of the first voltage level in the high-voltage circuit includes a high-voltage protection unit and a high-voltage loop control unit, and the unit built based on the components of the second voltage level in the high-voltage circuit includes a second DAC control unit and a third register, the second DAC control unit and the third register being located between the first interface control unit and the unit built based on the components of the first voltage level; the control circuit further includes a fast charging protocol unit, a second ADC control unit, a fourth register, a second MCU core and a second storage control unit, the fast charging protocol unit, the second ADC control unit, the fourth register, the second MCU core and the second storage control unit being fabricated on one side of the second wafer, and one side of the second wafer being away from the first wafer.

[0017] Optionally, in some embodiments of this application, at least one of the fast charging protocol unit, the second ADC control unit, the fourth register, the second MCU core, and the second storage control unit includes components of the third voltage level.

[0018] Optionally, in some embodiments of this application, the protocol pin of the fast charging protocol chip is connected to the high-voltage protection unit so that the signal of the protocol pin is transmitted through the first interface control unit after being protected by high voltage.

[0019] Optionally, in some embodiments of this application, the high-voltage circuit is fabricated on the first wafer using a first process, and the control circuit is fabricated on the second wafer using a second process, wherein the first process and the second process are different.

[0020] Specifically, the first process is a BCD process, and the second process is a CMOS process.

[0021] Secondly, embodiments of this application provide a power management system, including a mixed-signal chip as described in the above embodiments.

[0022] According to the power management system of the present application embodiment, based on the mixed-signal chip described in the above embodiment, by using two different wafers to fabricate the high-voltage circuit and control circuit during the design of the mixed-signal chip, and by interconnecting the two wafers to package them together, the first wafer can eliminate the component layer of the third voltage level and the second wafer can eliminate the component layer of the first voltage level, which can greatly reduce the number of mask layers in the manufacturing of each circuit, and without increasing the wafer area by much, the fabrication process is not complicated, which greatly reduces the chip manufacturing cost. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1A A block diagram illustrating a mixed-signal chip according to an embodiment of this application;

[0025] Figure 1B A block diagram illustrating a mixed-signal chip according to another embodiment of this application;

[0026] Figure 1C A block diagram illustrating a mixed-signal chip according to yet another embodiment of this application;

[0027] Figure 1D A block diagram of a mixed-signal chip is provided in another embodiment of this application;

[0028] Figure 2 A block diagram of a PSE chip provided in one embodiment of this application;

[0029] Figure 3 A block diagram of a fast charging protocol chip provided in another embodiment of this application;

[0030] Figure 4 A block diagram illustrating a single-wafer design for a PSE chip in related technologies;

[0031] Figure 5 A block diagram of a fast charging protocol chip designed for a single wafer in related technologies;

[0032] Figure 6 This is a block diagram of a power management system provided in one embodiment of this application. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] In related technologies, the design of mixed-signal chips requires consideration of both high-voltage and low-voltage circuit design, as well as the interaction design between the two circuits. To facilitate the interconnection and routing of the high-voltage and low-voltage circuits, mixed-signal chip design generally adopts a single-wafer approach, fabricating both low-voltage and high-voltage circuits on the same wafer, thus eliminating concerns about the large number of interconnect lines.

[0035] However, the high-voltage circuitry requires not only 5V components but also high-voltage components such as 40V or 80V components, necessitating additional layers of high-voltage components that are unnecessary for the low-voltage circuitry. Similarly, the low-voltage circuitry typically uses even lower-voltage components, such as 1.8V or 1.5V components, in addition to 5V components, requiring additional layers of low-voltage components that are unnecessary for the high-voltage circuitry. Fabricating both low-voltage and high-voltage circuits on the same wafer using the same process platform would result in an excessive number of mask layers during wafer fabrication, typically exceeding 30 layers, increasing manufacturing difficulty and cost.

[0036] Therefore, the mixed-signal chip and power management system with the mixed-signal chip provided in this application embodiment are made by using two different wafers to fabricate the high-voltage circuit and control circuit during chip design, and the two wafers are interconnected and packaged together. In this way, the number of mask layers corresponding to some components can be saved on each wafer. Without increasing the wafer area too much, the number of mask layers in the manufacturing of each circuit is greatly reduced, thus reducing the manufacturing cost.

[0037] The following describes in detail, with reference to the accompanying drawings, the mixed-signal chip and the power management system having the mixed-signal chip provided in the embodiments of this application.

[0038] refer to Figure 1A The diagram shown is a block illustration of a mixed-signal chip according to an embodiment of this application. Figure 1A As shown, the mixed-signal chip 100 includes a first wafer 101, a second wafer 102, a high-voltage circuit 103, and a control circuit 104.

[0039] The high-voltage circuit 103 is fabricated on the first wafer 101, and the high-voltage circuit 103 is constructed based on components of a first voltage level, or based on components of a first voltage level and components of a second voltage level, wherein the first voltage level is greater than the second voltage level. Specifically, the first voltage level can be 40V or 80V, and the second voltage level can be 5V or 3.3V.

[0040] The control circuit 104 is fabricated on the second wafer 102, and the control circuit 103 is built based on components of a third voltage level, or based on components of a second voltage level and components of a third voltage level, wherein the second voltage level is greater than the third voltage level. Specifically, the third voltage level can be 1.8V or 1.5V.

[0041] Furthermore, interconnect wire bonding is performed between the first wafer 101 and the second wafer 102 to merge and package the first wafer 101 and the second wafer 102.

[0042] Therefore, it can be seen that the mixed-signal chip 100 of this application uses two different wafers to fabricate the high-voltage circuit 103 and the control circuit 104. As a result, the first wafer 101 can eliminate the component layer of the third voltage level, and the second wafer 102 can eliminate the component layer of the first voltage level. This allows each wafer to eliminate a portion of the mask layer corresponding to the components, greatly reducing the number of mask layers in the manufacturing of each circuit and lowering the wafer manufacturing cost. Furthermore, the two wafers are interconnected and bonded together for convenient customer application.

[0043] Optionally, in some embodiments of this application, such as Figure 2 or Figure 3 As shown, in the case where the high-voltage circuit 103 is constructed based on components of a first voltage level, such as 40V or 80V, and components of a second voltage level, such as 5V, and the control circuit 104 is constructed based on components of a second voltage level, such as 5V, and components of a third voltage level, such as 1.5V or 1.8V, the high-voltage circuit 103 includes a first interface control unit 11, which is constructed based on components of the second voltage level in the high-voltage circuit 103. The control circuit 104 includes a second interface control unit 12, at least a portion of which is constructed based on components of the second voltage level in the control circuit 104. Interconnect wire bonding is performed between the first wafer 101 and the second wafer 102 to enable signal interaction between the first interface control unit 11 and the second interface control unit 12.

[0044] In other words, in this embodiment, interface control units are designed in the high-voltage circuit 103 and the control circuit 104 respectively, and the signal interaction between the high-voltage circuit 103 and the control circuit 104 is realized based on the interconnection wire design between the two wafers. In this way, even if the chip is fabricated using two wafers, there is no need to worry about the problem of too many interconnects.

[0045] Furthermore, such as Figure 2 or Figure 3As shown, the first interface control unit 11 is fabricated on the first wafer 101 adjacent to the second wafer 102, and the second interface control unit 12 is fabricated on the second wafer 102 adjacent to the first wafer 101. In other words, the two interface control units are each located on an adjacent side of the two wafers, which facilitates the interconnection routing design between the two wafers and reduces the difficulty of wafer manufacturing.

[0046] Alternatively, in some other embodiments of this application, such as Figure 1B As shown, when the high voltage circuit 103 is built based on components of a first voltage level, such as 40V or 80V, and the control circuit 104 is built based on components of a third voltage level, such as 1.8V or 1.5V, the high voltage circuit 103 includes a third interface control unit 1033, and the control circuit 104 includes a fourth interface control unit 1044. The first wafer 101 and the second wafer 102 are interconnected by wire bonding to enable signal interaction between the third interface control unit 1033 and the fourth interface control unit 1044.

[0047] In other words, the third interface control unit 1033 may include components with a first voltage level, such as 40V or 80V, and the fourth interface control unit 1044 may include components with a third voltage level, such as 1.8V or 1.5V. The two are interconnected to achieve signal interaction.

[0048] Alternatively, in some other embodiments of this application, such as Figure 1C As shown, in the case where the high-voltage circuit 103 is constructed based on components of a first voltage level, such as 40V or 80V, and components of a second voltage level, such as 5V, and the control circuit 104 is constructed based on components of a third voltage level, such as 1.5V or 1.8V, the high-voltage circuit 103 includes a fifth interface control unit 1035, which is constructed based on components of the second voltage level in the high-voltage circuit 103. The control circuit 104 includes a sixth interface control unit 1046, which is constructed based on components of the third voltage level in the control circuit 104. Interconnect wire bonding is performed between the first wafer 101 and the second wafer 102 to enable signal interaction between the fifth interface control unit 1035 and the sixth interface control unit 1046.

[0049] That is to say, the fifth interface control unit 1035 may include components of a second voltage level, such as 5V, and the sixth interface control unit 1046 may include components of a third voltage level, such as 1.8V or 1.5V, and the two are interconnected to realize signal interaction.

[0050] Alternatively, in some other embodiments of this application, such as Figure 1DAs shown, in the case where the high-voltage circuit 103 is constructed based on components of a first voltage level, such as 40V or 80V, and the control circuit 104 is constructed based on components of a second voltage level, such as 5V, and components of a third voltage level, such as 1.5V or 1.8V, the high-voltage circuit 103 includes a seventh interface control unit 1037, which is constructed based on components of the first voltage level in the high-voltage circuit 103. The control circuit 104 includes an eighth interface control unit 1048, at least a portion of which is constructed based on components of the second voltage level in the control circuit 104. Interconnect wire bonding is performed between the first wafer 101 and the second wafer 102 to enable signal interaction between the seventh interface control unit 1037 and the eighth interface control unit 1048.

[0051] In other words, the seventh interface control unit 1037 may include components with a first voltage level, such as 40V or 80V, and the eighth interface control unit 1044 may include components with a second voltage level, such as 5V. The two are interconnected to achieve signal interaction.

[0052] Therefore, in the embodiments of this application, the operating voltage of the first voltage level component does not exceed the maximum withstand voltage of the third voltage level component, and the two voltage level components are designed on different wafers. Through interconnection routing design, it can be ensured that the two wafers can be packaged together.

[0053] Optionally, in one embodiment of this application, such as Figure 2 or Figure 3 As shown, the unit built based on the first voltage level components in the high voltage circuit 103 is fabricated on one side of the first wafer 101, and one side of the first wafer 101 is far away from the second wafer 102.

[0054] In other words, the high-voltage device of the first voltage level, such as 40V or 80V, is designed on one side of the first wafer 101 away from the second wafer 102. This leaves more space on the other side of the first wafer 101 adjacent to the second wafer 102, which facilitates the design of the second voltage level device on the first wafer 101. This makes wafer fabrication easier and reduces the complexity of the fabrication process.

[0055] In one embodiment of this application, such as Figure 2As shown, when the mixed-signal chip is a PSE chip, the unit built based on components of the first voltage level in the high-voltage circuit 103 includes a high-voltage ESD unit 31 and a high-voltage power device 32. The unit built based on components of the second voltage level in the high-voltage circuit 103 includes a first DAC control unit 33, a first ADC control unit 34, and a first register 35. The first DAC control unit 33, the first ADC control unit 34, and the first register 35 are located between the first interface control unit 11 and the unit built based on components of the first voltage level. The control circuit 104 also includes a PSE protocol control unit 41, a second register 42, a first MCU core 43, and a first storage control unit 44. The PSE protocol control unit 41, the second register 42, the first MCU core 43, and the first storage control unit 44 are fabricated on one side of the second wafer 102, and one side of the second wafer 102 is away from the first wafer 101.

[0056] Furthermore, at least one of the second interface control unit 12, PSE protocol control unit 41, second register 42, first MCU core 43, and first storage control unit 44 includes a component with a third voltage level.

[0057] Specifically, such as Figure 2 As shown, the PSE chip includes a first wafer 101 and a second wafer 102. The first wafer 101 is designed with a high-voltage ESD unit 31 and a high-voltage power device 32, such as a high-voltage power MOSFET. The components in the high-voltage ESD unit 31 and the high-voltage power device 32 are components with a first voltage level, such as 40V or 80V, and are located on the left side of the first wafer 101. A first interface control unit 11, built based on components with a second voltage level, such as 5V or 3.3V, in the high-voltage circuit 103, is located on the right side of the first wafer 101. Furthermore, a first DAC control unit 33, a first ADC control unit 34, and a first register 35, built based on components with a second voltage level, such as 5V or 3.3V, in the high-voltage circuit 103, are located in the middle of the first wafer 101, i.e., they can be designed between the circuit built based on components with a first voltage level, such as 40V or 80V, and the first interface control unit 11.

[0058] Therefore, the positions of the circuits built by the components of different voltage levels in the high voltage circuit 103 on the first wafer 101 can be reasonably designed to reduce the complexity of the fabrication process.

[0059] like Figure 2As shown, the second interface control unit 12, designed on the second wafer 102, is located near the left side of the second wafer 102 to facilitate interconnection with the first interface control unit 11. The first interface control unit 11 and the second interface control unit 12 are connected via a serial interface with interrupt capability and exchange reset signals. The control circuit 104 also includes a PSE protocol control unit 41, a second register 42, a first MCU core 43, and a first storage control unit 44. The first MCU core 43 and the first storage control unit 44 are located near the right side of the second wafer 102, while the PSE protocol control unit 41 and the second register 42 are located in the middle of the second wafer 102. Furthermore, at least one of the second interface control unit 12, the PSE protocol control unit 41, the second register 42, the first MCU core 43, and the first storage control unit 44 may include components with a third voltage level, such as 1.8V or 1.5V.

[0060] and Figure 4 Compared to the PSE chips with separate wafer designs in the related technologies shown, the PSE chip in this embodiment separates the high-voltage circuit section and the control circuit section into two wafer designs. As a result, the number of mask layers in the first wafer of the high-voltage circuit section can be reduced to less than 20 layers, and the number of mask layers in the second wafer of the control circuit section can be reduced to about 23 layers. Furthermore, it does not increase the wafer area by much, which greatly reduces the wafer manufacturing cost. The two wafers communicate with each other through interconnect wire bonding and are packaged in the same package, which is convenient for customers to use.

[0061] Alternatively, in another embodiment of this application, such as Figure 3 As shown, when the mixed-signal chip is a fast-charging protocol chip, the unit built based on components of the first voltage level in the high-voltage circuit 103 includes a high-voltage protection unit 36 ​​and a high-voltage loop control unit 37. The unit built based on components of the second voltage level in the high-voltage circuit 103 includes a second DAC control unit 38 and a third register 39. The second DAC control unit 38 and the third register 39 are located between the first interface control unit 11 and the unit built based on components of the first voltage level. The control circuit 104 also includes a fast-charging protocol unit 45, a second ADC control unit 46, a fourth register 47, a second MCU core 48, and a second storage control unit 49. The fast-charging protocol unit 45, the second ADC control unit 46, the fourth register 47, the second MCU core 48, and the second storage control unit 49 are fabricated on one side of the second wafer 102, and one side of the second wafer 102 is away from the first wafer 101.

[0062] Furthermore, at least one of the fast charging protocol unit 45, the second ADC control unit 46, the fourth register 47, the second MCU core 48, and the second storage control unit 49 includes components of a third voltage level.

[0063] Specifically, such as Figure 3 As shown, the fast charging protocol chip includes a first wafer 101 and a second wafer 102. The first wafer 101 is equipped with a high-voltage protection unit 36 ​​(e.g., a high-voltage ESD protection circuit) and a high-voltage loop control unit 37. The components in the high-voltage protection unit 36 ​​and the high-voltage loop control unit 37 are components with a first voltage level, such as 40V or 80V, and are located on the left side of the first wafer 101. The protocol pins of the fast charging protocol chip, such as identification pins CC1 and CC2, and data transmission pins DP and DM, are connected to the high-voltage protection unit 36 ​​so that the signals from the protocol pins are protected by high voltage before being transmitted through the first interface control unit 11. The first interface control unit 11, built based on components with a second voltage level, such as 5V or 3.3V, in the high-voltage circuit 103, is located on the right side of the first wafer 101. The second DAC control unit 38 and the second register 39, which are built based on components of the second voltage level, such as 5V or 3.3V in the high voltage circuit 103, are located in the middle of the first wafer 101, that is, they can be designed between the circuit built based on components of the first voltage level, such as 40V or 80V, and the first interface control unit 11.

[0064] Therefore, by rationally designing the positions of the circuits built with components of different voltage levels in the high-voltage circuit 103 on the first wafer 101, it is easy to reduce the difficulty of the fabrication process.

[0065] like Figure 3 As shown, the second interface control unit 12, designed on the second wafer 102, is located near the left side of the second wafer 102 to facilitate interconnection with the first interface control unit 11. The first interface control unit 11 and the second interface control unit 12 are connected via a serial interface with interrupt capability, and exchange protocol pin signals with each other, as well as transmit ADC signals from the first interface control unit 11 to the second interface control unit 12. The control circuit 104 also includes a fast charging protocol unit 45, a second ADC control unit 46, a fourth register 47, a second MCU core 48, and a second storage control unit 49. The second MCU core 48 and the second storage control unit 49 are located near the right side of the second wafer 102, while the fast charging protocol unit 45, the second ADC control unit 46, and the fourth register 47 are located in the middle of the second wafer 102. Furthermore, at least one of the fast charging protocol unit 45, the second ADC control unit 46, the fourth register 47, the second MCU core 48, and the second storage control unit 49 may include components with a third voltage level, such as 1.8V or 1.5V.

[0066] and Figure 5 Compared to the fast charging protocol chips in related technologies that use a separate wafer design, the fast charging protocol chip in this embodiment separates the high-voltage circuit section and the control circuit section into two wafer designs. This reduces the number of mask layers in the first wafer of the high-voltage circuit section to 19 layers and the number of mask layers in the second wafer of the control circuit section to 23 layers. In contrast, a USB fast charging protocol chip in related technologies using a single wafer design requires 40V high-voltage devices, and when fabricated using a 90nm BCD process platform, the number of mask layers in a single wafer is typically greater than 30 layers. Therefore, the fast charging protocol chip in this embodiment significantly reduces wafer manufacturing costs without increasing wafer area considerably. Furthermore, the two wafers interact via interconnect wire bonding, and are encapsulated in a single package, facilitating customer applications.

[0067] Optionally, in some embodiments of this application, the high-voltage circuit 103 is fabricated on the first wafer 101 using a first process, and the control circuit 104 is fabricated on the second wafer 102 using a second process, wherein the first process and the second process are different.

[0068] Specifically, the first process can be BCD process, and the second process can be CMOS process.

[0069] In other words, this application addresses the high manufacturing cost of high-voltage mixed-signal chips by separating the high-voltage circuit section and the MCU control circuit section of such chips into two separate wafer designs. The two wafers are then interconnected via wire bonding to achieve a single package. This eliminates the need for lower-voltage components, such as 1.8V or 1.5V components, in the high-voltage circuit section, and eliminates the need for high-voltage components, such as 40V or 80V components, in the MCU control circuit section. By selecting appropriate fabrication processes for each wafer, the number of mask layers for each circuit can be reduced, thereby lowering chip manufacturing costs without significantly increasing wafer area.

[0070] In summary, the mixed-signal chip according to the embodiments of this application fabricates a high-voltage circuit including components of a first voltage level on a first wafer, and a control circuit including components of a third voltage level on a second wafer. This allows the high-voltage circuit and the control circuit to be fabricated on two different wafers, thereby eliminating the need for a third voltage level component layer on the first wafer and a first voltage level component layer on the second wafer. This significantly reduces the number of mask layers required for each circuit. Furthermore, interconnect wire bonding is performed between the first and second wafers to achieve integrated packaging. This process does not require significantly increasing the wafer area and is not complex, thus reducing chip manufacturing costs.

[0071] like Figure 6 As shown, in some embodiments of this application, a power management system 1 is also provided, which includes the mixed-signal chip 100 described in the above embodiments.

[0072] According to the power management system 1 of this application embodiment, based on the mixed-signal chip 100 described in the above embodiment, by using two different wafers to fabricate the high-voltage circuit and control circuit during the design of the mixed-signal chip, and by interconnecting the two wafers to package them together, the first wafer can eliminate the component layer of the third voltage level and the second wafer can eliminate the component layer of the first voltage level, which can greatly reduce the number of mask layers in the fabrication of each circuit, and without increasing the wafer area by much, the fabrication process is not complicated, which greatly reduces the chip manufacturing cost.

[0073] In the description of this specification, the terms "one embodiment," "some embodiments," "embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0074] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make modifications, alterations, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A mixed-signal chip, characterized in that, include: First wafer; A high-voltage circuit fabricated on the first wafer, the high-voltage circuit being constructed based on components of a first voltage level, or based on components of the first voltage level and components of a second voltage level, wherein the first voltage level is greater than the second voltage level; Second wafer; A control circuit fabricated on the second wafer, the control circuit being built based on components of a third voltage level, or based on components of the second voltage level and components of the third voltage level, wherein the second voltage level is greater than the third voltage level; Interconnect wire bonding is performed between the first wafer and the second wafer to merge and package the first wafer and the second wafer.

2. The mixed-signal chip according to claim 1, characterized in that, In the case where the high-voltage circuit is constructed based on components of the first voltage level and components of the second voltage level, and the control circuit is constructed based on components of the second voltage level and components of the third voltage level, The high-voltage circuit includes a first interface control unit, which is built based on components of the second voltage level in the high-voltage circuit. The control circuit includes a second interface control unit, at least a portion of which is built based on components of a second voltage level in the control circuit. Interconnect wire bonding is performed between the first wafer and the second wafer to enable signal interaction between the first interface control unit and the second interface control unit.

3. The mixed-signal chip according to claim 1, characterized in that, In the case where the high-voltage circuit is constructed based on components of the first voltage level and the control circuit is constructed based on components of the third voltage level, the high-voltage circuit includes a third interface control unit and the control circuit includes a fourth interface control unit, wherein the first wafer and the second wafer are interconnected by wire bonding to enable signal interaction between the third interface control unit and the fourth interface control unit.

4. The mixed-signal chip according to claim 1, characterized in that, In the case where the high-voltage circuit is constructed based on components of the first voltage level and components of the second voltage level, and the control circuit is constructed based on components of the third voltage level, The high-voltage circuit includes a fifth interface control unit, which is built based on components of the second voltage level in the high-voltage circuit. The control circuit includes a sixth interface control unit, which is built based on components of the third voltage level in the control circuit. Interconnect wire bonding is performed between the first wafer and the second wafer to enable signal interaction between the fifth interface control unit and the sixth interface control unit.

5. The mixed-signal chip according to claim 1, characterized in that, In the case where the high-voltage circuit is constructed based on components of the first voltage level, and the control circuit is constructed based on components of the second voltage level and components of the third voltage level, The high-voltage circuit includes a seventh interface control unit, which is built based on components of the first voltage level in the high-voltage circuit. The control circuit includes an eighth interface control unit, at least a portion of which is built based on components of the second voltage level in the control circuit. Interconnect wire bonding is performed between the first wafer and the second wafer to enable signal interaction between the seventh interface control unit and the eighth interface control unit.

6. The mixed-signal chip according to claim 2, characterized in that, The first interface control unit is fabricated on a first wafer adjacent to the second wafer, and the second interface control unit is fabricated on a second wafer adjacent to the first wafer.

7. The mixed-signal chip according to claim 2, characterized in that, The unit built based on the first voltage level in the high voltage circuit is fabricated on one side of the first wafer, and one side of the first wafer is far away from the second wafer.

8. The mixed-signal chip according to claim 7, characterized in that, In the case where the mixed-signal chip is a PSE chip. The high-voltage circuit includes a high-voltage ESD unit and a high-voltage power device built based on the components of the first voltage level, and the high-voltage circuit includes a first DAC control unit, a first ADC control unit and a first register built based on the components of the second voltage level. The first DAC control unit, the first ADC control unit and the first register are located between the first interface control unit and the unit built based on the components of the first voltage level. The control circuit further includes a PSE protocol control unit, a second register, a first MCU core, and a first storage control unit. The PSE protocol control unit, the second register, the first MCU core, and the first storage control unit are fabricated on one side of the second wafer, and one side of the second wafer is away from the first wafer.

9. The mixed-signal chip according to claim 8, characterized in that, At least one of the second interface control unit, the PSE protocol control unit, the second register, the first MCU core, and the first storage control unit includes components of the third voltage level.

10. The mixed-signal chip according to claim 7, characterized in that, In the case where the mixed-signal chip is a fast-charging protocol chip. The high-voltage circuit includes a high-voltage protection unit and a high-voltage loop control unit, and the high-voltage circuit includes a second DAC control unit and a third register, with the second DAC control unit and the third register located between the first interface control unit and the unit built based on the components of the first voltage level. The control circuit further includes a fast charging protocol unit, a second ADC control unit, a fourth register, a second MCU core, and a second storage control unit. The fast charging protocol unit, the second ADC control unit, the fourth register, the second MCU core, and the second storage control unit are fabricated on one side of the second wafer, and one side of the second wafer is far away from the first wafer.

11. The mixed-signal chip according to claim 10, characterized in that, At least one of the fast charging protocol unit, the second ADC control unit, the fourth register, the second MCU core, and the second storage control unit includes components of the third voltage level.

12. The mixed-signal chip according to claim 10, characterized in that, The protocol pins of the fast charging protocol chip are connected to the high-voltage protection unit so that the signals from the protocol pins are protected by high voltage before being transmitted through the first interface control unit.

13. The mixed-signal chip according to any one of claims 1-12, characterized in that, The high-voltage circuit is fabricated on the first wafer using a first process, and the control circuit is fabricated on the second wafer using a second process, wherein the first process and the second process are different.

14. The mixed-signal chip according to claim 13, characterized in that, The first process is BCD process, and the second process is CMOS process.

15. A power management system, characterized in that, Includes a mixed-signal chip according to any one of claims 1-14.

Images