Bus transmitter, chip and electronic device

Abstract

A bus transmitter, chip and electronic device belong to the technical field of electronic circuit, through logic circuit in response to over-temperature signal, timeout signal and / or standby signal, stop based on sending signal output selection signal and digital signal; drive circuit in response to the disconnection of standby signal and selection signal, stop amplifying digital signal, and disconnect the output of differential signal; port circuit based on the disconnection of differential signal, stop clamping and amplifying differential signal, to disconnect the output of serial communication signal; In the case of access to invisible signal timeout and high temperature of chip, the internal drive circuit and port circuit stop working, thereby reducing the power consumption and improving the reliability.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a bus transmitter, chip and electronic device. Background Technology

[0002] Bus transmitters, such as CAN bus transmitters, are adapted to digital signal serial communication network protocols and serve as the physical interface between the CAN controller and the CAN bus. They are widely used in the fields of electronics and industrial control.

[0003] The relevant bus transmitter stops outputting serial communication signals when a standby signal is received; however, when the stealth signal times out or the chip temperature is too high, the internal driver module and port module continue to operate, resulting in high power consumption and poor reliability.

[0004] Therefore, the related bus transmitters have high power consumption and poor reliability. Summary of the Invention

[0005] The purpose of this application is to provide a bus transmitter, chip, and electronic device, which aims to solve the problems of small adjustment range, poor accuracy, and large layout area of ​​related bus transmitters.

[0006] This application provides a bus transmitter, including: A logic circuit, configured to stop outputting a selection signal and a digital signal based on a transmit signal in response to an over-temperature signal, a timeout signal, and / or a standby signal; a drive circuit, connected to the logic circuit, configured to stop amplifying the digital signal and disconnect the output of the differential signal in response to the disconnection of the standby signal and the selection signal; and a port circuit, connected to the drive circuit, configured to stop clamping and amplifying the differential signal based on the disconnection of the differential signal, thereby disconnecting the output of the serial communication signal.

[0007] This invention also provides a chip that includes the bus transmitter described above.

[0008] This invention also provides an electronic device, which includes the bus transmitter described above.

[0009] The beneficial effects of this invention compared to the prior art are as follows: Because the logic circuit stops outputting selection and digital signals based on the transmit signal in response to over-temperature signals, timeout signals, and / or standby signals; the drive circuit stops amplifying the digital signal and disconnects the differential signal output in response to the disconnection of the standby signal and the selection signal; the port circuit stops clamping and amplifying the differential signal based on the disconnection of the differential signal, thereby disconnecting the serial communication signal output; therefore, in the case of timeout of the access stealth signal and excessively high chip temperature, the internal drive circuit and port circuit stop working, thereby reducing power consumption and improving reliability. Attached Figure Description

[0010] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A schematic diagram of a bus transmitter provided in one embodiment of this application; Figure 2 A schematic diagram of a driving circuit in a bus transmitter provided in an embodiment of this application; Figure 3 A schematic diagram of the logic circuit in a bus transmitter provided in an embodiment of this application; Figure 4 This is a schematic diagram of another structure of a bus transmitter provided in one embodiment of this application; Figure 5 This is a schematic diagram of another structure of a bus transmitter provided in one embodiment of this application; Figure 6 This is a partial example circuit schematic of a bus transmitter provided in one embodiment of this application. Detailed Implementation

[0012] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0013] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0014] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0015] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0016] Figure 1 A schematic diagram of a bus transmitter provided in a preferred embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below: The aforementioned bus transmitter includes logic circuit 10, driver circuit 20, and port circuit 30.

[0017] Logic circuit 10, in response to an over-temperature signal, a timeout signal, and / or a standby signal, stops outputting a selection signal and a digital signal based on a transmit signal. Driver circuit 20, connected to logic circuit 10, stops amplifying the digital signal and disconnects the differential signal output in response to a standby signal disconnection and a selection signal. Port circuit 30, connected to driver circuit 20, stops clamping and amplifying the differential signal based on the disconnection of the differential signal, thereby disconnecting the serial communication signal output.

[0018] Among them, the over-temperature signal indicates that the temperature of the bus transmitter is greater than the preset temperature, and the timeout signal indicates that the duration of the transmitted signal as an invisible signal exceeds the preset duration.

[0019] The selection signal is active when an over-temperature signal, timeout signal, and / or standby signal are connected; it is inactive when the over-temperature signal, timeout signal, and / or standby signal are disconnected and the transmitted signal is inactive; and it is active when the over-temperature signal, timeout signal, and / or standby signal are disconnected and the transmitted signal is active.

[0020] Through the above technical solution, in the event of a timeout in the access to the stealth signal or an excessively high chip temperature, the internal drive circuit 20 and port circuit 30 stop working, thereby reducing power consumption and improving reliability.

[0021] like Figure 2As shown, the driving circuit 20 includes a disable circuit 21, a current mirror 22, and an amplifier circuit 23.

[0022] The disable circuit 21 is used to output a disable signal in response to a standby signal; the current mirror 22 is connected to the disable circuit 21 and is used to stop mirroring the bias current in response to the disconnection of the selection signal and / or the disable signal, so as to disconnect the output of the mirrored current; the amplifier circuit 23 is connected to the current mirror 22 and is used to stop amplifying the digital signal based on the mirrored current in response to the disconnection of the mirrored current, so as to disconnect the output of the differential signal.

[0023] Through the above technical solution, the current mirror 22 is turned off when the standby signal and the selection signal are disconnected; thus, the current mirror 22 only works when the over-temperature signal, timeout signal and / or standby signal are disconnected and the transmitted signal is a dominant signal, thereby reducing power consumption.

[0024] like Figure 3 As shown, the logic circuit 10 includes a first logic module 11 and a second logic module 12.

[0025] The first logic module 11 is used to output a disabling signal in response to an over-temperature signal, a timeout signal, and / or a standby signal; the second logic module 12 is connected to the first logic module 11 and the drive circuit 20, and is used to stop outputting selection signals and digital signals based on the transmission signal in response to the disabling signal.

[0026] The above technical solution realizes the control logic of the drive signal, and the circuit is simple and reliable.

[0027] like Figure 4 As shown, the bus transmitter also includes an equalization circuit 40.

[0028] The equalization circuit 40, connected to the drive circuit 20 and the port circuit 30, is used to clamp the common-mode level of the differential signal and the differential signal. Specifically, the port circuit 30 is used to stop clamping and amplifying the differential signal based on the disconnection of the clamped differential signal, so as to disconnect the output of the serial communication signal.

[0029] The above technical solution clamps the common-mode level and differential signal of the differential signal, thereby improving the stability and reliability of the bus transmitter.

[0030] like Figure 5 As shown, the differential signal includes a positive differential signal and a negative differential signal, and the serial communication signal includes a positive serial communication signal and a negative serial communication signal; the bus transmitter also includes a first protection circuit 50 and a second protection circuit 60.

[0031] The first protection circuit 50, connected to the drive circuit 20 and the port circuit 30, is configured to copy the positive serial communication signal according to a preset ratio to output a positive sampling signal, and to perform current limiting and short-circuit protection on the positive differential signal based on the positive sampling signal, so as to output a positive differential signal after current limiting and short-circuit protection; the second protection circuit 60, connected to the drive circuit 20 and the port circuit 30, is configured to copy the negative serial communication signal according to a preset ratio to output a negative sampling signal, and to perform current limiting and short-circuit protection on the negative differential signal based on the negative sampling signal, so as to output a negative differential signal after current limiting and short-circuit protection; the port circuit 30 is specifically used to stop clamping and amplifying the differential signal based on the disconnection of the differential signal after current limiting and short-circuit protection, so as to disconnect the output of the serial communication signal.

[0032] The above technical solutions provide current limiting and short-circuit protection for differential signals, thereby improving the stability and reliability of the bus transmitter.

[0033] Figure 6 The diagram illustrates a partial example circuit structure of a bus transmitter provided in an embodiment of the present invention. For ease of explanation, only the parts relevant to the embodiment of the present invention are shown, and are described in detail below: The disable signals include a first disable signal, a second disable signal, a third disable signal, and a fourth disable signal; the mirror currents include a first mirror current and a second mirror current; the current mirror 22 includes a first PMOS transistor Mp1, a second PMOS transistor Mp2, a third PMOS transistor Mp3, a fourth PMOS transistor Mp4, a fifth PMOS transistor Mp5, a sixth PMOS transistor Mp6, a seventh PMOS transistor Mp7, a first NMOS transistor Mn1, a second NMOS transistor Mn2, a third NMOS transistor Mn3, and a first resistor R1.

[0034] The sources of the first PMOS transistor Mp1, the second PMOS transistor Mp2, the third PMOS transistor Mp3, the fourth PMOS transistor Mp4, and the fifth PMOS transistor Mp5 are connected and together form the power supply terminal of the current mirror 22, which is connected to the first power supply VDD; the sources of the first NMOS transistor Mn1, the second NMOS transistor Mn2, and the third NMOS transistor Mn3 are connected to the power supply ground; the gate of the first PMOS transistor Mp1, the drain of the first PMOS transistor Mp2, and the second PMOS transistor Mp5 are connected to the power supply ground. The gate of Mp2, the gate of the third PMOS transistor Mp3, and the positive terminal of the first current source IBd are connected and together form the first control terminal of the current mirror 22, which is connected to the disable circuit 21 to receive the first disable signal; the drain of the second NMOS transistor Mn2, the gate of the fourth PMOS transistor Mp4, the drain of the fourth PMOS transistor Mp4, and the source of the fifth PMOS transistor Mp5 are connected and together form the second control terminal of the current mirror 22, which is connected to the disable circuit 21 to receive the second disable signal; the gate of the sixth PMOS transistor Mp6 forms The third control terminal of the current mirror 22 is connected to the disable circuit 21 to receive the third disable signal; the gate and drain of the first NMOS transistor Mn1, the gate of the second NMOS transistor Mn2, the gate of the third NMOS transistor Mn3, and the drain of the seventh PMOS transistor Mp7 are connected and together form the fourth control terminal of the current mirror 22, which is connected to the disable circuit 21 to receive the fourth disable signal; the drain of the fifth PMOS transistor Mp5 forms the first output terminal of the current mirror 22, which is connected to the amplifier circuit 23 to output... The first mirror current; the drain of the third NMOS transistor Mn3 forms the second output terminal of the current mirror 22, which is connected to the amplifier circuit 23 to output the second mirror current; the gate of the seventh PMOS transistor Mp7 forms the fifth control terminal of the current mirror 22, which is connected to the logic circuit 10 to receive the selection signal; the drain of the second PMOS transistor Mp2 is connected to the first terminal of the first resistor R1 and the source of the sixth PMOS transistor Mp6, and the second terminal of the first resistor R1 is connected to the drain of the third PMOS transistor Mp3 and the source of the seventh PMOS transistor Mp7.

[0035] The standby signal is inverted by the inverter and then output as a standby inverted signal; the disable circuit 21 includes the eighth PMOS transistor Mps8, the ninth PMOS transistor Mps9, the tenth PMOS transistor Mps10, the eleventh PMOS transistor Mps11, the fourth NMOS transistor Mn4, and the fifth NMOS transistor Mn5.

[0036] The drain and gate of the ninth PMOS transistor Mps9, the source of the tenth PMOS transistor Mps10, and the source of the eleventh PMOS transistor Mps11 are connected and together form the power supply terminal of the disable circuit 21, which is connected to the first power supply VDD; the source of the fourth NMOS transistor Mn4 and the source of the fifth NMOS transistor Mn5 are connected to the power supply ground; the gate of the fifth NMOS transistor Mn5, the gate of the tenth PMOS transistor Mps10, and the gate of the eleventh PMOS transistor Mps11 are connected and together form the first input terminal of the disable circuit 21 to receive the standby inverted signal; the gate of the fourth NMOS transistor Mn4 forms the second input terminal of the disable circuit 21 to receive the standby inverted signal. The first output terminal of the disable circuit 21 is formed by the drain of the tenth PMOS transistor Mps10, which is connected to the current mirror 22 to output the first disable signal; the second output terminal of the disable circuit 21 is formed by the drain of the eleventh PMOS transistor Mps11, which is connected to the current mirror 22 to output the second disable signal; the third output terminal of the disable circuit 21 is formed by the source of the ninth PMOS transistor Mps9, the gate of the eighth PMOS transistor Mps8, and the drain of the eighth PMOS transistor Mps8, which are connected together to form the third disable signal; the fourth output terminal of the disable circuit 21 is formed by the drain of the fourth NMOS transistor Mn4, which is connected to the current mirror 22 to output the fourth disable signal.

[0037] The differential signal includes a positive differential signal and a negative differential signal; the amplifier circuit 23 includes a twelfth PMOS transistor Mps12, a sixth NMOS transistor Mn6, and a first diode ds1.

[0038] The source of the twelfth PMOS transistor Mps12 is connected to the first power supply VDD, and the source of the sixth NMOS transistor Mn6 is connected to the power supply ground. The drain of the twelfth PMOS transistor Mps12 is connected to the anode of the first diode ds1. The gates of the twelfth PMOS transistor Mps12 and the sixth NMOS transistor Mn6 form the first input terminal of the amplifier circuit 23, which is connected to the logic circuit 10 to receive digital signals. The cathode of the first diode ds1 forms the second input terminal and the first output terminal of the amplifier circuit 23, which is connected to the logic circuit 10 and the port circuit 30 to receive the second mirror current and output a positive differential signal. The drain of the sixth NMOS transistor Mn6 forms the third input terminal and the second output terminal of the amplifier circuit 23, which is connected to the logic circuit 10 and the port circuit 30 to receive the first mirror current and output a negative differential signal.

[0039] The differential signal includes a positive differential signal and a negative differential signal; the equalization circuit 40 includes a thirteenth PMOS transistor Mps13, a seventh NMOS transistor Mn7, an eighth NMOS transistor Mn8, a first Zener diode Z1, a second Zener diode Z2, a second diode ds2, a third diode ds3, a fourth diode ds4, a fifth diode ds5, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5.

[0040] The positive terminal of the first Zener diode Z1 is connected to the first power supply VDD, and the negative terminal of the second Zener diode Z2 is connected to the power supply ground. The negative terminal of the first Zener diode Z1 is connected to the source of the thirteenth PMOS transistor Mps13. The drain of the thirteenth PMOS transistor Mps13 is connected to the drain of the seventh NMOS transistor Mn7, the first terminal of the second resistor R2, the first terminal of the third resistor R3, the first terminal of the fourth resistor R4, and the first terminal of the fifth resistor R5. The source of the seventh NMOS transistor Mn7 is connected to the positive terminal of the second Zener diode Z2. The second terminal of the second resistor R2 is connected to the positive terminal of the second diode ds2. The second terminal of the third resistor R3 is connected to the positive terminal of the third diode ds3. The second terminal of the fourth resistor R4 is connected to the positive terminal of the fourth diode ds4. The fifth... The second terminal of resistor R5 is connected to the anode of the fifth diode ds5, and the cathode of the fifth diode ds5 is connected to the drain of the eighth NMOS transistor Mn8. The gate of the thirteenth PMOS transistor Mps13, the cathode of the second diode ds2, and the anode of the fourth diode ds4 are connected to form the first input / output terminal of the equalization circuit 40, which is connected to the drive circuit 20 and the port circuit 30 to receive the positive differential signal and output the clamped positive differential signal. The gate of the seventh NMOS transistor Mn7, the anode of the third diode ds3, and the source of the eighth NMOS transistor Mn8 are connected to form the second input / output terminal of the equalization circuit 40, which is connected to the drive circuit 20 and the port circuit 30 to receive the negative differential signal and output the clamped negative differential signal.

[0041] The first protection circuit 50 includes a second current source N-IBp2, a third current source IBp3, a fourth current source IBp4, a fourteenth PMOS transistor MPH14, a fifteenth PMOS transistor Mp15, a sixteenth PMOS transistor Mp16, a seventeenth PMOS transistor Mp17, a first sampling resistor X-Rp, and a second sampling resistor Y-Rp.

[0042] The source of the seventeenth PMOS transistor Mp17, the first terminal of the first sampling resistor X-Rp, and the first terminal of the second sampling resistor Y-Rp are all connected to the first power supply VDD; the gate of the fourteenth PMOS transistor MPH14 and the drain of the seventeenth PMOS transistor Mp17 constitute the input and output terminals of the first protection circuit 50, which are connected to the drive circuit 20 and the port circuit 30 to receive the positive differential signal and output the positive differential signal after current limiting and short-circuit protection; the drain of the fourteenth PMOS transistor MPH14 constitutes the output terminal of the first protection circuit 50, which is connected to the port circuit 30 to output the positive sampling signal; the second terminal of the first sampling resistor X-Rp is connected to the second current source N- IBp2 is connected to the source of the fifteenth PMOS transistor Mp15. The second terminal of the second sampling resistor Y-Rp is connected to the source of the sixteenth PMOS transistor Mp16 and the source of the fourteenth PMOS transistor MPH14. The gate of the fifteenth PMOS transistor Mp15 is connected to the drain of the fifteenth PMOS transistor Mp15, the gate of the sixteenth PMOS transistor Mp16, and the third current source IBp3. The drain of the sixteenth PMOS transistor Mp16 is connected to the gate of the fourth current source IBp4 and the seventeenth PMOS transistor Mp17. The negative terminals of the second current source N-IBp2, the third current source IBp3, and the fourth current source IBp4 are all connected to the power supply ground.

[0043] The second protection circuit 60 includes a fifth current source N-IBn5, a sixth current source IBn6, a sixth current source Ibn7, an eighteenth PMOS transistor MPL18, a ninth NMOS transistor Mn9, a tenth NMOS transistor Mn10, an eleventh NMOS transistor Mn11, a third sampling resistor X-Rn, and a fourth sampling resistor Y-Rn. The positive terminals of the fifth current source N-IBn5, the sixth current source IBn6, and the sixth current source Ibn7 are all connected to the second power supply V1. The source of the eleventh NMOS transistor Mn11, the second terminal of the third sampling resistor X-Rn, and the second terminal of the fourth sampling resistor Y-Rn are all connected to the power supply ground. The gate of the eighteenth PMOS transistor MPL18 and the drain of the eleventh NMOS transistor Mn11 are connected and together form the input and output terminals of the second protection circuit 60, which are connected to the drive circuit 20 and the port circuit 3. 0 connection, to receive the negative differential signal and output the negative differential signal after current limiting and short circuit protection; the drain of the eighteenth PMOS transistor MPL18 forms the output terminal of the second protection circuit 60, which is connected to the port circuit 30 to output the negative sampling signal; the source of the eighteenth PMOS transistor MPL18 is connected to the source of the tenth NMOS transistor Mn10 and the first end of the fourth sampling resistor Y-Rn; the negative terminal of the sixth current source Ibn7 is connected to the drain of the tenth NMOS transistor Mn10 and the gate of the eleventh NMOS transistor Mn11; the negative terminal of the sixth current source IBn6 is connected to the drain of the ninth NMOS transistor Mn9, the gate of the ninth NMOS transistor Mn9 and the gate of the tenth NMOS transistor Mn10; the negative terminal of the fifth current source N-IBn5 is connected to the source of the ninth NMOS transistor Mn9 and the first end of the third sampling resistor X-Rn.

[0044] The first logic module 11 includes a first NOR gate U1, a second NOR gate U2, a first OR gate U3, and a second OR gate U4. The first input terminals of the first NOR gate U1 and the first OR gate U3 are connected and together constitute the first input terminal of the first logic module 11 to receive an over-temperature signal. The second input terminal of the second OR gate U4 constitutes the second input terminal of the first logic module 11 to receive a timeout signal. The third input terminal of the second OR gate U4 constitutes the third input terminal of the first logic module 11 to receive a standby signal. The second input terminal of the second NOR gate U2 constitutes the fourth input terminal of the first logic module 11 to receive a transmission signal. The output terminal of the first NOR gate U1 is connected to the first input terminal of the second NOR gate U2, the second input terminal of the first NOR gate U1 is connected to the output terminal of the second NOR gate U2 and the first input terminal of the first OR gate U3, and the output terminal of the first OR gate U3 is connected to the first input terminal of the second OR gate U4. The output terminal of the second OR gate U4 constitutes the output terminal of the first logic module 11 and is connected to the second logic module 12 to output a disabling signal.

[0045] The second logic module 12 includes a third NOR gate U5, a first NOT gate U6, a second NOT gate U7, and a third NOT gate U8. The first input terminal of the third NOR gate U5 constitutes the first input terminal of the second logic module 12 and is connected to the first logic module to receive a disabling signal. The second input terminal of the third NOR gate U5 constitutes the first input terminal of the second logic module 12 to receive a transmission signal. The output terminal of the third NOR gate U5 is connected to the input terminal of the first NOT gate U6. The input terminals of the first NOT gate U6 and the second NOT gate U7 are connected and together constitute the first output terminal of the second logic module 12, which is connected to the driving circuit 20 to output a selection signal. The output terminal of the second NOT gate U7 and the input terminal of the third NOT gate U8 are connected and together constitute the second output terminal of the second logic module 12, which is connected to the driving circuit 20 to output a positive digital signal. The output terminal of the third NOT gate U8 constitutes the third output terminal of the second logic module 12 and is connected to the driving circuit 20 to output a negative digital signal.

[0046] Port circuit 30 includes a positive port circuit 30 and a negative port circuit 30. The positive port circuit 30, connected to the positive amplifier circuit 23, is used to stop clamping and amplifying the positive differential signal based on the disconnection of the positive differential signal, thereby disconnecting the output of the positive serial communication signal. The negative port circuit 30, connected to the negative amplifier circuit 23, is used to stop clamping and amplifying the negative differential signal based on the disconnection of the negative differential signal, thereby disconnecting the output of the negative serial communication signal.

[0047] The positive terminal circuit 30 includes a first power transistor MPH1, a first Schottky diode dsH, and a first power diode dpH. The anode of the first Schottky diode dsH is connected to the first power supply VDD, the cathode of the first Schottky diode dsH is connected to the anode of the first power diode dpH, and the cathode of the first power diode dpH is connected to the source of the first power transistor MPH1. The drain of the first power transistor MPH1 forms the output terminal of the positive terminal circuit 30 to output a positive serial communication signal. The gate of the first power transistor MPH1 forms the input terminal of the positive terminal circuit 30 and is connected to the driving circuit 20 to receive a positive differential signal.

[0048] The negative terminal circuit 30 includes a second power transistor MPL1, a second Schottky diode dsL, and a second power diode dpL. The anode of the second Schottky diode dsL forms the output terminal of the negative terminal circuit 30 to output a negative serial communication signal. The source of the second power transistor MPL1 is connected to the power supply ground. The cathode of the second Schottky diode dsL is connected to the anode of the second power diode dpL. The cathode of the second power diode dpL is connected to the drain of the second power transistor MPL1. The gate of the second power transistor MPL1 forms the input terminal of the negative terminal circuit 30 and is connected to the drive circuit 20 to receive a negative differential signal.

[0049] The following is based on the working principle. Figure 6 Further explanation is provided below: In normal operating mode, when the circuit does not trigger any protection mechanism, the over-temperature signal TSC, the timeout signal TOC, and the standby signal PD are all low. At this time, the latch composed of the first NOR gate U1 and the second NOR gate U2 is in the reset state, and the output is low. The transmit signal TXD can pass through the NOR gate, OR gate, and subsequent inverter link without interference, sequentially generating the selection signal Func_Selec, the positive digital signal Vg_Hb, and the negative digital signal Vg_Lb, driving the subsequent MOSFET to realize normal differential transmission of the CAN bus.

[0050] When an over-temperature fault occurs in the circuit, the over-temperature signal TSC is set to high, the latch latches the fault state, and the latch output remains high, resulting in a high-level disable signal and a high-level drive selection signal Func_Selec. Furthermore, when a bus malfunction causes the positive serial communication signal to remain below a preset value for a duration exceeding a set threshold, the timeout signal TOC is set to high, and the direct drive selection signal Func_Selec is set to high. Similarly, the standby signal PD is set to high, and the direct drive selection signal Func_Selec is set to high.

[0051] When the select signal Func_Selec goes high, it immediately blocks the transmission path of the transmit signal TXD, shuts down the drive circuit 20 link, and keeps the CAN bus in a recessive state to prevent device damage or bus malfunction. Specifically, the standby PD, the over-temperature signal TSC latch output, and the timeout signal TOC have the same priority in shielding the transmit signal TXD; a high level for any of these signals can force the bus into a recessive state.

[0052] It is worth emphasizing that, in order to meet the low power consumption requirement, when the standby signal PD is high, in addition to shielding the transmit signal TXD, the circuit will also simultaneously turn off the current mirror 22, so that the circuit enters a zero static power consumption state, significantly reducing system power consumption in fault protection or low power mode. Specifically, when the circuit does not trigger protection or low power shutdown, the standby signal PD is low and the selection signal Func_Selec (equivalent to a slightly delayed transmit signal TXD) is low (the serial communication signal is in a dominant state), and the drive circuit 20 enters the normal operating state. At this time, the inverter outputs a high-level standby reverse signal (PDN), the tenth PMOS transistor Mps10 and the eleventh PMOS transistor Mps11 are turned off, and the fifth NMOS transistor Mn5 is working normally, providing a low-impedance ground path for the current mirror 22 array. This, in turn, enables the sixth PMOS transistor Mp6, the eighth PMOS transistor Mp8, and the ninth PMOS transistor Mp9 in the auxiliary bias branch to work normally. The selection signal Func_Selec is active low, meaning the seventh PMOS transistor Mp7 is turned on. The current output from the first current source IBd flows through Mp1, and after being replicated by the current mirror 22 array, it becomes the second PMOS transistor Mp2, the third PMOS transistor Mp3, and the fourth PMOS transistor Mp9. PMOS transistors Mp4 and Mp5 provide stable bias current in their respective branches. The first resistor R1 enhances the current mirror 22's replication accuracy through source-level negative feedback, reducing the impact of process deviations. According to the low-level output of the selection signal Func_Selec in the front-end logic circuit 10, the positive digital signal Vg_Hb and the negative digital signal Vg_Lb are high and low, respectively, thereby turning on the sixth NMOS transistor Mn6 and the twelfth PMOS transistor Mp12 and receiving the bias current. This generates a stable bias voltage for the power transistors in the port circuit 30, driving the power transistors in the subsequent port circuit 30 to switch normally, thus realizing normal bus communication.

[0053] When either of the following two conditions occurs, the entire circuit module enters a shutdown protection state: 1) When the standby signal PD is high, the fourth NMOS transistor Mn4 is turned on, pulling down the gate levels of the first NMOS transistors Mn1, the second NMOS transistor Mn2, and the third NMOS transistor Mn3, thus turning off the current mirror array 22; the inverter output (PDN) is low, the tenth PMOS transistor Mps10 and the eleventh PMOS transistor Mps11 are turned on, pulling up the gate levels of the current mirrors 22 (Mp1, Mp2, Mp3, Mp4, Mp5), thereby turning off the current mirror array 22; the second NMOS transistor Mn2 is turned off. 2) When the selection signal Func_Selec is high (TXD recessive state), the seventh PMOS transistor Mp7 is not turned on, and the positive digital signal Vg_Hb and the negative digital signal Vg_Lb are low and high respectively, and the sixth NMOS transistor Mn6 and the twelfth PMOS transistor Mp12 are not turned on.

[0054] It should be noted that the symmetry of the output signal of the bus transmitter is very important. Controlling the opening and closing of the port circuit 30 through the f and g branches in the driver circuit 20 is equivalent to controlling the dominance-recession switching of the serial communication signal. From the gate signals Vg_H and Vg_L of the power transistor in the amplifier circuit 23, it can be observed that when switching from recessive to dominant, the current mirror 22 is used to limit the current and control the power transistor to turn on; when switching from dominant to recessive, the power transistor is directly controlled to turn off through the switch.

[0055] In the recessive state during normal operation (PDN is high), the equalization circuit 40 is turned on. At this time, the first Zener diode Z1 and the second Zener diode Z2 hard clamp the first power supply VDD and the power ground GND respectively to cope with rapid surges and ESD impacts, protecting the gate from instantaneous high voltage damage. The fourth diode ds4, the fourth resistor R4, the fifth resistor R5, the fifth diode ds5, and the branch of the eighth NMOS transistor Mn8 are turned on, maintaining a stable common-mode level Vg_CM. At this time, the common-mode level Vg_CM is clamped at a stable common-mode level. When the low-power mode is turned off (PDN is low), the gate of the eighth NMOS transistor Mn8 is turned off at a low level, and the clamping branch j is cut off. At this time, only the third diode ds3 and the fourth diode ds4 maintain the hard clamping function, and the intermediate branch i has no quiescent current. The quiescent power consumption of the entire clamping protection circuit is zero, consuming no additional current.

[0056] The port circuit 30 includes high-voltage power transistors (MPH1, MPL1) to provide driving capability for the bus (such as CANH / CANL). The power transistor dimensions are designed proportionally to ensure that the on-resistance and load capacity meet the bus voltage specifications. The withstand voltage protection diodes dsH / dpH (CANH) and dsL / dpL (CANL) are stacked structures of Schottky diodes and power diodes, which can withstand the wide voltage range requirements of the bus with positive and negative high voltages, while controlling substrate leakage current. The gate clamping diode dz5 is a Zener diode that clamps the gate of the first power transistor MPH1 to prevent the gate from being over-voltaged and broken down due to high voltage backflow from the bus.

[0057] The protection circuit is divided into a first protection circuit 50 for the CANH channel (high-side upper transistor) and a second protection circuit 60 for the CANL channel (low-side lower transistor). The upper and lower transistors have a symmetrical structure, consisting of sampling current transistors (MPH14 and MPL18), differential amplifier circuit 23, sampling resistors, and a feedback control loop. It proportionally replicates the current flowing through the power transistor in port circuit 30, amplifies it, and then uses feedback to adjust the gate drive voltage of the power transistor to achieve dynamic current limiting. The fourteenth PMOS transistor, MPH14, and the eighteenth PMOS transistor, MPL18, are sampling current transistors proportional to the main power transistor, used to replicate the output current for current sampling. dz1, dz2, dz3, and dz4 are Zener diodes used to clamp the voltage at the nodes of amplifier circuit 23 and the gate of the power transistor to prevent overvoltage damage. N-IBp2, IBp3, IBp4, N-IBn5, IBn6, and IBn7 are bias current sources (standard design values) providing a stable bias current for differential amplifier circuit 23. X-Rp, Y-Rp, X-Rn, and Y-Rn are sampling resistors that convert the sampled current into a voltage signal for current detection.

[0058] Taking the CANL (negative serial communication signal) terminal as an example, where IBn is the external standard bias current value, the design value of the short-circuit current satisfies the following formula:

[0059] Among them I o(sc) The current of the negative serial communication signal, V gs_Mn9 V is the source voltage of the ninth NMOS transistor Mn9. gs_Mn10 This is the source voltage of the tenth NMOS transistor, Mn10.

[0060] In normal communication mode, the power transistors (MPH1 and MPL1) turn on or off according to the differential signals (Vg_H and Vg_L), outputting a dominant or recessive differential signal. At this time, the output current is within the normal range. The current is relatively small due to the use of current transistors MPH14 / MPL18 for replication, and the amplifier circuit 23 has no feedback action. The gate drive voltage of the power transistors remains normal, and the circuit operates stably. The diode stack structure at the bus port can withstand the bus voltage normally, without overvoltage or leakage issues.

[0061] When a short-circuit fault occurs at the port, the output current of the power transistor increases sharply. The sampling current transistor synchronously replicates this current, forming the sampling current Isampling. Current flows through the sampling resistors X-Rp / Y-Rp or X-Rn / Y-Rn, generating a voltage signal that is sent to amplifier circuit 23. Amplifier circuit 23 amplifies this signal and adjusts the differential signal Vg_H or Vg_L (gate drive voltage) through a feedback loop. For the positive serial communication signal (such as CANH) channel, when the short-circuit current exceeds the limit, the feedback signal raises the gate voltage of MPH1, increasing the conduction of the PMOS power transistor and limiting the output current. Simultaneously, the Zener diode clamps the circuit nodes to prevent voltage fluctuations from damaging the devices. The entire closed-loop control process dynamically adjusts to limit the short-circuit current within a safe range, preventing the power transistor from burning out. For the negative serial communication signal channel, the feedback signal lowers the gate voltage of MPL1, increasing the on-resistance of the NMOS power transistor and limiting the output current.

[0062] For the bus port module, the main considerations are high-voltage protection and ultra-low leakage current. The bus port uses a stacked structure of Schottky diodes and power diodes, capable of withstanding a wide positive and negative voltage range. The Schottky diodes dsH / dsL have low forward voltage drop and fast response characteristics, which can quickly conduct to suppress negative voltage surges at the port while reducing forward conduction losses. The power diodes dpH / dpL have high reverse breakdown voltage and can withstand high forward overvoltages, while also being compatible with the substrate's extremely low reverse leakage current. Taking the positive serial communication signal port as an example, when the CANH port voltage exceeds the safety threshold, the power diode dpH breaks down in the reverse direction. Combined with the fast response of the Schottky diode dsH, the port voltage is clamped at a safe level, preventing high voltage from damaging the internal circuitry. When the CANH port is subjected to negative voltage, the Schottky diode dsH conducts in the forward direction, quickly dissipating the negative voltage current. At the same time, the power transistor MPH1 shares the negative voltage stress, preventing the device from being damaged by negative voltage breakdown. In addition, by optimizing the number of diodes connected in series, the substrate leakage current can be controlled within the design margin, thus meeting the low leakage current requirement at the port.

[0063] This invention also provides a chip that includes the bus transmitter described above.

[0064] This invention also provides an electronic device that includes the bus transmitter described above.

[0065] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0066] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A bus transmitter, characterized in that, include: Logic circuitry for stopping the output of selection signals and digital signals based on the transmitted signal in response to over-temperature signals, timeout signals, and / or standby signals; A driving circuit, connected to the logic circuit, is used to stop amplifying the digital signal and disconnect the output of the differential signal in response to the disconnection of the standby signal and the selection signal. A port circuit, connected to the drive circuit, is used to stop clamping and amplifying the differential signal based on the disconnection of the differential signal, thereby disconnecting the output of the serial communication signal.

2. The bus transmitter as described in claim 1, characterized in that, The driving circuit includes: A power-disabling circuit is used to output a power-disabling signal in response to a standby signal. A current mirror, connected to the disable circuit, is used to stop mirroring the bias current in response to the disconnection of the selection signal and / or the disable signal, so as to disconnect the output of the mirrored current; An amplifier circuit, connected to the current mirror, is used to stop amplifying the digital signal based on the mirror current in response to the disconnection of the mirror current, thereby disconnecting the output of the differential signal.

3. The bus transmitter as described in claim 2, characterized in that, The power-disabling signals include a first power-disabling signal, a second power-disabling signal, a third power-disabling signal, and a fourth power-disabling signal; the mirror current includes a first mirror current and a second mirror current; The current mirror includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a first resistor; The sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are connected and together form the power supply terminal of the current mirror, which is connected to the first power supply. The source of the first NMOS transistor, the source of the second NMOS transistor, and the source of the third NMOS transistor are all connected to the power supply ground. The gate, drain, gate, and gate of the first PMOS transistor, and the positive terminal of the first current source are connected and together form the first control terminal of the current mirror, which is connected to the disable circuit to receive the first disable signal. The drain of the second NMOS transistor, the gate of the fourth PMOS transistor, the drain of the fourth PMOS transistor, and the source of the fifth PMOS transistor are connected and together form the second control terminal of the current mirror, which is connected to the disable circuit to receive the second disable signal; The gate of the sixth PMOS transistor forms the third control terminal of the current mirror and is connected to the disable circuit to receive the third disable signal; The gate of the first NMOS transistor, the drain of the first NMOS transistor, the gate of the second NMOS transistor, the gate of the third NMOS transistor, and the drain of the seventh PMOS transistor are connected and together form the fourth control terminal of the current mirror, which is connected to the disable circuit to receive the fourth disable signal. The drain of the fifth PMOS transistor forms the first output terminal of the current mirror, which is connected to the amplifier circuit to output the first mirror current. The drain of the third NMOS transistor becomes the second output terminal of the current mirror and is connected to the amplifier circuit to output the second mirror current; The gate of the seventh PMOS transistor forms the fifth control terminal of the current mirror and is connected to the logic circuit to receive the selection signal; The drain of the second PMOS transistor is connected to the first terminal of the first resistor and the source of the sixth PMOS transistor, and the second terminal of the first resistor is connected to the drain of the third PMOS transistor and the source of the seventh PMOS transistor.

4. The bus transmitter as described in claim 3, characterized in that, The standby signal is inverted by an inverter and then output as a standby inverted signal; the power-disable circuit includes an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; The drain, gate, source, and source of the ninth PMOS transistor are connected and together form the power supply terminal of the power-disabled circuit, which is connected to the first power supply. The source of the fourth NMOS transistor and the source of the fifth NMOS transistor are both connected to the power supply ground; The gates of the fifth NMOS transistor, the tenth PMOS transistor, and the eleventh PMOS transistor are connected and together form the first input terminal of the disable circuit to receive the standby inverted signal. The gate of the fourth NMOS transistor forms the second input terminal of the disable circuit to receive the standby signal; The drain of the tenth PMOS transistor forms the first output terminal of the power-disable circuit and is connected to the current mirror to output the first power-disable signal. The drain of the eleventh PMOS transistor forms the second output terminal of the power-disable circuit, which is connected to the current mirror to output the second power-disable signal; The source of the ninth PMOS transistor, the gate of the eighth PMOS transistor, and the drain of the eighth PMOS transistor are connected and together form the third output terminal of the disable circuit, which is connected to the current mirror to output the third disable signal. The drain of the fourth NMOS transistor forms the fourth output terminal of the disable circuit, which is connected to the current mirror to output the fourth disable signal.

5. The bus transmitter as described in claim 4, characterized in that, The differential signal includes a positive differential signal and a negative differential signal; the amplifier circuit includes a twelfth PMOS transistor, a sixth NMOS transistor, and a first diode; The source of the twelfth PMOS transistor is connected to the first power supply, and the source of the sixth NMOS transistor is connected to the power supply ground; the drain of the twelfth PMOS transistor is connected to the positive terminal of the first diode. The gate of the twelfth PMOS transistor and the gate of the sixth NMOS transistor constitute the first input terminal of the amplifier circuit, which is connected to the logic circuit to receive the digital signal. The cathode of the first diode forms the second input terminal and the first output terminal of the amplifier circuit, and is connected to the logic circuit and the port circuit to receive the second mirror current and output a positive differential signal; The drain of the sixth NMOS transistor forms the third input terminal and the second output terminal of the amplifier circuit, and is connected to the logic circuit and the port circuit to receive the first mirror current and output a negative differential signal.

6. The bus transmitter as claimed in claim 1, characterized in that, The logic circuit includes: The first logic module is configured to output a disabling signal in response to the over-temperature signal, the timeout signal, and / or the standby signal. The second logic module, connected to the first logic module and the driving circuit, is used to stop outputting the selection signal and the digital signal based on the transmission signal in response to the disabling signal.

7. The bus transmitter as claimed in claim 1, characterized in that, Also includes: An equalization circuit, connected to the driving circuit and the port circuit, is used to clamp the common-mode level of the differential signal and the differential signal; The port circuit is specifically used to disconnect the differential signal after clamping, stop clamping and amplifying the differential signal, and disconnect the output of the serial communication signal.

8. The bus transmitter as described in claim 7, characterized in that, The differential signal includes a positive differential signal and a negative differential signal; the equalization circuit includes a thirteenth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a first Zener diode, a second Zener diode, a second diode, a third diode, a fourth diode, a fifth diode, a second resistor, a third resistor, a fourth resistor, and a fifth resistor; The positive terminal of the first Zener diode is connected to the first power supply, and the negative terminal of the second Zener diode is connected to the power supply ground. The negative terminal of the first Zener diode is connected to the source of the thirteenth PMOS transistor. The drain of the thirteenth PMOS transistor is connected to the drain of the seventh NMOS transistor, the first terminal of the second resistor, the first terminal of the third resistor, the first terminal of the fourth resistor, and the first terminal of the fifth resistor. The source of the seventh NMOS transistor is connected to the positive terminal of the second Zener diode. The second terminal of the second resistor is connected to the positive terminal of the second diode. The second terminal of the third resistor is connected to the positive terminal of the third diode. The second terminal of the fourth resistor is connected to the positive terminal of the fourth diode. The second terminal of the fifth resistor is connected to the positive terminal of the fifth diode. The negative terminal of the fifth diode is connected to the drain of the eighth NMOS transistor. The gate of the thirteenth PMOS transistor, the cathode of the second diode, and the anode of the fourth diode ds4 are connected to form the first input / output terminal of the equalization circuit, which is connected to the driving circuit and the port circuit to receive the positive differential signal and output the clamped positive differential signal; the gate of the seventh NMOS transistor, the anode of the third diode, and the source of the eighth NMOS transistor are connected to form the second input / output terminal of the equalization circuit, which is connected to the driving circuit and the port circuit to receive the negative differential signal and output the clamped negative differential signal.

9. The bus transmitter as claimed in claim 1, characterized in that, The differential signal includes a positive differential signal and a negative differential signal; the serial communication signal includes a positive serial communication signal and a negative serial communication signal; the bus transmitter further includes: The first protection circuit, connected to the driving circuit and the port circuit, is configured to copy the positive serial communication signal according to a preset ratio to output the positive sampling signal, and to perform current limiting and short-circuit protection on the positive differential signal based on the positive sampling signal, so as to output the positive differential signal after current limiting and short-circuit protection. The second protection circuit is connected to the driving circuit and the port circuit, and is configured to copy the negative serial communication signal according to a preset ratio to output the negative sampling signal, and to perform current limiting and short-circuit protection on the negative differential signal based on the negative sampling signal, so as to output the negative differential signal after current limiting and short-circuit protection. The port circuit is specifically used to disconnect the differential signal after current limiting and short-circuit protection, stop clamping and amplifying the differential signal, and disconnect the output of the serial communication signal.

10. The bus transmitter as claimed in claim 9, characterized in that, The first protection circuit includes a second current source, a third current source, a fourth current source, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, a first sampling resistor, and a second sampling resistor; The source of the seventeenth PMOS transistor, the first terminal of the first sampling resistor, and the first terminal of the second sampling resistor Y-Rp are all connected to the first power supply. The gate of the fourteenth PMOS transistor and the drain of the seventeenth PMOS transistor constitute the input and output terminals of the first protection circuit, which are connected to the driving circuit and the port circuit to receive the positive differential signal and output the positive differential signal after current limiting and short circuit protection. The drain of the fourteenth PMOS transistor forms the output terminal of the first protection circuit, which is connected to the port circuit to output the positive sampling signal. The second end of the first sampling resistor is connected to the second current source and the source of the fifteenth PMOS transistor. The second end of the second sampling resistor is connected to the source of the sixteenth PMOS transistor and the source of the fourteenth PMOS transistor. The gate of the fifteenth PMOS transistor is connected to the drain of the fifteenth PMOS transistor, the gate of the sixteenth PMOS transistor, and the third current source. The drain of the sixteenth PMOS transistor is connected to the fourth current source and the gate of the seventeenth PMOS transistor. The negative terminals of the second current source, the third current source, and the fourth current source are all connected to the power supply ground. The second protection circuit includes a fifth current source, a sixth current source, a sixth current source, an eighteenth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a third sampling resistor, and a fourth sampling resistor; The positive terminals of the fifth current source, the sixth current source, and the sixth current source are all connected to the second power source. The source of the eleventh NMOS transistor, the second terminal of the third sampling resistor, and the second terminal of the fourth sampling resistor are all connected to the power supply ground; The gate of the eighteenth PMOS transistor and the drain of the eleventh NMOS transistor are connected and together form the input and output terminals of the second protection circuit. They are connected to the driving circuit and the port circuit to receive the negative differential signal and output the negative differential signal after current limiting and short circuit protection. The drain of the eighteenth PMOS transistor forms the output terminal of the second protection circuit, which is connected to the port circuit to output the negative sampling signal. The source of the eighteenth PMOS transistor is connected to the source of the tenth NMOS transistor and the first terminal of the fourth sampling resistor. The negative terminal of the sixth current source is connected to the drain of the tenth NMOS transistor and the gate of the eleventh NMOS transistor. The negative terminal of the sixth current source is connected to the drain of the ninth NMOS transistor, the gate of the ninth NMOS transistor, and the gate of the tenth NMOS transistor. The negative terminal of the fifth current source is connected to the source of the ninth NMOS transistor and the first terminal of the third sampling resistor.

11. A chip, characterized in that, The chip includes a bus transmitter as described in any one of claims 1 to 10.

12. An electronic device, characterized in that, The electronic device includes a bus transmitter as described in any one of claims 1 to 10.

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