A software control-based RS-485 bus polarity adaptive identification method and system

Abstract

The application discloses a RS-485 bus polarity self-adaptive identification method and system based on software control, which is applied to a communication system comprising a microcontroller, an analog switch and a RS-485 transceiver, and comprises the following steps: after the system is powered on, the microcontroller outputs a first level signal to a gate end of the analog switch through a GPIO pin of the microcontroller, and controls the analog switch to be in a first gate state, the application discloses discarding an expensive hardware self-correcting RS-485 transceiver (such as SN65HVD888), and instead adopting a most basic standard RS-485 chip, utilizing a UART hardware frame error interrupt and a parity check error interrupt of the MCU as a trigger signal for triggering polarity inversion, without waiting for a long data packet to be completely received and verified to fail, and the detection and switching can be completed within a character period (microsecond to millisecond level, depending on the baud rate) of the first distorted character.

Description

[0001] This invention belongs to the field of industrial automation control and embedded serial communication technology, specifically a software-controlled RS-485 bus polarity adaptive identification method and system. Background Technology

[0002] Due to its advantages such as strong common-mode interference resistance, long transmission distance, and simple structure, the RS-485 bus has been widely used in industrial control, building automation, power meter reading and other fields. The standard RS-485 bus adopts two-wire differential signal transmission, consisting of A line (non-inverted signal) and B line (inverted signal).

[0003] In actual construction sites, due to complicated wiring, unclear cable markings, or negligence by construction personnel, it is very easy to have a physical polarity error where the A and B lines are reversed. That is, the A line of the master node is incorrectly connected to the B line of the slave node, and the B line of the master node is incorrectly connected to the A line of the slave node. Once the wire sequence is reversed, the original "idle high level" will become a "low level" at the receiving end, causing the logical polarity of the serial communication to be completely reversed. The device will generate continuous frame errors or be unable to receive data, causing the entire communication network to be paralyzed. Troubleshooting such faults on site is often time-consuming and labor-intensive.

[0004] To solve this problem, existing technologies typically employ the following two methods, but each has significant drawbacks: Option 1: Use a dedicated RS-485 transceiver chip with built-in automatic polarity correction (such as SN65HVD888). The drawback is that the procurement cost of this type of dedicated chip is several times higher than that of ordinary standard RS-485 chips (such as SP3485, MAX485). In large-scale distributed I / O systems or dense node devices, it will significantly increase the hardware BOM cost. In addition, this type of chip completely depends on the bus being in a clearly biased state when powered on. If there is a lack of active bias resistors in the network or in a complex noise environment, misjudgment is likely to occur. Option 2: Relying on manual inspection and wiring changes using a multimeter at each node. Its drawbacks are: extremely high maintenance costs, heavy reliance on manual experience, and inability to achieve on-site self-healing and maintenance-free operation. It is evident that existing technologies suffer from technical defects such as high cost, high hardware resource requirements, reliance on manual labor, slow switching speed, or poor versatility. To address this, this application proposes a software-controlled RS-485 bus polarity adaptive identification method and system. Summary of the Invention: The purpose of this invention is to provide a software-controlled RS-485 bus polarity adaptive identification method and system to solve the above-mentioned problems. It does not require expensive dedicated hardware and is based entirely on low-cost, common standard RS-485 chips and analog switches. Through the software state machine control of a microcontroller (MCU), it realizes automatic identification and self-healing communication of RS-485 bus polarity reversal. Without significantly increasing hardware costs, it solves the communication failure caused by reversed A and B lines in industrial fields, improves system fault tolerance, and reduces maintenance costs.

[0005] To address the above problems, the present invention provides a technical solution: A software-controlled RS-485 bus polarity adaptive identification method, applied to a communication system including a microcontroller, analog switches, and an RS-485 transceiver, includes the following steps: S1. After the system is powered on, the microcontroller outputs a first-level signal to the selection terminal of the analog switch through its GPIO pin, controlling the analog switch to be in the first selection state, so that the microcontroller's UART interface is connected to the RS-485 transceiver in the forward direction through the analog switch, and the RS-485 transceiver and the RS-485 bus maintain a forward physical connection. S2. The microcontroller sends a preset feature data packet to the RS-485 bus via an analog switch in the first strobe state and an RS-485 transceiver. The feature data packet contains a feature code with alternating high and low levels. S3. The microcontroller monitors the hardware error interrupts of its UART controller. When a frame error interrupt or parity error interrupt is detected, it determines that the current bus polarity is reversed and generates a polarity switching trigger signal. S4. In response to the polarity switching trigger signal, the microcontroller outputs a second-level signal to the selection terminal of the analog switch through the GPIO pin, controlling the analog switch to switch from the first selection state to the second selection state, so that the microcontroller's UART interface is cross-connected to the RS-485 transceiver through the analog switch, and the differential signal lines between the RS-485 transceiver and the RS-485 bus realize the cross-connection of the A line and the B line. S5. After switching to the second strobe state, the microcontroller sends a verification data packet to the RS-485 bus again via the analog switch and RS-485 transceiver. If a valid response frame is received within the preset timeout period, the polarity correction is determined to be successful, and the current polarity state is latched in the microcontroller's memory unit.

[0006] Preferably, the feature data includes a feature code that alternates between high and low levels, and the feature code is 0x55 or 0xAA.

[0007] Preferably, when the microcontroller receives invalid distorted bytes continuously within a preset timeout period, it generates a polarity switching trigger signal, wherein the invalid distorted bytes are 0xDF, 0xFF, or 0x00.

[0008] Preferably, after the microcontroller latches the polarity state in the storage unit, when a signal disturbance is detected on the RS-485 bus, the microcontroller maintains the current selection state of the analog switch unchanged and prohibits the generation of polarity switching trigger signals.

[0009] Preferably, the storage unit is a non-volatile memory, and the microcontroller writes the latched polarity state into the non-volatile memory and reads the polarity state upon the next power-on to configure the initial selection state of the analog switch.

[0010] A software-controlled RS-485 bus polarity adaptive identification system includes: a microcontroller with a UART interface and GPIO pins; An RS-485 transceiver has differential output terminals, which are respectively connected to the A line and the B line of the RS-485 bus; An analog switch has an input terminal, an output terminal, and a strobe terminal. The UART interface of the microcontroller is connected to the input terminal of the analog switch, the output terminal of the analog switch is connected to the logic control terminal of an RS-485 transceiver, and the GPIO pin of the microcontroller is connected to the strobe terminal of the analog switch. The analog switch responds to the level signal received at its selection terminal and switches between a first selection state and a second selection state; in the first selection state, the UART interface is forward-biased to the RS-485 transceiver. In the second strobe state, the UART interface is cross-connected with the RS-485 transceiver, so that the differential signal lines between the RS-485 transceiver and the RS-485 bus are cross-connected.

[0011] Preferably, the analog switch is a bidirectional analog switch or a multiplexer chip.

[0012] Preferably, the input terminal of the analog switch receives the transmit signal, receive signal and direction control signal of the UART interface of the microcontroller, and the output terminal of the analog switch is respectively connected to the transmit data input terminal, receive data output terminal and transmit / receive direction control terminal of the RS-485 transceiver, so as to realize the overall switching of the signal path between the UART interface and the RS-485 transceiver.

[0013] Preferably, the analog switch is cascaded between the A and B line outputs of the RS-485 transceiver and the A and B lines of the RS-485 bus, and the UART interface of the microcontroller is directly connected to the logic control terminal of the RS-485 transceiver without going through the analog switch.

[0014] Preferably, when the GPIO pin outputs a first level signal, the analog switch switches to the first strobe state; When the GPIO pin outputs a second level signal, the analog switch switches to the second strobe state. The first level signal is low and the second level signal is high, or the first level signal is high and the second level signal is low.

[0015] Compared with the prior art, the beneficial effects of the present invention are: it abandons the expensive hardware self-calibrating RS-485 transceiver (such as SN65HVD888) and instead adopts the most basic standard RS-485 chip (such as SP3485, MAX485), combined with a general analog switch chip (such as CH443K, SGM3157), which can reduce the overall BOM cost by more than 60%, and is particularly suitable for distributed industrial systems with a large number of nodes; By utilizing the MCU's built-in UART hardware frame error interrupt and parity error interrupt as trigger signals for polarity reversal, there is no need to wait for a lengthy data packet to be fully received and for the parity check to fail. Detection and switching can be completed within one character cycle (microseconds to milliseconds, depending on the baud rate) when the first distorted character arrives. Compared to the 76ms correction time of the SN65HVD888 chip, the millisecond response of the relay solution, and the longer delay of traditional software algorithms, it has significant real-time advantages. Through the dual mechanism of initial switching and secondary verification locking, it can effectively isolate the occasional random code caused by strong electromagnetic transient interference in industrial sites, avoid high-frequency oscillation of polarity control pins due to bus noise, and ensure the stability of operation in complex electromagnetic environments. It is worth mentioning that it does not rely on the MCU having dual UART resources or specific timer peripherals, but only requires a common GPIO pin, and can be widely used in various mainstream MCU platforms. Detailed Implementation

[0016] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] Example 1 This embodiment provides an RS-485 bus polarity adaptive identification system based on CH443K analog switch and STM32F103 microcontroller; The system includes an STM32F103 microcontroller (MCU), a CH443K bidirectional analog switch, and an SP3485 standard RS-485 transceiver; The MCU's UART interface (UART_TX, UART_RX) and direction control pins (DE / RE) are connected to the input terminals of the CH443K analog switch, and the output terminals of the CH443K analog switch are connected to the corresponding logic control terminals of the SP3485 transceiver. A general-purpose GPIO pin of the MCU (defined as POL_CTRL) is connected to the CH443K's strobe pin SEL. The A and B differential outputs of the SP3485 transceiver are connected to the A and B lines of the RS-485 bus, respectively. gating logic When POL_CTRL is low, CH443K selects the first path, the MCU's UART_TX is connected to the SP3485's D pin, UART_RX is connected to the SP3485's R pin, and the DE / RE direction control pins are connected in the forward direction. At this time, the bus is in the forward physical wiring sequence. When POL_CTRL is high, CH443K switches to the second path. The MCU's UART_TX and UART_RX are internally crossed and connected to SP3485. The DE / RE direction control signals are correspondingly crossed, which is equivalent to physically swapping the logic polarities of lines A and B. Software implementation After the MCU is powered on, it performs the following initialization operations: sets the POL_CTRL pin to low level, puts the analog switch in the first strobe state, configures the UART controller, sets the baud rate to 9600bps, data bits to 8 bits, stop bits to 1 bit, no parity, and enables the UART frame error interrupt and parity error interrupt. The main program executes according to the following state machine flow: State S0 (Initial State): The system is powered on, the analog switch is in the first strobe state (positive connection), and the MCU sends a feature data packet 0x55 (binary 01010101) to the bus through the UART interface. This data packet alternates between high and low levels frequently. If the bus polarity is reversed, the receiving end will receive the waveform after the logic is inverted. State S1 (Monitoring State): The MCU continuously monitors the frame error interrupt and parity error interrupt of the UART controller, and starts the timeout counter at the same time. The preset timeout time T_timeout is set according to the baud rate. In this embodiment, T_timeout=10ms. State S2 (Abnormality Detection): If a frame error interruption or parity error interruption is detected, or if invalid distorted bytes (such as 0xDF, 0xFF or 0x00) are read continuously within the timeout period, it is determined that the current bus polarity is reversed, and the process transitions to State S3. During normal communication, the bus idle level is high (logic 1), and the UART start bit is low (logic 0). The receiving end can correctly detect the start bit and complete the data frame reception. When the A and B lines are reversed, the bus idle level becomes low (logic 0), and the UART start bit becomes high (logic 1). The receiving end cannot correctly detect the start bit, thus triggering a frame error interrupt. State S3 (Polarity Switching): The MCU outputs a high level through the POL_CTRL pin to control the CH443K analog switch to switch from the first gating state to the second gating state, realizing the cross connection of differential signal lines. This switching process is completed within microseconds. State S4 (Secondary Verification): After the switch is completed, the MCU sends a verification data packet (such as 0xAA) again. If a correct response frame is received within the preset timeout period, the polarity switch is determined to be successful, and the process proceeds to State S5. If an error frame is still received, the process returns to State S2 for re-determination (to prevent false switching caused by momentary interference). State S5 (Latch State): The current polarity state (second strobe state) is latched in the MCU's RAM and optionally written to the EEPROM for direct use on the next power-on. After that, when a signal disturbance on the bus is detected, the MCU keeps the current strobe state of the analog switch unchanged and prohibits the generation of polarity switching trigger signals to ensure the stable operation of the system in complex electromagnetic environments. The entire process, from detecting a frame error interruption to completing a polarity switch and restoring communication, is completed within milliseconds, with anomaly detection completed within a single distorted character cycle (microseconds).

[0018] Parameter Description In this embodiment, the timeout T_timeout is dynamically configured according to the bus baud rate. For a baud rate of 9600bps, the transmission time of a single character is about 1.04ms. Setting T_timeout to 10ms can cover a receiving window of about 9 characters, ensuring that it will not be falsely triggered due to normal communication delay. For a baud rate of 115200bps, T_timeout can be shortened to 1ms. The characteristic data packets 0x55 (01010101) and 0xAA (10101010) are complementary codes with the highest level alternation frequency. The distortion characteristics produced when the polarity is reversed are the most obvious, and they are most likely to trigger frame error interruption.

[0019] Example 2 This embodiment provides an alternative implementation method based on the SGM3157 analog switch and different MCU platforms; Unlike Embodiment 1, the cascading position of the analog switch is different in this embodiment. The SGM3157 analog switch is not cascaded between the UART interface of the MCU and the logic control terminal of the RS-485 transceiver, but is directly cascaded between the A and B differential output terminals of the RS-485 transceiver and the RS-485 bus. The specific connection method is as follows: the MCU's UART interface is directly connected to the logic control terminal of the RS-485 transceiver (without going through the analog switch); the A and B output terminals of the RS-485 transceiver are respectively connected to the two input terminals of the SGM3157 analog switch; the two output terminals of the SGM3157 analog switch are respectively connected to the A and B lines of the RS-485 bus; the MCU's GPIO pin (POL_CTRL) is connected to the strobe terminal of the SGM3157. When POL_CTRL is low, the SGM3157 connects the transceiver's A terminal to the A line of the bus and its B terminal to the B line of the bus (forward connection). When POL_CTRL is high, the SGM3157 connects the transceiver's A terminal to the B line of the bus and its B terminal to the A line of the bus (cross connection). The advantage of this connection method is that the signal path between the MCU's UART interface and the RS-485 transceiver is not affected by the analog switch, resulting in better signal integrity. The disadvantage is that the analog switch needs to withstand the differential signal swing on the bus side, which places slightly higher demands on the voltage withstand capability and bandwidth of the analog switch. This embodiment is suitable for application scenarios with small bus voltage swing (such as a 3.3V power supply system).

[0020] The software process is exactly the same as in Example 1, and will not be repeated here.

[0021] Example 3 This embodiment provides an alternative solution that uses only parity error interruption as the triggering condition; For some MCU platforms that do not support frame error interrupts, or in scenarios where parity checking has been enabled in some communication protocols, parity error interrupts can be used alone as the trigger condition for polarity switching. Specifically, when configuring UART, parity check (such as even check or odd check) is enabled. When the bus polarity is reversed, all received data bits are logically inverted, which destroys the logical relationship between the parity bits and the data bits. The UART controller will trigger a parity error interrupt. In response to the interrupt, the MCU will execute the same polarity switching process as in Example 1. The detection speed of this embodiment is comparable to that of the frame error interruption scheme, both of which complete the detection within a single character cycle. It is applicable to applications where the communication protocol itself already requires parity checking, without the need to additionally enable frame error interruption.

[0022] Example 4 This embodiment provides a dual verification enhancement scheme, which is suitable for industrial sites under strong electromagnetic interference environments; Based on the aforementioned embodiments, this embodiment adds a multiple handshake confirmation mechanism in state S4 (secondary verification). Specifically, after the polarity switch, the MCU continuously sends three verification data packets (0x55, 0xAA, 0x55), requiring the other end to reply with the corresponding response frames in sequence. Only when all three response frames are received correctly is the polarity switch determined to be successful and state S5 (latch state) entered. If any response frame is incorrect, it is determined to be a false trigger caused by transient interference, and the analog switch is restored to the selection state before the switch.

[0023] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A software-controlled RS-485 bus polarity adaptive identification method, applied to a communication system including a microcontroller, analog switches, and an RS-485 transceiver, characterized in that, Includes the following steps: S1. After the system is powered on, the microcontroller outputs a first-level signal to the selection terminal of the analog switch through its GPIO pin, controlling the analog switch to be in the first selection state, so that the microcontroller's UART interface is connected to the RS-485 transceiver in the forward direction through the analog switch, and the RS-485 transceiver and the RS-485 bus maintain a forward physical connection. S2. The microcontroller sends a preset feature data packet to the RS-485 bus via an analog switch in the first strobe state and an RS-485 transceiver. The feature data packet contains a feature code with alternating high and low levels. S3. The microcontroller monitors the hardware error interrupts of its UART controller. When a frame error interrupt or parity error interrupt is detected, it determines that the current bus polarity is reversed and generates a polarity switching trigger signal. S4. In response to the polarity switching trigger signal, the microcontroller outputs a second-level signal to the selection terminal of the analog switch through the GPIO pin, controlling the analog switch to switch from the first selection state to the second selection state, so that the microcontroller's UART interface is cross-connected to the RS-485 transceiver through the analog switch, and the differential signal lines between the RS-485 transceiver and the RS-485 bus realize the cross-connection of the A line and the B line. S5. After switching to the second strobe state, the microcontroller once again sends a verification data packet to the RS-485 bus via the analog switch and RS-485 transceiver. If a valid response frame is received within the preset timeout period, the polarity correction is considered successful, and the current polarity state is latched into the microcontroller's memory.

2. The software-controlled RS-485 bus polarity adaptive identification method according to claim 1, characterized in that, The feature data packet contains a feature code that alternates between high and low levels, and the feature code is 0x55 or 0xAA.

3. The software-controlled RS-485 bus polarity adaptive identification method according to claim 1, characterized in that, When the microcontroller receives invalid distorted bytes continuously within a preset timeout period, it generates a polarity switching trigger signal. The invalid distorted bytes are 0xDF, 0xFF, or 0x00.

4. The software-controlled RS-485 bus polarity adaptive identification method according to claim 3, characterized in that, After the microcontroller latches the polarity state into the storage unit, when it detects a signal disturbance on the RS-485 bus, the microcontroller maintains the current selection state of the analog switch unchanged and prohibits the generation of polarity switching trigger signals.

5. The software-controlled RS-485 bus polarity adaptive identification method according to claim 4, characterized in that, The storage unit is a non-volatile memory. The microcontroller writes the latched polarity state into the non-volatile memory and reads the polarity state upon the next power-on to configure the initial selection state of the analog switch.

6. A software-controlled RS-485 bus polarity adaptive identification system, characterized in that, include: The microcontroller has a UART interface and GPIO pins; An RS-485 transceiver has differential output terminals, which are respectively connected to the A line and the B line of the RS-485 bus; An analog switch has an input terminal, an output terminal, and a strobe terminal. The UART interface of the microcontroller is connected to the input terminal of the analog switch, the output terminal of the analog switch is connected to the logic control terminal of an RS-485 transceiver, and the GPIO pin of the microcontroller is connected to the strobe terminal of the analog switch. The analog switch responds to the level signal received at its selection terminal and switches between a first selection state and a second selection state; in the first selection state, the UART interface is forward-biased to the RS-485 transceiver. In the second strobe state, the UART interface is cross-connected with the RS-485 transceiver, so that the differential signal lines between the RS-485 transceiver and the RS-485 bus are cross-connected. The microcontroller is configured to perform the method as described in any one of claims 1 to 5.

7. The software-controlled RS-485 bus polarity adaptive identification system according to claim 6, characterized in that, The analog switch is a bidirectional analog switch or a multiplexer chip.

8. The software-controlled RS-485 bus polarity adaptive identification system according to claim 6, characterized in that, The input terminal of the analog switch receives the transmit signal, receive signal and direction control signal of the UART interface of the microcontroller. The output terminal of the analog switch is connected to the transmit data input terminal, receive data output terminal and transmit / receive direction control terminal of the RS-485 transceiver, respectively, so as to realize the overall switching of the signal path between the UART interface and the RS-485 transceiver.

9. The software-controlled RS-485 bus polarity adaptive identification system according to claim 6, characterized in that, The analog switch is cascaded between the A and B line outputs of the RS-485 transceiver and the A and B lines of the RS-485 bus. The UART interface of the microcontroller is directly connected to the logic control terminal of the RS-485 transceiver without going through the analog switch.

10. The software-controlled RS-485 bus polarity adaptive identification system according to claim 6, characterized in that, When the GPIO pin outputs a first-level signal, the analog switch switches to the first strobe state. When the GPIO pin outputs a second level signal, the analog switch switches to the second strobe state. The first level signal is low and the second level signal is high, or the first level signal is high and the second level signal is low.