A three-cycle directional projection synthesis hardware pipeline circuit
Patent Information
- Application Number
- CN202611130132.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-28
- Publication Date
- 2026-10-13
AI Technical Summary
[0008]综上，现有技术共性缺陷在于：无专用硬连线流水线实现坐标-定向向量内积投影，依赖通用运算单元分时调度，单单元处理延迟达微秒级；仅支持全局固定阈值，不具备沿任意自定义空间方向平滑渐变生成能力；缺少多正交方向并行生成硬件，多场耦合场景只能串行计算，吞吐率低；过渡映射（tanh/sign/erf）依赖软件重配置，存在总线传输延迟，无法硬件单周期切换；各类调控硬件架构专用化，张量、MEMS、硅光、存储芯片阈值生成电路互不通用
[0034]本发明相较于传统软件分时计算与固定全局参数硬件方案，具备如下突出技术优势：
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Figure CN122903367A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of dedicated computing IP technology for digital integrated circuits, and specifically relates to a three-cycle directional projection synthesis hardware pipeline circuit, which is used to project spatial coordinates along a custom direction and then synthesize and output directional gradient control parameters. Background Technology
[0002] Spatial distributed hardware systems (such as information manifold simulation arrays, MEMS actuation arrays, silicon photonics phased arrays, memristor cross arrays, etc.) all require applying threshold parameters that vary with spatial orientation to discrete units. Current mainstream implementation schemes fall into two categories: one relies on time-sharing operations using a general-purpose CPU or ALU, loading unit coordinates and orientation vectors into software, iteratively calculating gradient thresholds, and then distributing them unit by unit; the other uses fixed global threshold hardware, configuring only a single reference threshold on-chip, without spatial orientation correction logic, and all units share the same control parameter.
[0003] The above solutions all have inherent flaws in four typical application scenarios:
[0004] (i) In the simulation scenario of information manifold tensors, the accuracy of topology propulsion and variable stiffness control is highly dependent on the spatial anisotropic truncation center parameters. Existing hardware circuits only support globally fixed... One-way corrective control of parameters or single curvature cannot generate spatially smooth and gradually changing anisotropic truncated fields based on custom propagation vectors. At the same time, existing solutions generally reuse general-purpose ALUs to complete directional projection solutions in a time-sharing manner, resulting in a large amount of software scheduling and timing reuse overhead, introducing microsecond-level computational delays, which can easily cause topological gradient distortion, ultimately leading to a decrease in manifold simulation accuracy and a significant reduction in numerical convergence speed.
[0005] (ii) MEMS Actuation Array Control Scenarios. Flexible MEMS deformation control requires gradually adjusting the unit stiffness threshold voltage along the deformation gradient. Existing controllers output a uniform reference voltage and lack spatial orientation offset hardware logic, relying solely on software table lookup to issue values unit by unit, resulting in low array deformation accuracy and microsecond-level response delay.
[0006] (III) Silicon Photonics Phased Array Scenarios. Optical waveguide arrays require continuous modulation of the refractive index loss threshold along the light transmission direction. Existing hardware has a globally uniform threshold and lacks a spatial projection correction mechanism, resulting in severe beam phase distortion, while software real-time compensation bandwidth is insufficient.
[0007] (iv) Memristor cross-connected memory array scenario. The array read / write conduction threshold needs to be set in layers along the row and column gradients to reduce read / write noise. Existing hardware lacks address projection threshold offset logic and can only rely on software to configure it row by row and column by column, resulting in severe loss of read / write throughput.
[0008] In summary, the common shortcomings of existing technologies are as follows: there is no dedicated hard-wired pipeline to realize coordinate-oriented vector inner product projection, relying on time-sharing scheduling of general-purpose computing units, with single-unit processing latency reaching microsecond levels; only global fixed thresholds are supported, and the ability to generate smooth gradients along arbitrary custom spatial directions is not available; there is a lack of hardware for parallel generation in multiple orthogonal directions, and multi-field coupling scenarios can only be calculated serially, resulting in low throughput; transition mapping (tanh / sign / erf) relies on software reconfiguration, resulting in bus transmission latency and the inability to switch in hardware in a single cycle; various control hardware architectures are specialized, and threshold generation circuits for tensors, MEMS, silicon photonics, and memory chips are not interchangeable. Summary of the Invention
[0009] Inventive concept
[0010] The core concept of this invention is to build a pure hard-wired universal gradient generation pipeline with a fixed three-clock cycle, and to hardware-encode the entire link of spatial coordinate directional projection, normalization scaling, bounded transition mapping, and reference offset synthesis to achieve fixed three-cycle output of directional gradient parameters; optionally, three sets of independent orthogonal channels and 3×3 coupled aggregation hardware can be extended to achieve multi-directional parameter interference superposition.
[0011] Specifically, it includes two core innovation directions:
[0012] Firstly, a single-channel, three-stage, fixed-cycle computational pipeline (a fundamental and essential architecture). Internally, the hardware utilizes three stages of purely hard-wired combinational logic to form a complete computational path, performing coordinate difference inner product projection, normalization scaling, bounded transition mapping, and reference offset synthesis in parallel. The entire process is independent of software scheduling and involves no bus read / write waits. The overall computation timing is highly deterministic, with the input coordinates latched to the output of the directional control parameters fixed at three clock cycles. The built-in hardware-switchable bounded transition computation unit supports switching between tanh, sign, and erf mapping modes, with a switching latency of less than one clock cycle. The pipeline operates without flushing or interruptions, adaptable to different gradient smoothing and step boundary control requirements.
[0013] Secondly, a multi-channel coupling and aggregation path (optional extended architecture). Functional expansion is achieved based on the aforementioned single-channel basic pipeline without affecting the independent operation of the basic circuitry. Multiple additional independent directional computation sub-units, consistent with the basic path architecture, are added, along with dedicated multi-channel coupling and aggregation hardware. This hardware incorporates an adjustable coupling coefficient register, a parallel multiplication tree, and a global adder. It performs weighted aggregation and output of independently generated control parameters from multiple orthogonal directions, adapting to scenarios involving coordinated control of multiple physics fields and multiple sensor orthogonal channels.
[0014] The technical problem to be solved by the present invention
[0015] This invention aims to solve multiple technical bottlenecks in existing distributed array orientation parameter generation hardware architectures. The specific technical problems are as follows:
[0016] First, there is no dedicated projection hardware; it relies on general-purpose computing units to calculate directional gradients in a time-sharing manner, with single-unit processing latency reaching the microsecond level.
[0017] Secondly, it only supports globally fixed parameters and cannot generate smooth, gradual adjustment parameters along any custom spatial direction.
[0018] Third, there are no multi-parallel directional channels, and multi-physical coupling scenarios can only be computed serially, resulting in low throughput.
[0019] Fourth, the transition function switching relies on software bus reconfiguration, which results in transmission delays and non-real-time mode switching.
[0020] Fifth, the parameter generation hardware is specialized for specific fields, and tensors, MEMS, silicon photonics, and memory chips cannot be reused, resulting in high R&D costs.
[0021] Overall technical solution
[0022] This invention hardwareifies the entire computational chain of the general directional gradient model, replacing the microsecond-level nondeterministic delay of the traditional general ALU time-sharing computation with a deterministic delay of fixed three clock cycles, thereby realizing the single-cycle real-time generation of spatially distributed array direction-dependent parameters.
[0023] This invention discloses a direction-dependent parameter hardware acceleration circuit and a general gradient generation method, which realizes a general directional gradient model through a three-stage fixed-delay pure hard-wired pipeline. Hardware parallel solution. The model input is D-dimensional spatial coordinates x, combined with a programmable orientation vector d and a reference centroid. Characteristic scale R, offset amplitude and benchmark value Configuration parameters, after being accelerated by pipeline hardware, output directional and gradually varying control parameters to meet the single-cycle real-time generation requirements of various distributed spatial arrays. The specific technical solution is as follows:
[0024] (i) Spatial coordinate input interface. Used to latch the spatial coordinates of D-dimensional physical units clock cycle by clock cycle, with a built-in synchronous latch register, and outputs all dimension vectors completely within one clock cycle; the coordinate vector format is compatible with different dimension coordinate inputs.
[0025] (ii) Programmable Parameter Register Set. Contains five independently configurable registers, rewritable only via the on-chip configuration bus; the computational path is purely hardwired with no software intervention. Specifically: the orientation vector register stores the unit gradient vector d; the reference centroid register stores the system reference coordinates. The feature scale register stores the normalized scale parameter R; the offset magnitude register stores the maximum gradient offset. The reference parameter register stores the global basic control value T0.
[0026] (III) Multi-path parallel vector dot product projection calculation unit. It has a built-in D-path parallel multiplier and adder tree, which completes the inner product operation of coordinate difference x-x_c and orientation vector d in a single cycle, and outputs the signed projection distance s=〈x-x_c,d〉, which is implemented by pure combinational logic.
[0027] (iv) Normalized division unit. Combinatorial logic division is used. The input is the projection distance s and the feature scale R. The output is the normalized projection value z=s / R in a single cycle, without pipeline bubbles.
[0028] (v) Switchable bounded transition function unit. Configure mode selection register, and switch tanh, sign and erf three types of mapping in a single cycle; the three types of mapping are implemented in parallel hardware path, and the output is selected by multiplexer according to the value of mode selection register. The output value range of all mappings is fixed in [-1,1].
[0029] (vi) Parameter offset synthesis operation chain. Includes multiplier completion. Gradient offset calculation, and adder stacking reference. Generate final orientation parameters .
[0030] (vii) Standardized output interface. The output port with unified timing and bit width is hardwired and can be directly connected to various back-end driver circuits.
[0031] (viii) Multi-channel coupled expansion architecture (optional). Multiple complete computing sub-units and coupling aggregators are added on the basis of single channel to weighted summation of multiple independent parameters to output comprehensive control parameters.
[0032] Basic pipeline timing rules: coordinate latching and projection are completed in cycle 1, normalization and transition mapping are completed in cycle 2, offset synthesis and output are completed in cycle 3, and the operation is completed in three fixed clock cycles with no branches and no arbitration waiting throughout the process.
[0033] Beneficial effects
[0034] Compared with traditional software time-sharing computing and hardware solutions with fixed global parameters, this invention has the following outstanding technical advantages:
[0035] (i) A single pipeline hardware can switch between different application scenarios without modifying the computing path, only by rewriting the register parameters. There is no need to modify the hardware pipeline structure, and the hardware IP can be reused across product lines, which greatly reduces the R&D cost of multi-chips.
[0036] (ii) Compared with the general ALU time-division software calculation (single unit microsecond level delay), the present invention outputs directional parameters with fixed three clock cycles. With a main frequency of 1GHz, the single unit processing is only 3ns, and the delay is reduced by more than 99%, which fully meets the array's real-time control requirements for each unit.
[0037] (iii) Directional projection, mapping and synthesis are all implemented independently in hardware, without reusing multi-channel ALU array resources. The main computing power of the chip can be used entirely for core operations, and the overall throughput is significantly improved.
[0038] (iv) The tanh / sign / erf transition functions can be switched instantaneously by simply rewriting the mode register, without the need to send out configuration data packets. The switching delay is less than 1 clock cycle, which is suitable for scenarios where the smoothness of dynamic switching needs to be adjusted.
[0039] (v) Multiple sets of directional gradients are generated synchronously by multiple positive traffic channels and aggregated by weighted coupling matrix, eliminating the need for multiple serial calculations and improving array throughput by nearly 3 times.
[0040] (vi) The output signal timing and bit width are uniform, and it can be directly cascaded with the multi-channel ALU out-of-order scheduling circuit and the trace completeness determination circuit. There is no switching logic, and the chip top-level integration difficulty is low.
[0041] (vii) The entire pipeline has no data-dependent branches and no global bus arbitration. The combinational logic depth of the critical path is low, the timing convergence is simple, the hardware equivalent gate count is small, and the chip surface area is extremely small.
[0042] Terminology Definition
[0043] Directional projection synthesis circuit: refers to the three-cycle fixed-delay pure hard-wired pipeline circuit described in this invention, which is used to project, normalize, and perform bounded transition mapping of spatial coordinates along a custom direction to synthesize and output directional gradient control parameters.
[0044] Projected distance: refers to the scalar projection value of the difference between the spatial unit coordinates and the reference centroid coordinates along the direction of the orientation vector. This reflects the degree to which the unit deviates from the reference position along the gradient direction.
[0045] Normalized projection value: refers to the dimensionless value of the projection distance after normalization by the characteristic scale parameter, which serves as the input to the bounded transition function unit.
[0046] Bounded transition function: refers to a nonlinear function that maps normalized projected values to a finite range [-1,1]. This invention supports three types of functions: tanh, sign, and erf, which are used to control the gradual smoothness of the adjustment parameters along the spatial direction.
[0047] Mode selection register: refers to the hardware register that controls the output mapping type of the bounded transition function unit. By rewriting its value, the three mapping types tanh / sign / erf can be switched in a single cycle without software intervention.
[0048] Three-cycle fixed delay: This means that the pipeline circuit of this invention occupies a fixed 3 clock cycles from coordinate latching to parameter output, which does not change with the input data, mode configuration or process conditions, and has completely deterministic timing characteristics.
[0049] Pure hardwired: refers to a computing path without software scheduling, microcode decoding, or bus arbitration, where all operations and decisions are performed in real time by combinational and sequential logic hardware.
[0050] Directional gradual control parameters: These are control parameters that change continuously with coordinate position along a custom spatial direction. In information manifold simulation, they are represented by anisotropic truncation centers, and in MEMS control, they are represented by stiffness reference voltage offsets.
[0051] Single unit: A single spatial discrete unit (manifold patch, MEMS actuation micro-unit) in information manifold tensor simulation and MEMS actuation array is the smallest independent control object for field distribution regulation. Attached Figure Description
[0052] Figure 1 This is a schematic diagram of the overall architecture of the basic single-channel directional gradient generation circuit of this invention. The solid arrows indicate the direction of the forward data flow; the dashed boxes represent the programmable parameter register groups, showing the configuration of five register groups; the circled labels ① to ⑦ indicate the serial connection positions of the seven core modules in the pipeline.
[0053] Figure 2 This diagram illustrates the internal hardware structure of the bounded transition function unit and the three types of mapping switching paths of the present invention. The diagram shows three parallel mapping hardware paths: tanh, sign, and erf, as well as the path selection logic controlled by the mode selection register; solid arrows represent the main data flow, and dotted-dash arrows represent the mode selection control signals.
[0054] Figure 3 This is a schematic diagram of the optional multi-channel coupled expansion architecture of the present invention. The diagram shows the cascading relationship of multiple independent projection-normalization-transition operation sub-units and coupling aggregators (with built-in coupling coefficient registers, parallel multiplication trees, and global adders); solid arrows represent single-channel data flows, and dashed arrows represent coupled aggregated data flows. Detailed Implementation
[0055] Example 1: Generation of Oriented Truncation Parameters for Information Manifold Patches
[0056] like Figure 1Based on the basic single-channel architecture shown, this embodiment takes the generation of anisotropic truncation centers in five-dimensional patch space in information manifold simulation as an example to verify the functional correctness and timing performance of the directional gradient generation circuit.
[0057] Configuration parameters: 5D coordinates of the patch (x), propagation orientation vector (d), feature scale (R), baseline truncation. The transition function uses the tanh mode, and the offset amplitude is... .
[0058] Pipeline timing:
[0059] Period T1: The coordinate input interface latches the coordinates of the five-dimensional patch, and the parallel projection calculation unit synchronously completes the inner product operation and outputs the projection distance. .
[0060] Period T2: Output of the normalized division unit The bounded transition function unit outputs the tanh(z) gradient coefficient (implemented by a 256-level direct-reading LUT with a maximum error of less than 1 / 256).
[0061] Period T3: Offset synthesis link superposition reference truncation, output spatial orientation truncation center .
[0062] Actual test results (RTL simulation based on 28nm process and 1GHz clock speed):
[0063] Targeted truncation parameter generation effect ( , );
[0064] Direction of advancement (dot=+0.30): (Truncation enhancement);
[0065] Reverse direction (dot=-0.30): (Truncation weakens);
[0066] Orthogonal direction (dot≈0): (No offset).
[0067] A single-sided pipeline with a fixed delay of three clock cycles (3ns at 1GHz) achieves an equivalent throughput of 250–333 M patches / s. Simulation results show that the gradient patch field is smoothly generated along the propagation vector, the direction-dependent truncation response is completely correct, and the 256-level LUT approximation accuracy meets the requirements for fixed-point computation.
[0068] Example 2: Verification of Dynamic Switching of Transition Function
[0069] like Figure 2 The internal structure of the bounded transition function unit is shown in the figure. This embodiment verifies the dynamic switching capability of the transition function during runtime.
[0070] During system operation, only the 2-bit func_mode register is modified, completing the tanh / sign / erf switching within a single cycle. The pipeline operates without flushing or interruptions, and the changes take effect immediately in the next cycle. Simulation results (based on the same RTL simulation conditions):
[0071] sign mode: σc=0.8000 (step full amplitude output);
[0072] ERF mode: σc=0.2003 (smooth transition);
[0073] tanh mode: σc = 0.5864 (continuous saturation).
[0074] The measured switching delay is less than 1 clock cycle (less than 1 ns at 1 GHz), and the simulation waveform fully records the switching process of the three modes, verifying its correctness.
[0075] Example 3: Multi-channel Coupled Extension Architecture
[0076] like Figure 3 The optional multi-channel coupling architecture is shown, and this embodiment takes multi-directional parameter composite generation as an example. Multiple independent projection-normalization-transition operation sub-units are added to the single-channel architecture to generate multiple sets of directional gradient parameters along multiple directions. These parameters are then weighted and aggregated by the coupling matrix to output a comprehensive control parameter. The timing sequence within each channel is exactly the same as in Embodiment 1, with a fixed three-cycle output. Multiple channels execute in parallel without interference.
[0077] Example 4: Hardware Resource and Timing Comprehensive Verification
[0078] Based on a 28nm standard process and a 1GHz clock frequency, the estimated number of gates for the entire single-channel hardware is approximately 8000. The longest combinational logic level in the pipeline critical path is three levels. Static timing analysis shows sufficient setup / hold margins and no timing violations. This IP can be directly connected to various back-end driver circuits.
Claims
1. A hardware pipeline circuit for synthesizing three-cycle directional projection parameters, characterized in that, include: Spatial coordinate input interface, used to latch D-dimensional physical unit spatial coordinates clock cycle; The programmable parameter register set includes an orientation vector register, a reference centroid register, a feature scale register, an offset magnitude register, and a reference parameter register; The multi-path parallel vector dot product projection calculation unit has a built-in D-path parallel multiplier and adder tree, which completes the inner product operation of coordinate difference and orientation vector in a single clock cycle and outputs a one-dimensional projection distance. The normalization operation unit receives the projection distance and feature scale, and outputs the normalized projection value; The bounded transition function operation unit is configured with a mode selection register, supports multiple hardware-switchable bounded nonlinear transition mappings, and has a fixed output value range of [-1, 1]. The offset synthesis operation chain, which includes multipliers and adders, completes the superposition of gradient offset and reference parameters; The standardized output interface outputs fixed-width, timing-synchronized directional gradual control parameters, and this interface is time-matched with the hard-wired connection of the back-end hardware unit. The entire circuit consists of three fixed pipeline clock cycles from coordinate latching to parameter output. All computational paths are pure hard-wired combinational logic architectures, with no software scheduling, no microcode computation, no time-division multiplexing, and no reliance on external instructions for computation.
2. The hardware pipeline circuit for three-cycle directional projection parameter synthesis according to claim 1, characterized in that, The bounded transition function operation unit supports single-cycle hardware switching of three types of mappings: tanh, sign, and erf. The mode switching is free from pipeline flushing and waiting cycles. The tanh mapping is implemented using a 256-level direct-read ROM lookup table, and the maximum absolute error across the entire input range is less than 1 / 256.
3. The hardware pipeline circuit for synthesizing three-cycle directional projection parameters according to claim 1, characterized in that, The internal addition tree of the multi-path parallel vector dot product projection calculation unit is a fixed structure of level D-1. The multiplier output and the addition tree input are directly connected by pure combinational logic, and there is no additional pipeline register inserted inside the operation path.
4. The hardware pipeline circuit for three-cycle directional projection parameter synthesis according to claim 1, characterized in that, Multiple independent projection-normalization-transition operation subunits can be added to form a multi-parallel expansion channel. Adding a second and third set of independent operation subunits forms a three-parallel orientation parameter generation channel. The multi-parallel channel is an optional expansion structure.
5. The hardware pipeline circuit for three-cycle directional projection parameter synthesis according to claim 4, characterized in that, It also includes a multi-channel coupling aggregator with built-in coupling coefficient registers, parallel multiplication trees and global adders, used to weight and aggregate multiple independently generated directional parameters and output coupled integrated control parameters.