Ai chip, ai chip on-chip cache level data flow control circuit and control method thereof

Abstract

Embodiments of the present application disclose an AI chip, an on-chip cache level data flow control circuit of the AI chip and a control method thereof. The data flow control circuit comprises a traffic monitoring module, a power consumption calculation and statistics module, a risk detection module and a risk processing module. The traffic monitoring module is configured to obtain data flow of input / output ports. The power consumption calculation and statistics module is configured to calculate power consumption credit values of each detection period and to count power consumption credit summary values of fixed detection periods. The risk detection module is configured to determine a current load risk state of an on-chip cache according to a plurality of continuously counted power consumption credit summary values. The risk processing module is configured to determine a target control back pressure rate according to the power consumption credit summary values within a preset statistical time when the current load risk state is an alarm state, so as to limit the data flow of the input / output ports of the on-chip cache. The present application can realize fine monitoring and limitation of the on-chip cache level data flow, thereby effectively protecting the power integrity of the on-chip system.

Description

Technical Field

[0001] This invention relates to the field of AI chip technology, and in particular to an AI chip, an on-chip cache-level data flow control circuit for the AI ​​chip, and a control method thereof. Background Technology

[0002] As the data stream bandwidth of AI chips continues to increase, the current load and power consumption of the on-chip system power rails, which power core data stream components such as on-chip networks, on-chip caches, and memory controllers, will increase significantly, posing a severe challenge to chip power integrity. Current AI chip architectures use analog devices to detect voltage jitter and, when frequency throttling protection is triggered, use voltage drop detection combined with rapid frequency throttling to limit the on-chip system current, thus protecting the power rails under electrical design current scenarios. However, to meet the boundary constraints of electrical design current and voltage-frequency, significant frequency throttling for frequency throttling protection severely sacrifices the operating performance of the AI ​​chip and lacks fine-grained monitoring and flow limitation of the data stream source, thus failing to fundamentally reduce the probability and frequency of triggering frequency throttling protection. Summary of the Invention

[0003] This invention provides an AI chip, an on-chip cache-level data flow control circuit and control method thereof, to achieve fine-grained monitoring and restriction of on-chip cache-level data flow, thereby effectively protecting the power integrity of the on-chip system and reducing the probability and frequency of triggering frequency reduction protection.

[0004] In a first aspect, embodiments of the present invention provide an on-chip cache-level data flow control circuit for an AI chip, which includes a flow monitoring module, a power consumption calculation and statistics module, a risk detection module, and a risk processing module. The flow monitoring module is connected to the input / output port of the on-chip buffer, and the flow monitoring module is used to acquire the data stream of the input / output port; The traffic monitoring module is connected to the power consumption calculation and statistics module; the power consumption calculation and statistics module is used to calculate the power consumption credit value for each detection cycle and to calculate the power consumption credit summary value for a fixed detection cycle. The power consumption calculation and statistics module is connected to the risk detection module; the risk detection module is used to determine the current load risk status of the on-chip cache based on multiple consecutively statistically summarized power consumption credit values. The risk detection module, the power consumption calculation and statistics module, and the input / output ports of the on-chip buffer are all connected to the risk processing module. The risk processing module is used to determine the target control reverse voltage ratio based on the power consumption credit summary value within a preset statistical time when the current load risk state is in an alarm state, so as to limit the data flow of the input / output ports of the on-chip buffer.

[0005] Optionally, the power consumption calculation and statistics module includes a power consumption credit conversion unit, a power consumption credit aggregation unit, and a power consumption credit storage unit; The power consumption credit conversion unit is connected to the traffic monitoring module. The power consumption credit conversion unit is used to calculate the power consumption credit value of each event in each detection period based on the data stream of each event in each detection period. The power consumption credit conversion unit is connected to the power consumption credit aggregation unit, and the power consumption credit aggregation unit is used to calculate the periodic power consumption credit value of all events in each detection period. The power consumption credit aggregation unit, the risk detection module, and the risk processing module are all connected to the power consumption credit storage unit. The power consumption credit storage unit is used to calculate the power consumption credit aggregation value of multiple periodic power consumption credit values ​​within the fixed detection period.

[0006] Optionally, the risk detection module includes a voltage spike detection unit, a short-time limiting current detection unit, and a long-term thermal power consumption detection unit; The voltage spike detection unit and the short-time limiting current detection unit are both connected to the power consumption calculation and statistics module. The long-term thermal power consumption detection unit is connected to the short-time limiting current detection unit. The voltage spike detection unit, the short-time limiting current detection unit, and the long-term thermal power consumption detection unit are all connected to the risk processing module. The voltage spike detection unit is used to determine the voltage spike risk state based on the sum of multiple consecutive statistical power consumption credit values; the short-time limiting current detection unit is used to determine the short-time limiting current risk state based on the average power consumption credit of multiple consecutive statistical sum of power consumption credit values; and the long-term thermal power consumption detection unit is used to determine the long-term thermal power consumption risk state based on the average power consumption credit of multiple consecutive statistical sum of power consumption credit values.

[0007] Optionally, the risk handling module includes a voltage spike risk handling unit, a short-time limiting current risk handling unit, a long-term thermal power consumption risk handling unit, and a risk arbitration unit. The voltage spike detection unit is connected to the voltage spike risk processing unit, the short-time limiting current detection unit is connected to the short-time limiting current risk processing unit, the long-term thermal power consumption detection unit is connected to the long-term thermal power consumption risk processing unit, the voltage spike risk processing unit, the short-time limiting current risk processing unit, and the long-term thermal power consumption risk processing unit are all connected to the risk arbitration unit, the short-time limiting current risk processing unit is connected to the power consumption calculation and statistics module, the long-term thermal power consumption risk processing unit is connected to the short-time limiting current risk processing unit, and the risk arbitration unit is connected to the input / output port of the on-chip buffer; The voltage spike risk processing unit is used to generate a first reverse voltage ratio when the voltage spike risk state is a first alarm state; the short-time limiting current risk processing unit is used to calculate a second reverse voltage ratio based on the power consumption credit summary value within a first preset statistical time period when the short-time limiting current risk state is a second alarm state; the long-term thermal power consumption risk processing unit is used to calculate a third reverse voltage ratio based on the power consumption credit average value within a second preset statistical time period when the long-term thermal power consumption risk state is a third alarm state; and the risk arbitration unit is used to determine the target control reverse voltage ratio based on the first reverse voltage ratio, the second reverse voltage ratio, and the third reverse voltage ratio.

[0008] Optionally, the on-chip cache-level data flow control circuit of the AI ​​chip also includes an idle state monitoring module and a performance statistics module; The idle state monitoring module is connected to the power consumption calculation and statistics module. The idle state monitoring module is used to determine the load idle state of the on-chip cache based on the power consumption credit summary value of each fixed detection period. Both the risk detection module and the risk processing module are connected to the performance statistics module. The performance statistics module is used to count the number of times the current load risk state is in an alarm state and the target control back voltage rate corresponding to the current load risk state being in an alarm state.

[0009] Secondly, embodiments of the present invention also provide an AI chip on-chip cache-level data flow control method, which is executed by the AI ​​chip on-chip cache-level data flow control circuit provided in any embodiment of the present invention; AI chip on-chip cache-level data flow control methods include: The traffic monitoring module acquires the data stream from the input / output ports; The power consumption calculation and statistics module calculates the power consumption credit value for each detection cycle and compiles the power consumption credit summary value for a fixed detection cycle. The risk detection module determines the current load risk status of the on-chip cache based on multiple consecutively statistical power consumption credit summaries. When the current load risk state is in an alarm state, the risk processing module determines the target control reverse voltage ratio based on the power consumption credit summary value within a preset statistical time period, so as to limit the data flow of the input / output ports of the on-chip buffer.

[0010] Optionally, the power consumption calculation and statistics module includes a power consumption credit conversion unit, a power consumption credit aggregation unit, and a power consumption credit storage unit; The power consumption credit conversion unit is connected to the traffic monitoring module, the power consumption credit conversion unit is connected to the power consumption credit aggregation unit, and the power consumption credit aggregation unit, the risk detection module, and the risk processing module are all connected to the power consumption credit storage unit. The power consumption calculation and statistics module calculates the power consumption credit value for each detection cycle and compiles the total power consumption credit value for a fixed detection cycle, including: The power consumption credit conversion unit calculates the power consumption credit value of each event in each detection period based on the data stream of each event in each detection period. The power consumption credit aggregation unit calculates the periodic power consumption credit value of all events within each detection period. The power consumption credit storage unit calculates the sum of power consumption credit values ​​for multiple cycles within the fixed detection period.

[0011] Optionally, the risk detection module includes a voltage spike detection unit, a short-time limiting current detection unit, and a long-term thermal power consumption detection unit; The voltage spike detection unit and the short-time limiting current detection unit are both connected to the power consumption calculation and statistics module. The long-term thermal power consumption detection unit is connected to the short-time limiting current detection unit. The voltage spike detection unit, the short-time limiting current detection unit, and the long-term thermal power consumption detection unit are all connected to the risk processing module. The risk detection module determines the current load risk status of the on-chip cache based on multiple consecutively statistically summarized power consumption credit values, including: The voltage spike detection unit determines the voltage spike risk status based on multiple consecutively statistically summarized power consumption credit values. The short-time limiting current detection unit determines the short-time limiting current risk status based on the average power consumption credit of multiple continuously statistical power consumption credit aggregate values. The long-term thermal power consumption detection unit determines the long-term thermal power consumption risk status based on multiple continuously statistically averaged power consumption credit values.

[0012] Optionally, the voltage spike risk state includes a first alarm state and a first no-alarm state; The voltage spike detection unit determines the voltage spike risk status based on multiple consecutively statistically summarized power consumption credit values, including: The power consumption credit summary values ​​from multiple consecutive statistics are divided into a near-end power consumption credit summary dataset and a far-end power consumption credit summary dataset. The number of first samples in the near-end power consumption credit summary dataset that are greater than the first power consumption credit threshold is counted. The number of second samples in the remote power consumption credit aggregate dataset that are less than the second power consumption credit threshold is counted. If the number of the first samples is greater than or equal to the first determination threshold and the number of the second samples is greater than or equal to the second determination threshold, then the voltage spike risk state is the first alarm state; otherwise, the voltage spike risk state is the first no-alarm state.

[0013] Optionally, the short-time limiting current risk state includes a second alarm state and a second no-alarm state; The short-time limiting current detection unit determines the short-time limiting current risk status based on the power consumption credit average of multiple continuously statistically aggregated power consumption credit values, including: Calculate the power credit mean of the summation values ​​of the power credit from multiple consecutive statistics; If the average power consumption credit is greater than or equal to the third judgment threshold, then the short-time limit current risk state is the second alarm state; otherwise, the short-time limit current risk state is the second no-alarm state.

[0014] Optionally, the long-term thermal power consumption risk state includes a third alarm state and a third no-alarm state; The long-term thermal power consumption detection unit determines the long-term thermal power consumption risk status based on multiple continuously statistically averaged power consumption credit values, including: The average of the power consumption credits of multiple consecutive statistics is calculated to obtain multiple first average values; By accumulating the average of the first averages of multiple consecutive statistics, multiple second averages are obtained; Calculate the average of the second averages of multiple consecutive statistics to obtain the third average; If the third average value is greater than or equal to the fourth determination threshold, then the long-term thermal power consumption risk state is the third alarm state; otherwise, the long-term thermal power consumption risk state is the third no-alarm state.

[0015] Optionally, the risk handling module includes a voltage spike risk handling unit, a short-time limiting current risk handling unit, a long-term thermal power consumption risk handling unit, and a risk arbitration unit. The voltage spike detection unit is connected to the voltage spike risk processing unit, the short-time limiting current detection unit is connected to the short-time limiting current risk processing unit, the long-term thermal power consumption detection unit is connected to the long-term thermal power consumption risk processing unit, the voltage spike risk processing unit, the short-time limiting current risk processing unit, and the long-term thermal power consumption risk processing unit are all connected to the risk arbitration unit, the short-time limiting current risk processing unit is connected to the power consumption calculation and statistics module, the long-term thermal power consumption risk processing unit is connected to the short-time limiting current risk processing unit, and the risk arbitration unit is connected to the input / output port of the on-chip buffer; When the current load risk state is in an alarm state, the risk processing module determines the target control reverse voltage ratio based on the power consumption credit summary value within a preset statistical time period, including: When the voltage spike risk processing unit is in the first alarm state, it outputs the first reverse voltage ratio. When the short-time limiting current risk state is the second alarm state, the short-time limiting current risk processing unit calculates the second reverse voltage ratio based on the power consumption credit summary value within the first preset statistical time period. When the long-term thermal power consumption risk processing unit is in the third alarm state, it calculates the third reverse voltage ratio based on the average power consumption credit within the second preset statistical time period. The risk arbitration unit determines the target control counterpressure rate based on the first counterpressure rate, the second counterpressure rate, and the third counterpressure rate.

[0016] Optionally, calculating the second reverse voltage ratio based on the power consumption credit summary value within a first preset statistical time period includes: Based on the power consumption credit summary value within the first preset statistical time period, calculate the first read / write overhead ratio and the first unread / write overhead ratio. The second back pressure ratio is determined based on the first read / write overhead ratio and the first non-read / write overhead ratio.

[0017] Optionally, calculating the third reverse voltage ratio based on the average power consumption credit over a second preset statistical time period includes: Based on the average power consumption credit within the second preset statistical time period, calculate the second read / write overhead ratio and the second unread / write overhead ratio. The absolute back pressure ratio is determined based on the second read / write overhead ratio and the second non-read / write overhead ratio. Based on the power consumption credit summary value of each detection cycle within the second preset statistical time period, calculate the third read / write overhead ratio and the third unread / write overhead ratio. The real-time backpressure rate is determined based on the third read / write overhead ratio and the third unread / write overhead ratio. Based on the real-time back pressure rate and the absolute back pressure rate of each detection cycle, determine the corrected back pressure rate space corresponding to each detection cycle; The third back pressure ratio is determined based on the corrected back pressure ratio space and the absolute back pressure ratio corresponding to each detection cycle.

[0018] Optionally, determining the target control backpressure ratio based on the first backpressure ratio, the second backpressure ratio, and the third backpressure ratio includes: The maximum value among the first back pressure rate, the second back pressure rate, and the third back pressure rate is selected as the target control back pressure rate.

[0019] Thirdly, embodiments of the present invention also provide an AI chip, which includes at least one on-chip cache-level data flow control circuit and chip management module provided in any embodiment of the present invention. Each AI chip's on-chip cache-level data flow control circuit is connected to the chip management module.

[0020] This invention employs a flow monitoring module to acquire data streams from input / output ports, and a power consumption calculation and statistics module to calculate the power consumption credit value for each detection cycle. It also aggregates the power consumption credit values ​​for a fixed detection cycle to achieve refined monitoring of the on-chip cache-level data stream. A risk detection module determines the current load risk status of the on-chip cache based on multiple continuously calculated power consumption credit values, enabling the detection of three types of current load risks: voltage spikes, short-term limiting currents, and long-term thermal dissipation caused by the data stream. When the current load risk status is in an alarm state, the risk handling module determines the target control reverse voltage ratio based on the power consumption credit values ​​within a preset statistical time period to limit the data streams from the input / output ports of the on-chip cache. This effectively protects the power integrity of the on-chip system (voltage stability, low ripple, no voltage drops, no oscillations, thus protecting the on-chip system power supply from failure and burnout), reduces the probability and frequency of triggering frequency reduction protection, and minimizes the negative impact on the AI ​​chip's data stream processing performance. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1A schematic diagram of the structure of an on-chip cache-level data flow control circuit for an AI chip provided in an embodiment of the present invention; Figure 2 A schematic diagram of another AI chip on-chip cache-level data flow control circuit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the connection structure between a traffic monitoring module and a power consumption calculation and statistics module provided in an embodiment of the present invention; Figure 4 A schematic diagram of another AI chip on-chip cache-level data flow control circuit provided in an embodiment of the present invention; Figure 5 A flowchart illustrating the steps for determining a voltage spike risk state, provided in an embodiment of the present invention; Figure 6 A flowchart illustrating the steps for determining a short-time limiting current risk state, provided in an embodiment of the present invention; Figure 7 A flowchart illustrating the steps for determining a long-term thermal power consumption risk state is provided in an embodiment of the present invention; Figure 8 A schematic diagram of another AI chip on-chip cache-level data flow control circuit provided in an embodiment of the present invention; Figure 9 A flowchart illustrating an on-chip cache-level data flow control method for an AI chip, provided as an embodiment of the present invention; Figure 10 This is a flowchart illustrating the steps of a power consumption calculation and statistics module for calculating the power consumption credit value for each detection cycle and summarizing the power consumption credit value for a fixed detection cycle, as provided in an embodiment of the present invention. Figure 11 A flowchart illustrating the steps of a risk detection module in an embodiment of the present invention to determine the current load risk status of an on-chip cache based on multiple consecutively statistical power consumption credit summaries; Figure 12 A flowchart illustrating the steps of a voltage spike detection unit to determine the voltage spike risk state based on multiple consecutively statistical power consumption credit summaries, provided in an embodiment of the present invention. Figure 13 This is a flowchart illustrating the steps of a short-time limiting current detection unit to determine the short-time limiting current risk state based on the power consumption credit average of multiple continuously statistical power consumption credit summaries, as provided in an embodiment of the present invention. Figure 14 A flowchart illustrating the steps of a long-term thermal power consumption detection unit to determine the long-term thermal power consumption risk status based on multiple continuously statistical power consumption credit averages, provided in an embodiment of the present invention. Figure 15This is a flowchart illustrating the steps of a risk processing module in an embodiment of the present invention to determine the target control reverse voltage rate based on the power consumption credit summary value within a preset statistical time when the current load risk state is in an alarm state. Figure 16 This is a schematic diagram of the structure of an AI chip provided in an embodiment of the present invention. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] Figure 1 A schematic diagram of an on-chip cache-level data flow control circuit for an AI chip, as provided in an embodiment of the present invention, is shown below. Figure 1 As shown, the on-chip cache-level data flow control circuit of the AI ​​chip includes a flow monitoring module 110, a power consumption calculation and statistics module 120, a risk detection module 130, and a risk processing module 140. The flow monitoring module 110 is connected to the input / output ports of the on-chip buffer 20 and is used to acquire the data flow of the input / output ports. The flow monitoring module 110 is also connected to the power consumption calculation and statistics module 120. The power consumption calculation and statistics module 120 is used to calculate the power consumption credit value for each detection cycle and to collect the power consumption credit summary value for a fixed detection cycle. The power consumption calculation and statistics module 120 is also connected to the risk detection module 130. The risk detection module 130 is used to determine the current load risk status of the on-chip buffer 20 based on the power consumption credit summary values ​​collected in multiple consecutive statistical periods. The risk detection module 130, the power consumption calculation and statistics module 120, and the input / output ports of the on-chip buffer 20 are all connected to the risk processing module 140. When the current load risk status is in an alarm state, the risk processing module 140 is used to determine the target control reverse voltage ratio based on the power consumption credit summary value within a preset statistical time period to limit the data flow of the input / output ports of the on-chip buffer 20.

[0026] The flow monitoring module 110 includes a first throughput counter configured on the input port of the on-chip buffer 20 and a second throughput counter configured on the output port of the on-chip buffer 20, to collect the read and write data streams buffered at the input port and output of the on-chip buffer 20. Both the read and write data streams are configured with independent counting channels, and a shadow buffer is configured to store the counting results. Both the first and second throughput counters operate on the constant-on clock of the on-chip buffer 20. The monitoring sampling interval of the flow monitoring module 110 can be set according to actual needs; for example, the monitoring sampling interval can be configured to 128 / 256 / 512 on-chip buffer clock cycles, where the on-chip buffer clock cycle is preset. For example, the specific process by which the flow monitoring module 110 obtains the data flow of the input / output port is as follows: in each monitoring sampling interval, the read data flow and write data flow of the input / output port of the on-chip buffer 20 are counted independently in 128 bytes, supporting infinite repeated counting. After each monitoring sampling interval ends, the counting result is stored in the shadow buffer, the first throughput counter and the second throughput counter are cleared to zero, and the counting result is output to the power consumption calculation module.

[0027] The power consumption calculation and statistics module 120 can correlate power consumption with current load (data flow) through quantified power consumption credit values, providing standardized data for subsequent risk detection. The specific process by which the power consumption calculation and statistics module 120 calculates the power consumption credit value for each detection cycle and summarizes the power consumption credit value for a fixed detection cycle is as follows: 1) Combine the data flow of each event within each detection cycle with the power consumption corresponding to each event (obtained from the read / write energy bank) to calculate the total power consumption of each event within each detection cycle, and then convert the total power consumption of each event within each detection cycle into a power consumption credit value; 2) Calculate the periodic power consumption credit value for all events within each detection cycle; 3) Calculate the sum of power consumption credit values ​​for multiple periodic power consumption credit values ​​within a fixed detection cycle. The fixed detection cycle is a positive integer multiple of the detection cycle.

[0028] The risk detection module 130 can detect three types of current load risks caused by data flow: voltage spikes, short-time limiting current, and long-term thermal dissipation. It utilizes the characteristic that the voltage is not regulated when the on-chip system is working normally to achieve indirect and accurate detection of current load risk status through the stable conversion relationship between power consumption and current.

[0029] Specifically, the risk detection module 130 determines the current load risk status of the on-chip cache 20 by monitoring multiple consecutive power consumption credit summaries from the power consumption calculation and statistics module 120. The current load risk status of the on-chip cache 20 includes voltage spike risk status, short-time limiting current risk status, and long-term thermal dissipation risk status. The voltage spike risk status determines whether the on-chip cache 20 has a voltage transient impact risk; the short-time limiting current risk status determines whether the on-chip cache 20 has a short-time peak current overload risk; and the long-term thermal dissipation risk status determines whether the on-chip cache 20 has a long-term steady-state thermal overload risk. When the risk detection module 130 determines that the on-chip cache 20 has at least one of the following risks: voltage transient impact risk, short-time peak current overload risk, and long-term steady-state thermal overload risk, the current load risk status of the on-chip cache 20 is set to an alarm state.

[0030] The risk processing module 140 can limit data flow by applying reverse voltage to the read / write channels of the on-chip cache 20's input / output ports when the current load risk state is in an alarm state. The core configurable parameter reverse voltage granularity is 1 / 16 (minimum unit), and the read / write channels can independently configure reverse voltage parameters, achieving fine-grained control over the current load and avoiding the impact of frequency reduction on AI chip performance. In addition, when the current load risk state is in an alarm state, the risk processing module 140 can determine the absolute reverse voltage rate of the channel, i.e., the target control reverse voltage rate, based on the power consumption credit summary value within a preset statistical time period.

[0031] In this embodiment of the invention, the data flow of the input / output ports is acquired by the flow monitoring module 110, and the power consumption calculation and statistics module 120 calculates the power consumption credit value for each detection cycle and summarizes the power consumption credit value for a fixed detection cycle to achieve fine-grained monitoring of the on-chip cache level data flow. The risk detection module 130 determines the current load risk status of the on-chip cache 20 based on multiple continuously calculated power consumption credit summaries to detect three types of current load risks caused by the data flow: voltage spikes, short-term limiting current, and long-term thermal dissipation. When the current load risk status is in an alarm state, the risk processing module 140 determines the target control reverse voltage ratio based on the power consumption credit summaries within a preset statistical time period to limit the data flow of the input / output ports of the on-chip cache 20, thereby limiting the on-chip cache level data flow and effectively protecting the power integrity of the on-chip system (voltage stability, low ripple, no drops, no oscillations, thus protecting the on-chip system power supply from failure and burnout), reducing the probability and frequency of triggering frequency reduction protection, and reducing the negative impact on the data flow processing performance of the AI ​​chip.

[0032] Based on the above embodiments, optionally, Figure 2 This is a schematic diagram of another AI chip on-chip cache-level data flow control circuit provided in an embodiment of the present invention. Figure 3 This is a schematic diagram illustrating the connection structure between a traffic monitoring module and a power consumption calculation and statistics module, provided in an embodiment of the present invention. Figure 2 and Figure 3 As shown, the power consumption calculation and statistics module 120 includes a power consumption credit conversion unit 121, a power consumption credit aggregation unit 122, and a power consumption credit storage unit 123. The power consumption credit conversion unit 121 is connected to the traffic monitoring module 110 and is used to calculate the power consumption credit value of each event in each detection period based on the data stream of each event in each detection period. The power consumption credit conversion unit 121 is connected to the power consumption credit aggregation unit 122 and is used to statistically analyze the periodic power consumption credit values ​​of all events in each detection period. The power consumption credit aggregation unit 122, the risk detection module 130, and the risk processing module 140 are all connected to the power consumption credit storage unit 123 and are used to statistically analyze the power consumption credit aggregation value of multiple periodic power consumption credit values ​​in a fixed detection period.

[0033] The power consumption credit conversion unit 121 calculates the power consumption credit value of each event within each detection cycle based on the data stream of each event within each detection cycle as follows: It acquires the data stream of each event within each detection cycle (the first throughput counter periodically captures the number of input events, and the second throughput counter periodically captures the number of output events); it calculates the total power consumption of each event within each detection cycle based on the power consumption corresponding to each event (obtained in conjunction with the read / write energy bank) and the data stream of each event within each detection cycle; and it calculates the power consumption credit value of each event within each detection cycle based on the total power consumption of each event within each detection cycle (power consumption credit value of each event within each detection cycle = total power consumption of each event within each detection cycle / single-cycle power consumption credit value). The power consumption credit aggregation unit 122 can aggregate (sum) the power consumption credit values ​​of all events within each detection cycle to obtain the cycle power consumption credit value. The cycle power consumption credit value does not exceed a preset maximum power consumption credit value. The fixed detection cycle is a positive integer multiple of the detection cycle. The power consumption credit storage unit 123 can calculate the sum of power consumption credit values ​​for multiple cycles within a fixed detection period, and use it as a power consumption credit summary value. It also stores the power consumption credit summary value for each fixed detection period (e.g., the power consumption credit summary value History0 for the first fixed detection period, the power consumption credit summary value History1 for the second fixed detection period, ..., the power consumption credit summary value Historyn-1 for the (n-1)th fixed detection period, and the power consumption credit summary value Historyn for the nth fixed detection period).

[0034] Based on the above embodiments, optionally, Figure 4 This is a schematic diagram of another AI chip on-chip cache-level data flow control circuit provided in an embodiment of the present invention. Figure 4 As shown, the risk detection module 130 includes a voltage spike detection unit 131, a short-time limiting current detection unit 132, and a long-term thermal power consumption detection unit 133. The voltage spike detection unit 131 and the short-time limiting current detection unit 132 are both connected to the power consumption calculation and statistics module 120, the long-term thermal power consumption detection unit 133 is connected to the short-time limiting current detection unit 132, and the voltage spike detection unit 131, the short-time limiting current detection unit 132, and the long-term thermal power consumption detection unit 133 are all connected to the risk processing module 140.

[0035] The voltage spike detection unit 131 is used to determine the voltage spike risk state based on the sum of multiple consecutive statistical power consumption credit values; the short-time limiting current detection unit 132 is used to determine the short-time limiting current risk state based on the power consumption credit average of multiple consecutive statistical power consumption credit values; and the long-term thermal power consumption detection unit 133 is used to determine the long-term thermal power consumption risk state based on the power consumption credit average of multiple consecutive statistical values.

[0036] The voltage spike risk states include a first alarm state and a first non-alarm state. The first alarm state indicates that the on-chip buffer 20 has a voltage transient impact risk, and the first non-alarm state indicates that the on-chip buffer 20 does not have a voltage transient impact risk. The short-time limiting current risk states include a second alarm state and a second non-alarm state. The second alarm state indicates that the on-chip buffer 20 has a short-time peak current overload risk, and the second non-alarm state indicates that the on-chip buffer 20 does not have a short-time peak current overload risk. The long-term thermal power consumption risk states include a third alarm state and a third non-alarm state. The third alarm state indicates that the on-chip buffer 20 has a long-term steady-state thermal overload risk, and the third non-alarm state indicates that the on-chip buffer 20 does not have a long-term steady-state thermal overload risk.

[0037] Figure 5 This is a flowchart illustrating the steps for determining a voltage spike risk state according to an embodiment of the present invention, as shown below. Figure 5 As shown, the steps for the voltage spike detection unit to determine the voltage spike risk state based on multiple consecutively statistically summarized power consumption credit values ​​are described as follows: Multiple consecutively statistically summarized power consumption credit values ​​(power consumption credit summary value 1, power consumption credit summary value 2, ..., power consumption credit summary value 8) are divided into a near-end power consumption credit summary dataset [power consumption credit summary value 1, power consumption credit summary value 2, power consumption credit summary value 3, power consumption credit summary value 4] and a far-end power consumption credit summary dataset [power consumption credit summary value 5, power consumption credit summary value 6, power consumption credit summary value 7, power consumption credit summary value 8]; the number of samples M1 in the near-end power consumption credit summary dataset that are greater than the first power consumption credit threshold THL1 is counted; the number of samples M2 in the far-end power consumption credit summary dataset that are less than the second power consumption credit threshold THL2 is counted; if the number of samples M1 is greater than or equal to the first judgment threshold N1 and the number of samples M2 is greater than or equal to the second judgment threshold N2 (i.e., M1≥N1&M2≥N2), then the voltage spike risk state is the first alarm state; otherwise, the voltage spike risk state is the first non-alarm state.

[0038] The near-end power consumption credit summary dataset is extracted using a near-end window, while the far-end power consumption credit summary dataset is extracted using a far-end window. The near-end window length, far-end window length, first power consumption credit threshold, second power consumption credit threshold, first judgment threshold, and second judgment threshold are all preset values.

[0039] Figure 6 This is a flowchart illustrating the steps for determining a short-time limiting current risk state according to an embodiment of the present invention, as shown below. Figure 6As shown, the steps for the short-time limiting current detection unit to determine the short-time limiting current risk state based on the power consumption credit average of multiple consecutively statistical power consumption credit summary values ​​are described: Calculate the power consumption credit average of multiple consecutively statistical power consumption credit summary values ​​(power consumption credit summary value 1, power consumption credit summary value 2, ..., power consumption credit summary value 8); if the power consumption credit average is greater than or equal to the third judgment threshold N3, the short-time limiting current risk state is the second alarm state; otherwise, the short-time limiting current risk state is the second non-alarm state.

[0040] The power consumption credit average is calculated as follows: (Power consumption credit summary value 1 + Power consumption credit summary value 2 + ... + Power consumption credit summary value 8) / 8. Additionally, a moving average window can be used to collect multiple consecutive statistical power consumption credit summary values. The moving average window length and the third judgment threshold are both preset values.

[0041] Figure 7 A flowchart illustrating the steps for determining a long-term thermal dissipation risk state is provided in this embodiment of the invention, as follows: Figure 7 As shown, the steps of the long-term thermal power consumption detection unit to determine the long-term thermal power consumption risk status based on multiple consecutive statistical average power consumption credit values ​​are described: The average of multiple consecutive statistical average power consumption credit values ​​(average power consumption credit value 1, average power consumption credit value 2, average power consumption credit value 3, average power consumption credit value 4) is accumulated to obtain multiple first average values; the average of multiple consecutive statistical first average values ​​(first average value 1, first average value 2, first average value 3, first average value 4) is accumulated to obtain multiple second average values; the average of multiple consecutive statistical second average values ​​(second average value 1, second average value 2, second average value 3, second average value 4) is calculated to obtain a third average value; if the third average value is greater than or equal to the fourth judgment threshold N4, the long-term thermal power consumption risk status is the third alarm status; otherwise, the long-term thermal power consumption risk status is the third non-alarm status.

[0042] Wherein, the first average value = (power consumption credit average 1 + power consumption credit average 2 + ... + power consumption credit average 4) / 4; the second average value = (first average value 1 + first average value 2 + ... + first average value 4) / 4; the third average value = (second average value 1 + second average value 2 + ... + second average value 4) / 4.

[0043] In addition, the number of samples for obtaining the power consumption credit average, the number of samples for obtaining the first average, the number of samples for obtaining the second average, and the fourth judgment threshold are all preset values. Figure 7 The number of samples for obtaining the power consumption credit mean, the number of samples for obtaining the first average value, and the number of samples for obtaining the second average value are all preset to 4.

[0044] Based on the above embodiments, alternatively, refer to the following: Figure 4 The risk handling module 140 includes a voltage spike risk handling unit 141, a short-time limiting current risk handling unit 142, a long-term thermal power consumption risk handling unit 143, and a risk arbitration unit 144. Voltage spike detection unit 131 is connected to voltage spike risk processing unit 141; short-time limiting current detection unit 132 is connected to short-time limiting current risk processing unit 142; long-term thermal power consumption detection unit 133 is connected to long-term thermal power consumption risk processing unit 143; voltage spike risk processing unit 141, short-time limiting current risk processing unit 142, and long-term thermal power consumption risk processing unit 143 are all connected to risk arbitration unit 144; short-time limiting current risk processing unit 142 is connected to power consumption calculation and statistics module 120; long-term thermal power consumption risk processing unit 143 is connected to short-time limiting current risk processing unit 142; and risk arbitration unit 144 is connected to the input / output port of on-chip buffer 20. The connection between short-time limiting current risk processing unit 142 and power consumption calculation and statistics module 120 refers to the connection between short-time limiting current risk processing unit 142 and power consumption credit storage unit 123.

[0045] The voltage spike risk processing unit 141 is used to generate a first reverse voltage ratio when the voltage spike risk state is a first alarm state; the short-time limiting current risk processing unit 142 is used to calculate a second reverse voltage ratio based on the power consumption credit summary value within a first preset statistical time period when the short-time limiting current risk state is a second alarm state; the long-term thermal power consumption risk processing unit 143 is used to calculate a third reverse voltage ratio based on the average power consumption credit value within a second preset statistical time period when the long-term thermal power consumption risk state is a third alarm state; and the risk arbitration unit 144 is used to determine a target control reverse voltage ratio based on the first reverse voltage ratio, the second reverse voltage ratio, and the third reverse voltage ratio.

[0046] The steps of the voltage spike risk processing unit 141 generating a first reverse voltage ratio when the voltage spike risk state is the first alarm state are described: the first reverse voltage ratio is obtained in advance. The first reverse voltage ratio can be configured independently. For example, the first reverse voltage ratio can be applied after rounding up to 1 / 16 granularity.

[0047] The steps for calculating the second reverse voltage ratio based on the power consumption credit summary value within the first preset statistical time period are described as follows: Calculate the first read / write overhead ratio and the first non-read / write overhead ratio based on the power consumption credit summary value within the first preset statistical time period; determine the second reverse voltage ratio based on the first read / write overhead ratio and the first non-read / write overhead ratio. For example, within the statistical window (a first preset statistical time period, e.g., 1024 cycles), the number of valid read / write requests is counted (800 cycles). Assuming the power consumption credit summary value of the second alarm state causing short-term overcurrent risk in 800 cycles is 120, and the third judgment threshold for judging short-term overcurrent risk is 100, then the reverse voltage ratio is 1 - (100 / 120) × 100% = 17%. Therefore, 3 (17% × 16) cycles within 16 cycles require reverse voltage, meaning the first read / write overhead ratio is 3 / 16. (1024 - 800) / 1024 = 22%, meaning that on average, 4 cycles within 16 cycles (22% × 16) have no read / write requests, meaning the first non-read / write overhead ratio is 4 / 16. The second reverse voltage ratio = first read / write overhead ratio + first non-read / write overhead ratio = 7 / 16.

[0048] The steps for calculating the third backvoltage ratio based on the average power consumption credit over a second preset statistical period are described as follows: Calculate the second read / write overhead ratio and the second non-read / write overhead ratio based on the average power consumption credit over the second preset statistical period; determine the absolute backvoltage ratio based on the second read / write overhead ratio and the second non-read / write overhead ratio; calculate the third read / write overhead ratio and the third non-read / write overhead ratio based on the sum of power consumption credits for each detection cycle within the second preset statistical period; determine the real-time backvoltage ratio based on the third read / write overhead ratio and the third non-read / write overhead ratio; determine the corrected backvoltage ratio space for each detection cycle based on the real-time backvoltage ratio and the absolute backvoltage ratio for each detection cycle; and determine the third backvoltage ratio based on the corrected backvoltage ratio space and the absolute backvoltage ratio for each detection cycle.

[0049] The calculation methods for the absolute back pressure ratio and the real-time back pressure ratio are the same as those for calculating the second back pressure ratio, and will not be repeated here. For example, the absolute back pressure ratio is 7 / 16; the real-time back pressure ratio for the first detection cycle within the second preset statistical time period is 10 / 16, for the second detection cycle it is 5 / 16, for the third detection cycle it is 9 / 16, for the fourth detection cycle it is 4 / 16, for the fifth detection cycle it is 7 / 16, for the sixth detection cycle it is 6 / 16, for the seventh detection cycle it is 1 / 16, for the eighth detection cycle it is 7 / 16, for the ninth detection cycle it is 11 / 16, and for the tenth detection cycle it is 7 / 16. Therefore, the corrected back pressure ratio space for the first testing cycle is 10 / 16 - 7 / 16 = 3 / 16; for the second testing cycle, it is 3 / 16 + (5 / 16 - 7 / 16) = 1 / 16; for the third testing cycle, it is 1 / 16 + (9 / 16 - 7 / 16) = 3 / 16; for the fourth testing cycle, it is 3 / 16 + (4 / 16 - 7 / 16) = 0; for the fifth testing cycle, it is 0 + (7 / 16 - 7 / 16) = 0; and for the sixth testing cycle, it is 0 + (6 / 16 - 7 / 16). =-1 / 16, the corrected back pressure ratio space for the seventh detection cycle is -1 / 16 + (1 / 16 - 7 / 16) = -7 / 16, the corrected back pressure ratio space for the eighth detection cycle is -7 / 16 + (7 / 16 - 7 / 16) = -7 / 16, the corrected back pressure ratio space for the ninth detection cycle is -7 / 16 + (11 / 16 - 7 / 16) = -3 / 16, the corrected back pressure ratio space for the tenth detection cycle is -3 / 16 + (7 / 16 - 7 / 16) = -3 / 16; the third back pressure ratio = absolute back pressure ratio - corrected back pressure ratio space = 7 / 16 - (-3 / 16) = 10 / 16.

[0050] The steps of risk arbitration unit 144 in determining the target control counterpressure rate based on the first counterpressure rate, the second counterpressure rate, and the third counterpressure rate are described as follows: the maximum value among the first counterpressure rate, the second counterpressure rate, and the third counterpressure rate is selected as the target control counterpressure rate.

[0051] Based on the above embodiments, optionally, Figure 8 This is a schematic diagram of another AI chip on-chip cache-level data flow control circuit provided in an embodiment of the present invention. Figure 8As shown, the AI ​​chip on-chip cache-level data flow control circuit also includes an idle state monitoring module 150 and a performance statistics module 160; the idle state monitoring module 150 is connected to the power consumption calculation and statistics module 120, and the idle state monitoring module 150 is used to determine the load idle state of the on-chip cache 20 based on the power consumption credit summary value of each fixed detection cycle. Both the risk detection module 130 and the risk processing module 140 are connected to the performance statistics module 160. The performance statistics module 160 is used to count the number of times the current load risk state is in the alarm state and the target control back voltage rate corresponding to the current load risk state in the alarm state.

[0052] The idle state monitoring module 150 collects the average power consumption credit of multiple continuously statistical power consumption credit summaries. When the average power consumption credit is less than the idle threshold, it determines that the data flow of the on-chip cache 20 is in an idle / very low load state. The performance statistics module 160 includes registers that support software clearing and reading, and can count the number of alarms from the risk detection module 130 and the target control backpressure rate generated by the risk processing module 140.

[0053] Figure 9 This is a flowchart illustrating an on-chip cache-level data flow control method for an AI chip, as provided in an embodiment of the present invention. Figure 9 As shown, the AI ​​chip on-chip cache-level data flow control method is executed using the AI ​​chip on-chip cache-level data flow control circuit provided in any embodiment of the present invention; The AI ​​chip on-chip cache-level data flow control method provided in this embodiment specifically includes: S110, the flow monitoring module acquires the data stream from the input / output ports.

[0054] S120 The power consumption calculation and statistics module calculates the power consumption credit value for each detection cycle and compiles the power consumption credit summary value for a fixed detection cycle.

[0055] S130 The risk detection module determines the current load risk status of the on-chip cache based on the sum of multiple continuously statistical power consumption credit values.

[0056] S140. When the current load risk state is in an alarm state, the risk processing module determines the target control reverse voltage ratio based on the power consumption credit summary value within a preset statistical time period in order to limit the data flow of the input / output ports of the on-chip buffer.

[0057] This invention employs a flow monitoring module to acquire data streams from input / output ports, and a power consumption calculation and statistics module to calculate the power consumption credit value for each detection cycle. It also aggregates the power consumption credit values ​​for a fixed detection cycle to achieve refined monitoring of the on-chip cache-level data stream. A risk detection module determines the current load risk status of the on-chip cache based on multiple continuously calculated power consumption credit values, enabling the detection of three types of current load risks: voltage spikes, short-term limiting currents, and long-term thermal dissipation caused by the data stream. When the current load risk status is in an alarm state, the risk handling module determines the target control reverse voltage ratio based on the power consumption credit values ​​within a preset statistical time period to limit the data streams from the input / output ports of the on-chip cache. This effectively protects the power integrity of the on-chip system (voltage stability, low ripple, no voltage drops, no oscillations, thus protecting the on-chip system power supply from failure and burnout), reduces the probability and frequency of triggering frequency reduction protection, and minimizes the negative impact on the AI ​​chip's data stream processing performance.

[0058] Based on the above embodiments, optionally, the power consumption calculation and statistics module includes a power consumption credit conversion unit, a power consumption credit aggregation unit, and a power consumption credit storage unit; the power consumption credit conversion unit is connected to the traffic monitoring module, the power consumption credit conversion unit is connected to the power consumption credit aggregation unit, and the power consumption credit aggregation unit, the risk detection module, and the risk processing module are all connected to the power consumption credit storage unit.

[0059] Figure 10 This is a flowchart illustrating the steps of a power consumption calculation and statistics module for calculating the power consumption credit value for each detection cycle and summarizing the power consumption credit value for a fixed detection cycle, as provided in an embodiment of the present invention. Figure 10 The steps for the power consumption calculation and statistics module to calculate the power consumption credit value for each detection cycle and to summarize the power consumption credit value for a fixed detection cycle are described below: S210, the power consumption credit conversion unit calculates the power consumption credit value of each event in each detection cycle based on the data stream of each event in each detection cycle.

[0060] S220, the power consumption credit aggregation unit calculates the periodic power consumption credit value of all events within each detection cycle.

[0061] S230, the power consumption credit storage unit calculates the sum of power consumption credit values ​​for multiple cycles within a fixed detection period.

[0062] Based on the above embodiments, optionally, the risk detection module includes a voltage spike detection unit, a short-time limiting current detection unit, and a long-term thermal power consumption detection unit; the voltage spike detection unit and the short-time limiting current detection unit are both connected to the power consumption calculation and statistics module, the long-term thermal power consumption detection unit is connected to the short-time limiting current detection unit, and the voltage spike detection unit, the short-time limiting current detection unit, and the long-term thermal power consumption detection unit are all connected to the risk processing module.

[0063] Based on the above embodiments, optionally, Figure 11 This is a flowchart illustrating the steps of a risk detection module in an embodiment of the present invention to determine the current load risk status of an on-chip cache based on a summation of multiple consecutive power consumption credit values. Figure 11 As shown, the steps of the risk detection module in determining the current load risk status of the on-chip cache based on the aggregated power consumption credit values ​​from multiple consecutive statistics are explained: S310, the voltage spike detection unit determines the voltage spike risk status based on the sum of multiple continuously statistical power consumption credit values.

[0064] The S320 short-time limiting current detection unit determines the short-time limiting current risk status based on the average power consumption credit of multiple continuously statistical power consumption credit aggregated values.

[0065] The S330 long-term thermal power consumption detection unit determines the long-term thermal power consumption risk status based on the average power consumption credit values ​​of multiple consecutive statistics.

[0066] Based on the above embodiments, optionally, the voltage spike risk state includes a first alarm state and a first non-alarm state; the short-time limiting current risk state includes a second alarm state and a second non-alarm state; and the long-term thermal dissipation risk state includes a third alarm state and a third non-alarm state.

[0067] Figure 12 This is a flowchart illustrating the steps of a voltage spike detection unit, as provided in an embodiment of the present invention, to determine the voltage spike risk state based on a summation of multiple consecutively statistical power consumption credit values. Figure 12 The steps for the voltage spike detection unit to determine the voltage spike risk state based on the sum of multiple consecutive statistical power consumption credit values ​​are described below: S410. Divide the power consumption credit summary values ​​of multiple consecutive statistics into near-end power consumption credit summary dataset and far-end power consumption credit summary dataset.

[0068] S420, Count the number of first samples in the near-end power consumption credit summary dataset that are greater than the first power consumption credit threshold.

[0069] S430, Count the number of second samples in the remote power consumption credit summary dataset that are less than the second power consumption credit threshold.

[0070] S440. If the number of first samples is greater than or equal to the first judgment threshold and the number of second samples is greater than or equal to the second judgment threshold, then the voltage spike risk state is the first alarm state; otherwise, the voltage spike risk state is the first non-alarm state.

[0071] Figure 13 This is a flowchart illustrating the steps of a short-time limiting current detection unit, provided in an embodiment of the present invention, to determine the short-time limiting current risk state based on the power consumption credit average of multiple continuously statistical power consumption credit summaries. Figure 13 The steps for the short-time limiting current detection unit to determine the short-time limiting current risk state based on the power consumption credit average of multiple consecutive statistical power consumption credit summaries are described below: S510. Calculate the power credit mean of the sum of power credit values ​​of multiple consecutive statistics.

[0072] S520. If the average power consumption credit is greater than or equal to the third judgment threshold, the short-time limit current risk state is the second alarm state; otherwise, the short-time limit current risk state is the second non-alarm state.

[0073] Figure 14 This is a flowchart illustrating the steps of a long-term thermal power consumption detection unit, as provided in an embodiment of the present invention, to determine the long-term thermal power consumption risk status based on multiple continuously statistical power consumption credit averages. Figure 14 As shown, the steps for the long-term thermal power consumption detection unit to determine the long-term thermal power consumption risk status based on the average of multiple continuously statistical power consumption credit values ​​are explained: S610: Accumulate and calculate the average of multiple consecutive statistical power consumption credit averages to obtain multiple first average values.

[0074] S620. Calculate the average of the first averages of multiple consecutive statistics to obtain multiple second averages.

[0075] S630. Calculate the average of the second averages of multiple consecutive statistics to obtain the third average.

[0076] S640. If the third average value is greater than or equal to the fourth judgment threshold, the long-term thermal power consumption risk status is the third alarm status; otherwise, the long-term thermal power consumption risk status is the third non-alarm status.

[0077] Based on the above embodiments, optionally, the risk processing module includes a voltage spike risk processing unit, a short-time limiting current risk processing unit, a long-term thermal power consumption risk processing unit, and a risk arbitration unit; the voltage spike detection unit is connected to the voltage spike risk processing unit, the short-time limiting current detection unit is connected to the short-time limiting current risk processing unit, the long-term thermal power consumption detection unit is connected to the long-term thermal power consumption risk processing unit, the voltage spike risk processing unit, the short-time limiting current risk processing unit, and the long-term thermal power consumption risk processing unit are all connected to the risk arbitration unit, the short-time limiting current risk processing unit is connected to the power consumption calculation and statistics module, the long-term thermal power consumption risk processing unit is connected to the short-time limiting current risk processing unit, and the risk arbitration unit is connected to the input / output port of the on-chip buffer.

[0078] Figure 15 This is a flowchart illustrating the steps of a risk processing module in an embodiment of the present invention to determine a target control reverse voltage rate based on the power consumption credit summary value within a preset statistical time period when the current load risk state is in an alarm state. Figure 15 As shown, the steps for the risk handling module to determine the target control reverse voltage ratio based on the power consumption credit summary value within a preset statistical time period when the current load risk state is in an alarm state are explained: When the voltage spike risk processing unit is in the first alarm state, the S710 outputs the first reverse voltage ratio.

[0079] S720, when the short-time limit current risk processing unit is in the second alarm state, calculates the second reverse voltage ratio based on the power consumption credit summary value within the first preset statistical time period.

[0080] Specifically, based on the power consumption credit summary value within the first preset statistical time period, the first read / write overhead ratio and the first unread / write overhead ratio are calculated; based on the first read / write overhead ratio and the first unread / write overhead ratio, the second reverse voltage ratio is determined.

[0081] When the long-term thermal power consumption risk processing unit is in the third alarm state, it calculates the third reverse voltage rate based on the average power consumption credit within the second preset statistical time period.

[0082] Specifically, based on the average power consumption credit within the second preset statistical time period, the second read / write overhead ratio and the second non-read / write overhead ratio are calculated; based on the second read / write overhead ratio and the second non-read / write overhead ratio, the absolute back voltage ratio is determined; based on the power consumption credit summary value of each detection cycle within the second preset statistical time period, the third read / write overhead ratio and the third non-read / write overhead ratio are calculated; based on the third read / write overhead ratio and the third non-read / write overhead ratio, the real-time back voltage ratio is determined; based on the real-time back voltage ratio and the absolute back voltage ratio of each detection cycle, the corrected back voltage ratio space corresponding to each detection cycle is determined; based on the corrected back voltage ratio space and the absolute back voltage ratio corresponding to each detection cycle, the third back voltage ratio is determined.

[0083] S740, The risk arbitration unit determines the target control counterpressure rate based on the first counterpressure rate, the second counterpressure rate, and the third counterpressure rate.

[0084] Specifically, the maximum value among the first, second, and third back pressure rates is selected as the target control back pressure rate.

[0085] Figure 16 This is a schematic diagram of the structure of an AI chip provided in an embodiment of the present invention. The structure of the AI ​​chip includes at least one on-chip cache-level data flow control circuit 10 and a chip management module 30 provided in any embodiment of the present invention; each on-chip cache-level data flow control circuit 10 is connected to the chip management module 30.

[0086] Specifically, the idle state monitoring module 150 and performance statistics module 160 of the on-chip cache-level data flow control circuit 10 of each AI chip are connected to the chip management module 30.

[0087] The idle state monitoring module 150 aggregates the load idle state signal to the chip management module 30 via a sideband interface, providing hardware basis for low-power management of the AI ​​chip. The performance statistics module 160 aggregates the alarm count of the risk detection module and the target control backpressure rate generated by the risk processing module to the chip management module 30 via a sideband interface, thereby improving the debuggability and analyzability of the protection scheme.

[0088] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0089] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A data flow control circuit for on-chip cache level in an AI chip, characterized in that, It includes a traffic monitoring module, a power consumption calculation and statistics module, a risk detection module, and a risk handling module; The flow monitoring module is connected to the input / output port of the on-chip buffer, and the flow monitoring module is used to acquire the data stream of the input / output port; The traffic monitoring module is connected to the power consumption calculation and statistics module; the power consumption calculation and statistics module is used to calculate the power consumption credit value for each detection cycle and to calculate the power consumption credit summary value for a fixed detection cycle. The power consumption calculation and statistics module is connected to the risk detection module; the risk detection module is used to determine the current load risk status of the on-chip cache based on multiple consecutively statistically summarized power consumption credit values. The risk detection module, the power consumption calculation and statistics module, and the input / output ports of the on-chip buffer are all connected to the risk processing module. The risk processing module is used to determine the target control reverse voltage ratio based on the power consumption credit summary value within a preset statistical time when the current load risk state is in an alarm state, so as to limit the data flow of the input / output ports of the on-chip buffer.

2. The AI ​​chip on-chip cache-level data flow control circuit according to claim 1, characterized in that, The power consumption calculation and statistics module includes a power consumption credit conversion unit, a power consumption credit aggregation unit, and a power consumption credit storage unit. The power consumption credit conversion unit is connected to the traffic monitoring module. The power consumption credit conversion unit is used to calculate the power consumption credit value of each event in each detection period based on the data stream of each event in each detection period. The power consumption credit conversion unit is connected to the power consumption credit aggregation unit, and the power consumption credit aggregation unit is used to calculate the periodic power consumption credit value of all events in each detection period. The power consumption credit aggregation unit, the risk detection module, and the risk processing module are all connected to the power consumption credit storage unit. The power consumption credit storage unit is used to calculate the power consumption credit aggregation value of multiple periodic power consumption credit values ​​within the fixed detection period.

3. The AI ​​chip on-chip cache-level data flow control circuit according to claim 1, characterized in that, The risk detection module includes a voltage spike detection unit, a short-time limiting current detection unit, and a long-term thermal power consumption detection unit. The voltage spike detection unit and the short-time limiting current detection unit are both connected to the power consumption calculation and statistics module. The long-term thermal power consumption detection unit is connected to the short-time limiting current detection unit. The voltage spike detection unit, the short-time limiting current detection unit, and the long-term thermal power consumption detection unit are all connected to the risk processing module. The voltage spike detection unit is used to determine the voltage spike risk status based on multiple consecutively statistical power consumption credit summaries. The short-time limiting current detection unit is used to determine the short-time limiting current risk status based on the power consumption credit average of multiple continuously statistical power consumption credit aggregate values. The long-term thermal power consumption detection unit is used to determine the long-term thermal power consumption risk status based on multiple continuously statistical average power consumption credit values.

4. The AI ​​chip on-chip cache-level data flow control circuit according to claim 3, characterized in that, The risk handling module includes a voltage spike risk handling unit, a short-time limiting current risk handling unit, a long-term thermal power consumption risk handling unit, and a risk arbitration unit. The voltage spike detection unit is connected to the voltage spike risk processing unit, the short-time limiting current detection unit is connected to the short-time limiting current risk processing unit, the long-term thermal power consumption detection unit is connected to the long-term thermal power consumption risk processing unit, the voltage spike risk processing unit, the short-time limiting current risk processing unit, and the long-term thermal power consumption risk processing unit are all connected to the risk arbitration unit, the short-time limiting current risk processing unit is connected to the power consumption calculation and statistics module, the long-term thermal power consumption risk processing unit is connected to the short-time limiting current risk processing unit, and the risk arbitration unit is connected to the input / output port of the on-chip buffer; The voltage spike risk processing unit is used to generate a first reverse voltage ratio when the voltage spike risk state is a first alarm state; the short-time limiting current risk processing unit is used to calculate a second reverse voltage ratio based on the power consumption credit summary value within a first preset statistical time period when the short-time limiting current risk state is a second alarm state; the long-term thermal power consumption risk processing unit is used to calculate a third reverse voltage ratio based on the power consumption credit average value within a second preset statistical time period when the long-term thermal power consumption risk state is a third alarm state; and the risk arbitration unit is used to determine the target control reverse voltage ratio based on the first reverse voltage ratio, the second reverse voltage ratio, and the third reverse voltage ratio.

5. The AI ​​chip on-chip cache-level data flow control circuit according to claim 1, characterized in that, It also includes an idle state monitoring module and a performance statistics module; The idle state monitoring module is connected to the power consumption calculation and statistics module. The idle state monitoring module is used to determine the load idle state of the on-chip cache based on the power consumption credit summary value of each fixed detection period. Both the risk detection module and the risk processing module are connected to the performance statistics module. The performance statistics module is used to count the number of times the current load risk state is in an alarm state and the target control back voltage rate corresponding to the current load risk state being in an alarm state.

6. A method for controlling the data flow at the on-chip cache level of an AI chip, characterized in that, The AI ​​chip on-chip cache-level data flow control circuit described in any one of claims 1-5 is used for execution. AI chip on-chip cache-level data flow control methods include: The traffic monitoring module acquires the data stream from the input / output ports; The power consumption calculation and statistics module calculates the power consumption credit value for each detection cycle and compiles the power consumption credit summary value for a fixed detection cycle. The risk detection module determines the current load risk status of the on-chip cache based on multiple consecutively statistical power consumption credit summaries. When the current load risk state is in an alarm state, the risk processing module determines the target control reverse voltage ratio based on the power consumption credit summary value within a preset statistical time period, so as to limit the data flow of the input / output ports of the on-chip buffer.

7. The AI ​​chip on-chip cache-level data flow control method according to claim 6, characterized in that, The power consumption calculation and statistics module includes a power consumption credit conversion unit, a power consumption credit aggregation unit, and a power consumption credit storage unit. The power consumption credit conversion unit is connected to the traffic monitoring module, the power consumption credit conversion unit is connected to the power consumption credit aggregation unit, and the power consumption credit aggregation unit, the risk detection module, and the risk processing module are all connected to the power consumption credit storage unit. The power consumption calculation and statistics module calculates the power consumption credit value for each detection cycle and compiles the power consumption credit summary value for a fixed detection cycle, including: The power consumption credit conversion unit calculates the power consumption credit value of each event in each detection period based on the data stream of each event in each detection period. The power consumption credit aggregation unit calculates the periodic power consumption credit value of all events within each detection period. The power consumption credit storage unit calculates the sum of power consumption credit values ​​for multiple cycles within the fixed detection period.

8. The AI ​​chip on-chip cache-level data flow control method according to claim 6, characterized in that, The risk detection module includes a voltage spike detection unit, a short-time limiting current detection unit, and a long-term thermal power consumption detection unit. The voltage spike detection unit and the short-time limiting current detection unit are both connected to the power consumption calculation and statistics module. The long-term thermal power consumption detection unit is connected to the short-time limiting current detection unit. The voltage spike detection unit, the short-time limiting current detection unit, and the long-term thermal power consumption detection unit are all connected to the risk processing module. The risk detection module determines the current load risk status of the on-chip cache based on multiple consecutively statistically summarized power consumption credit values, including: The voltage spike detection unit determines the voltage spike risk status based on multiple consecutively statistically summarized power consumption credit values. The short-time limiting current detection unit determines the short-time limiting current risk status based on the average power consumption credit of multiple continuously statistical power consumption credit aggregate values. The long-term thermal power consumption detection unit determines the long-term thermal power consumption risk status based on multiple continuously statistically averaged power consumption credit values.

9. The AI ​​chip on-chip cache-level data flow control method according to claim 8, characterized in that, The voltage spike risk state includes a first alarm state and a first no alarm state; The voltage spike detection unit determines the voltage spike risk status based on multiple consecutively statistically summarized power consumption credit values, including: The power consumption credit summary values ​​from multiple consecutive statistics are divided into a near-end power consumption credit summary dataset and a far-end power consumption credit summary dataset. The number of first samples in the near-end power consumption credit summary dataset that are greater than the first power consumption credit threshold is counted. The number of second samples in the remote power consumption credit aggregate dataset that are less than the second power consumption credit threshold is counted. If the number of the first samples is greater than or equal to the first determination threshold and the number of the second samples is greater than or equal to the second determination threshold, then the voltage spike risk state is the first alarm state; otherwise, the voltage spike risk state is the first no-alarm state.

10. The AI ​​chip on-chip cache-level data flow control method according to claim 8, characterized in that, The short-time limiting current risk state includes a second alarm state and a second no-alarm state; The short-time limiting current detection unit determines the short-time limiting current risk status based on the power credit average of multiple continuously statistically aggregated power credit values, including: Calculate the power credit mean of the summation values ​​of the power credit from multiple consecutive statistics; If the average power consumption credit is greater than or equal to the third judgment threshold, then the short-time limit current risk state is the second alarm state; otherwise, the short-time limit current risk state is the second no-alarm state.

11. The AI ​​chip on-chip cache-level data flow control method according to claim 8, characterized in that, The long-term thermal power consumption risk status includes a third alarm status and a third no alarm status; The long-term thermal power consumption detection unit determines the long-term thermal power consumption risk status based on multiple continuously statistically averaged power consumption credit values, including: The average of the power consumption credits of multiple consecutive statistics is calculated to obtain multiple first average values; By accumulating the average of the first averages of multiple consecutive statistics, multiple second averages are obtained; Calculate the average of the second averages of multiple consecutive statistics to obtain the third average; If the third average value is greater than or equal to the fourth determination threshold, then the long-term thermal power consumption risk state is the third alarm state; otherwise, the long-term thermal power consumption risk state is the third no-alarm state.

12. The AI ​​chip on-chip cache-level data flow control method according to claim 8, characterized in that, The risk handling module includes a voltage spike risk handling unit, a short-time limiting current risk handling unit, a long-term thermal power consumption risk handling unit, and a risk arbitration unit. The voltage spike detection unit is connected to the voltage spike risk processing unit, the short-time limiting current detection unit is connected to the short-time limiting current risk processing unit, the long-term thermal power consumption detection unit is connected to the long-term thermal power consumption risk processing unit, the voltage spike risk processing unit, the short-time limiting current risk processing unit, and the long-term thermal power consumption risk processing unit are all connected to the risk arbitration unit, the short-time limiting current risk processing unit is connected to the power consumption calculation and statistics module, the long-term thermal power consumption risk processing unit is connected to the short-time limiting current risk processing unit, and the risk arbitration unit is connected to the input / output port of the on-chip buffer; When the current load risk state is in an alarm state, the risk processing module determines the target control reverse voltage ratio based on the power consumption credit summary value within a preset statistical time period, including: When the voltage spike risk processing unit is in the first alarm state, it outputs the first reverse voltage ratio. When the short-time limiting current risk state is the second alarm state, the short-time limiting current risk processing unit calculates the second reverse voltage ratio based on the power consumption credit summary value within the first preset statistical time period. When the long-term thermal power consumption risk processing unit is in the third alarm state, it calculates the third reverse voltage ratio based on the average power consumption credit within the second preset statistical time period. The risk arbitration unit determines the target control counterpressure rate based on the first counterpressure rate, the second counterpressure rate, and the third counterpressure rate.

13. The AI ​​chip on-chip cache-level data flow control method according to claim 12, characterized in that, The step of calculating the second reverse voltage ratio based on the power consumption credit summary value within a first preset statistical time period includes: Based on the power consumption credit summary value within the first preset statistical time period, calculate the first read / write overhead ratio and the first unread / write overhead ratio. The second back pressure ratio is determined based on the first read / write overhead ratio and the first non-read / write overhead ratio.

14. The AI ​​chip on-chip cache-level data flow control method according to claim 12, characterized in that, The step of calculating the third reverse voltage ratio based on the average power consumption credit over a second preset statistical time period includes: Based on the average power consumption credit within the second preset statistical time period, calculate the second read / write overhead ratio and the second unread / write overhead ratio. The absolute back pressure ratio is determined based on the second read / write overhead ratio and the second non-read / write overhead ratio. Based on the power consumption credit summary value of each detection cycle within the second preset statistical time period, calculate the third read / write overhead ratio and the third unread / write overhead ratio. The real-time backpressure rate is determined based on the third read / write overhead ratio and the third unread / write overhead ratio. Based on the real-time back pressure rate and the absolute back pressure rate of each detection cycle, determine the corrected back pressure rate space corresponding to each detection cycle; The third back pressure ratio is determined based on the corrected back pressure ratio space and the absolute back pressure ratio corresponding to each detection cycle.

15. The AI ​​chip on-chip cache-level data flow control method according to claim 12, characterized in that, Determining the target control counterpressure ratio based on the first counterpressure ratio, the second counterpressure ratio, and the third counterpressure ratio includes: The maximum value among the first back pressure rate, the second back pressure rate, and the third back pressure rate is selected as the target control back pressure rate.

16. An AI chip, characterized in that, Includes at least one on-chip cache-level data flow control circuit and chip management module as described in any one of claims 1-5; Each AI chip's on-chip cache-level data flow control circuit is connected to the chip management module.

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