Fast QR decomposition algorithm based on mirror transformation IP device and construction method

Abstract

The application provides a fast QR decomposition algorithm IP device and a construction method based on mirror transformation, comprising: a pulsating matrix multiplication module for calculating output matrix multiplication; a Householder mirror transformation module for constructing a Householder mirror transformation matrix; a QR-cycle module for performing one Householder transformation on an input non-singular matrix based on the mirror transformation matrix, in combination with the pulsating matrix multiplication module, a row output timing module and a column output timing module, and outputting an updated non-singular upper triangular matrix, a column vector to be transformed and a multiplied orthogonal transformation matrix; and a top-level loop operation control module for multiplexing the n-1 QR-cycle modules for an n-order non-singular matrix, and finally outputting a non-singular upper triangular matrix and an orthogonal matrix. The application has the advantages of fast response and low resource consumption.

Description

Technical Field

[0001] This invention relates to the field of array signal processing technology, and in particular to a fast QR decomposition algorithm IP device and its construction method based on mirror transformation. Background Technology

[0002] In the field of array signal processing, multi-channel signal processing algorithms such as phased array beamforming and multiple-input multiple-output (MIMO) typically involve a large number of matrix decomposition and matrix inversion operations. For example, radar anti-jamming requires MVDR minimum variance beamforming to retain the desired direction signal and suppress interference noise from other directions. It also involves reconstructing spatial filtering weights using the inverse matrix to align the main lobe of the beam with the target, thus suppressing sidelobe interference. In 5G multi-antenna communication, the aliasing of multiple antenna transmit and receive signals necessitates separating the transmitted signals, inverting the channel combination matrix, canceling crosstalk between antennas, suppressing noise interference, and restoring the original transmitted data. Adaptive beamforming SMI algorithms and DOA direction-of-arrival estimation algorithms require inverting the data covariance matrix to split the signal subspace and noise subspace to achieve target angle estimation. The core of the inversion algorithm lies in matrix decomposition. Because beam weight calculation requires extremely high real-time performance and matrix decomposition operations have a high computational load, stringent requirements are placed on the computational speed and resource consumption of the solution module. Therefore, there is an urgent need to design a fast QR decomposition algorithm IP based on FPGA.

[0003] In practical engineering, the choice of matrix factorization and inversion algorithm is mainly related to computational complexity, matrix order, number of matrix elimination iterations, and number of matrix multiplication iterations. Mathematically, commonly used matrix factorization methods include Cholesky matrix factorization, LU triangular matrix factorization, SVD singular value matrix factorization, and QR matrix factorization. However, Cholesky matrix factorization is only applicable to Hermite positive definite matrices; LU triangular matrix factorization requires all principal minors of the matrix to be non-zero; QR matrix factorization is applicable to all non-singular matrices; and SVD singular value matrix factorization can be applied to any matrix, but its implementation is relatively complex. Under certain design requirements of high stability and high accuracy, QR decomposition has gained widespread attention due to its lack of requirements on the input matrix and its high numerical stability.

[0004] Currently, there are three basic methods for QR matrix factorization algorithms: matrix factorization based on Gram-Schmidt orthogonal transformation, matrix factorization based on Givens rotation transformation, and matrix factorization based on Householder mirror transformation matrix. Later, some new algorithms were proposed, but most were modifications of the above three methods. A comprehensive analysis of the computational complexity and algorithm structure of matrix factorization reveals that the Gram-Schmidt orthogonal transformation-based method generates a large number of temporary variables during the computation loop. When on-chip resources are limited, sufficient latch resources are often insufficient to store these temporary variables. If some temporary variables are stored in BRAM to distribute resources evenly, repeated read and write operations will reduce loop efficiency, thus slowing down the computation. While the Givens rotation transformation-based matrix factorization method can offset the demand for register resources through pipelining, the decomposition process still requires computation... Sub-elementary rotation matrices involve a large amount of computation in their decomposition, requiring numerous divisions and square root operations, which often fails to meet the requirements of fixed-point, high-precision data. In contrast, matrix decomposition based on Householder mirror transformation matrices only requires left multiplication. The elementary reflection matrix can be used to complete the matrix decomposition operation with low computational complexity. Its structure not only conforms to the basic characteristics of pipeline operation, but also meets the requirement of low computational load. Moreover, the algorithm structure is suitable for design using hardware description language (HDL).

[0005] Furthermore, the development of various reconfigurable computing platforms, such as Xilinx's Versal architecture, has provided computational power guarantees for real-time high-precision, high-dimensional matrix factorization operations in different array signal processing applications. However, current research on hardware implementations of matrix factorization largely focuses on sparse and low-bit matrices. Research on non-sparse and high-bit matrix factorization circuits is relatively limited. Moreover, most hardware implementations of QR factorization are slow and resource-intensive, making it difficult to meet high-speed, real-time requirements. Therefore, to meet the demands of modern signal processing, researching how to implement a fast QR matrix factorization algorithm suitable for high-precision data matrices in hardware is a worthwhile area of ​​investigation. Summary of the Invention

[0006] The present invention aims to provide an IP device and construction method for a fast QR decomposition algorithm based on mirror transformation that overcomes or at least partially solves the above problems.

[0007] To achieve the above objectives, the technical solution of the present invention is specifically implemented as follows: One aspect of the present invention provides a fast QR decomposition algorithm IP device based on mirror transformation, comprising: The pulse matrix multiplication module is used to input each column element of the first matrix and each row element of the second matrix as input first and second matrices respectively. It uses the same adder and multiplier to calculate each addition unit in sequence, and obtains the output matrix elements by accumulation. The nth-order matrix multiplication is completed after n clock cycles. The Householder mirror transformation module is used to calculate the Householder unit vector and construct the Householder mirror transformation matrix based on the column vectors of the initial non-singular matrix and the mirror direction unit vector. The QR-cycle module is used to perform a Householder transformation on the input non-singular sampling matrix based on the mirror transformation matrix, combined with the pulse matrix multiplication module, the row output timing module and the column output timing module, and output the updated non-singular upper triangular matrix, the column vector to be transformed and the orthogonal transformation matrix after accumulation. The top-level loop operation control module is used to reuse the QR-cycle module n-1 times for an n-order non-singular matrix. The input of each loop comes from the output of the previous loop, and the final output is a non-singular upper triangular matrix and an orthogonal matrix.

[0008] Optionally, the device further includes: The general handshake coordination mechanism construction module is used to latch the input data into the data loading register by triggering the data valid signal on the rising edge, and latch the output data into the data output register after completing the data processing, while pulling the output valid signal high.

[0009] Optionally, the pulsating matrix multiplication module inputs each column element of the first matrix and each row element of the second matrix as inputs the first and second matrices in the following manner: it reuses the same adder and multiplier to calculate each addition unit sequentially, and obtains the output matrix elements by accumulation, thus completing the nth-order matrix multiplication after n clock cycles. For multiplication of an n-order matrix, set up n multipliers and n adders; In each clock cycle, the multiplier is used to calculate the product of the corresponding elements in the i-th column of the first matrix and the j-th row of the second matrix, and the adder is used to accumulate the product to an intermediate result; After n clock cycles, the accumulation of all elements is completed, the final result is output, and the valid output signal is pulled high.

[0010] Optionally, the Householder mirror transformation module specifically includes: The ω molecule calculation module is used to calculate the numerator of the difference vector ω between the column vectors of a non-singular matrix and the unit vector in the mirror direction; A vector magnitude calculation module is used to calculate the magnitude of the molecular part; The vector normalization calculation module is used to normalize the numerator part to obtain the normalized ω vector; The H matrix calculation module is used to calculate the diagonal and off-diagonal elements based on the normalized ω vector to construct the Householder mirror transformation matrix.

[0011] Optionally, the QR-cycle module specifically includes: The first pulsating matrix multiplier is used to multiply the current mirror transformation matrix with the current non-singular sampling matrix to obtain the updated non-singular upper triangular matrix; The second pulsating matrix multiplier is used to multiply the current mirror transformation matrix by the identity matrix to obtain the cumulative result of the orthogonal transformation matrix; The first and second row-by-row timing modules are used to output the data of the right multiplication matrix row by row, respectively. The first and second sub-sequence timing modules are used to output the data of the left multiplication matrix column by column, respectively. The branch output timing module, the first branch output timing module, and the second branch output timing module synchronize the time consumption on each data link through a peak output mode with a timing stamp, so that the total link time consumption from input to output is consistent.

[0012] Optionally, the input / output links synchronized via the peak output mode of the tapping include: First link: The non-singular sampling matrix enters the first pulsating matrix multiplier after passing through the first branch timing module; Second link: After the H matrix calculation module calculates the mirror transformation matrix between the column vector to be transformed and the unit column vector, the matrix is ​​then fed into the first pulsating matrix multiplier via the first splitting timing module. Third link: After the H matrix calculation module calculates the mirror transformation matrix between the column vector to be transformed and the unit column vector, the second column timing module enters the second pulsating matrix multiplier. Third link: The identity matrix or cumulative multiplication matrix enters the second pulsating matrix multiplier after passing through the second branch output timing module; Each link consumes m clock cycles, where m is the matrix order.

[0013] Optionally, the QR-cycle module is further configured to extract the k-th column of the updated matrix and set the first k rows to zero to obtain the next round of transformation vector, where k is the current cycle number.

[0014] Another aspect of the present invention provides a method for constructing a fast QR decomposition algorithm IP based on mirror transformation, comprising: For the first and second input matrices, each column element of the first matrix is ​​input column by column, and each row element of the second matrix is ​​input row by row. The same adder and multiplier are reused to calculate each addition unit in sequence. The output matrix elements are obtained by accumulation. The nth-order matrix multiplication is completed after n clock cycles. Based on the column vectors of the initial non-singular matrix and the mirror direction unit vector, calculate the Householder unit vector and construct the Householder mirror transformation matrix; Based on the mirror transformation matrix, combined with the pulsating matrix multiplication module, the row output timing module and the column output timing module, a Householder transformation is performed on the input non-singular sampling matrix, and the updated non-singular upper triangular matrix, the column vector to be transformed and the orthogonal transformation matrix after accumulation are output. The QR-cycle module is reused n-1 times for an n-order non-singular matrix. The input of each loop comes from the output of the previous loop, and the final output is a non-singular upper triangular matrix and an orthogonal matrix.

[0015] Optionally, the method further includes: The input data is latched into the data loading register by triggering the data valid signal on the rising edge, and the output data is latched into the data output register after data processing is completed, while the output valid signal is pulled high.

[0016] Optionally, the step of calculating the Householder unit vector and constructing the Householder mirror transformation matrix based on the initial non-singular matrix column vectors and the mirror direction unit vector includes: Calculate the numerator of the difference vector ω between the column vectors of a nonsingular matrix and the unit vector in its mirror direction; Calculate the modulus of the molecular portion; Normalize the molecule to obtain the normalized ω vector; The Householder mirror transformation matrix is ​​constructed by calculating the diagonal and off-diagonal elements based on the normalized ω vector.

[0017] Therefore, the fast QR decomposition algorithm IP device and construction method based on mirror transformation provided by this invention performs pulsation matrix construction and QR optimization decomposition on waveform data, so that the orthogonal matrix Q waveform and non-singular upper triangular matrix R waveform output by the phased array receiver have the advantages of fast response and low resource consumption. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of the structure of the fast QR decomposition algorithm IP device based on mirror transformation provided in an embodiment of the present invention; Figure 2 This is a block diagram illustrating the design of a module handshake collaboration mechanism provided in an embodiment of the present invention. Figure 3 This is a schematic diagram illustrating the principle of the column-by-column calculation method for the pulsating matrix multiplication module provided in this embodiment of the invention. Figure 4 This is a schematic diagram of the Householder mirror transformation principle provided in an embodiment of the present invention; Figure 5 This is a design block diagram of the Householder mirror transformation module provided in an embodiment of the present invention; Figure 6 The structural diagram of the QR-cycle module IP design method based on mirror transformation provided in the embodiments of the present invention; Figure 7 A block diagram of the top-level loop operation control module provided in an embodiment of the present invention; Figure 8 A flowchart illustrating the fast QR decomposition algorithm IP construction method based on mirror transformation provided in this embodiment of the invention; Figure 9 This is a flowchart of a specific example of the fast QR decomposition algorithm IP construction method based on mirror transformation provided in the embodiments of the present invention. Detailed Implementation

[0020] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0021] Figure 1 This diagram illustrates the structure of the fast QR decomposition algorithm IP device based on mirror transformation provided in an embodiment of the present invention. (See also...) Figure 1 The fast QR decomposition algorithm IP device based on mirror transformation provided in this embodiment of the invention includes: The pulse matrix multiplication module is used to input each column element of the first matrix and each row element of the second matrix as input first and second matrices respectively. It reuses the same adder and multiplier to calculate each addition unit in sequence, and obtains the output matrix elements by accumulation. The nth-order matrix multiplication is completed after n clock cycles. The Householder mirror transformation module is used to calculate the Householder unit vector and construct the Householder mirror transformation matrix based on the column vectors of the initial non-singular matrix and the mirror direction unit vector. The QR-cycle module is used to perform a Householder transformation on the input non-singular sampling matrix based on the mirror transformation matrix, combined with the pulsating matrix multiplication module, the row output timing module, and the column output timing module. The output is the updated non-singular upper triangular matrix, the column vector to be transformed, and the orthogonal transformation matrix after accumulation. The top-level loop operation control module is used to reuse the QR-cycle module n-1 times for an n-order non-singular matrix. The input of each loop comes from the output of the previous loop, and the final output is a non-singular upper triangular matrix and an orthogonal matrix.

[0022] Specifically, this invention is a fast QR decomposition algorithm IP design scheme based on mirror transformation, which includes the following contents, as shown in Table 1:

[0023] This invention constructs a pulsation matrix by multiplying each column element of one matrix with each row element of another matrix to obtain a single addition unit; the column and row traversals of the two matrices are completed sequentially, and then the addition units are accumulated to obtain the pulsation matrix.

[0024] This invention uses a row-by-row timing method to output each row element of the matrix to be processed sequentially, and outputs data at specific times through a peak output mode to ensure clock synchronization.

[0025] This invention employs a staggered timing method, where each row of elements in the matrix to be processed is output sequentially, and data is output at specific times using a peak output mode to ensure clock synchronization.

[0026] As an optional implementation of the present invention, the fast QR decomposition algorithm IP device based on mirror transformation provided in the present invention further includes: a general handshake coordination mechanism construction module, which is used to trigger a data valid signal by the rising edge, latch the input data into the data loading register, and latch the output data into the data output register after data processing is completed, while pulling up the output valid signal.

[0027] This invention constructs a universal handshake collaboration mechanism. For system-level hardware design, information interaction between modules must be established under an effective link mechanism. To improve the efficiency and accuracy of information interaction between modules at all levels, this invention designs a simple and effective inter-module handshake collaboration mechanism based on the handshake mechanism design concept, such as... Figure 2 As shown.

[0028] For the input stage, in order to accurately capture data and determine its validity, this invention sets up a data loading register I_Reg for the input stage of the "handshake" mechanism module. I_valid is sensitively triggered on the rising edge, storing the incoming data in the data loading register for easy access by the Func module. For the output stage, in order to accurately release data and make it valid for a short period, the module sets up a data output register O_Reg. When the module completes a data processing operation, it pulls O_valid high and simultaneously stores the outgoing data in the data output register for easy access by subsequent modules.

[0029] In other words, this invention confirms the validity of data by triggering the rising edge. When the data is valid, it latches and outputs the data, thereby reducing the dynamic power consumption of each module and avoiding the need for subsequent stages to latch the input. This saves on the resource consumption of registers in both the front and rear stages and greatly simplifies the overall module design process.

[0030] Specifically Figure 2 The phased array radar receiver is used to output the digital waveform information received by multi-channel narrow-width sampling, denoted as... This represents the waveform digital information of channel 1.

[0031] This represents the waveform digital information of the second channel.

[0032] Indicates the first Digital waveform information of the channel.

[0033] Indicates the first Digital waveform information of the channel.

[0034] In this invention, the first in the multi-channel narrow-width acquisition unit The channel acquires a set of time-domain snapshots at each rising edge of the clock over a period of time, resulting in a row vector of length 1024. Then there is .

[0035] Similarly, we can conclude that .

[0036] Similarly, we can conclude that .

[0037] Similarly, we can conclude that .

[0038] In this invention, the number of channels is used as a row vector, and the number of snapshots acquired is used as a column vector for multi-channel waveform digital information. Sort by row and column to obtain waveform digital information. ,but Also expressed as .

[0039]

[0040] In this invention, the waveform digital information is sorted by row and column. Transpose, denoted as .

[0041]

[0042] This invention constructs a pulsating matrix multiplication module. As an optional implementation of this invention, the pulsating matrix multiplication module, for the input first matrix and the second matrix, inputs each column element of the first matrix column-by-column and each row element of the second matrix row-by-row, reuses the same adder and multiplier to calculate each addition unit sequentially, and obtains the output matrix elements by accumulation, completing an nth-order matrix multiplication after n clock cycles: For multiplication of an n-order matrix, set up n multipliers and n adders; In each clock cycle, the multiplier is used to calculate the product of the corresponding elements in the i-th column of the first matrix and the j-th row of the second matrix, and the adder is used to accumulate the product to the intermediate result; After n clock cycles, the accumulation of all elements is completed, the final result is output, and the valid output signal is pulled high.

[0043] Specifically, this invention employs a pulsation matrix construction method. and The construction yields the column-row waveform pulsation matrix. In this invention, It is . a non-singular matrix.

[0044] Let this be the first addition unit, simplified to .

[0045] Let this be the second addition unit, simplified to .

[0046] Recorded as the number One addition unit, simplified to .

[0047] Let it be the Mth addition unit, which is simplified to .

[0048] The addition unit is represented in matrix form as a column-row waveform pulsation matrix. .

[0049] In this invention, initially, The first column vector in the matrix is ​​denoted as the initial non-singular matrix column vector. Mirror the unit vector in a given direction Below, the mirror vector can be obtained. , And based on Get a dimension The identity matrix is .

[0050] Non-singular matrix column vector Mirror unit vector Mirror vector All Column vectors.

[0051] The pulsating matrix multiplication method designed in this invention improves upon conventional matrix multiplication operations, for... 1-th order matrix and 1-th order matrix Matrix multiplication operations Input each column element of matrix A column-wise and each row element of matrix B row-wise, and use an addition unit to process the result of a single multiplication. Expressed as shown in formula (1): (1) Record the final result as That is, it satisfies formula (2).

[0052] (2) In terms of resource consumption, two When multiplying matrices of order 1, if the output... When performing conventional parallel matrix multiplication on elements, it is necessary to A multiplier, One adder, one clock cycle output. However, when using the systolic matrix column-by-column calculation method designed in this invention, because this invention... Each element in When multiplying and adding elements in a given array, the same adder and multiplier are used repeatedly, meaning only one is needed. A multiplier and An adder, in The matrix multiplication operation can be completed in one clock cycle. That is, compared to conventional parallel matrix multiplication, this invention can almost complete the computation in one clock cycle. To exchange for one clock cycle The module offers significant resource savings, and its gains are substantial when used on high-order dimensional matrices.

[0053] The present invention is based on the following Figure 3 The timing flow diagram for the column-by-column calculation method of the systolic matrix multiplication module is shown. The clock signal I_CLK, the input valid signal I_valid, and the output valid signal O_Valid are all triggered on the rising edge. For each output element O_C_ij, the matrix can be used sequentially according to the column-by-column and column-by-column output modules. Each column I_A_i and the matrix For each row I_B_i, the corresponding element is multiplied for each addition unit to obtain C_ij_current. Then, the result of each output element O_C_ij is obtained by accumulating the C_ij_current values ​​each time. The accumulation operation is evenly distributed in the time dimension. Each clock cycle has an intermediate accumulated value of C_ij_temp_add. Matrix multiplication of order 1 only requires The entire addition and accumulation operation can be completed in one clock cycle. For timing consistency, this can be achieved on the first clock cycle after the valid input signal I_valid is active high. The final result O_C_ij is output after one clock cycle, and the valid output signal O_Valid is pulled high at the same time.

[0054] This invention constructs a Householder mirror transformation module. As an optional implementation of this invention, the Householder mirror transformation module specifically includes: The ω molecule calculation module is used to calculate the numerator of the difference vector ω between the column vectors of a non-singular matrix and the unit vector in the mirror direction; The vector magnitude calculation module is used to calculate the magnitude of the molecule part; The vector normalization calculation module is used to normalize the numerator part to obtain the normalized ω vector; The H matrix calculation module is used to calculate the diagonal and off-diagonal elements based on the normalized ω vector, and construct the Householder mirror transformation matrix.

[0055] Specifically, this invention is based on the initial non-singular matrix column vectors Mirror vector Calculate the Householder unit vector , Corresponding dimensions ( The identity matrix of ) is denoted as Then the first Householder mirror transformation array can be obtained. , .

[0056] This invention designs a QR decomposition based on Householder mirror transformation for the fundamental invertible covariance matrix (real (complex) nonsingular matrix) of array signals, wherein the covariance matrix... It can be a matrix containing noise components, or an orthogonal matrix. satisfy , represent An identity matrix of order 1, i.e., a real (complex) nonsingular matrix. of Perform a Householder transformation on the column vectors. Left multiplication The next mirror transformation matrix yields a non-singular upper triangular matrix. As shown in formula (3).

[0057] (3) The Householder mirror transformation array of the present invention is according to Figure 4 The method shown yields the result for non-singular matrices. any non-zero column vector In two-dimensional space, it can be transformed into a unit vector with a given mirror direction. Vectors in the same direction ,Right now The time is intuitively apparent. , Representing vectors In Householder unit vector The projection in the direction satisfies formula (4).

[0058] (4) That is, a single Householder mirror transformation matrix, according to Figure 4 The geometric projection relationship shown yields the Householder unit vector. The calculation expression satisfies formula (5).

[0059] (5) This invention designs sub-modules, as listed in Table 2, to calculate the mirror transformation matrix required by each module. and .

[0060]

[0061] Molecular calculation module: based on the input and calculate The molecular part.

[0062] Vector magnitude calculation module: Calculates the magnitude of the input vector.

[0063] Vector normalization calculation module: Normalizes the input vector by its magnitude.

[0064] Matrix calculation module: based on the input Calculation required .

[0065] According to Table 2, this invention corresponds to an FPGA, and is achieved through, as follows: Figure 5 The Householder mirror transformation module shown calculates the Householder mirror transformation matrix.

[0066] The Householder mirror transformation module is named Final_H, and its input is... The corresponding column vectors I_eta_i and The corresponding column vector I_ei_i, that is, transforming I_eta_i into the direction of I_ei_i, outputs the corresponding required mirror transformation matrix. The Final_H module contains The calculation module Get_final_omega and The matrix calculation module Get_H_matrix and the Get_final_omega module are now complete. The calculation is performed by the Get_H_matrix module. The calculation.

[0067] In the Get_final_omega module, firstly by The Get_omega_molecule module performs molecular calculations. The molecule is then calculated by the vector magnitude calculation module Get_vec_amp. The modulus of the molecule is finally calculated by the vector normalization calculation module Diagonal_element_divider, resulting in a normalized value. The output is latched by the latch module Latch_final_omega. .

[0068] In the Get_H_matrix module, through the input calculate The calculation process is divided into diagonal elements. off-diagonal elements Calculation in two parts. Diagonal element off-diagonal element ,in and Corresponding to The first in The and the first There are elements, among which It is a column vector.

[0069] This invention constructs a QR-cycle module. As an optional implementation of this invention, the QR-cycle module specifically includes: The first pulsating matrix multiplier is used to multiply the current mirror transformation matrix with the current non-singular sampling matrix to obtain the updated non-singular upper triangular matrix; The second pulsating matrix multiplier is used to multiply the current mirror transformation matrix by the identity matrix to obtain the cumulative result of the orthogonal transformation matrix; The first and second row-by-row timing modules are used to output the data of the right multiplication matrix row by row, respectively. The first and second sub-sequence timing modules are used to output the data of the left multiplication matrix column by column, respectively. The branch output timing module, the first branch output timing module, and the second branch output timing module synchronize the time consumption on each data link through the peak output mode of the timing, so that the total link time consumption from input to output is consistent.

[0070] As an optional implementation of this invention, the input / output links synchronized by the peak output mode of the tapping include: First link: The non-singular sampling matrix enters the first pulsating matrix multiplier after passing through the first branch timing module; Second link: After the H matrix calculation module calculates the mirror transformation matrix between the column vector to be transformed and the unit column vector, the matrix enters the first pulsating matrix multiplier through the first split timing module. Third link: After the H matrix calculation module calculates the mirror transformation matrix between the column vector to be transformed and the unit column vector, the second splitter enters the second pulse matrix multiplier through the timing module. Third link: The identity matrix or cumulative multiplication matrix enters the second pulsating matrix multiplier after passing through the second branch timing module; Each link consumes m clock cycles, where m is the matrix order.

[0071] Specifically, the overall block diagram of the QR-cycle module IP design method based on mirror transformation designed in this invention is as follows: Figure 6 As shown, its function is to quickly complete a single loop operation of QR matrix decomposition. The QR-cycle module's IPs are all triggered by a valid rising edge, and Input1 is... OK non-singular sampling matrix of columns Input2 is The column vector to be transformed by mirroring Input3 is a column vector. Unit column vectors of the same dimension The first input to Input4 is OK column identity matrix This is used as the input for the cumulative multiplication of the mirror transformation matrix in subsequent loops. And for... Figure 6 The multiplier icon given in the image is ⑧ and Both employ a pulsating matrix multiplier IP based on the Householder mirror transformation matrix, and the multiplier time is... The matrices corresponding to module ⑦ and the timing module ⑩ are the left matrix when multiplying matrices. The timing module ⑥ and... The corresponding matrix is ​​the right matrix when multiplying matrices.

[0072] First, in module ⑤, Vector and Vector Seek After Obtain the mirror transformation matrix This is how long it has taken. .then, Time spent The column vector data obtained from module ⑦ is compared with... The row vector data obtained after passing through the timing module enters the pulsating matrix multiplier (⑧) for multiplication to obtain Output1. corresponding , This will serve as the input for the next module ①, Input1. ⑨ The Extract the column and the first Setting rows to zero takes time Output2 is obtained. corresponding , Input2 will serve as the input for the next module ②.

[0073] The column vector data obtained by separating the timing module ⑩ and the timing module obtained by separating the rows of module ④ are then compared. The obtained row vector data is then synchronously fed into the systolic matrix multiplier. Multiplying the results gives Output3, which serves as the input Input4 for the next module ④. The diagram illustrates that all timing modules synchronize the time consumption of the four links—Input1 to Output1, Input2 and Input3 to Output1, Input2 and Input3 to Output2, and Input4 to Output3—through a peak output pattern. The time consumption for each link is... .

[0074] As an optional implementation of this invention, the QR-cycle module is also used to extract the k-th column of the updated matrix and set the first k rows to zero to obtain the next round of transformation vector, where k is the current cycle number.

[0075] This invention constructs a top-level loop operation control module, which is applicable to... 1-th order matrix The decomposition requires reuse. The second QR-cycle module. For matrix factorization IP, the first... The outputs output1, output2, and output3 of the next loop are respectively the outputs of the [number]th [cycle]. The loop iterates through input1, input2, and input4. The input 'input3' for the next loop is the corresponding Column vectors. The top-level loop is designed in a serial stepping manner and reuses the QR-cycle module to the greatest extent.

[0076] Based on this, the present invention is based on the following Figure 7 The top-level loop operation control module shown constructs a QR matrix decomposition top-level loop pipeline. Each loop step uses 4 inputs and 3 outputs. Except for the first loop where input4 is... Apart from the above steps, all other inputs are processed in a cascading mode. After the cumulative multiplication in the second iteration, a non-singular upper triangular matrix can be obtained at Output1. At Output3, we get After transposing, an orthogonal matrix can be obtained. ,satisfy ,in , .

[0077] Thus, through the cooperation of the various modules described above, the Householder-based mirror transformation is completed. non-singular matrix of order Fast QR matrix decomposition.

[0078] Figure 8 This document illustrates a flowchart of a method for constructing a fast QR decomposition algorithm IP based on mirror transformation, provided by an embodiment of the present invention. This method utilizes the aforementioned apparatus. The following is a brief description of the flow and function of this method; for other matters not covered herein, please refer to the relevant descriptions in the aforementioned fast QR decomposition algorithm IP apparatus based on mirror transformation. Figure 8 The present invention provides a method for constructing a fast QR decomposition algorithm IP based on mirror transformation, comprising: S1, for the first and second input matrices, input each column element of the first matrix by column and each row element of the second matrix by row. Reuse the same adder and multiplier to calculate each addition unit in sequence, and obtain the output matrix elements by accumulation. The nth-order matrix multiplication is completed after n clock cycles. S2. Based on the column vectors of the initial non-singular matrix and the mirror direction unit vector, calculate the Householder unit vector and construct the Householder mirror transformation matrix. S3, based on the mirror transformation matrix, combined with the pulsating matrix multiplication module, the row output timing module and the column output timing module, performs a Householder transformation on the input non-singular sampling matrix, and outputs the updated non-singular upper triangular matrix, the column vector to be transformed and the orthogonal transformation matrix after accumulation. S4 reuses the QR-cycle module n-1 times for an n-order non-singular matrix. The input of each loop comes from the output of the previous loop, and the final output is a non-singular upper triangular matrix and an orthogonal matrix.

[0079] As an optional implementation of the present invention, the fast QR decomposition algorithm IP construction method based on mirror transformation provided in the present invention further includes: The input data is latched into the data loading register by triggering the data valid signal on the rising edge, and the output data is latched into the data output register after data processing is completed, while the output valid signal is pulled high.

[0080] As an optional implementation of this invention, the Householder unit vector is calculated based on the initial non-singular matrix column vectors and the mirror direction unit vector. The initial Householder mirror transformation matrix includes: Calculate the numerator of the difference vector ω between the column vectors of a nonsingular matrix and the unit vector in its mirror direction; Calculate the modulus of the molecular part; Normalize the molecule to obtain the normalized ω vector; Calculate the diagonal and off-diagonal elements based on the normalized ω vector, and construct the Householder mirror transformation matrix.

[0081] Figure 9 This paper presents a flowchart illustrating a specific example of a fast QR decomposition algorithm IP construction method based on mirror transformation provided in an embodiment of the present invention. The method includes: The pulsed multiplication module sorts the n-dimensional matrix data into rows and columns, reducing resource consumption by reusing n multipliers, accumulating intermediate calculation results, and outputting the matrix multiplication result after n cycles. Based on the column vectors and mirror vectors of the non-singular matrix, calculate the initial transformation matrix for the orthogonal transformation of hyperplane mirror reflection. Transform the initial transformation matrix into unit vectors in the mirror direction, calculate the magnitude and normalize it, and output the mirror transformation matrix required for each operation. QR decomposition is a fast computation. The non-singular sampling matrix, mirror transformation column vector, unit column vector and identity matrix are all triggered by the rising edge. The pulsating multiplier used to calculate the reflection orthogonal transformation matrix is ​​reused for cumulative multiplication and synchronized to the input of the next calculation. The top-level loop pipeline is designed with a serial step-by-step loop. The dimension minus one QR fast decomposition operation module is reused. Each loop step uses four inputs and three outputs. After multiplexing, the output is an upper triangular matrix and a transposed orthogonal matrix, and the matrix decomposition is completed.

[0082] The following section verifies the hardware solution for the fast QR decomposition algorithm IP of this invention: To verify the feasibility of the method designed in this invention, the 16nm hardware platform chip model XCVU13P-FHGB2104-2-I was selected for the specific implementation of this invention on an FPGA. Taking 8th-order matrix decomposition as an example, the resource data report of the QR-cycle module consuming in a single loop operation of QR matrix decomposition is shown in Table 3. Based on the QR matrix decomposition top-level loop pipeline designed according to this invention, for 8th-order matrices... The QR decomposition requires reusing the QR-cycle module 7 times, and the resource consumption is fixed as shown in Table 3.

[0083]

[0084] Regarding clock delay, this invention sets the clock period to 250MHz. Verification shows that a single QR-cycle can be completed in 230 clock cycles. Therefore, after 1610 clock cycles, the QR decomposition of an 8th-order matrix can be completed, yielding the corresponding orthogonal matrix. NAND non-singular upper triangular matrix .

[0085] Specifically, when solving for 64 output elements by multiplying two matrices, the resource consumption and clock latency of the multipliers and adders corresponding to the traditional parallel multiplication and the systolic matrix multiplication designed in this invention are shown in Table 4. It can be seen that although the systolic matrix multiplication incurs an additional time cost of 8 clock delays, it can achieve nearly 8 times the resource savings, freeing up more resource margin for the entire system.

[0086]

[0087] As can be seen, the fast QR matrix factorization algorithm based on mirror transformation designed in this invention was implemented with a clock cycle of 250MHz on a hardware platform with chip model xcvu13p-fhgb2104-2-i. This invention can perform QR decomposition of an 8th-order matrix within a single operation, with high speed and reliability. Theoretically, it can be applied to the decomposition of matrices up to the 128th order, and is suitable for engineering applications such as multi-channel real-time communication.

[0088] Therefore, the fast QR decomposition algorithm IP device and construction method based on mirror transformation provided in the embodiments of the present invention, in the array processing receiver, the present invention uses FPGA chip and FPGA software to process the waveform data, and performs pulsation matrix construction and QR optimization decomposition, so that the orthogonal matrix Q waveform and non-singular upper triangular matrix R waveform output by the phased array receiver have the advantages of fast response and low resource consumption.

[0089] This invention is applicable to high-dimensional, high-precision non-singular matrix decomposition. Designed specifically for Hardware Description Language (HDL), a corresponding loop operation pipeline was designed based on the algorithm characteristics to quickly implement QR matrix decomposition based on mirror transformation with maximum resource utilization, effectively saving on-chip resources. Simultaneously, it supports 64- to 128-bit high-precision fixed-point number formats, improving the accuracy of the matrix decomposition results. Furthermore, the hardware implementation and time and resource evaluation of the fast QR decomposition algorithm IP based on mirror transformation were completed on an FPGA, validating the theoretical basis of this invention.

[0090] The present invention has the following advantages: (1) The fast QR matrix factorization algorithm based on mirror transformation designed in this invention was implemented on a 16nm FPGA platform with a clock cycle of 250MHz. It can perform 8th order matrix decomposition operations internally, with high speed and reliability. Theoretically, it can be applied to the decomposition of matrices up to order 128, and is suitable for engineering applications such as multi-channel real-time communication.

[0091] (2) The fast QR decomposition algorithm IP design method based on mirror transformation proposed in this invention is suitable for fast decomposition of high-dimensional, high-precision non-singular matrices in the real number domain. The algorithm is optimized through local serial-parallel processing to form a pipeline design, which achieves a better balance between resource utilization and data processing efficiency.

[0092] (3) The present invention confirms the validity of the data by triggering the rising edge. When the data is valid, it latches and outputs the data, thereby reducing the dynamic power consumption of each module and avoiding the subsequent stage from latching the input again. This saves the consumption of register resources of the front and rear stages, improves the reuse efficiency and modifiability of the module, and greatly simplifies the overall module design process.

[0093] (4) In fields such as array signal processing, matrix decomposition algorithms are frequently used in hardware platforms. This invention utilizes the fast QR decomposition algorithm IP based on mirror transformation, employing a "pulsating" matrix multiplication method to design a top-level loop pipeline for QR matrix decomposition, significantly improving development efficiency. Compared to traditional parallel matrix computation methods, it can save [data / efforts]. This method consumes significantly more resources. Compared to higher-level synthesis methods, it can improve computation time by more than 35 times in the same clock cycle when performing 8th-order matrix decomposition operations.

[0094] (5) The "pulsating" matrix multiplier module designed in this invention optimizes the calculation of row and column vectors. By using the idea of ​​inputting in rows and columns, it performs multiplication and addition of specific elements. Theoretically, it can achieve the following calculations: To exchange for one clock cycle The module offers significant resource savings, and its improvement in resource utilization is particularly noticeable when used with high-dimensional matrices.

[0095] (6) Matrix operations in traditional FPGA design and HLS rely heavily on Bram-based registers and reads, which severely consume register resources and suffer from low read rates. This invention configures the mirror transformation as a cyclic calculation mode, which can quickly obtain the results. Matrix and Matrix-based computation reduces computational complexity, supports 64- to 128-bit high-precision fixed-point number formats, exhibits good numerical stability in high-precision calculations, and has no intermediate register matrix, resulting in better scalability and higher resource utilization.

[0096] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0097] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A fast QR decomposition algorithm IP device based on mirror transformation, characterized in that, include: The pulse matrix multiplication module is used to input each column element of the first matrix and each row element of the second matrix as input first and second matrices respectively. It uses the same adder and multiplier to calculate each addition unit in sequence, and obtains the output matrix elements by accumulation. The nth-order matrix multiplication is completed after n clock cycles. The Householder mirror transformation module is used to calculate the Householder unit vector and construct the Householder mirror transformation matrix based on the column vectors of the initial non-singular matrix and the mirror direction unit vector. The QR-cycle module is used to perform a Householder transformation on the input non-singular sampling matrix based on the mirror transformation matrix, combined with the pulse matrix multiplication module, the row output timing module and the column output timing module, and output the updated non-singular upper triangular matrix, the column vector to be transformed and the orthogonal transformation matrix after accumulation. The top-level loop operation control module is used to reuse the QR-cycle module n-1 times for an n-order non-singular matrix. The input of each loop comes from the output of the previous loop, and the final output is a non-singular upper triangular matrix and an orthogonal matrix.

2. The apparatus according to claim 1, characterized in that, Also includes: The general handshake coordination mechanism construction module is used to latch the input data into the data loading register by triggering the data valid signal on the rising edge, and latch the output data into the data output register after completing the data processing, while pulling the output valid signal high.

3. The apparatus according to claim 2, characterized in that, The pulse matrix multiplication module takes the first and second input matrices as follows: inputs each column element of the first matrix column-by-column and each row element of the second matrix row-by-row; reuses the same adder and multiplier to calculate each addition unit sequentially; and obtains the output matrix elements by accumulating the results, completing an nth-order matrix multiplication after n clock cycles. For multiplication of an n-order matrix, set up n multipliers and n adders; In each clock cycle, the multiplier is used to calculate the product of the corresponding elements in the i-th column of the first matrix and the j-th row of the second matrix, and the adder is used to accumulate the product to an intermediate result; After n clock cycles, the accumulation of all elements is completed, the final result is output, and the valid output signal is pulled high.

4. The apparatus according to claim 2, characterized in that, The Householder mirror transformation module specifically includes: The ω molecule calculation module is used to calculate the numerator of the difference vector ω between the column vectors of a non-singular matrix and the unit vector in the mirror direction; A vector magnitude calculation module is used to calculate the magnitude of the molecular part; The vector normalization calculation module is used to normalize the numerator part to obtain the normalized ω vector; The H matrix calculation module is used to calculate the diagonal and off-diagonal elements based on the normalized ω vector to construct the Householder mirror transformation matrix.

5. The apparatus according to claim 2, characterized in that, The QR-cycle module specifically includes: The first pulsating matrix multiplier is used to multiply the current mirror transformation matrix with the current non-singular sampling matrix to obtain the updated non-singular upper triangular matrix; The second pulsating matrix multiplier is used to multiply the current mirror transformation matrix by the identity matrix to obtain the cumulative result of the orthogonal transformation matrix; The first and second row-by-row timing modules are used to output the data of the right multiplication matrix row by row, respectively. The first and second sub-sequence timing modules are used to output the data of the left multiplication matrix column by column, respectively. The branch output timing module, the first branch output timing module, and the second branch output timing module synchronize the time consumption on each data link through a peak output mode with a timing stamp, so that the total link time consumption from input to output is consistent.

6. The apparatus according to claim 5, characterized in that, The input / output links synchronized by the peak output mode of the tapping include: First link: The non-singular sampling matrix enters the first pulsating matrix multiplier after passing through the first branch timing module; Second link: After the H matrix calculation module calculates the mirror transformation matrix between the column vector to be transformed and the unit column vector, the matrix is ​​then fed into the first pulsating matrix multiplier via the first splitting timing module. Third link: After the H matrix calculation module calculates the mirror transformation matrix between the column vector to be transformed and the unit column vector, the second column timing module enters the second pulsating matrix multiplier. Third link: The identity matrix or cumulative multiplication matrix enters the second pulsating matrix multiplier after passing through the second branch output timing module; Each link consumes m clock cycles, where m is the matrix order.

7. The apparatus according to claim 6, characterized in that, The QR-cycle module is also used to extract the k-th column of the updated matrix and set the first k rows to zero to obtain the next round of transformation vector, where k is the current cycle number.

8. A method for constructing a fast QR decomposition algorithm IP based on mirror transformation, characterized in that, include: For the first and second input matrices, each column element of the first matrix is ​​input column by column, and each row element of the second matrix is ​​input row by row. The same adder and multiplier are reused to calculate each addition unit in sequence. The output matrix elements are obtained by accumulation. The nth-order matrix multiplication is completed after n clock cycles. Based on the column vectors of the initial non-singular matrix and the mirror direction unit vector, calculate the Householder unit vector and construct the Householder mirror transformation matrix; Based on the mirror transformation matrix, combined with the pulsating matrix multiplication module, the row output timing module and the column output timing module, a Householder transformation is performed on the input non-singular sampling matrix, and the updated non-singular upper triangular matrix, the column vector to be transformed and the orthogonal transformation matrix after accumulation are output. The QR-cycle module is reused n-1 times for an n-order non-singular matrix. The input of each loop comes from the output of the previous loop, and the final output is a non-singular upper triangular matrix and an orthogonal matrix.

9. The method according to claim 8, characterized in that, Also includes: The input data is latched into the data loading register by triggering the data valid signal on the rising edge, and the output data is latched into the data output register after data processing is completed, while the output valid signal is pulled high.

10. The method according to claim 9, characterized in that, The step of calculating the Householder unit vector and constructing the Householder mirror transformation matrix based on the initial non-singular matrix column vectors and the mirror direction unit vector includes: Calculate the numerator of the difference vector ω between the column vectors of a nonsingular matrix and the unit vector in its mirror direction; Calculate the modulus of the molecular portion; Normalize the molecule to obtain the normalized ω vector; The Householder mirror transformation matrix is ​​constructed by calculating the diagonal and off-diagonal elements based on the normalized ω vector.

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