A multi-stage testing method and system for power electronics devices

Abstract

The application discloses a multi-stage test method and system for power electronic devices, and the method comprises the following steps: constructing a virtual power model and a logic control model according to the main power topology structure and real-time operation control logic of the power electronic device to be tested; matching a test mode according to the structure type of the power electronic device to be tested; constructing a closed-loop data channel between the virtual power model and the logic control model, a single-board signal channel of the power electronic device to be tested and the virtual power model, or a host computer signal channel of the power electronic device to be tested and the virtual power model according to the test mode; driving the virtual power model and the logic control model to obtain single-mode test data output by the power electronic device to be tested according to the test mode, the closed-loop data channel, the single-board signal channel and the host computer signal channel; and obtaining a multi-stage test result of the power electronic device to be tested according to the single-mode test data and the test mode, so that the test efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of device testing technology, and more specifically to a multi-level testing method and system for power electronic devices. Background Technology

[0002] The power system is upgrading from a single-point radiation architecture to a flexible grid-based bidirectional control architecture, and the level of power grid intelligence is constantly improving, leading to a continuous increase in demand for new power electronic equipment. To verify the effectiveness of the topology and control algorithms of new power electronic devices, it is usually necessary to build a laboratory equipment testing platform for functional and performance verification. In the traditional testing platform construction process, researchers need to first complete the development of a prototype, then develop the code based on the simulation verification of the control algorithm and burn the code into the control chip, and then connect it to a top-level host computer to achieve communication and collaborative control. The entire process involves using electrical testing equipment such as AC / DC power sources and waveform recorders to complete the control, communication, and performance verification of the device. This model relies on a pre-assembled power hardware platform and requires repeated algorithm iteration and online debugging based on test results, which consumes power supply and measurement equipment resources for a long time and can easily affect the development progress of other devices.

[0003] Various hardware-in-the-loop (HIL) simulation testing schemes have been disclosed in the prior art. For example, existing technologies may disclose testing systems that include computer control units, integrated test equipment units, data acquisition units, and data processing units to ensure the accuracy of test results through automated control and automatic data processing and analysis. Alternatively, they may disclose HIL simulation systems that use FPGA simulators to implement valve control and valve body models and digital simulation hosts to implement real-time AC / DC system simulation for testing control and protection devices. Or, they may disclose systems that connect multiple processing boards to physical controllers and generate output signals based on simulation models for verification by the physical controllers. Or, they may disclose in-the-loop simulation systems that include RTLAB simulators and DSP controllers, where the model in the RTLAB simulator is established based on a flexible DC-DC interconnected distribution network, and the DSP controller is used to acquire voltage and current analog signals and generate switching signals to input to the RTLAB simulator to test the control performance of the interconnected devices.

[0004] However, the aforementioned existing technical solutions still have the following shortcomings: First, the testing of power electronic modules or devices still relies on the already prototyped power unit, making it impossible to conduct purely digital verification without physical devices. Before the hardware equipment is fully manufactured and assembled, neither the control algorithm nor the host computer control function can be effectively verified, resulting in a significant time lag in software and hardware development and severely restricting overall R&D efficiency. Second, when verifying control algorithms and fault protection, it is often necessary to connect to a real high-voltage environment to conduct joint testing of the signal board, control board, and main topology. This not only poses safety risks such as high-voltage electric shock and damage to power devices, but also involves a cumbersome debugging process and a long iteration cycle. Furthermore, in terms of host computer control strategy verification, for complex operating scenarios such as low-voltage mitigation and heavy overload mitigation, debugging using a physical platform requires repeatedly setting up actual operating conditions, consuming a large amount of experimental equipment and human resources, making it difficult to quickly reproduce various extreme operating conditions, resulting in insufficient verification of the host computer logic flow and control reliability. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention discloses a multi-level testing method and system for power electronic devices, which improves testing efficiency.

[0006] To achieve the above objectives, the present invention discloses a multi-level testing method for power electronic devices, comprising: Based on the main power topology and real-time operation control logic of the power electronic device under test, construct the virtual power model and logic control model corresponding to the power electronic device under test; Match the test mode of the power electronic device under test according to the structural type of the power electronic device under test; Construct a closed-loop data channel between the virtual power model and the logic control model, a single-board signal channel between the power electronic device under test and the virtual power model, or a host computer signal channel between the power electronic device under test and the virtual power model according to the test mode. Drive the virtual power model and the logic control model to obtain single-mode test data output by the power electronic device under test according to the test mode, the closed-loop data channel, the single-board signal channel or the host computer signal channel; Based on the single-mode test data and the test mode, obtain the multi-level test results of the power electronic device under test.

[0007] This invention discloses a multi-level testing method for power electronic devices. It constructs a virtual power model and a logic control model based on the main power topology and real-time operation control logic of the power electronic device under test (DUT). The method automatically matches the test mode according to the device's structural type, constructs corresponding data channels, drives the model operation, acquires test data from multiple modes, and performs comprehensive evaluation and processing on the multi-mode test data to obtain a comprehensive verification result characterizing the DUT from control logic to single-board functions and upper-level computer communication. Specifically, when the device does not yet have any physical boards, a control logic test mode is matched. In this mode, the control algorithm and fault protection logic can be independently verified digitally without waiting for the completion of hardware such as signal boards, control boards, and upper-level controllers. This invention abandons the traditional serial development model that requires the completion of a physical power hardware prototype before testing, achieving parallel development capability for control logic testing before hardware development is complete, thereby improving the testing efficiency of the device.

[0008] As a preferred example, the step of constructing a virtual power model and a logic control model corresponding to the power electronic device under test based on the main power topology and real-time operation control logic of the device under test includes: The main power topology of the power electronic device under test is obtained, and the main power topology is deployed in the first computing resource within a preset simulation platform to obtain a virtual power model of the power electronic device under test. The real-time operation control logic of the power electronic device under test is obtained, and the real-time operation control logic is deployed in the second computing resource within the simulation platform to obtain the logic control model of the power electronic device under test; wherein, the real-time operation control logic includes control logic and fault protection logic.

[0009] The above scheme obtains a dual-model architecture within the same simulation platform, where different computing resources respectively carry out power main circuit simulation and control algorithm execution, thereby obtaining the data channel foundation that characterizes the low-latency, high-synchronization closed-loop interaction capability between models; at the same time, it obtains the integrated verification capability of integrating control logic and fault protection logic into the same real-time running control code, thus enabling simultaneous verification of algorithm accuracy and protection function reliability in the pure digital verification stage, improving testing efficiency.

[0010] As a preferred example, the step of matching the test mode of the power electronic device under test according to the structural type of the power electronic device under test includes: When it is determined that the power electronic device under test does not have a physical board based on the structural type of the power electronic device under test, the test mode of the power electronic device under test is determined to be the control logic test mode. When it is determined from the structure type that the power electronic device under test has a physical board but no host computer controller, the test mode of the power electronic device under test is determined to be the single board function test mode. When it is determined that the power electronic device under test has a host computer controller based on the structure type, the test mode of the power electronic device under test is determined to be the communication and control test mode.

[0011] The above scheme acquires the physical board status information and host computer controller status information of the power electronic device under test (PDD). It then performs structural type determination processing on this status information. If a physical board is not found, a control logic test mode is matched; if a physical board is found but a host computer controller is not, a single-board function test mode is matched; and if a host computer controller is found, a communication and control test mode is matched. This allows the test process to automatically adapt to different verification levels based on the device's development stage, enabling parallel testing and improving test efficiency. Specifically, the above scheme, through hierarchical matching processing, obtains progressive logic that automatically proceeds to physical board verification only after pure digital verification passes, and progressive logic that automatically proceeds to host computer verification only after single-board function verification passes. This prevents defective code or hardware from entering subsequent testing stages and significantly reduces the risk of power device damage.

[0012] As a preferred example, the step of constructing a closed-loop data channel between the virtual power model and the logic control model, a single-board signal channel between the power electronic device under test and the virtual power model, or a host computer signal channel between the power electronic device under test and the virtual power model according to the test mode includes: When the test mode is the control logic test mode, a first data channel from the virtual power model to the logic control model and a second data channel from the logic control model to the virtual power model are established in the simulation platform; wherein, the first data channel and the second data channel are used as closed-loop data channels; When the test mode is the single-board function test mode, the signal board and control board of the power electronic device under test are acquired, and the analog output channel from the virtual power model to the signal board, the sampling signal channel from the signal board to the control board, the drive signal feedback channel from the control board to the virtual power model, and the control execution signal feedback channel from the control board to the virtual power model are constructed; wherein, the analog output channel, the sampling signal channel, the drive signal feedback channel, and the control execution signal feedback channel are used as the single-board signal channels; When the test mode is the communication and control test mode, the host computer controller of the power electronic device under test is obtained, and the operating status data channel from the virtual power model to the host computer controller and the control command data channel from the host computer controller to the virtual power model are constructed; wherein, the operating status data channel and the control command data channel are used as host computer signal channels.

[0013] The above scheme, when the test mode is control logic test mode, acquires the first data channel from the virtual power model to the logic control model and the second data channel from the logic control model to the virtual power model within the simulation platform, thus obtaining a data channel characterizing the pure digital closed-loop interaction capability. When the test mode is single-board function test mode, it acquires four types of single-board signal channels: analog output channel, sampling signal channel, drive signal feedback channel, and control execution signal feedback channel, thus obtaining a data channel characterizing the complete bidirectional closed-loop connection between the virtual power model and the physical signal board and control board. When the test mode is communication and control test mode, it acquires the operating status data channel and the control command data channel, thus obtaining a data channel characterizing the bidirectional data interaction capability between the host computer controller and the virtual power model. Furthermore, by constructing and processing the above channels, the scheme achieves the environmental conditions for verification at each level without high-voltage power or connection to the main power circuit, thereby completely eliminating the safety risks of high-voltage testing and significantly reducing hardware resource consumption.

[0014] As a preferred example, the step of driving the virtual power model and the logic control model to acquire single-mode test data output by the power electronic device under test according to the test mode, the closed-loop data channel, the single-board signal channel, or the host computer signal channel includes: When the test mode is the control logic test mode, the virtual power model is driven to output initial electrical quantity data, and the initial electrical quantity data is sent to the logic control model according to the first data channel, so that the logic control model outputs pulse drive signal and fault protection signal; The pulse drive signal and the fault protection signal are sent to the virtual power model through the second data channel, so that the virtual power model outputs adjusted electrical quantity data according to the pulse drive signal and the fault protection signal; The pulse drive signal, the fault protection signal, the adjusted electrical quantity data, and the initial electrical quantity data are used as the operation verification data of the power electronic device under test, and the operation verification data are used as the single-mode test data of the power electronic device under test in the control logic test mode.

[0015] The above scheme drives the virtual power model to output initial electrical quantity data. This initial electrical quantity data is then sent to the logic control model via a first data channel. The initial electrical quantity data is processed by the control algorithm and fault protection logic to obtain the pulse drive signal and fault protection signal output by the logic control model. The pulse drive signal and fault protection signal are then sent to the virtual power model via a second data channel. The pulse drive signal and fault protection signal are then processed to update the on / off state of the switching devices to obtain the adjusted electrical quantity data output by the virtual power model. The pulse drive signal, fault protection signal, adjusted electrical quantity data, and initial electrical quantity data are used as operational verification data. This scheme obtains a complete dataset generated by closed-loop iteration in a purely digital environment. The pulse drive signal in this dataset characterizes the correctness of the PWM (Pulse Width Modulation) waveform generated by the control algorithm. The fault protection signal characterizes the accuracy of the fault detection logic triggering. The difference between the adjusted electrical quantity data and the initial electrical quantity data characterizes the adjustment accuracy and dynamic response characteristics of the control algorithm. Therefore, the performance of the control algorithm and the reliability of fault protection can be quantitatively evaluated without any physical circuit boards.

[0016] As a preferred example, the step of driving the virtual power model and the logic control model to acquire single-mode test data output by the power electronic device under test according to the test mode, the closed-loop data channel, the single-board signal channel, or the host computer signal channel includes: When the test mode is the single-board function test mode, the virtual power model is driven to output an initial analog electrical signal, and the initial analog electrical signal is transmitted to the signal board through the analog output channel, so that the signal board outputs the standard analog signal corresponding to the analog electrical signal, and generates a trigger signal corresponding to the standard analog signal according to the comparator on the signal board; The standard analog signal and the trigger signal are transmitted to the control board through the sampling signal channel, so that the control board processes the standard analog signal according to the programmed real-time operation control code to generate an analog pulse drive signal and processes the trigger signal according to the real-time operation control code to generate a fault protection signal; wherein, the fault protection signal includes a fault feedback signal and a status latch signal; The analog pulse drive signal is transmitted to the virtual power model through the drive signal feedback channel; The fault protection signal is transmitted back to the virtual power model through the control execution signal feedback channel to obtain the updated electrical signal output by the virtual power model; The standard analog signal, the analog pulse drive signal, the fault protection signal, the initial analog electrical signal, and the updated electrical signal are used as the single-board function test data of the power electronic device under test, so as to use the single-board function test data as the single-mode test data of the power electronic device under test in the single-board function test mode.

[0017] The above scheme drives the virtual power model to output an initial analog electrical signal. This initial analog electrical signal is transmitted to the signal board via an analog output channel. The initial analog electrical signal undergoes differential processing, filtering, and amplitude scaling to obtain a standard analog signal output by the signal board. This standard analog signal is then transmitted to the control board via a sampling signal channel. The standard analog signal undergoes analog-to-digital conversion and code execution processing to obtain an analog pulse drive signal generated by the control board based on the programmed real-time control code. A comparator on the signal board generates a trigger signal, which is transmitted to the control board to generate fault protection signals such as fault feedback and state latching. The analog pulse drive signal is transmitted to the virtual power model via a drive signal feedback channel, and the fault protection signal is transmitted back to the virtual power model via a control execution signal feedback channel. This feedback signal is then used to update the states of components such as switches and relays, obtaining the updated electrical signal output by the virtual power model. The standard analog signal, analog pulse drive signal, fault protection signal, initial analog electrical signal, and updated electrical signal are used as single-board functional test data. The comparison results between the standard analog signal and the initial analog electrical signal in the above scheme are used to characterize the actual accuracy and linearity of the signal board sampling and conditioning circuit. The comparison results between the analog pulse drive signal and the expected drive waveform are used to characterize the correctness of the control board code execution and the fidelity of the drive signal transmission. The comparison results between the fault protection signal and the preset fault injection conditions are used to characterize the response time and action correctness of hardware protection logic such as CPLD. The updated electrical signal is used to characterize the response capability of the virtual power model to the PWM drive signal. By acquiring the above data, the hardware performance of the physical signal board and control board can be comprehensively and quantitatively evaluated without high power or connection to the main power circuit, thereby improving the efficiency and safety of the test.

[0018] As a preferred example, the step of driving the virtual power model and the logic control model to acquire single-mode test data output by the power electronic device under test according to the test mode, the closed-loop data channel, the single-board signal channel, or the host computer signal channel includes: When the test mode is the communication and control test mode, the virtual power model is driven according to the preset power grid operating parameters to obtain the real-time electrical quantity data and real-time fault status data output by the virtual power model. The real-time electrical quantity data and the real-time fault status data are uploaded to the host computer controller through the operating status data channel, so that the host computer controller can output control commands. The control command is sent to the virtual power model through the control command data channel to obtain the updated electrical quantity data and updated fault status data output by the virtual power model. The control command, the real-time electrical quantity data, the real-time fault status data, the updated electrical quantity data, and the updated fault status data are used as the communication and control test data of the power electronic device under test, so as to use the communication and control test data as the single-mode test data of the power electronic device under test in the communication and control test mode.

[0019] The above scheme drives a virtual power model based on preset power grid operating parameters, and obtains real-time electrical quantity data and real-time fault status data output by the virtual power model; it uploads the real-time electrical quantity data and real-time fault status data to a host computer controller through an operating status data channel, processes the uploaded data using a governance strategy program, and obtains control commands output by the host computer controller; it then sends the control commands to the virtual power model through a control command data channel, performs parameter adjustment and status update processing on the control commands, and obtains updated electrical quantity data and updated fault status data output by the virtual power model; finally, it uses the control commands, real-time electrical quantity data, real-time fault status data, updated electrical quantity data, and updated fault status data as communication and control test data. In the above scheme, the comparison results of the real-time electrical quantity data and the updated electrical quantity data are used to characterize the response effect of the host computer governance strategy to the power grid operating conditions. The comparison results of the control commands and the changes in operating conditions are used to characterize the correctness of the governance strategy triggering logic. The comparison results of the real-time fault status data and the updated fault status data are used to characterize the reliability of the fault ride-through and recovery logic. Thus, without the need to build a real distribution network physical environment, extreme operating conditions can be reproduced with one click and the consistency of the host computer communication protocol and the correctness of the control logic can be quantitatively evaluated by simply modifying the simulation parameters, thereby improving the efficiency of the test.

[0020] As a preferred example, obtaining the multi-level test results of the power electronic device under test based on the single-mode test data and the test mode includes: When the test mode is the control logic test mode, the first comparison result between the real-time electrical quantity data in the operation verification data and the preset control performance index threshold is obtained; The second comparison result between the fault protection signal in the operation verification data and the preset fault protection threshold is obtained, so as to obtain the control logic function test result of the power electronic device under test based on the first comparison result and the second comparison result; When the test mode is the single-board function test mode, the third comparison result between the standard analog signal and the initial analog electrical signal in the single-board function test data is obtained; Obtain the waveform comparison results between the preset pulse drive signal and the simulated pulse drive signal in the single-board functional test data; The signal comparison results between the preset fault protection signal and the fault protection signal in the single-board function test data are obtained, so as to obtain the single-board function test results of the power electronic device under test according to the third comparison result, the waveform comparison result and the signal comparison result. When the test mode is communication and control test mode, the control logic is verified based on the control commands, real-time electrical quantity data, real-time fault status data, updated electrical quantity data and updated fault status data in the communication and control test data, so as to obtain the test results of the communication and control function of the power electronic device under test. Based on the test results of the control logic function, the test results of the single board function, and the test results of the communication and control function, the multi-level test results of the power electronic device under test are obtained.

[0021] The above scheme obtains a first comparison result between real-time electrical quantity data in the operation verification data and a preset control performance index threshold; obtains a second comparison result between the fault protection signal in the operation verification data and a preset fault protection threshold; performs a logical AND operation on the first and second comparison results to obtain the control logic function test result characterizing the accuracy of the control algorithm and the fault protection logic of the power electronic device under test; obtains a third comparison result between the standard analog signal and the initial analog electrical signal in the single-board function test data; obtains a waveform comparison result between the preset pulse drive signal and the analog pulse drive signal in the single-board function test data; obtains a signal comparison result between the preset fault protection signal and the fault protection signal in the single-board function test data; and performs a logical AND operation on the third comparison result, the waveform comparison result, and the signal comparison result to obtain the control logic function test result characterizing the accuracy of the control algorithm and the fault protection logic of the power electronic device under test. The test results include single-board function tests to assess the accuracy of signal board sampling and conditioning, the correctness of control board code execution, and the reliability of hardware protection functions; acquisition of control commands, real-time electrical quantity data, real-time fault status data, updated electrical quantity data, and updated fault status data from communication and control test data; and control logic verification processing of the data, including verifying whether communication delay exceeds a preset threshold, whether the triggering and execution of mitigation strategies match preset operating conditions, and whether the fault recovery sequence meets expectations, to obtain communication and control function test results characterizing the consistency of communication protocols and the correctness of control logic; and comprehensive judgment processing of the control logic function test results, single-board function test results, and communication and control function test results to obtain multi-level test results characterizing the overall pass / fail status of the power electronic device under test, thereby improving the overall testing efficiency of the device.

[0022] On the other hand, the present invention discloses a multi-level testing system for power electronic devices, including a model building module, a pattern matching module, a channel construction module, a data acquisition module, and a multi-level testing module; The model building module is used to construct the virtual power model and logic control model corresponding to the power electronic device under test based on the main power topology and real-time operation control logic of the power electronic device under test; The pattern matching module is used to match the test mode of the power electronic device under test according to the structural type of the power electronic device under test. The channel construction module is used to construct a closed-loop data channel between the virtual power model and the logic control model, a single-board signal channel between the power electronic device under test and the virtual power model, or a host computer signal channel between the power electronic device under test and the virtual power model according to the test mode. The data acquisition module is used to drive the virtual power model and the logic control model to acquire single-mode test data output by the power electronic device under test according to the test mode, the closed-loop data channel, the single-board signal channel or the host computer signal channel. The multi-level testing module is used to obtain the multi-level test results of the power electronic device under test based on the single-mode test data and the test mode.

[0023] This invention discloses a multi-level testing system for power electronic devices. Based on the main power topology and real-time operation control logic of the power electronic device under test (DUT), a virtual power model and a logic control model are constructed. The system automatically matches the test mode according to the device's structural type, constructs corresponding data channels, drives the model operation, acquires multi-mode test data, and performs comprehensive evaluation and processing on the multi-mode test data to obtain a comprehensive verification result characterizing the DUT from control logic to board functionality and upper-level computer communication. The method disclosed in this invention abandons the traditional serial development model that requires the completion of a physical power hardware prototype before testing, achieving parallel development capability without waiting for hardware completion, thereby improving the testing efficiency of the device.

[0024] As a preferred example, the model building module includes a power model unit and a logic model unit; The power model unit is used to obtain the main power topology of the power electronic device under test, and deploy the main power topology in the first computing resource within the preset simulation platform to obtain the virtual power model of the power electronic device under test. The logic model unit is used to acquire the real-time operation control logic of the power electronic device under test, and deploy the real-time operation control logic in the second computing resource within the simulation platform to obtain the logic control model of the power electronic device under test; wherein, the real-time operation control logic includes control logic and fault protection logic.

[0025] The above scheme obtains a dual-model architecture within the same simulation platform, where different computing resources respectively carry out power main circuit simulation and control algorithm execution, thereby obtaining the data channel foundation that characterizes the low-latency, high-synchronization closed-loop interaction capability between models; at the same time, it obtains the integrated verification capability of integrating control logic and fault protection logic into the same real-time running control code, thus enabling simultaneous verification of algorithm accuracy and protection function reliability in the pure digital verification stage, improving testing efficiency. Attached Figure Description

[0026] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This is a flowchart illustrating a multi-level testing method for power electronic devices provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a virtual power model based on a T-type three-level converter provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a virtual power model of a flexible DC voltage regulating device provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a multi-level testing system for power electronic devices provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of a single-board functional test mode for a multi-level test method for power electronic devices provided in an embodiment of the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] See Figure 1To improve testing efficiency, this embodiment discloses a multi-level testing method for power electronic devices, including: Step 101: Based on the main power topology and real-time operation control logic of the power electronic device under test, construct the virtual power model and logic control model corresponding to the power electronic device under test; Step 102: Match the test mode of the power electronic device under test according to the structural type of the power electronic device under test; Step 103: Construct a closed-loop data channel between the virtual power model and the logic control model, a single-board signal channel between the power electronic device under test and the virtual power model, or a host computer signal channel between the power electronic device under test and the virtual power model according to the test mode; Step 104: Drive the virtual power model and the logic control model to obtain single-mode test data output by the power electronic device under test according to the test mode, the closed-loop data channel, the single-board signal channel or the host computer signal channel; Step 105: Based on the single-mode test data and the test mode, obtain the multi-level test results of the power electronic device under test.

[0030] In this embodiment, the power electronic device under test (DUT) refers to a power electronic device that requires functional, performance, or reliability testing, such as a flexible DC voltage regulator, a flexible interconnect device, or a converter. The virtual power model is a mathematical model built on an FPGA (Field-Programmable Gate Array) that can simulate the main power topology of the power electronic device in real time. This model includes converter topology, switching device models, line impedance, grid / load models, fault models, sensors, relays, etc., and operates in microsecond-level real-time steps, capable of outputting electrical quantities such as voltage, current, and power in real time. The logic control model is a software model simulating the control algorithm and protection logic of the DUT, typically running on a CPU or DSP platform, used to generate control signals (such as PWM pulses) and respond to faults. The test mode is a pre-set test scheme based on the structural type of the DUT (such as a flexible DC voltage regulator, a flexible interconnect device, etc.), including normal operation mode, fault ride-through mode, and power step mode. The closed-loop data channel is a data link connecting the virtual power model and the logic control model, used for... The system transmits bidirectional electrical quantity sampling values ​​(from the virtual power model to the logic control model) and control signals (from the logic control model to the virtual power model) to form a closed-loop control circuit. The single-board signal channel is a signal link connecting the actual controller board of the power electronic device under test (DUT) to the virtual power model. It transmits PWM pulse signals or control commands output by the actual board to the virtual power model and sends back electrical quantity signals fed back from the virtual power model to the DUT. The host computer signal channel is a communication link connecting the host computer (monitoring computer) to the virtual power model, the logic control model, and the DUT. It is used for parameter configuration, status monitoring, test command issuance, and test data upload. The multi-mode test data consists of raw data such as electrical quantities (voltage, current, power), control signals, fault response time, and protection action values ​​collected through the above channels under different test modes. The multi-level test results are test conclusions obtained after processing, analyzing, and evaluating the multi-mode test data, such as graded evaluation results for whether the function is normal, whether the performance indicators meet the standards, and whether the protection logic is correct.

[0031] In this first embodiment, a corresponding virtual power model and logic control model are constructed based on the main power topology and real-time operation control logic of the power electronic device under test. Preferably, a hardware description model consistent with the main power topology of the device under test is built based on an FPGA platform. This model includes the converter topology used (e.g., a T-type three-level converter), switching device model (e.g., SiC MOSFET or IGBT), line impedance, power grid / load model, and fault model. The model operates in real-time steps at the microsecond level and can calculate and output electrical quantities such as voltage, current, and power in real time.

[0032] Preferably, with Figure 2 The virtual power model of the T-type three-level converter shown uses SiCMOSFETs as the switching device, but IGBTs can also be used. And as... Figure 3 Taking the flexible DC voltage regulating device shown as an example, this device consists of a rectifier and an inverter. Its two ends are connected to the 380V AC power grid, and the DC side is connected via a 750V DC bus. The line impedance on the DC line is determined based on the installation distance between the rectifier and inverter units and the conductivity of the cables used. For example, if the cable used is BLVV-120, and its maximum conductor resistance at 20℃ is 0.253Ω / km, and the distance between the two locations is 1.05km, then the purely resistive impedance is 0.26565Ω. This virtual power model aims to regulate the voltage quality at the end of the distribution network.

[0033] Taking a flexible interconnection device as an example, its rectifier and inverter units are integrated into one device with no impedance on the DC connection line. The device is connected between two transformer substations and solves the problem of heavy overload in the substations by regulating power flow. The rectifier unit rectifies 380V AC to ±375V DC using pulse width modulation (PWM) commutation technology (such as carrier stacked modulation SPWM and space vector modulation SVPWM), and the inverter unit inverts ±375V DC to 380V AC using the same PWM technology. Real-time values ​​of electrical quantities, such as grid-side current and voltage, bridge arm-side voltage and current, total DC bus voltage, and upper and lower capacitor voltages, are obtained through sensors, and the real-time value of output power is obtained through the power calculation formula of the three-phase AC power grid.

[0034] Construction of the logic control model: Based on the actual control algorithm and protection logic of the power electronic device under test (e.g., voltage and current dual closed-loop control, DC voltage balance control, fault detection and protection action logic, etc.), a corresponding control model is constructed on a CPU or DSP platform. This model receives electrical quantity sampling values ​​fed back from the virtual power model, calculates them through the control algorithm, and outputs PWM pulses or switching commands to drive the state switching of switching device models, relay elements, etc. in the virtual power model.

[0035] Based on the structural type of the power electronic device under test (e.g., flexible DC voltage regulator or flexible interconnect device), the corresponding test mode is matched. The test modes may include: normal operation mode (to assess steady-state control accuracy), power step mode (to assess dynamic response performance), fault ride-through mode (to assess uninterrupted operation capability during faults), protection action mode (to assess the correctness of overcurrent, overvoltage, short circuit and other protection logic), etc. The test modes applicable to different structural types of devices are pre-stored in the test case library. In this embodiment, the test mode is automatically matched according to the device model or manually selected by the tester.

[0036] This embodiment constructs the following three types of data channels based on the determined test mode: Closed-loop data channel: A bidirectional data link is established between the virtual power model and the logic control model. On one hand, the virtual power model sends the real-time calculated electrical quantities (such as grid-side voltage and current, DC bus voltage, output power, etc.) to the logic control model through this channel; on the other hand, the logic control model sends the calculated PWM control signals (switch duty cycle or pulse sequence) to the virtual power model through this channel to drive the state switching of switching device models, relay elements, etc.; Single-board signal channel: A signal link is established between the actual controller board of the power electronic device under test and the virtual power model. This channel is used to transmit the PWM pulse signals or control commands output by the actual board to the virtual power model, and simultaneously transmit the electrical quantity signals (analog sensor output) fed back by the virtual power model to the control board of the device under test, forming a hardware-in-the-loop (HIL) test loop; Host computer signal channel: A communication link is established between the host computer (monitoring computer) and the virtual power model, the logic control model, and the power electronic device under test. This channel is used by the host computer to send test parameters (such as fault type, time, amplitude), mode switching commands, and monitoring status information, and to receive test data in real time for display and storage.

[0037] The virtual power model and logic control model are started, and test commands are issued through the host computer channel according to the test mode (e.g., setting a power step target value, triggering a grid voltage drop fault, etc.). In this embodiment, the output data of the power electronic device under test in different test modes are collected in real time through the closed-loop data channel, the single-board signal channel, and the host computer signal channel. These data include: instantaneous values ​​of electrical quantities (voltage, current, power waveforms), control response time (delay from command issuance to power change), protection action values ​​(overcurrent protection trigger threshold and action time), and uninterrupted power supply time during fault ride-through. The above data are collectively referred to as multi-mode test data.

[0038] The acquired multi-mode test data is processed, analyzed, and evaluated to obtain multi-level test results. This embodiment constructs a virtual power model and a logic control model based on the main power topology and real-time operation control logic of the power electronic device under test (PDD). It automatically matches the test mode according to the device's structural type, constructs corresponding data channels, and drives the model to run, acquiring multi-mode test data. This multi-mode test data is then comprehensively evaluated and processed to obtain comprehensive verification results characterizing the PDD from control logic to board functionality and upper-level computer communication. This approach abandons the traditional serial development model that requires the completion of a physical power hardware prototype before testing, achieving parallel development capabilities that allow testing to proceed without waiting for hardware completion, thereby improving the device's testing efficiency.

[0039] In this embodiment, step 101 includes: Step 1011: Obtain the main power topology of the power electronic device under test, and deploy the main power topology in the first computing resource within the preset simulation platform to obtain the virtual power model of the power electronic device under test; Step 1012: Obtain the real-time operation control logic of the power electronic device under test, and deploy the real-time operation control logic in the second computing resource within the simulation platform to obtain the logic control model of the power electronic device under test; wherein, the real-time operation control logic includes control logic and fault protection logic.

[0040] In this embodiment, the main power topology of the power electronic device under test is obtained. The topology includes the converter topology type used (e.g., T-type three-level converter), the switching device model (e.g., SiC MOSFET or IGBT), the DC bus connection method (e.g., the rectifier and inverter of the flexible DC voltage regulator are connected through a 750V DC bus), the line impedance parameters (calculated based on the installation distance and the conduction resistance of the cables used), the power grid / load model, and the fault model.

[0041] Taking a flexible DC voltage regulator as an example, this device consists of a rectifier and an inverter. Its two ends are connected to a 380V AC power grid, and the DC side is connected via a 750V DC bus. The line impedance on the DC line is determined based on the installation distance between the rectifier and inverter units and the conductivity of the cables used. For example, if the cable used is BLVV-120, and its maximum conductor resistance at 20℃ is 0.253Ω / km, and the distance between the two locations is 1.05km, then the purely resistive impedance is 0.26565Ω. This device aims to regulate the voltage quality at the end of the distribution network.

[0042] Taking a flexible interconnection device as an example, its rectifier and inverter units are integrated into one device with no impedance on the DC connection line. The device is connected between two transformer substations and solves the problem of heavy overload in the substations by regulating power flow. The rectifier unit rectifies 380V AC to ±375V DC using pulse width modulation (PWM) commutation technology (such as carrier stacked modulation SPWM and space vector modulation SVPWM), and the inverter unit inverts ±375V DC to 380V AC using the same PWM technology. This implementation obtains real-time values ​​of electrical quantities through sensors, such as grid-side current and voltage, bridge arm-side voltage and current, total DC bus voltage, and upper and lower capacitor voltages, and obtains the real-time value of output power using the power calculation formula of a three-phase AC power grid.

[0043] Then, in the pre-defined simulation platform, the aforementioned main power topology is deployed on the first computing resource (i.e., the FPGA). The FPGA operates in real-time steps at the microsecond level, using hardware description languages ​​(such as Verilog or VHDL) to implement the switching behavior of switching devices, voltage drop calculations of line impedance, equivalent models of the power grid / load, and various preset faults (such as single-phase grounding and phase-to-phase short circuits). The resulting model is the virtual power model of the power electronic device under test (DUT). This model can output electrical quantities such as voltage, current, and power in real time and transmit them to the logic control model or the actual controller of the DUT via a data channel.

[0044] The real-time operation control logic of the power electronic device under test is acquired. This control logic includes control logic used to adjust the device output under normal operating conditions, such as voltage and current dual closed-loop control, DC voltage balance control, and PWM modulation algorithms (including SPWM, SVPWM, etc.). This part of the logic calculates the duty cycle or switching sequence of the switching devices based on the sampled values ​​of the input electrical quantities (such as grid-side voltage and current, DC bus voltage). The fault protection logic is used to protect the device under abnormal operating conditions, such as overcurrent protection (blocking the pulse when the current exceeds the threshold), overvoltage protection (operating when the voltage exceeds the threshold), and short-circuit protection. This part of the logic monitors whether the electrical quantities exceed the preset protection settings in real time and executes the corresponding protection actions (such as tripping and blocking).

[0045] Then, in the same preset simulation platform, the above-mentioned real-time operation control logic is deployed in the second computing resource (i.e., CPU or DSP core). The CPU / DSP runs at a step size suitable for the control algorithm (usually a few microseconds), and the code for the control algorithm and protection logic is implemented through a programming language. The model obtained after this deployment is the logic control model of the power electronic device under test. The logic control model receives electrical quantity feedback from the virtual power model (through a closed-loop data channel), generates PWM pulses or switching commands after control calculations, and then sends them back to the virtual power model to drive the state switching of switching devices, relay elements, etc. At the same time, the logic control model can also receive test commands (such as fault triggering, mode switching) through the host computer channel and report status information. It should be noted that in this embodiment, the first computing resource and the second computing resource are two different types of computing units that are physically independent or logically isolated within the simulation platform; wherein, the first computing resource refers to hardware logic circuits suitable for running large-scale, high-parallelism, fixed-step, and real-time requirements down to the microsecond level, typically such as field-programmable gate arrays. The first computing resource is used to deploy the main power topology of the device under test (DUT) and realize the real-time solution of the virtual power model. Its characteristic is that it can perform parallel computation in nanosecond to microsecond increments, accurately simulating the high-speed switching transient process of power devices. The second computing resource refers to a general-purpose or dedicated processor core suitable for running serial, branch-based software algorithm tasks with real-time requirements on the order of tens of microseconds; typical examples include central processing units (CPUs) or digital signal processors (DSPs). The second computing resource is also used to deploy the real-time operational control logic of the DUT, realizing the execution of the logic control model. Its characteristic is its ability to efficiently execute complex control algorithms (such as PID calculation, coordinate transformation, and PWM generation) and fault protection logic software code.

[0046] The above implementation method obtains a dual-model architecture in which different computing resources within the same simulation platform respectively carry out power main circuit simulation and control algorithm execution, thereby obtaining the data channel foundation that characterizes the low-latency, high-synchronization closed-loop interaction capability between models; at the same time, it obtains the integrated verification capability of integrating control logic and fault protection logic into the same real-time running control code, thereby enabling simultaneous verification of algorithm accuracy and protection function reliability in the pure digital verification stage, improving the efficiency of testing.

[0047] In this embodiment, step 102 includes: Step 1021: When it is determined that the power electronic device under test does not have a physical board based on the structural type of the power electronic device under test, the test mode of the power electronic device under test is determined to be the control logic test mode. Step 1022: When it is determined from the structure type that the power electronic device under test has a physical board but no host computer controller, the test mode of the power electronic device under test is determined to be the single board function test mode. Step 1023: When it is determined that the power electronic device under test has a host computer controller based on the structure type, the test mode of the power electronic device under test is determined to be the communication and control test mode.

[0048] In this embodiment, during the early stages of device development, when the signal board and control board have not yet been prototyped or delivered, it is determined that there is no physical board, and the system enters the control logic test mode. If the signal board and control board have been prototyped and soldered together, but the software for the host computer controller has not yet been developed or connected, it is determined that there is a physical board but no host computer controller, and the system enters the single-board function test mode. If the host computer controller has already deployed the governance strategy program and can connect to the simulation platform via a communication protocol, it is determined that there is a host computer controller, and the system enters the communication and control test mode. In this embodiment, the structure type can be a manually input status parameter or can be determined by automatically detecting the connection status between the physical board and the host computer.

[0049] The above implementation acquires the physical board status information and host computer controller status information of the power electronic device under test (PDD). It then performs structure type determination processing on the status information. If a physical board is not found, a control logic test mode is matched; if a physical board is found but a host computer controller is not, a single-board function test mode is matched; and if a host computer controller is found, a communication and control test mode is matched. This allows the test process to automatically adapt to different verification levels based on the device's development stage, enabling parallel testing and improving test efficiency. Specifically, the above scheme, through hierarchical matching processing, obtains progressive logic that automatically proceeds to physical board verification only after pure digital verification passes, and progressive logic that automatically proceeds to host computer verification only after single-board function verification passes. This prevents defective code or hardware from entering subsequent testing stages and significantly reduces the risk of power device damage.

[0050] In this embodiment, step 103 includes: Step 1031: When the test mode is the control logic test mode, establish a first data channel from the virtual power model to the logic control model and a second data channel from the logic control model to the virtual power model in the simulation platform; wherein, the first data channel and the second data channel are used as closed-loop data channels; Step 1032: When the test mode is the single-board function test mode, acquire the signal board and control board of the power electronic device under test, and construct the analog output channel from the virtual power model to the signal board, the sampling signal channel from the signal board to the control board, the drive signal feedback channel from the control board to the virtual power model, and the control execution signal feedback channel from the control board to the virtual power model; wherein, the analog output channel, the sampling signal channel, the drive signal feedback channel, and the control execution signal feedback channel are used as single-board signal channels; Step 1033: When the test mode is the communication and control test mode, obtain the host computer controller of the power electronic device under test, and construct the operating status data channel from the virtual power model to the host computer controller and the control command data channel from the host computer controller to the virtual power model; wherein, the operating status data channel and the control command data channel are used as host computer signal channels.

[0051] In this embodiment, when the test mode is the control logic test mode, a first data channel from the virtual power model to the logic control model and a second data channel from the logic control model to the virtual power model are established in the simulation platform; wherein, the first data channel and the second data channel are used as closed-loop data channels.

[0052] In this embodiment, the first data channel is used to transmit electrical quantity data (such as grid-side voltage and current, DC bus voltage, etc.) calculated in real time by the virtual power model to the logic control model; the second data channel is used to transmit the PWM drive signal and fault protection signal generated by the logic control model to the virtual power model. Since the virtual power model and the logic control model are deployed on different computing resources of the same simulation platform, the above channels can be implemented through the platform's internal bus or shared memory, resulting in extremely low latency.

[0053] When the test mode is the single-board function test mode, the signal board and control board of the power electronic device under test are acquired, and an analog output channel from the virtual power model to the signal board, a sampling signal channel from the signal board to the control board, a drive signal feedback channel from the control board to the virtual power model, and a control execution signal feedback channel are constructed. The analog output channel, the sampling signal channel, the drive signal feedback channel, and the control execution signal feedback channel are used as the single-board signal channels. In this embodiment, the signal board is a physical PCB board, undertaking the core functions of sampling filtering, hardware protection linkage, DSP power supply, and bidirectional communication. The control board includes a DSP chip and a CPLD chip, where the DSP chip is responsible for control algorithm calculation and signal processing, and the CPLD chip is responsible for hardware fault detection and protection linkage. The above physical channels are established through the hardware I / O board of the simulation platform: the analog output channel converts the digital electrical quantities generated by the virtual power model into analog signals (0~5V) and outputs them to the sampling input terminal of the signal board. In the sampling signal channel, the signal board performs differential processing, filtering, and amplitude scaling on the analog signal, and then transmits the standard analog signal to the AD sampling channel of the DSP chip on the control board; in the drive signal feedback channel, the PWM drive signal generated by the DSP chip on the control board is fed back to the virtual power model of the simulation platform through the digital I / O port.

[0054] When the test mode is the communication and control test mode, the host computer controller of the power electronic device under test is obtained, and the operating status data channel from the virtual power model to the host computer controller and the control command data channel from the host computer controller to the virtual power model are constructed; wherein, the operating status data channel and the control command data channel are used as host computer signal channels.

[0055] In this embodiment, the host computer controller is a physical controller, internally deploying the main program for power grid governance strategies. A bidirectional connection is established via standard communication protocols (such as TCP / IP, Modbus, RTU, etc.). If the communication protocols used by the host computer controller and the virtual power model are inconsistent, a protocol converter is required. For example, if the host computer uses the RTU protocol while the virtual power model uses the TCP / IP protocol, an interconnection is achieved by constructing a local area network using a protocol converter. The protocol converter has a built-in protocol parsing module and a format conversion unit. After receiving raw data from the host computer or the virtual power model, the parsing module identifies the protocol type and extracts valid data, and the conversion unit converts the data format into a protocol specification that the other party can recognize, while ensuring the real-time performance and integrity of data transmission.

[0056] In the above implementation scheme, when the test mode is control logic test mode, the first data channel from the virtual power model to the logic control model and the second data channel from the logic control model to the virtual power model are acquired within the simulation platform, thereby obtaining a data channel characterizing the pure digital closed-loop interaction capability. When the test mode is single-board function test mode, four types of single-board signal channels are acquired: analog output channel, sampling signal channel, drive signal feedback channel, and control execution signal feedback channel, thereby obtaining a data channel characterizing the complete bidirectional closed-loop connection between the virtual power model and the physical signal board and control board. When the test mode is communication and control test mode, the operating status data channel and control command data channel are acquired, thereby obtaining a data channel characterizing the bidirectional data interaction capability between the host computer controller and the virtual power model. The above scheme, through the construction and processing of the above channels, obtains an environment where verification at each level can be achieved without high-voltage power or connection to the main power circuit, thus completely eliminating the safety risks of high-voltage testing and significantly reducing hardware resource consumption.

[0057] In this embodiment, step 104 includes: Step 1041: When the test mode is the control logic test mode, drive the virtual power model to output initial electrical quantity data, and send the initial electrical quantity data to the logic control model according to the first data channel, so that the logic control model outputs pulse drive signal and fault protection signal; send the pulse drive signal and the fault protection signal to the virtual power model according to the second data channel, so that the virtual power model outputs adjusted electrical quantity data according to the pulse drive signal and the fault protection signal; use the pulse drive signal, the fault protection signal, the adjusted electrical quantity data and the initial electrical quantity data as the operation verification data of the power electronic device under test, and use the operation verification data as the single-mode test data of the power electronic device under test in the control logic test mode.

[0058] Step 1042: When the test mode is the single-board function test mode, the virtual power model is driven to output an initial analog electrical signal, and the initial analog electrical signal is transmitted to the signal board through the analog output channel, so that the signal board outputs a standard analog signal corresponding to the analog electrical signal, and generates a trigger signal corresponding to the standard analog signal according to the comparator on the signal board; the standard analog signal and the trigger signal are transmitted to the control board through the sampling signal channel, so that the control board processes the standard analog signal according to the burned real-time operation control code, generates an analog pulse drive signal, and processes the trigger signal according to the real-time operation control code, so as to... A fault protection signal is generated; wherein the fault protection signal includes a fault feedback signal and a status latch signal; the analog pulse drive signal is transmitted to the virtual power model through the drive signal feedback channel; the fault protection signal is transmitted back to the virtual power model through the control execution signal feedback channel to obtain the updated electrical signal output by the virtual power model; the standard analog signal, the analog pulse drive signal, the fault protection signal, the initial analog electrical signal, and the updated electrical signal are used as the single-board function test data of the power electronic device under test, so that the single-board function test data is used as the single-mode test data of the power electronic device under test in the single-board function test mode.

[0059] Step 1043: When the test mode is the communication and control test mode, drive the virtual power model according to the preset power grid operating parameters to obtain the real-time electrical quantity data and real-time fault status data output by the virtual power model; upload the real-time electrical quantity data and real-time fault status data to the host computer controller through the operating status data channel so that the host computer controller outputs control commands; send the control commands to the virtual power model according to the control command data channel to obtain the updated electrical quantity data and updated fault status data output by the virtual power model; use the control commands, the real-time electrical quantity data, the real-time fault status data, the updated electrical quantity data, and the updated fault status data as the communication and control test data of the power electronic device under test, so as to use the communication and control test data as the single-mode test data of the power electronic device under test in the communication and control test mode.

[0060] In this embodiment, when the power electronic device under test does not have any physical circuit boards (i.e., the signal board and control board are neither prototyped nor delivered) and is not connected to a host computer controller, it automatically matches to the control logic test mode. In this mode, the following operations are performed: The virtual power model deployed on the first computing resource (e.g., FPGA) of the simulation platform is driven to start running in real-time steps at the microsecond level. The virtual power model calculates and outputs initial electrical quantity data in real time based on preset initial operating conditions (e.g., grid voltage 380V / 50Hz, DC bus voltage command value 750V, load is no-load or half-load). The initial electrical quantity data includes at least: instantaneous values ​​of three-phase grid-side voltage, instantaneous values ​​of three-phase grid-side current, total DC bus voltage, upper and lower capacitor voltages, bridge arm voltage and current, and output active power and reactive power. This data exists in digital form through the data bus within the simulation platform.

[0061] Secondly, the first data channel transmits the aforementioned initial electrical quantity data in real time to the logic control model deployed in the second computing resource (e.g., CPU). The transmission cycle is consistent with the execution cycle of the control algorithm, for example, set to 25kHz (i.e., once every 40μs).

[0062] Furthermore, after receiving the initial electrical quantity data, the logic control model executes the deployed real-time operation control code, which includes a control algorithm and a fault protection logic. The control algorithm can be configured to use either rectification or inverter mode, depending on the current testing requirements. Preferably, taking the rectification mode as an example, a dual closed-loop control structure of voltage outer loop + current inner loop is adopted. In the voltage outer loop, the real-time value of the received DC bus total voltage is compared with the command value. The difference is calculated by the PI regulator and output as the d-axis current command of the current inner loop. The q-axis current command is set according to the reactive power demand (usually set to 0 to achieve unity power factor). In the current inner loop, the actual d / q-axis current obtained by coordinate transformation of the grid-side current is compared with the command value. The difference is adjusted by the PI regulator and output as the d / q-axis reference voltage. Then, the reference modulation wave in the three-phase stationary coordinate system is obtained by inverse coordinate transformation. Next, in the PWM modulation, the reference modulation wave is compared with the triangular carrier (carrier frequency, for example, 10kHz to 25kHz). The space vector pulse width modulation (SVPWM) or sinusoidal pulse width modulation (SPWM) algorithm is used to generate the turn-on / turn-off signals of each power switching device, i.e., pulse drive signals. This signal is a series of high and low level sequences, where high level represents the switch being turned on and low level represents the switch being turned off.

[0063] Simultaneously, the logic control model compares the received electrical quantity data with preset fault protection thresholds. For example, it determines whether the total DC bus voltage exceeds a set voltage (e.g., 835V), whether the effective value of the grid-side current exceeds 1.2 times the rated value, whether the custom temperature exceeds 75℃, or whether the grid frequency exceeds the specified range. When any electrical quantity exceeds the corresponding threshold, the fault protection logic immediately generates a fault protection signal. This signal may include: an instruction to block all PWM drive outputs, a device state switch to fault shutdown, and the generation of a corresponding binary fault code. Each bit represents a fault signal with a fixed parameter: 1 for fault and 0 for normal (e.g., binary 1011 represents A-phase grid current overcurrent, B-phase grid current normal, C-phase grid current overcurrent, and N-phase grid current overcurrent). The logic control model transmits the generated pulse drive signal and fault protection signal back in real time through the second data channel.

[0064] Finally, upon receiving the pulse drive signal, the virtual power model updates the on / off state of its internal switching devices based on the signal level (e.g., setting the corresponding IGBT or SiC MOSFET model to on when the level is high, and setting it to off when the level is low). Simultaneously, if a PWM blocking command is received from a fault protection signal, all switches are forcibly turned off. Subsequently, the virtual power model resolves the circuit differential equations in microsecond-level steps to calculate the electrical quantities at the next moment, obtaining adjusted electrical quantity data (e.g., the total DC bus voltage rises from its initial value to near the command value due to rectification, and the grid-side current tracks the command value, etc.).

[0065] During the interaction of the above model, pulse drive signals (including duty cycle, frequency, and dead time information in each switching cycle), fault protection signals (including trigger time, fault word, and protection action type), adjusted electrical quantity data (such as updated DC bus total voltage, grid-side current, output power, etc.) and initial electrical quantity data (as a comparison benchmark) are collected and stored as the operation verification data of the power electronic device under test.

[0066] When the power electronic device under test already has physical signal boards and physical control boards (i.e., the PCB boards have been prototyped and soldered), but has not yet been connected to the host computer controller, this embodiment automatically matches it to the single-board function test mode. In this mode, the following operations are performed.

[0067] First, the physical signal board and control board of the device under test (DUT) are physically connected to the virtual power model via the hardware I / O board of the simulation platform. The signal board is powered by an external 24V regulated power supply, and its internal level conversion circuit provides 5V and 3.3V operating power to the core control board (DSP+CPLD). Simultaneously, the project file containing real-time running control code is written to the DSP chip via a programmer, and the CPLD code is written to the CPLD chip. The entire testing process requires no connection to the main power circuit and no application of real high voltage (i.e., no connection to 380V AC or 750V DC).

[0068] Secondly, the virtual power model is driven to run in microsecond steps to generate digital domain electrical quantity data that represents the real operating conditions. These data are converted into analog voltage signals by the digital-to-analog converter (DAC) in the hardware I / O board of the simulation platform. For example, the output range is 0~5V, and this signal is the initial analog electrical signal.

[0069] Next, the analog output channel (AO channel of the IO board) transmits the initial analog electrical signal to the sampling input terminal of the physical signal board via a wired method (such as shielded twisted pair cable), so that after the signal board receives the initial analog electrical signal, it performs the following conditioning operations in sequence: differential processing to eliminate common-mode interference through differential circuit, filtering processing to remove high-frequency noise through filter circuit, and calibrating the signal amplitude to the adaptation range (e.g., 0-3V) of the DSP chip ADC module through arithmetic circuit to obtain the amplitude scaling of the standard analog signal.

[0070] Furthermore, the standard analog signal is transmitted to the control board through the sampling signal channel on the signal board. Specifically, the sampling signal channel transmits the standard analog signal to the control board in real time, and the DSP chip on the control board performs analog-to-digital conversion on the standard analog signal through its ADC peripheral to obtain digital electrical quantities.

[0071] Next, the DSP chip runs the pre-programmed real-time control code (the same code used in the control logic test mode), executes a dual closed-loop control algorithm and PWM modulation based on digital electrical quantities, and generates an analog pulse drive signal (i.e., a PWM waveform). Simultaneously, the standard analog signal is used by a comparator on the signal board to generate a trigger signal, which is then transmitted to the CPLD chip on the control board. This chip monitors the output level of the hardware fault detection module (e.g., an overcurrent comparator) in real time. When the injected analog electrical signal triggers the hardware fault detection module, the control board immediately outputs a control execution signal to the virtual power model (e.g., blocking the PWM drive signal, disconnecting the grid-connected relay, etc.).

[0072] Finally, the drive signal feedback channel and the control execution signal feedback channel transmit the analog pulse drive signal and fault protection signal generated by the control board to the virtual power model of the simulation platform. The simulation platform uses these signals as input to drive the virtual power model. The virtual power model updates the on / off state of its internal switching devices based on the returned analog pulse drive signal and executes protection actions (such as blocking switches) based on the fault protection signal. Then, the electrical quantities are recalculated to obtain the updated electrical signals (e.g., updated DC bus total voltage, grid-side current, etc.).

[0073] During the interaction between the model and the device, standard analog signals (characterizing the sampled values ​​after signal board conditioning), analog pulse drive signals (characterizing the PWM waveform actually output by the control board), fault protection signals (characterizing hardware protection actions), and initial analog electrical signals (as reference benchmarks) are acquired and stored as single-board functional test data.

[0074] In summary, referring to Figure 5 As shown in the schematic diagram of the single-board function test mode, in the single-board function test mode, a closed-loop test circuit is formed between the virtual power model, the physical signal board and the physical control board, and the entire test process does not require connection to the real main circuit power.

[0075] from Figure 5 It is known that the virtual power model deployed in the simulation platform (such as RT-LAB) contains the main circuit topology (including power devices and passive components), sensor models (voltage sensors and current sensors), and relay models, which are used to simulate the electrical behavior of the power electronic device under test in real time; the physical signal board of the power electronic device under test contains differential circuits, filter circuits, amplitude scaling circuits, and comparators, which are used to perform signal conditioning and hardware fault detection on the analog electrical quantities output by the virtual power model; the physical control board of the power electronic device under test contains a DSP controller (used to execute control algorithms and generate PWM pulse signals) and a CPLD / FPGA (used for hardware fault feedback and state latching).

[0076] from Figure 5 It can be seen that the virtual power model obtains electrical analog quantities (such as the measured voltage) representing the state of the main circuit through its internal sensor model. The measured current ), and output it to the physical signal board; The signal board sequentially performs differential, filtering, and amplitude scaling on the received electrical analog quantities to generate a standard analog signal that matches the AD sampling range of the control board. This standard analog signal is then transmitted to the DSP controller of the control board via the sampling signal channel. Simultaneously, the conditioned standard analog signal is processed by a comparator on the signal board to generate a trigger signal, which is then transmitted to the CPLD / FPGA of the control board for hardware-level fault detection and rapid protection. The DSP controller on the control board runs the pre-programmed real-time control code based on the sampled signal, generates PWM pulse signals, and feeds them back to the virtual power model through the drive signal feedback channel to drive the power device model in the virtual power model. After detecting a hardware fault trigger signal, the CPLD / FPGA on the control board generates fault feedback and status latch signals, which are transmitted to the virtual power model through the control execution signal feedback channel to control the relay to disconnect or perform other protection actions.

[0077] Through the aforementioned connection and data interaction, the test architecture disclosed in this embodiment can fully verify the sampling and conditioning accuracy of the physical signal board, the code execution correctness of the physical control board, and the reliability of the hardware protection logic without high power supply or connection to the actual main power circuit.

[0078] When the power electronic device under test is connected to a physical host computer controller (such as an industrial control computer with power grid management strategy programs deployed therein), this embodiment automatically matches it to the communication and control test mode. In this mode, the following operations are performed.

[0079] First, configure a bidirectional communication point table based on the communication protocol used by the host computer controller and the simulation platform. For example, if the host computer uses the RTU protocol (serial port) while the simulation platform uses the TCP / IP protocol, the two are inconsistent, requiring a protocol converter. The protocol converter has a built-in protocol parsing module (identifying RTU or TCP frame structure) and a format conversion unit (encapsulating RTU data into TCP packets or extracting RTU data from TCP packets). Simultaneously, configure the point table in the simulation platform, mapping each data item (such as three-phase voltage, current, active power, fault words, control commands, etc.) to a specified IO channel number or register memory address, and setting data conversion rules (such as the conversion factor from raw values ​​to engineering values).

[0080] Next, the power grid operating parameters are set on the simulation platform's interface. For example, the effective value of the load-side voltage is set to be below the preset lower limit of the normal range, the load current is set to exceed the rated value, the overload duration is set, and the voltage amplitudes of each phase are set to be unequal. The virtual power model operates based on these parameters, calculating the corresponding real-time electrical quantity data (such as three-phase voltage, current, power, frequency, and unbalance) and real-time fault status data (such as fault words, initially set to 0). It is important to note that the real-time electrical quantity data is used to process the operational verification data. It is compared with preset control performance index thresholds, thus representing the actual output electrical quantity of the power electronic device under test under the control algorithm—that is, the adjusted electrical quantity data. This is because the initial electrical quantity data is an open-loop input and does not reflect the control effect; while the adjusted electrical quantity data is the output electrical quantity of the virtual power model after adjustment by the logic control model (control algorithm), which can truly characterize the adjustment accuracy and dynamic response performance of the control algorithm.

[0081] Simultaneously, the simulation platform reads the corresponding memory address from the point table, packages the real-time electrical quantities and fault status data according to the protocol (if protocol conversion is required, it is first sent to the protocol converter), and sends it to the host computer controller through the running status data channel. It also supports event-triggered supplementary transmission: when the fault status word changes from 0 to non-zero, or when the electrical quantity undergoes a step change exceeding a preset threshold, the simulation platform immediately sends a frame of data.

[0082] Furthermore, after receiving the data, the host computer controller runs its internal power grid management strategy main program. Taking a flexible DC voltage regulator as an example: if the terminal voltage is detected to be too low (below the preset lower limit of the normal voltage range), the low voltage management strategy is automatically activated: generating control commands to start the device and direct power flow from the beginning to the end of the power grid; if the terminal voltage is detected to be too high (above the preset upper limit of the normal voltage range), the high voltage management strategy is activated: generating commands to direct power flow from the end to the beginning of the power grid; if the power grid imbalance is detected to be too large, the phase-by-phase control algorithm is activated: generating independent power commands for each phase; if a non-zero fault word is received, a fault reset or shutdown command is generated according to the fault type. These commands are packaged in a preset data format and sent through the control command data channel.

[0083] Simultaneously, the control command data channel transmits command packets from the host computer to the simulation platform. If the protocols are inconsistent, they also pass through a protocol converter. The simulation platform parses the command packets and writes the command values ​​to the memory addresses corresponding to the point tables (such as the reference power register, operating mode register, and fault reset register).

[0084] Finally, the virtual power model reads the updated register values ​​and adjusts its internal control parameters and operating status. For example, upon receiving a start-up device and a power flow direction from the beginning to the end, the rectifier in the virtual power model switches from standby to operation and adjusts its output according to the given power command, thereby changing the end voltage. After several control cycles, the end voltage gradually returns to the normal range. Simultaneously, if the fault is reset, the fault status word is cleared. These changed data constitute the updated electrical quantity data and the updated fault status data.

[0085] During the interaction between the above model and the device, control commands (a sequence of commands issued by the host computer, including timestamps and command content), real-time electrical quantity data and real-time fault status data (uploaded data), as well as updated electrical quantity data and updated fault status data (response data after command execution) are acquired as communication and control test data.

[0086] The above implementation method drives the virtual power model to output initial electrical quantity data. This initial electrical quantity data is then sent to the logic control model via a first data channel. The initial electrical quantity data is processed by control algorithms and fault protection logic to obtain pulse drive signals and fault protection signals output by the logic control model. The pulse drive signals and fault protection signals are then sent to the virtual power model via a second data channel. The pulse drive signals and fault protection signals are then processed to update the on / off states of switching devices to obtain adjusted electrical quantity data output by the virtual power model. The pulse drive signals, fault protection signals, adjusted electrical quantity data, and initial electrical quantity data are used as operational verification data. The above scheme obtains a complete dataset generated by closed-loop iteration in a purely digital environment. The pulse drive signal in this dataset is used to characterize the correctness of the PWM (Pulse Width Modulation) waveform generated by the control algorithm, the fault protection signal is used to characterize the accuracy of the fault detection logic triggering, and the difference between the adjusted electrical quantity data and the initial electrical quantity data is used to characterize the adjustment accuracy and dynamic response characteristics of the control algorithm. Therefore, the performance of the control algorithm and the reliability of fault protection can be quantitatively evaluated without any physical circuit board. The driving virtual power model outputs an initial analog electrical signal, which is transmitted to the signal board through the analog output channel. The initial analog electrical signal undergoes differential, filtering, and amplitude scaling processing to obtain the signal... The standard analog signal output from the board is transmitted to the control board via a sampling signal channel. The standard analog signal undergoes analog-to-digital conversion and code execution processing to obtain an analog pulse drive signal generated by the control board based on the programmed real-time running control code. Simultaneously, the standard analog signal is used by a comparator on the signal board to generate a trigger signal, which is then transmitted to the control board to generate fault protection signals such as fault feedback and status latching. The analog pulse drive signal is transmitted to the virtual power model via a drive signal feedback channel. The fault protection signal is also transmitted back to the virtual power model via a control execution signal feedback channel. The returned signal undergoes switch state update processing to obtain the updated electrical signal output by the virtual power model. The standard analog signal, analog pulse drive signal, fault protection signal, initial analog electrical signal, and updated electrical signal are used as single-board functional test data.The comparison results between the standard analog signal and the initial analog electrical signal in the above scheme are used to characterize the actual accuracy and linearity of the signal board sampling and conditioning circuit; the comparison results between the analog pulse drive signal and the expected drive waveform are used to characterize the correctness of the control board code execution and the fidelity of the drive signal transmission; the comparison results between the fault protection signal and the preset fault injection conditions are used to characterize the response time and correctness of the hardware protection logic such as the CPLD; and the updated electrical signal is used to characterize the response capability of the virtual power model to the PWM drive signal. By acquiring the above data, the hardware performance of the physical signal board and control board can be comprehensively and quantitatively evaluated without high-voltage power or connection to the main power circuit, thereby improving the efficiency and safety of the test; and according to the preset... A virtual power model is driven by power grid operating parameters to acquire real-time electrical quantity data and real-time fault status data output by the virtual power model. This real-time electrical quantity data and real-time fault status data are uploaded to a host computer controller via an operating status data channel. The uploaded data undergoes governance strategy program execution processing to acquire control commands output by the host computer controller. Based on the control command data channel, the control commands are sent to the virtual power model, and parameter adjustments and status updates are performed on the control commands to acquire updated electrical quantity data and updated fault status data output by the virtual power model. The control commands, real-time electrical quantity data, real-time fault status data, updated electrical quantity data, and updated fault status data are used as communication and control test data. In the above scheme, the comparison results of the real-time electrical quantity data and the updated electrical quantity data are used to characterize the response effect of the host computer governance strategy to the power grid operating conditions. The comparison results of the control commands and the changes in operating conditions are used to characterize the correctness of the governance strategy triggering logic. The comparison results of the real-time fault status data and the updated fault status data are used to characterize the reliability of the fault ride-through and recovery logic. Thus, without the need to build a real distribution network physical environment, extreme operating conditions can be reproduced with one click and the consistency of the host computer communication protocol and the correctness of the control logic can be quantitatively evaluated by simply modifying the simulation parameters, thereby improving the efficiency of the test.

[0087] In this embodiment, the multi-mode test data includes operational verification data, single-board functional test data, and communication and control test data; step 105 includes: Step 1051: When the test mode is the control logic test mode, obtain the first comparison result between the real-time electrical quantity data in the operation verification data and the preset control performance index threshold. Step 1052: Obtain the second comparison result between the fault protection signal in the operation verification data and the preset fault protection threshold, so as to obtain the control logic function test result of the power electronic device under test based on the first comparison result and the second comparison result; Step 1053: When the test mode is the single-board function test mode, obtain the third comparison result of the standard analog signal and the initial analog electrical signal in the single-board function test data; Step 1054: Obtain the waveform comparison result between the preset pulse drive signal and the simulated pulse drive signal in the single-board functional test data; Step 1055: Obtain the signal comparison result between the preset fault protection signal and the fault protection signal in the single-board function test data, so as to obtain the single-board function test result of the power electronic device under test according to the third comparison result, the waveform comparison result and the signal comparison result; Step 1056: When the test mode is the communication and control test mode, the control logic is verified based on the control instructions, real-time electrical quantity data, real-time fault status data, updated electrical quantity data and updated fault status data in the communication and control test data, so as to obtain the communication and control function test results of the power electronic device under test. Step 1057: Based on the control logic function test results, the single-board function test results, and the communication and control function test results, obtain the multi-level test results of the power electronic device under test.

[0088] This embodiment acquires the collected operational verification data, which includes initial electrical quantity data, adjusted electrical quantity data, pulse drive signals, and fault protection signals. It also extracts real-time electrical quantity data (mainly adjusted electrical quantity data, such as DC bus total voltage, grid-side current, output power, etc.) from the operational verification data and compares it with the control accuracy range required by the device design specifications to obtain a first comparison result.

[0089] The control accuracy range is the basis for verifying the effectiveness of the control algorithm. This embodiment compares various indicators in the real-time electrical quantity data (such as voltage stability, current tracking, and dynamic response characteristics) with preset requirements. If all indicators meet the control accuracy requirements, the first comparison result is qualified; if any indicator fails to meet the requirements, the first comparison result is unqualified, and the out-of-tolerance item is recorded.

[0090] This embodiment acquires a fault protection signal (including a trigger time, a fault word, and a protection action type) in operation verification data, and compares it with a preset fault protection threshold to obtain a second comparison result. The preset fault protection threshold is preset according to the technical specifications of the device. If the device needs to have protection functions such as overvoltage, overcurrent, over-temperature, and over-frequency, an electrical quantity value capable of triggering protection can be set in the power model, or the preset fault protection threshold can be adjusted, so as to verify the accuracy of the fault detection logic. During the test process, this embodiment actively injects fault conditions by modifying the electrical quantity value in the virtual power model or adjusting the fault protection threshold. This embodiment monitors the output of the fault protection signal: if the fault protection signal is triggered after fault injection (for example, the device model shuts down immediately), and the fault word is consistent with the preset fault type, the second comparison result is qualified; if the protection is not triggered after fault injection, or the fault word is incorrect, the second comparison result is unqualified, and the abnormal item is recorded. This embodiment obtains a control logic function test result of the power electronic device under test according to the first comparison result and the second comparison result: if both the first comparison result and the second comparison result are qualified, the control logic function test result is qualified; if any comparison result is unqualified, the control logic function test result is unqualified, and a corresponding error report is output. At this time, according to the progressive principle of multi-level testing, subsequent single-board function tests and communication and control tests are not executed, and the final result is directly output as that the control logic test is unqualified.

[0091] This embodiment acquires collected single-board function test data, which includes an initial analog electrical signal, a standard analog signal, an analog pulse drive signal, a fault protection signal, and an updated electrical signal, and compares the standard analog signal with the initial analog electrical signal to obtain a third comparison result. Specifically, this embodiment takes the initial analog electrical signal as a reference reference value, and calculates the deviation between the standard analog signal and the initial analog electrical signal. The deviation reflects the accuracy and linearity of the sampling conditioning circuit of the signal board. If the deviation is within the allowable range of the device design, the third comparison result is qualified; otherwise, it is unqualified, and the channel with excessive error is recorded.

[0092] This embodiment compares the analog pulse drive signal (the PWM waveform actually output by the control board) in the single-board function test data with an expected waveform theoretically calculated according to the control algorithm, so as to obtain a waveform comparison result. The parameters of the expected waveform (such as duty cycle, frequency, and dead time) are derived from the theoretical output of the control algorithm under given working conditions. This embodiment extracts the actual waveform parameters of the analog pulse drive signal, and compares them with the expected values item by item. If all waveform parameters meet the design requirements (for example, the duty cycle error, frequency error, and dead time are all within the allowable range), the waveform comparison result is qualified; otherwise, it is unqualified, and the deviation item is recorded.

[0093] In this embodiment, the fault protection signal (the protection signal actually output by the CPLD) in the single-board function test data is compared with the expected protection action (preset according to the hardware fault injection condition) to obtain a signal comparison result. In this embodiment, a simulated fault (for example, an overcurrent signal higher than a threshold is injected) is injected into the hardware fault detection module of the signal board through the IO board. The expected protection actions include: the CPLD shall block the PWM drive signal in a very short time and light the fault indicator on the signal board. In this embodiment, the level change of the fault protection signal and the PWM enable signal are monitored by controlling the execution signal return channel: if the action time and blocking effect of the actual fault protection signal are consistent with expectations, the signal comparison result is qualified; if no fault protection signal is detected, or the action time exceeds the expectation, or the PWM is not enabled, the signal comparison result is unqualified, and the abnormal situation is recorded; in this embodiment, according to the third comparison result, the waveform comparison result and the signal comparison result, the single-board function test result of the power electronic device to be tested is obtained: if all of the third comparison result, the waveform comparison result and the signal comparison result are qualified, the single-board function test result is qualified; if any comparison result is unqualified, the single-board function test result is unqualified, and a corresponding single-board error report is output. At this time, according to the progressive principle, the communication and control test will not be executed, and the final result is directly output as that the single-board function test is unqualified.

[0094] This embodiment acquires the collected communication and control test data, which includes control instructions, real-time electrical quantity data, real-time fault state data, updated electrical quantity data, and updated fault state data. In this embodiment, control logic verification is performed based on these data to obtain the communication and control function test result of the power electronic device to be tested. Specifically, this embodiment checks whether the data interaction between the upper computer controller and the virtual power model conforms to the preset communication protocol specification. It should be noted that a two-way communication point table needs to be configured, and the data is bound to the IO channel number or the register memory address in a one-to-one manner to ensure the accuracy of data transmission; meanwhile, periodic transmission and event-triggered supplementary transmission are supported. This embodiment counts the communication success rate, end-to-end delay, and data integrity (such as the correctness of the check code), and compares them with the preset requirements. If the requirements are met, the communication protocol consistency verification result is qualified; otherwise, it is unqualified, and the abnormal frame or timeout event is recorded.

[0095] This embodiment verifies whether the host computer controller executes the expected strategy based on preset power grid operating parameters (such as low voltage at the end, heavy overload in the distribution area, short-term overload, power grid imbalance, etc.). Taking a flexible DC voltage regulator as an example, when the voltage at the end is too low, a low voltage mitigation strategy is activated, and the power flow of the device is directed from the beginning of the power grid to the end to raise the voltage; when the voltage at the end is too high, a high voltage mitigation strategy is activated, and the power flow is directed from the end to the beginning to lower the voltage; when a large power grid imbalance is detected, a phase-by-phase control algorithm is activated to restore the imbalance to normal.

[0096] Based on the above logic, this embodiment checks whether the host computer generates correct control commands under preset operating conditions, and whether the updated electrical quantity data changes as expected (e.g., voltage returns to the normal range, imbalance decreases). Simultaneously, it checks whether the host computer issues fault reset or shutdown commands when fault status data changes (e.g., fault word is not 0), and whether the updated fault status data changes as expected.

[0097] If all governance strategies under the preset operating conditions are correctly triggered and the execution results meet expectations, the control logic correctness verification result is qualified; otherwise, it is unqualified, and the operating conditions that did not respond correctly and the reasons are recorded.

[0098] If both the communication protocol consistency and the control logic correctness are qualified, the communication and control function test result is qualified; if either fails, the communication and control function test result is unqualified, and the corresponding host computer error report is output.

[0099] This embodiment uses a progressive logic synthesis approach to determine the multi-level test results of the power electronic device under test based on the control logic function test results, the single-board function test results, and the communication and control function test results. If the control logic function test result is unqualified, the final multi-level test result is a control logic test failure, and a corresponding error report is output. If the control logic function test result is qualified, but the single-board function test result is unqualified, the final multi-level test result is a single-board function test failure, and a corresponding single-board error report is output. If the control logic function test result is qualified, the single-board function test result is qualified, and the communication and control function test results are qualified, the final multi-level test result is an overall qualified result. The final multi-level test results, as well as the intermediate comparison data and error reports at each stage, are recorded for subsequent review and traceability.

[0100] The above implementation method obtains a first comparison result between real-time electrical quantity data in the operation verification data and a preset control performance index threshold; obtains a second comparison result between the fault protection signal in the operation verification data and a preset fault protection threshold; performs a logical AND operation on the first and second comparison results to obtain control logic function test results characterizing the accuracy of the control algorithm and the fault protection logic of the power electronic device under test; obtains a third comparison result between the standard analog signal and the initial analog electrical signal in the single-board function test data; obtains a waveform comparison result between the preset pulse drive signal and the analog pulse drive signal in the single-board function test data; obtains a signal comparison result between the preset fault protection signal and the fault protection signal in the single-board function test data; and performs a logical AND operation on the third comparison result, the waveform comparison result, and the signal comparison result to obtain a table. The test results assess the single-board function of the signal board, including sampling and conditioning accuracy, correct code execution, and hardware protection reliability. It also acquires control commands, real-time electrical quantity data, real-time fault status data, updated electrical quantity data, and updated fault status data from the communication and control test data. This data undergoes control logic verification, including verifying whether communication delay exceeds a preset threshold, whether the triggering and execution of mitigation strategies match preset operating conditions, and whether the fault recovery sequence meets expectations. This yields communication and control function test results that characterize the consistency of the communication protocol and the correctness of the control logic. Finally, it performs comprehensive judgment processing on the control logic function test results, single-board function test results, and communication and control function test results to obtain multi-level test results that characterize the overall pass / fail status of the power electronic device under test, thereby improving the overall testing efficiency of the device.

[0101] Reference Figure 4 This embodiment also discloses a multi-level testing system for power electronic devices, including a model building module 401, a pattern matching module 402, a channel building module 403, a data acquisition module 404, and a multi-level testing module 405; The model building module 401 is used to build a virtual power model and a logic control model corresponding to the power electronic device under test based on the main power topology and real-time operation control logic of the power electronic device under test. The pattern matching module 402 is used to match the test mode of the power electronic device under test according to the structural type of the power electronic device under test. The channel construction module 403 is used to construct, according to the test mode, a closed-loop data channel between the virtual power model and the logic control model, a single-board signal channel between the power electronic device under test and the virtual power model, or a host computer signal channel between the power electronic device under test and the virtual power model; The data acquisition module 404 is used to drive the virtual power model and the logic control model to acquire single-mode test data output by the power electronic device under test according to the test mode, the closed-loop data channel, the single-board signal channel or the host computer signal channel. The multi-level test module 405 is used to obtain the multi-level test results of the power electronic device under test based on the single-mode test data and the test mode.

[0102] In this first embodiment, the model building module 401 includes a power model unit and a logic model unit; The power model unit is used to obtain the main power topology of the power electronic device under test, and deploy the main power topology in the first computing resource within the preset simulation platform to obtain the virtual power model of the power electronic device under test. The logic model unit is used to acquire the real-time operation control logic of the power electronic device under test, and deploy the real-time operation control logic in the second computing resource within the simulation platform to obtain the logic control model of the power electronic device under test; wherein, the real-time operation control logic includes control logic and fault protection logic.

[0103] This embodiment discloses a multi-level testing method and system for power electronic devices. Addressing the problems of existing technologies such as reliance on physical hardware, high risks associated with high-voltage testing, long debugging cycles, high manpower and equipment costs, and asynchronous software and hardware development, it provides a hardware-in-the-loop simulation method based on the RT-LAB platform. This method enables rapid verification of DSP control algorithms without requiring the construction of a complete power hardware platform or high-voltage testing. Furthermore, it achieves fault protection function verification and efficient debugging of the host computer control code through a combined digital analog simulation model, thereby improving the verification efficiency of engineering code and mitigation strategies, reducing experimental risks and development costs, and shortening the overall device development cycle. Simultaneously, even before the entire power control device is assembled, the IO boards configured by RTLAB can be connected to the actual signal board and control board to verify signal acquisition, drive protection, and other functions on the physical PCB, further improving the overall testing efficiency of the device.

[0104] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A multi-stage testing method for power electronic devices, characterized in that, include: Based on the main power topology and real-time operation control logic of the power electronic device under test, construct the virtual power model and logic control model corresponding to the power electronic device under test; Match the test mode of the power electronic device under test according to the structural type of the power electronic device under test; Construct a closed-loop data channel between the virtual power model and the logic control model, a single-board signal channel between the power electronic device under test and the virtual power model, or a host computer signal channel between the power electronic device under test and the virtual power model according to the test mode. Drive the virtual power model and the logic control model to obtain single-mode test data output by the power electronic device under test according to the test mode, the closed-loop data channel, the single-board signal channel or the host computer signal channel; Based on the single-mode test data and the test mode, obtain the multi-level test results of the power electronic device under test.

2. The multi-stage testing method for power electronic devices according to claim 1, characterized in that, The process of constructing a virtual power model and logic control model corresponding to the power electronic device under test (DUT) based on its main power topology and real-time operation control logic includes: The main power topology of the power electronic device under test is obtained, and the main power topology is deployed in the first computing resource within a preset simulation platform to obtain a virtual power model of the power electronic device under test. The real-time operation control logic of the power electronic device under test is obtained, and the real-time operation control logic is deployed in the second computing resource within the simulation platform to obtain the logic control model of the power electronic device under test; wherein, the real-time operation control logic includes control logic and fault protection logic.

3. The multi-stage testing method for power electronic devices according to claim 2, characterized in that, The step of matching the test mode of the power electronic device under test according to the structural type of the power electronic device under test includes: When it is determined that the power electronic device under test does not have a physical board based on the structural type of the power electronic device under test, the test mode of the power electronic device under test is determined to be the control logic test mode. When it is determined from the structure type that the power electronic device under test has a physical board but no host computer controller, the test mode of the power electronic device under test is determined to be the single board function test mode. When it is determined that the power electronic device under test has a host computer controller based on the structure type, the test mode of the power electronic device under test is determined to be the communication and control test mode.

4. The multi-stage testing method for power electronic devices according to claim 3, characterized in that, The construction of a closed-loop data channel between the virtual power model and the logic control model, a single-board signal channel between the power electronic device under test and the virtual power model, and a host computer signal channel between the power electronic device under test or the virtual power model according to the test mode includes: When the test mode is the control logic test mode, a first data channel from the virtual power model to the logic control model and a second data channel from the logic control model to the virtual power model are established in the simulation platform; wherein, the first data channel and the second data channel are used as closed-loop data channels; When the test mode is the single-board function test mode, the signal board and control board of the power electronic device under test are acquired, and the analog output channel from the virtual power model to the signal board, the sampling signal channel from the signal board to the control board, the drive signal feedback channel from the control board to the virtual power model, and the control execution signal feedback channel from the control board to the virtual power model are constructed; wherein, the analog output channel, the sampling signal channel, the drive signal feedback channel, and the control execution signal feedback channel are used as the single-board signal channels; When the test mode is the communication and control test mode, the host computer controller of the power electronic device under test is obtained, and the operating status data channel from the virtual power model to the host computer controller and the control command data channel from the host computer controller to the virtual power model are constructed; wherein, the operating status data channel and the control command data channel are used as host computer signal channels.

5. The multi-stage testing method for power electronic devices according to claim 4, characterized in that, The driving of the virtual power model and the logic control model, to acquire single-mode test data output by the power electronic device under test according to the test mode, the closed-loop data channel, the single-board signal channel, or the host computer signal channel, includes: When the test mode is the control logic test mode, the virtual power model is driven to output initial electrical quantity data, and the initial electrical quantity data is sent to the logic control model according to the first data channel, so that the logic control model outputs pulse drive signal and fault protection signal; The pulse drive signal and the fault protection signal are sent to the virtual power model through the second data channel, so that the virtual power model outputs adjusted electrical quantity data according to the pulse drive signal and the fault protection signal; The pulse drive signal, the fault protection signal, the adjusted electrical quantity data, and the initial electrical quantity data are used as the operation verification data of the power electronic device under test, and the operation verification data are used as the single-mode test data of the power electronic device under test in the control logic test mode.

6. The multi-stage testing method for power electronic devices according to claim 4, characterized in that, The driving of the virtual power model and the logic control model, to acquire single-mode test data output by the power electronic device under test according to the test mode, the closed-loop data channel, the single-board signal channel, or the host computer signal channel, includes: When the test mode is the single-board function test mode, the virtual power model is driven to output an initial analog electrical signal, and the initial analog electrical signal is transmitted to the signal board through the analog output channel, so that the signal board outputs a standard analog signal corresponding to the initial analog electrical signal, and generates a trigger signal corresponding to the standard analog signal according to the comparator on the signal board; The standard analog signal and the trigger signal are transmitted to the control board through the sampling signal channel, so that the control board processes the standard analog signal according to the programmed real-time operation control code to generate an analog pulse drive signal and processes the trigger signal according to the real-time operation control code to generate a fault protection signal; wherein, the fault protection signal includes a fault feedback signal and a status latch signal; The analog pulse drive signal is transmitted to the virtual power model through the drive signal feedback channel; The fault protection signal is transmitted back to the virtual power model through the control execution signal feedback channel to obtain the updated electrical signal output by the virtual power model; The standard analog signal, the analog pulse drive signal, the fault protection signal, the initial analog electrical signal, and the updated electrical signal are used as the single-board function test data of the power electronic device under test, so as to use the single-board function test data as the single-mode test data of the power electronic device under test in the single-board function test mode.

7. The multi-stage testing method for power electronic devices according to claim 4, characterized in that, The driving of the virtual power model and the logic control model, to acquire single-mode test data output by the power electronic device under test according to the test mode, the closed-loop data channel, the single-board signal channel, or the host computer signal channel, includes: When the test mode is the communication and control test mode, the virtual power model is driven according to the preset power grid operating parameters to obtain the real-time electrical quantity data and real-time fault status data output by the virtual power model. The real-time electrical quantity data and the real-time fault status data are uploaded to the host computer controller through the operating status data channel, so that the host computer controller can output control commands. The control command is sent to the virtual power model through the control command data channel to obtain the updated electrical quantity data and updated fault status data output by the virtual power model. The control command, the real-time electrical quantity data, the real-time fault status data, the updated electrical quantity data, and the updated fault status data are used as the communication and control test data of the power electronic device under test, so as to use the communication and control test data as the single-mode test data of the power electronic device under test in the communication and control test mode.

8. A multi-stage testing method for power electronic devices according to any one of claims 5-7, characterized in that, The step of obtaining multi-level test results for the power electronic device under test based on the single-mode test data and the test mode includes: When the test mode is the control logic test mode, the first comparison result between the real-time electrical quantity data in the operation verification data and the preset control performance index threshold is obtained; The second comparison result between the fault protection signal in the operation verification data and the preset fault protection threshold is obtained, so as to obtain the control logic function test result of the power electronic device under test based on the first comparison result and the second comparison result; When the test mode is the single-board function test mode, the third comparison result between the standard analog signal and the initial analog electrical signal in the single-board function test data is obtained; Obtain the waveform comparison results between the preset pulse drive signal and the simulated pulse drive signal in the single-board functional test data; The signal comparison results between the preset fault protection signal and the fault protection signal in the single-board function test data are obtained, so as to obtain the single-board function test results of the power electronic device under test according to the third comparison result, the waveform comparison result and the signal comparison result. When the test mode is communication and control test mode, the control logic is verified based on the control commands, real-time electrical quantity data, real-time fault status data, updated electrical quantity data and updated fault status data in the communication and control test data, so as to obtain the test results of the communication and control function of the power electronic device under test. Based on the test results of the control logic function, the test results of the single board function, and the test results of the communication and control function, the multi-level test results of the power electronic device under test are obtained.

9. A multi-level testing system for power electronic devices, characterized in that, It includes a model building module, a pattern matching module, a channel setup module, a data acquisition module, and a multi-level testing module; The model building module is used to construct the virtual power model and logic control model corresponding to the power electronic device under test based on the main power topology and real-time operation control logic of the power electronic device under test; The pattern matching module is used to match the test mode of the power electronic device under test according to the structural type of the power electronic device under test. The channel construction module is used to construct a closed-loop data channel between the virtual power model and the logic control model, a single-board signal channel between the power electronic device under test and the virtual power model, or a host computer signal channel between the power electronic device under test and the virtual power model according to the test mode. The data acquisition module is used to drive the virtual power model and the logic control model to acquire single-mode test data output by the power electronic device under test according to the test mode, the closed-loop data channel, the single-board signal channel or the host computer signal channel. The multi-level testing module is used to obtain the multi-level test results of the power electronic device under test based on the single-mode test data and the test mode.

10. A multi-level testing system for power electronic devices according to claim 9, characterized in that, The model building module includes a power model unit and a logic model unit; The power model unit is used to obtain the main power topology of the power electronic device under test, and deploy the main power topology in the first computing resource within the preset simulation platform to obtain the virtual power model of the power electronic device under test. The logic model unit is used to acquire the real-time operation control logic of the power electronic device under test, and deploy the real-time operation control logic in the second computing resource within the simulation platform to obtain the logic control model of the power electronic device under test; wherein, the real-time operation control logic includes control logic and fault protection logic.

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