Satellite electrical overall intelligent design and verification method

Abstract

The application provides a satellite electric system digital design and verification method, by constructing low-frequency interface specification, interface matching rule and process feasibility rule for digital verification; based on the low-frequency interface specification, performing interface attribute compliance verification on device low-frequency interface data, generating first-level feedback data to correct interface data errors; based on the interface matching rule and process feasibility rule, performing design correctness verification on electric system design results, generating second-level feedback data to correct design errors; performing consistency verification on on-off test data and insulation test data generated by product physical testing and the electric system design results, generating third-level feedback data to identify inconsistent items of the product and the design. In this way, the application improves the electric system design efficiency, ensures reasonable electric system design, matched interface design, topology optimization, and reliable product design and development.

Description

Technical Field

[0001] This invention relates to the field of spacecraft electrical system design technology, specifically to a satellite electrical system digital design and verification method. Background Technology

[0002] Spacecraft electrical system design refers to the design of low-frequency electrical systems such as power supply, telemetry, remote control, and bus between active devices within a spacecraft. This includes the design of power supply electrical channels, telemetry and remote control signal channels, bus design such as matrix Ethernet, and the design of the overall electrical characteristics.

[0003] The overall electrical design involves all active devices within the spacecraft. The correctness of the overall electrical characteristics design affects the safety of the spacecraft, and the overall electrical structure and topology design affects the layout and configuration of the spacecraft. Therefore, the effectiveness of the overall electrical design planning, the rationality of the topology, and the correctness of the channel design directly affect the reliability and safety of the spacecraft.

[0004] Large spacecraft are equipped with hundreds of active devices, involving tens of thousands of low-frequency interfaces and electrical systems. Because spacecraft development involves collaboration among multiple departments and personnel, electrical interface design is completed by dozens of designers from different specialties. Interface data is diverse, and verifying its standardization and accuracy is a massive undertaking. Different types of channels, such as electrical channels, telemetry and remote control channels, and bus channels, are designed by designers from various specialties. These different channels have cross-coupling interfaces, and the channel design directly affects the topology of the overall electrical system design, thus impacting subsequent product assembly and testing.

[0005] Traditional electrical overall design methods (such as) Figure 1 As shown, the following problems exist: (1) The electrical system designer manually reviews the low-frequency interface of the active equipment based on experience. After finding the definition error or ambiguity, the designer of the single equipment is given feedback and the low-frequency interface data is changed. This method of manual review involves a large amount of data and there are many problems that cannot be found in the first review, resulting in multiple iterations in the electrical system design process. (2) The electrical, telemetry and remote control and bus channel design are completed separately by the designers. During the electrical characteristic design of the overall electrical system, if serious channel coupling is found, the designer manually analyzes and locates the channel coupling point, negotiates with the mechanical characteristic designer to formulate a decoupling solution, and then notifies the relevant professional designers to complete the changes. The overall electrical system then completes the modified design. This design method has many iterations and affects the design progress. (3) After the electrical characteristics design is completed, the basic verification is completed using design software, and then the overall electrical design and low-frequency interface data of the equipment are manually verified. This process is time-consuming and carries the risk of human negligence. (4) After the product is manufactured, the amount of data obtained from the electrical performance index test is huge. The test data of the automatic tester and the electrical characteristic design data are not in one-to-one correspondence. The manual identification of the data is difficult. Therefore, the data interpretation can only interpret the test conclusion of the automatic tester. There is no technical means to feed the test data back to the design data for detailed interpretation, which poses a risk of misjudgment and omission. Summary of the Invention

[0006] To improve the overall design efficiency of satellite electrical systems and ensure reasonable overall design, interface matching, topology optimization, and consistency between product status and design status, this invention proposes a satellite electrical system digital intelligent design and verification method and system based on electromechanical collaboration, interface standardization, and three-loop feedback.

[0007] To achieve the above-mentioned technical effects, this invention provides a satellite electrical overall digital design and verification method, including the following steps: Construct a rule base for digital verification, which includes low-frequency interface specifications, interface matching rules, and process feasibility rules; Based on the aforementioned low-frequency interface specification, the low-frequency interface data of the device is subjected to interface attribute compliance verification, and first-level feedback data is generated to correct interface data errors. Based on the interface matching rules and process feasibility rules, the overall electrical design results are verified for design correctness, and secondary feedback data is generated to correct design errors. The continuity test data and insulation test data generated from the actual product testing are compared with the overall electrical design results to perform consistency verification, and three-level feedback data is generated to identify inconsistencies between the product and the design.

[0008] Furthermore, the construction of the rule base for digital verification specifically includes: Based on the principle of data parsing, the interface attribute items to be verified in the low-frequency interface of the device are defined with their compilation specifications to construct the low-frequency interface specification; wherein, the interface attribute items include signal name, destination contact, polarity, path number, shielding and twisted pair; Establish rules for determining the topology and path of cable networks that reflect the relationship between mechanical and electrical characteristics, as well as rules that reflect the limitations of cross-disciplinary information interaction, and combine these with rules for matching the attributes between the low-frequency interfaces of equipment and the cable network to construct interface matching rules. Based on the matching relationship between conductor type and current flow, and the matching relationship between electrical connector type and conductor type, process feasibility rules are constructed.

[0009] Furthermore, the step of performing interface attribute compliance verification on the low-frequency interface data of the device based on the low-frequency interface specification, and generating first-level feedback data to correct interface data errors, specifically includes: Import the low-frequency interface data of the equipment into the low-frequency interface database of the equipment; The interface name standardization verification module is invoked to perform standardization verification on the signal name attributes of low-frequency interfaces and to perform consistency verification on the signal names between interconnected low-frequency interfaces. Call the destination contact rationality verification module to perform correctness verification on the destination contact attributes of the low-frequency interface; Call the shielded twisted pair compatibility verification module to perform standardization verification on the shielding and twisted pair attributes of each contact, and determine whether the shielding and twisted pair requirements of two interconnected and matched contacts are consistent. The verification results of each verification module are summarized to generate primary feedback data.

[0010] Furthermore, the step of performing design correctness verification on the overall electrical design results based on the interface matching rules and process feasibility rules, and generating secondary feedback data to correct design errors, specifically includes: Import the overall electrical channel design results into the overall channel database. Perform polarity verification according to the rule that the positive and negative polarities of the low-frequency interface of the same device should be consistent with the positive and negative polarities of the overall channel. Perform path verification according to the rule that the path grouping of the low-frequency interface of the same device should be consistent with the overall path grouping relationship. Import the cable network connection table into the cable database. Use the low-frequency interface data of the equipment after first-level digital verification and the overall electrical channel design results as the benchmark database and the cable database as the comparison database. Perform consistency verification on the signal name, destination connection, twisted pair, and shielding attributes of the same connection in the two databases. The cable process rationality verification module is invoked to perform consistency verification on the matching relationship between conductor type and current flow, and the matching relationship between electrical connector type and conductor type, based on the pre-stored process data dictionary. Summarize the results of each verification and generate secondary feedback data.

[0011] Furthermore, the continuity test data and insulation test data generated from the actual product testing are compared with the overall electrical design results for consistency verification, generating three-level feedback data to identify inconsistencies between the product and the design. Specifically, this includes: Import the continuity test data and insulation test data of the cable network into the test result database and analyze them; The parsed continuity test data and insulation test data are automatically filled into the corresponding cable network connection table design result data to achieve structured reorganization of test data and design data; Based on preset electrical performance criteria, the system automatically determines the qualification of each piece of data after reassembly and generates three-level feedback data, which is a consistency report between the test object and the design.

[0012] Furthermore, the preset electrical performance criteria are as follows: a conduction resistance value of less than 5Ω is considered qualified, and an insulation resistance value of greater than 1MΩ is considered qualified.

[0013] On the other hand, the present invention also provides a satellite electrical overall digital design and verification system, comprising: The rule base construction module is used to build a rule base for digital verification, which includes low-frequency interface specifications, interface matching rules, and process feasibility rules. The Level 1 Feedback Report Output Module is used to perform interface attribute compliance verification on the low-frequency interface data of the device based on the low-frequency interface specification, and generate Level 1 feedback data to correct interface data errors. The secondary feedback report output module is used to perform design correctness verification on the overall electrical design results based on the interface matching rules and process feasibility rules, and generate secondary feedback data to correct design errors. The three-level feedback report output module is used to perform consistency verification between the continuity test data and insulation test data generated from the physical product test and the overall electrical design results, and generate three-level feedback data to identify inconsistencies between the product and the design.

[0014] The satellite electrical overall digital design and verification method described in this invention constructs electromechanical joint design rules and low-frequency interface specifications, and performs first-level, second-level, and third-level digital closed-loop feedback verification at the initial design stage, after design completion, and after product testing, respectively. Thus, by formulating electromechanical joint design specifications and prohibitions, and top-level planning of equipment partitioning for electrical channels, telemetry and remote control channels, and bus channels, this invention optimizes the overall electrical topology from the source, solving the problem of iterative electromechanical design in traditional methods. By standardizing low-frequency interface naming rules and the compilation rules for low-frequency interface data sheets, it lays the foundation for subsequent digital automatic verification. Through the three-level closed-loop feedback verification mechanism, the first-level closed loop identifies divergence points after verifying the initial design, completes information iteration of small loops, narrows the iteration loop, optimizes the design process, and saves design time. The second-level closed loop digitally verifies the overall electrical design results with the satellite's low-frequency interfaces. The third-level closed loop comprehensively compares and interprets the design results with the test results of the physical product through digital means.

[0015] Experimental results show that the number of iterations in this invention is significantly reduced, decreasing by more than two-thirds, and the overall design efficiency is improved by approximately 90%. The three-loop feedback electronic overall digital design and verification system improves the efficiency of electronic overall design correctness verification by 95%, the efficiency of product test data and state consistency verification by 90%, the data interpretation rate to 100%, and the design accuracy to 100%. This method can be widely used to guide the development of other spacecraft. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the traditional electrical overall design and development process; Figure 2 This is a schematic diagram of the development process of the satellite electrical overall digital design and verification method described in this invention; Figure 3 A flowchart illustrating the steps of the satellite electrical overall digital design and verification method provided in an embodiment of the present invention; Figure 4 This is a flowchart illustrating the first-level feedback of the satellite electrical overall digital design and verification method provided in an embodiment of the present invention; Figure 5 This is a flowchart illustrating the secondary feedback of the satellite electrical overall digital design and verification method according to an embodiment of the present invention; Figure 6 This is a flowchart illustrating the three-level feedback of the satellite electrical overall digital design and verification method provided in an embodiment of the present invention; Figure 7 A structural block diagram of the satellite electrical overall digital design and verification system provided in another embodiment of the present invention; Figure 8 This is a functional block diagram of the overall digital design and verification system of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0018] It should be noted that references to "an embodiment," "embodiment," "example embodiment," etc., in this specification refer to the described embodiment including specific features, structures, or characteristics, but not every embodiment must include these specific features, structures, or characteristics. Furthermore, such expressions do not refer to the same embodiment. Moreover, when describing specific features, structures, or characteristics in conjunction with embodiments, whether or not explicitly described, it is indicated that incorporating such features, structures, or characteristics into other embodiments is within the knowledge of those skilled in the art.

[0019] Furthermore, certain terms are used in the specification and subsequent claims to refer to specific components or parts. Those skilled in the art will understand that manufacturers may use different names or terms to refer to the same component or part. This specification and subsequent claims do not distinguish components or parts by differences in name, but rather by differences in function. The terms "comprising" and "including" used throughout the specification and subsequent claims are open-ended and should be interpreted as "including but not limited to." Additionally, the term "connection" here includes any direct and indirect electrical connection means. Indirect electrical connection means include connections made through other means.

[0020] Figure 3 This invention illustrates a satellite electrical overall digital design and verification method according to an embodiment of the present invention, comprising the following steps: S101: Construct a rule base for digital verification, the rule base including low-frequency interface specifications, interface matching rules, and process feasibility rules.

[0021] S102: Based on the low-frequency interface specification, perform interface attribute compliance verification on the low-frequency interface data of the device, and generate first-level feedback data to correct interface data errors.

[0022] S103: Based on the interface matching rules and process feasibility rules, perform design correctness verification on the overall electrical design results and generate secondary feedback data to correct design errors.

[0023] S104: Perform consistency verification between the continuity test data and insulation test data generated from the actual product testing and the overall electrical design results, and generate three-level feedback data to identify inconsistencies between the product and the design.

[0024] The following section uses a spacecraft as an example to illustrate the design and verification process using the method described in this embodiment, and provides a detailed explanation of each step.

[0025] In step S101, a rule base for digital verification is constructed, including the construction of electromechanical joint design rules and the formulation of low-frequency interface specifications; specifically, step S101 includes: This document establishes cable network topology and path determination rules reflecting the relationship between mechanical and electrical characteristics, as well as rules reflecting restrictions on cross-disciplinary information interaction. It also incorporates rules for matching the attributes of low-frequency interfaces of equipment with the cable network to construct interface matching rules. Furthermore, it establishes process feasibility rules based on the matching relationship between conductor type and current flow, and between electrical connector type and conductor type. In the early stages of overall electrical design, in accordance with electromechanical joint design requirements, electrical, information, and mechanical routing designers collaborate to establish cable network topology and path determination rules reflecting the relationship between mechanical and electrical characteristics, as well as rules reflecting restrictions on cross-disciplinary information interaction. Specifically, it clarifies the prohibitions on cross-disciplinary information interaction and plans the topology of electrical and information channels. Equipment zoning is established according to the rule of grouping adjacent equipment. For equipment with differing groupings, the grouping is determined through collective consultation. For example, equipment A1 to A16 are north-side equipment, A17 to A30 are south-side equipment, and the grouping of B1 and B2 is ambiguous; after consultation, B1 and B2 are classified as north-side equipment.

[0026] Following the principle of data parsingability, the compilation specifications for the interface attribute items to be verified in the low-frequency interface of the equipment are defined to construct the low-frequency interface specification. These interface attribute items include signal name, destination contact, polarity, path number, shielding, and twisted pair. This embodiment specifically sets several electrical interface attributes according to the principles of precise, unique, unambiguous, and compliant with digital parsing requirements, and formulates compilation specifications for each attribute. The interface attribute items to be standardized include signal name, destination contact, polarity, path number, shielding, and twisted pair. In the early stages of project development, individual equipment designers are organized to disseminate the low-frequency interface specification, ensuring that all equipment designers uniformly follow this specification when compiling low-frequency interface data.

[0027] Figure 4 This embodiment illustrates the specific process of performing first-level digital verification using the method described herein. Step S102 is executed in the initial stage of the overall electrical design, before the design results are generated. Based on the low-frequency interface specification, it performs interface attribute compliance verification on the low-frequency interface data of the equipment, specifically including: S1021: Import the device's low-frequency interface data into the device's low-frequency interface database; the loading process completes preliminary verification of file format, etc.

[0028] S1022: Call the interface name standardization verification module to perform standardization verification on the signal name attributes of low-frequency interfaces, and perform consistency verification on the signal names between low-frequency interfaces that are interconnected.

[0029] S1023: Call the destination contact rationality verification module to perform correctness verification on the destination contact attributes of the low-frequency interface.

[0030] S1024: Call the shielded twisted pair matching verification module to perform standardization verification on the shielding and twisted pair attributes of each contact, and determine whether the shielding and twisted pair requirements of two interconnected and matched contacts are consistent.

[0031] S1025: Summarize the verification results of each verification module and generate primary feedback data. That is, based on the verification results of each module, assess the correctness of the low-frequency interface, summarize and generate primary feedback data, and feed back the information requiring changes to the individual device designer.

[0032] By identifying and correcting interface data standardization and matching errors in the early stages of overall electrical design through step S102, information iteration of small loops is completed, avoiding the introduction of original errors into subsequent design stages and significantly saving design time.

[0033] Figure 5 This embodiment illustrates the specific process of performing secondary digital verification using the method described herein. Step S103 is executed after the overall electrical design results are generated and before the product is put into physical production. Based on interface matching rules and process feasibility rules, it performs design correctness verification on the overall electrical design results, specifically including: S1031: Import the overall channel design results into the overall channel database, perform polarity verification according to the rule that the positive and negative polarities of the low-frequency interface of the same device should be consistent with the positive and negative polarities of the overall channel, and perform path verification according to the rule that the path grouping of the low-frequency interface of the same device should be consistent with the overall path grouping relationship.

[0034] The following table 1 serves as an example for illustration: Table 1:

[0035] As shown in Table 1, the overall channel design verification results indicate that the polarity of the five points on connector H-J1 is "positive" at the low-frequency interface of the device and "negative" in the overall channel, with opposite polarities at both locations. Therefore, the polarity verification result is "inconsistent." Points 3 and 4 of H-J1 belong to the same path (path number 5A) at the low-frequency interface, but their signal content within the overall channel includes devices B and C respectively, indicating they do not go to the same device. Therefore, the path verification result for points 3 and 4 is also "inconsistent." The overall channel design is iterated based on the correctness of the verification results.

[0036] S1032: Import the cable network connection table into the cable database. Using the low-frequency interface data of the equipment after first-level digital verification and the overall electrical channel design results as the benchmark database, and the cable database as the comparison database, perform consistency verification on the signal name, destination connection, twisted pair, and shielding attributes of the same connection in the two databases. In this step S1032, the cable network connection table is imported into the cable database, and the connection relationship is structured. An interface matching verification module is used, using the low-frequency interface of the equipment and the overall electrical channel as the benchmark database, and the cable database as the comparison database, to verify whether the attributes of the same connection are consistent in the two databases. The comparison attributes include: signal name, destination connection, twisted pair, shielding, remarks, voltage, and current consistency; specifically, the following table 2 is used as an example for explanation: Table 2:

[0037] As shown in Table 2, the electrical characteristic design correctness verification revealed inconsistencies in the signal names at point 6 of connector D-J1, the shielding requirements at points 6 and 7, the twisted pair requirements at point 8, and the destination contact at point 4. These inconsistencies were found within the overall electrical design and the low-frequency interface of the device, resulting in a verification result of "inconsistency." The electrical characteristic design was iterated based on the verification results.

[0038] S1033: Call the cable process rationality verification module to perform consistency verification on the matching relationship between conductor type and current flow, and the matching relationship between electrical connector type and conductor type, based on the pre-stored process data dictionary.

[0039] For a specific example, see Table 3: Table 3:

[0040] As shown in Table 3, for the process correctness verification, wire 26 cannot withstand 5A current, so the wire type and current matching is "mismatched"; wire 28 does not meet the assembly requirements of the 7-15TK type connector, so the wire type and connector model matching test result is inconsistent; the results of the remaining items meet the data dictionary requirements, and the result is "consistent".

[0041] S1034: Summarize the verification results and generate secondary feedback data. The secondary feedback performs a comprehensive digital verification of the overall electrical design results with the satellite's low-frequency interface data and cable process data, ensuring that the design is both correct and manufacturable.

[0042] Figure 6 This embodiment illustrates the specific process for performing three-level digital verification. Step S104 is executed after the physical production of the product is completed and testing is performed. It verifies the consistency of the continuity test data and insulation test data generated from the physical product testing with the overall electrical design results, specifically including: S1041: Import the continuity test data and insulation test data of the cable network into the test result database and parse them.

[0043] S1042: The parsed continuity test data and insulation test data are automatically filled into the corresponding cable network connection table design result data to achieve structured reorganization of test data and design data.

[0044] S1043: Based on preset electrical performance criteria, automatically determine the qualification of each piece of data after recombination and generate three-level feedback data, which is a consistency report between the test object and the design; wherein, the preset electrical performance criteria are: a conduction resistance value of less than 5Ω is considered qualified, and an insulation resistance value of more than 1MΩ is considered qualified.

[0045] Table 4 below shows an example of the continuity test interpretation results: Table 4:

[0046] Table 5 below shows an example of insulation test interpretation results: Table 5:

[0047] A consistency report between the test prototype and the design is generated as third-level feedback data. Step S104 enables refined and automated interpretation of massive amounts of test data, increasing the data interpretation rate to 100% and completely eliminating the risk of misjudgment and omission caused by simply interpreting test conclusions in the traditional method, thus ensuring a high degree of consistency between the final product and the design state.

[0048] Figure 2 The development process of the satellite electrical overall digital design and verification method based on this invention is illustrated. (and...) Figure 1 Compared to the traditional process shown, Figure 2 The bolded work items in the text represent the innovative aspects of this invention. This process, based on traditional development processes, introduces three digital closed-loop feedback nodes: Level 1 Feedback: After equipment design and low-frequency interface coding, but before electrical characteristic design, a low-frequency interface digital verification step is added. This step automatically verifies the equipment's low-frequency interface data based on pre-defined low-frequency interface naming and coding standards and electromechanical co-design standards. If the verification fails, it is directly fed back to the equipment design stage for correction, forming a small-loop information iteration to avoid introducing interface data errors into the subsequent overall electrical design stage.

[0049] Secondary feedback: After the electrical, information, and bus channel designs are completed and design results are generated, a digital verification step is added to the design results. This step comprehensively verifies the correctness and process rationality of the overall electrical design results. If the verification fails, it is fed back to the electrical characteristic design step for correction, ensuring the correctness and manufacturability of the design results.

[0050] Three-level feedback: After product manufacturing is completed and test results are generated, a digital interpretation step for the test results is added. This step verifies the consistency between the physical test data and the design data and automatically interprets the results. If the interpretation fails, it is fed back to the product manufacturing stage for investigation and correction, ensuring a high degree of consistency between the physical product state and the design state.

[0051] Through the aforementioned three-level closed-loop feedback mechanism, this invention reconstructs the traditional large-loop iterative process into a multi-node digital closed-loop verification process, realizing the forward shift of design error correction, the automation of design verification, and the refinement of test interpretation, thereby significantly improving development efficiency and design quality.

[0052] Figure 7 This invention illustrates a satellite electrical overall digital design and verification system 100 according to another embodiment of the present invention, including a rule base construction module 10, a first-level feedback report output module 20, a second-level feedback report output module 30, and a third-level feedback report output module 40, wherein: The rule base construction module 10 is used to construct a rule base for digital verification, which includes electromechanical joint design rules, interface matching rules, and process feasibility rules. The first-level feedback report output module 20 is used to perform interface attribute compliance verification on the low-frequency interface data of the equipment based on the low-frequency interface specification, and generate first-level feedback data to correct interface data errors. The second-level feedback report output module 30 is used to perform design correctness verification on the overall electrical design results based on the interface matching rules and process feasibility rules, and generate second-level feedback data to correct design errors. The third-level feedback report output module 40 is used to perform consistency verification between the continuity test data and insulation test data generated by the physical product test and the overall electrical design results, and generate third-level feedback data to identify inconsistencies between the product and the design.

[0053] Figure 8 The diagram shows a functional block diagram of the overall digital design and verification system of the present invention. The system also includes a data import module, which is used to import the low-frequency interface of the equipment, the electrical telemetry and remote control bus channel, the cable network and the test data into the corresponding databases, including the low-frequency interface database, the overall channel database, the cable database and the test result database.

[0054] The specific implementation and operation process of each module in the system 100 described in this embodiment can be understood by referring to the relevant descriptions in the foregoing method embodiments, and all of them can achieve the functions and effects achieved by the corresponding method steps. For the sake of simplicity and to avoid repetition, they will not be described again here.

[0055] The method and system of this invention have been verified in multiple models, and the results show that the number of iterations is significantly reduced, the overall design efficiency is improved by more than 85%, and the design accuracy is 100%. This method can be widely used to guide the development of other spacecraft.

[0056] In summary, this invention, by constructing electromechanical joint design rules and low-frequency interface specifications, and by performing first-level, second-level, and third-level digital closed-loop feedback verification at the initial design stage, after design completion, and after product testing, fundamentally solves the technical problems in traditional satellite electrical overall design, such as repeated manual iterations, severe electromechanical coupling, and high risk of data interpretation errors, in an automated and intelligent manner. It achieves a comprehensive improvement in design efficiency, accuracy, and test coverage, demonstrating significant technological progress and broad application prospects.

[0057] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0058] Of course, the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. A method for overall digital design and verification of satellite electrical systems, characterized in that, Including the following steps: Construct a rule base for digital verification, which includes low-frequency interface specifications, interface matching rules, and process feasibility rules; Based on the aforementioned low-frequency interface specification, the low-frequency interface data of the device is subjected to interface attribute compliance verification, and first-level feedback data is generated to correct interface data errors. Based on the interface matching rules and process feasibility rules, the overall electrical design results are verified for design correctness, and secondary feedback data is generated to correct design errors. The continuity test data and insulation test data generated from the actual product testing are compared with the overall electrical design results to perform consistency verification, and three-level feedback data is generated to identify inconsistencies between the product and the design.

2. The method according to claim 1, characterized in that, The construction of the rule base for digital verification specifically includes: Based on the principle of data parsing, the interface attribute items to be verified in the low-frequency interface of the device are defined with their compilation specifications to construct the low-frequency interface specification; wherein, the interface attribute items include signal name, destination contact, polarity, path number, shielding and twisted pair; Establish rules for determining the topology and path of cable networks that reflect the relationship between mechanical and electrical characteristics, as well as rules that reflect the limitations of cross-disciplinary information interaction, and combine these with rules for matching the attributes between the low-frequency interfaces of equipment and the cable network to construct interface matching rules. Based on the matching relationship between conductor type and current flow, and the matching relationship between electrical connector type and conductor type, process feasibility rules are constructed.

3. The method according to claim 1, characterized in that, Based on the low-frequency interface specification, the process of performing interface attribute compliance verification on the device's low-frequency interface data and generating first-level feedback data to correct interface data errors specifically includes: Import the low-frequency interface data of the equipment into the low-frequency interface database of the equipment; The interface name standardization verification module is invoked to perform standardization verification on the signal name attributes of low-frequency interfaces and to perform consistency verification on the signal names between interconnected low-frequency interfaces. Call the destination contact rationality verification module to perform correctness verification on the destination contact attributes of the low-frequency interface; Call the shielded twisted pair compatibility verification module to perform standardization verification on the shielding and twisted pair attributes of each contact, and determine whether the shielding and twisted pair requirements of two interconnected and matched contacts are consistent. The verification results of each verification module are summarized to generate primary feedback data.

4. The method according to claim 1, characterized in that, Based on the interface matching rules and process feasibility rules, the overall electrical design results are verified for design correctness, and secondary feedback data is generated to correct design errors. Specifically, this includes: Import the overall electrical channel design results into the overall channel database. Perform polarity verification according to the rule that the positive and negative polarities of the low-frequency interface of the same device should be consistent with the positive and negative polarities of the overall channel. Perform path verification according to the rule that the path grouping of the low-frequency interface of the same device should be consistent with the overall path grouping relationship. Import the cable network connection table into the cable database. Use the low-frequency interface data of the equipment after first-level digital verification and the overall electrical channel design results as the benchmark database and the cable database as the comparison database. Perform consistency verification on the signal name, destination connection, twisted pair, and shielding attributes of the same connection in the two databases. The cable process rationality verification module is invoked to perform consistency verification on the matching relationship between conductor type and current flow, and the matching relationship between electrical connector type and conductor type, based on the pre-stored process data dictionary. Summarize the results of each verification and generate secondary feedback data.

5. The method according to claim 1, characterized in that, The process of performing consistency verification between the continuity test data and insulation test data generated from the actual product testing and the overall electrical design results, generating three-level feedback data to identify inconsistencies between the product and the design, specifically includes: Import the continuity test data and insulation test data of the cable network into the test result database and analyze them; The parsed continuity test data and insulation test data are automatically filled into the corresponding cable network connection table design result data to achieve structured reorganization of test data and design data; Based on preset electrical performance criteria, the system automatically determines the qualification of each piece of data after reassembly and generates three-level feedback data, which is a consistency report between the test object and the design.

6. The method according to claim 5, characterized in that, The preset electrical performance criteria are as follows: a conduction resistance value of less than 5Ω is considered qualified, and an insulation resistance value of more than 1MΩ is considered qualified.

7. A satellite electrical overall digital design and verification system, characterized in that, Including: The rule base construction module is used to build a rule base for digital verification, which includes low-frequency interface specifications, interface matching rules, and process feasibility rules. The Level 1 Feedback Report Output Module is used to perform interface attribute compliance verification on the low-frequency interface data of the device based on the low-frequency interface specification, and generate Level 1 feedback data to correct interface data errors. The secondary feedback report output module is used to perform design correctness verification on the overall electrical design results based on the interface matching rules and process feasibility rules, and generate secondary feedback data to correct design errors. The three-level feedback report output module is used to perform consistency verification between the continuity test data and insulation test data generated from the physical product test and the overall electrical design results, and generate three-level feedback data to identify inconsistencies between the product and the design.

Images