A filter circuit design method, filter circuit and new energy vehicle electric drive system

Abstract

The present application belongs to the technical field of new energy vehicles and power electronic electromagnetic compatibility, and particularly relates to a filter circuit design method, a filter circuit and a new energy vehicle electric drive system. The structure size and test data of a busbar are acquired; the parasitic inductance and capacitance parameters of the busbar are extracted and decoupled through simulation, and an equivalent circuit model is established; the key target suppression frequency is determined according to the exceeding frequency band; the required X and Y capacitance values are accurately calculated for each target frequency by using the model parameters, and the calculation results are checked and selected; and finally, a filter capacitor combination scheme is generated. Based on the modeling of the actual measured parasitic parameters, the filter design is accurately matched with the actual interference source, and the suppression efficiency is high. The decoupling check eliminates the parameter coupling error, and avoids the deviation of the traditional experience design. The X and Y capacitors are optimized, the mutual interference of differential mode and common mode filtering is avoided, and the overall EMI performance is improved.

Description

Technical Field

[0001] This invention belongs to the field of electromagnetic compatibility (EMC) technology of new energy vehicles and power electronics, specifically relating to a filter circuit design method based on DC bus parasitic parameters and electromagnetic interference exceeding frequency, the filter circuit, and the electric drive system of new energy vehicles. Background Technology

[0002] In power electronic devices such as all-in-one controllers for new energy vehicles, photovoltaic inverters, and high-power power supplies, the DC bus, as the power circuit carrier, has parasitic inductance and capacitance. Due to the high switching speed of high-frequency devices such as IGBTs / SiC / GaN, they easily form LC resonant circuits with the parasitic parameters of the bus, exciting differential-mode and common-mode electromagnetic interference in the 1MHz to 300MHz frequency band, which is the main source of electromagnetic interference causing EMC conducted / radiated tests to exceed the limits.

[0003] Existing electromagnetic interference suppression methods include optimizing the stacked busbar design by changing the parallel busbar design to a stacked busbar design. This involves reducing the DC busbar circuit inductance by design measures such as reducing the distance between the positive and negative poles, increasing the width, and shortening the length. However, the reduction is limited by structural, heat dissipation, and insulation limitations.

[0004] Selecting values ​​like 330nF or 1μF based on power level or frequency band experience, without considering the actual parasitic parameters of the busbar and the precise frequency exceeding the standard, makes it difficult to effectively suppress electromagnetic interference. Summary of the Invention

[0005] This invention provides a filter circuit based on DC bus parasitic parameters and electromagnetic interference (EMI) exceeding the standard frequency. Modeling is based on measured parasitic parameters, and the filter design is precisely matched to the actual interference source, resulting in high suppression efficiency. Decoupling verification eliminates parameter coupling errors, avoiding deviations in traditional empirical designs. Optimization of the X and Y capacitors prevents mutual interference between differential-mode and common-mode filtering, improving overall EMI performance.

[0006] The methods include: S1: Obtain the structural dimension parameters of the DC busbar in the target power electronic equipment, and obtain the electromagnetic interference amplitude and out-of-standard frequency band data of the equipment in the electromagnetic interference test; S2: Based on the structural dimension parameters of the DC busbar, extract the parasitic parameter set of the DC busbar through simulation; S3: Decouple and verify the extracted parasitic parameter set to determine the equivalent circuit model parameters of the DC busbar. The equivalent circuit model parameters include busbar loop inductance, positive busbar branch inductance, negative busbar branch inductance, inter-busbar parasitic capacitance, positive busbar to ground capacitance, and negative busbar to ground capacitance. S4: Determine at least one target suppression frequency based on the out-of-standard frequency band data, and use the busbar circuit inductance and the parasitic capacitance between the busbars as the first reference parameter; S5: Based on the first reference parameter, calculate the X capacitor value corresponding to each target suppression frequency using the LC series resonance principle, and verify the self-resonant frequency of each calculated X capacitor value. Determine the X capacitor combination circuit for suppressing differential mode interference based on the verification results and the preset installation space constraints. S6: Based on the positive busbar branch inductance, the negative busbar branch inductance, the positive busbar to ground capacitance, and the negative busbar to ground capacitance as second reference parameters, the positive side Y capacitor value and the negative side Y capacitor value corresponding to each target suppression frequency are calculated using the LC series resonance principle. The calculated Y capacitor values ​​are then checked for self-resonance frequency and safety energy. Based on the check results and the preset installation space constraints, the Y capacitor combination circuit for suppressing common-mode interference is determined. S7: Based on the X capacitor combination circuit and the Y capacitor combination circuit, generate a filter circuit design scheme that includes the specific parameter configurations of the X capacitor and the Y capacitor.

[0007] According to another embodiment of this application, a filter circuit is provided, the circuit including: a first capacitor C yn_P Second capacitor C yn_N Third capacitor C y2_P Fourth capacitor C y2_N Fifth capacitor C y1_P And multiple sixth capacitors C connected in parallel xn ; First capacitor C yn_P The first terminal is connected to the positive busbar of the DC busbar, and the second terminal of the first capacitor Cyn_P is grounded. Second capacitor C yn_N The first terminal is connected to the negative busbar of the DC busbar, and the second capacitor C yn_N The second terminal is grounded; Third capacitor C y2_P The first terminal is connected to the positive busbar of the DC busbar, and the third capacitor C y2_P The second terminal is grounded; Fourth capacitor C y2_N The first terminal is connected to the negative busbar of the DC busbar, and the fourth capacitor C y2_N The second terminal is grounded; Fifth capacitor C y1_P The first terminal is connected to the positive busbar of the DC busbar, and the fifth capacitor C y1_P The second terminal is grounded; Each sixth capacitor C xn The first terminal is connected to the positive busbar of the DC busbar, and the sixth capacitor C xn The second end is connected to the negative busbar of the DC busbar; All Y capacitors are connected to the same grounding plane, which is connected to the metal casing of the equipment.

[0008] According to another embodiment of this application, an electric drive system for new energy vehicles is also provided, the system including: a PDU board, a filter circuit, a DC bus, an MCU board, and three magnetic rings; The high-voltage DC output terminal of the PDU board is connected to the input terminal of the filter circuit; The output of the filter circuit is connected to the input of the DC bus. The output terminal of the DC busbar is connected to the input terminal of the MCU board; The three-phase AC output terminals of the MCU board are connected to one end of each of the three magnetic rings, and the other end of each magnetic ring is connected to the motor via a power cable.

[0009] As can be seen from the above technical solutions, the present invention has the following advantages: This invention collects specific busbar structural parameters and measured electromagnetic interference spectrum data, with data sources closely aligned with the actual operating conditions of new energy vehicle all-in-one controllers, photovoltaic inverters, and high-power power supplies. This ensures the design closely reflects the real characteristics of electromagnetic interference. Multi-dimensional parasitic parameters of the busbar are extracted through electromagnetic simulation, achieving parameter decoupling and separation. This enables independent differentiation of busbar circuit parameters, single-pole branch parameters, and inter-pole and ground capacitance parameters, providing accurate equivalent circuit model support for the separate management of differential-mode and common-mode interference. The invention uses the measured envelope peak frequency of the exceeding frequency band to lock the suppression target and classifies and defines the benchmark parameter groups for differential-mode and common-mode interference. Parameters correspond one-to-one with interference mechanisms, and interference frequencies generated by the resonance of high-frequency devices and busbar parasitic parameters are specifically set. The precise capacitance value of the X capacitor is calculated iteratively based on the actual parasitic parameters of the busbar, matching the specific differential-mode resonant frequency of the device. A 1.5 times self-resonant frequency threshold is set to control the high-frequency characteristics of the devices, avoiding capacitive-inductive failure under high-frequency operating conditions. By considering the space constraints of equipment installation, a multi-capacitor parallel topology is selected, and edge frequency devices are used to cover wide-band interference, filling the gap in narrow-band suppression of traditional fixed-capacitance capacitors, and specifically addressing differential-mode electromagnetic interference from 1MHz to 300MHz.

[0010] Adapting to the asymmetrical electrical characteristics of the positive and negative busbars, the parameters of the dual-sided Y capacitors are calculated separately to match the parameter differences caused by actual wiring and assembly. Self-resonance verification and 0.2 Joule energy storage safety threshold control are superimposed to constrain the operating performance and electrical safety of common-mode filtering devices. The filter circuit structure and output parameter configuration scheme are integrated. All component selections, topologies, and adapted frequency bands are matched to the actual operating conditions of the equipment, making it suitable for EMC rectification of high-power power electronic equipment. Attached Figure Description

[0011] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a filter circuit diagram; Figure 2 This is a schematic diagram of an electric drive system for new energy vehicles. Figure 3 Flowchart of filter circuit design method; Figure 4 This is a schematic diagram of parallel busbars; Figure 5 This is a schematic diagram of a stacked busbar; Figure 6 This is a schematic diagram of the frequency band where the electromagnetic interference amplitude exceeds the standard. Detailed Implementation

[0013] like Figure 1 and Figure 2 As shown, the circuit designed based on the filter circuit design method includes: a first capacitor C yn_P Second capacitor C yn_N Third capacitor C y2_P Fourth capacitor C y2_N Fifth capacitor C y1_P And multiple sixth capacitors C connected in parallel xn .

[0014] First capacitor C yn_P The first terminal is connected to the positive busbar of DC busbar 3, and the first capacitor C yn_P The second terminal is grounded.

[0015] Second capacitor C yn_N The first terminal is connected to the negative busbar of DC busbar 3, and the second capacitor C yn_N The second terminal is grounded.

[0016] Third capacitor C y2_P The first terminal is connected to the positive busbar of DC busbar 3, and the third capacitor C y2_P The second end is grounded.

[0017] Fourth capacitor C y2_N The first terminal is connected to the negative busbar of DC busbar 3, and the fourth capacitor C y2_N The second terminal is grounded.

[0018] Fifth capacitor C y1_P The first terminal is connected to the positive busbar of DC busbar 3, and the fifth capacitor C y1_P The second end is grounded.

[0019] Each sixth capacitor C xn The first terminal is connected to the positive busbar of DC busbar 3, and the sixth capacitor C xn The second end is connected to the negative busbar of DC busbar 3.

[0020] All Y capacitors are connected to the same grounding plane, which is connected to the metal casing of the equipment.

[0021] In the context of this invention, capacitor X includes multiple sixth capacitors C. xn The number of the sixth capacitor is set according to actual needs. Capacitor X is connected in parallel between the positive and negative terminals of DC bus 3, and has a parallel connection with the circuit parasitic inductance of DC bus 3. L s Multiple LC series resonant branches are formed. Each X capacitor exhibits extremely low impedance near its self-resonant frequency, short-circuiting the differential-mode interference current at the corresponding frequency, allowing differential-mode energy to circulate within the busbar loop without being conducted outwards. X capacitors of different capacitance values ​​are connected in parallel, each covering a different differential-mode resonant frequency, collectively suppressing multiple differential-mode peaks in the out-of-range frequency band.

[0022] The positive-side Y capacitor of the present invention includes a first capacitor C. yn_P Third capacitor C y2_P Fifth capacitor C y1_P The positive Y capacitor is connected in parallel between the positive busbar and ground, and has parasitic inductance with the positive branch of DC busbar 3. L 11 + M The resonance provides a low-impedance path from the positive terminal to ground for common-mode current. The negative-side Y capacitor includes a second capacitor C. yn_N Fourth capacitor C y2_N The negative Y capacitor is connected in parallel between the negative busbar and ground, and has parasitic inductance with the negative branch of DC busbar 3. L 22 + M The resonance provides a return path for common-mode current from ground to the negative terminal. The positive and negative Y capacitors work together to bypass common-mode interference energy from the busbar to ground, preventing it from propagating along the power line.

[0023] In the context of the electric drive system of new energy vehicles, the high-voltage DC power output from the power battery pack first enters the PDU board 1. After the relay inside the PDU board 1 closes, the DC current flows into the filter circuit 2.

[0024] When DC current passes through filter circuit 2, the high-speed switching of the IGBT / SiC switching devices inside MCU board 4 generates high-frequency differential-mode and common-mode interference. The differential-mode interference propagates along DC bus 3 and enters the X capacitor connected in parallel between the positive and negative terminals. The X capacitor and the loop inductance Ls of DC bus 3 resonate in series at the interference frequency, exhibiting extremely low impedance, which short-circuits the differential-mode interference current back into the bus loop, preventing it from continuing to propagate forward.

[0025] Common-mode interference occurs simultaneously on both the positive and negative busbars. The common-mode current on the positive busbar flows to the ground plane via the positive-side Y capacitor; the common-mode current on the negative busbar flows back to the negative busbar from the ground plane via the negative-side Y capacitor, forming a common-mode return path. During this process, common-mode energy is bypassed to ground and will not enter the PDU board 1 along the DC busbar 3 or contaminate the power battery pack in the reverse direction.

[0026] The purified DC power from filter circuit 2 is output from filter circuit 2, enters DC bus 3, and then is sent to MCU board 4. MCU board 4 inverts the DC power into three-phase AC power, with each phase of AC power passing through its corresponding magnetic ring 5 in sequence. Magnetic ring 5 acts as a second-stage common-mode suppression element, absorbing residual high-frequency common-mode interference on the AC side. Finally, the three-phase AC power drives the motor through the power cable.

[0027] It can be seen that filter circuit 2 directly utilizes the inherent parasitic inductance of DC bus 3 as a resonant element, without the need for additional common-mode or differential-mode inductors. The preset capacitor parameters achieve precise suppression of measured frequency points exceeding the standard, ensuring that the electromagnetic interference of the electric drive system meets the requirements in the 1MHz~300MHz frequency band.

[0028] Furthermore, the present invention also provides an electric drive system for new energy vehicles, the system comprising: a PDU board 1, a filter circuit 2, a DC busbar 3, an MCU board 4, and three magnetic rings 5.

[0029] The high-voltage DC output terminal of PDU board 1 is connected to the input terminal of filter circuit 2. The output terminal of filter circuit 2 is connected to the input terminal of DC bus 3. The output terminal of DC bus 3 is connected to the input terminal of MCU board 4. The three-phase AC output terminals of MCU board 4 are respectively connected to one end of three magnetic rings 5, and the other end of each magnetic ring 5 is connected to the motor through a power cable.

[0030] It should be noted that PDU board 1 is used to distribute high-voltage DC power, and the internal relays control the on / off of the main circuit to realize power-on, power-off and short-circuit protection.

[0031] The parasitic parameters of filter circuit 2 and DC bus 3 form an LC resonant notch filter to suppress differential and common-mode electromagnetic interference.

[0032] DC bus 3 is used to transmit DC power and is equipped with a loop inductance Ls, a positive branch inductance, a negative branch inductance, and an inter-bus capacitor C. p Capacitance C of positive terminal to ground g1 negative terminal capacitance to ground C g2 It is directly used as a resonant element in the filter circuit.

[0033] MCU board 4 is used to invert DC power into frequency-adjustable three-phase AC power to drive the motor; the high-frequency operation of the internal switching devices of the MCU board is the main source of electromagnetic interference.

[0034] The magnetic ring 5 is used to suppress common-mode conducted interference and radiated interference on the AC busbar, and further attenuate high-frequency noise.

[0035] It should be noted that the DC power from the power battery pack first enters the PDU board 1, and after being closed by the relay, flows to the filter circuit 2. The X capacitor on the filter circuit 2 is connected across the positive and negative terminals of the DC bus 3, and is connected to the loop inductance of the DC bus 3. L s This forms a series resonance, short-circuiting the differential-mode interference; the Y capacitors are connected from the positive terminal of DC busbar 3 to ground and the negative terminal to ground, respectively, to the positive branch inductance of DC busbar 3 ( L 11 + M ) and negative branch inductance ( L 22 + M The resonant circuit bypasses common-mode interference to ground. The purified DC power is then fed into the MCU board 4 via DC bus 3. The MCU board 4 inverts the DC power into three-phase AC power, with each phase passing through a magnetic ring 5. The magnetic ring 5 absorbs the remaining high-frequency components of the common-mode interference, ultimately driving the motor. Here, the magnetic ring 5 serves as a second-stage common-mode suppression, ensuring that residual interference on the AC side is further attenuated, resulting in reliable overall EMC performance.

[0036] The following describes in detail the filter circuit design method based on DC bus parasitic parameters and electromagnetic interference exceeding the standard frequency involved in this application. Specific details, such as particular system structures and techniques, are presented for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application can also be implemented in other embodiments without these specific details.

[0037] It should be understood that, when used in this specification, the term "comprising" indicates the presence of the described feature, integral, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] Please see Figure 3 The diagram shows a flowchart of a filter circuit design method based on DC bus parasitic parameters and electromagnetic interference exceeding frequency in a specific embodiment. The method includes: S1: Obtain the structural dimension parameters of the DC busbar in the target power electronic equipment, and obtain the electromagnetic interference amplitude and out-of-standard frequency band data of the equipment in the electromagnetic interference test.

[0040] like Figure 4 and Figure 5 This diagram illustrates two DC busbar structures. Parallel busbars and laminated busbars are shown, with the three geometric dimensions affecting parasitic inductance labeled: length... l Width w and spacing d between positive and negative terminals. Through comparison, it is shown that the positive and negative terminals of a parallel busbar are arranged side by side on the same plane, resulting in a larger loop inductance; the positive and negative terminals of a laminated busbar are arranged overlapping vertically, utilizing the mutual inductance cancellation effect to reduce the loop inductance.

[0041] Furthermore, step S1 specifically includes the following steps: S11: Read the design drawing file of the DC busbar in the target power electronic equipment, extract the effective length of the busbar, the spacing between the positive and negative busbars, the effective width of the busbar and the effective thickness of the busbar from the design drawing file; write the effective length of the busbar, the spacing between the positive and negative busbars, the effective width of the busbar and the effective thickness of the busbar into the structural dimension parameter table.

[0042] S12: Place the target power electronic equipment in an electromagnetic compatibility test environment. With the equipment operating under rated conditions, use a spectrum analyzer to scan the electromagnetic interference signals of the equipment in a preset frequency band and record the electromagnetic interference amplitude corresponding to each frequency point. The electromagnetic interference amplitude corresponding to each frequency point is compared with the electromagnetic compatibility standard limit, and the frequency points whose electromagnetic interference amplitude exceeds the standard limit are selected as non-standard frequency points; the continuously distributed non-standard frequency points are aggregated into non-standard frequency bands, the envelope peak frequency in each non-standard frequency band is extracted, and the envelope peak frequency and the start and end frequencies of the corresponding non-standard frequency band are written into the electromagnetic interference test data table.

[0043] It should be noted that the parasitic inductance and capacitance of the DC busbar are directly related to its geometry. The effective length of the busbar determines the total length of the magnetic flux link, the spacing between the positive and negative busbars affects the coupling degree between the positive and negative conductors, and the effective width and thickness of the busbar determine the cross-sectional area and current distribution of the conductors. Extracting these structural dimensional parameters directly from the design drawings allows for the acquisition of data for parasitic parameter calculations before the actual busbar is manufactured. When power electronic equipment operates under rated conditions, the high-speed switching of power devices and the parasitic parameters of the DC busbar create oscillations, generating electromagnetic interference energy in specific frequency bands. A spectrum analyzer captures the maximum interference amplitude at each frequency point through peak detection mode, enabling a complete record of the equipment's electromagnetic emission level under the worst operating conditions. By comparing the measured electromagnetic interference amplitude with electromagnetic compatibility standard limits, out-of-standard frequency points are identified and aggregated into out-of-standard frequency bands. The envelope peak frequencies are then extracted from these out-of-standard frequency bands. These envelope peak frequencies correspond to the frequencies where electromagnetic interference energy is most concentrated, which are the target frequencies that the filtering circuit needs to suppress.

[0044] S2: Based on the structural dimensions of the DC busbar, the parasitic parameter set of the DC busbar is extracted through simulation. The parasitic parameter set includes the busbar loop inductance, the inter-busbar parasitic capacitance, the positive busbar to ground capacitance, and the negative busbar to ground capacitance.

[0045] In some embodiments, step S2 specifically includes the following steps: S21: Read the structural dimension parameter table generated in step S11, and extract the effective length, effective width, effective thickness, positive and negative busbar spacing, and controller housing structural dimensions.

[0046] Import the above structural dimensions into the electromagnetic simulation software to create a three-dimensional solid model of the DC busbar.

[0047] Set the material properties of the positive and negative busbars to copper, and set the conductivity parameters to match the physical properties of copper.

[0048] Set the material properties of the insulation layer between busbars, and assign the corresponding relative permittivity parameter according to the type of insulation medium actually filled between busbars.

[0049] The controller housing is set as the solution domain boundary, given metallic material properties, and grounded. The mesh is refined at the busbar edges, bends, and areas directly opposite the positive and negative busbars, with the mesh element side lengths in these areas proportional to the busbar thickness, generating a finite element mesh.

[0050] S22: In the three-dimensional electromagnetic simulation model, a first current excitation port is set based on the input end face of the positive busbar, and a positive current excitation is applied to the first current excitation port.

[0051] A second current excitation port is set on the input end face of the negative busbar, and a reverse current excitation is applied to the second current excitation port.

[0052] Run the finite element method to solve for the magnetic field distribution and output the inductance matrix. Read the first row and first column elements from the inductance matrix as the positive DC busbar self-inductance, read the second row and second column elements as the negative DC busbar self-inductance, read the first row and second column elements as the first mutual inductance, and read the second row and first column elements as the second mutual inductance.

[0053] Analyze whether the values ​​of the first mutual inductance and the second mutual inductance are consistent. If they are inconsistent, run the finite element method again.

[0054] Specifically, the finite element method can be used to calculate the self-inductance and mutual inductance of the DC busbar, and to generate the inductance matrix. Busbar circuit inductance calculated by matrix reduction Positive busbar branch inductance Negative busbar branch inductance ; For differential mode interference current, the busbar circuit inductance

[0055] For common-mode interference current, the inductance of each branch

[0056] In the formula, The positive DC busbar has its own inductance. The negative DC busbar has its own inductance. M For busbar mutual inductance.

[0057] For differential mode interference current, busbar mutual inductance M The effect is to cancel each other out, which is based on the fact that the currents are reversed and the magnetic fields cancel each other out.

[0058] For common-mode interference current, busbar mutual inductance M The effect of enhancement is based on the fact that the currents are in the same direction and the magnetic fields are added together.

[0059] in M It is equal to both the first mutual inductance and the second mutual inductance. The calculated busbar circuit inductance is written into the first field of the parasitic parameter set.

[0060] The matrix reduction here transforms the two-dimensional matrix into a single-loop inductor, which can then be directly used for subsequent X-capacitor calculations.

[0061] S23: In the three-dimensional electromagnetic simulation model, a first voltage excitation port is set between the positive busbar and the negative busbar, and a voltage difference is applied to the first voltage excitation port.

[0062] A second voltage excitation port is set between the positive busbar and the controller housing ground, and a voltage difference is applied to the second voltage excitation port.

[0063] A third voltage excitation port is provided between the negative busbar and the controller housing ground, and a voltage difference is applied to the third voltage excitation port.

[0064] The capacitance value between the positive and negative busbars is extracted from the capacitance matrix as the inter-busbar parasitic capacitance. The capacitance value between the positive busbar and the controller housing ground is extracted as the positive busbar-to-ground capacitance. The capacitance value between the negative busbar and the controller housing ground is extracted as the negative busbar-to-ground capacitance. The inter-busbar parasitic capacitance, the positive busbar-to-ground capacitance, and the negative busbar-to-ground capacitance are written into the second, third, and fourth fields of the parasitic parameter set.

[0065] It should be noted that each element of the capacitance matrix corresponds to the charge coupling relationship between two conductors. The parasitic capacitance between busbars is determined by the area and spacing of the positive and negative busbars facing each other, reflecting the inherent capacitance in the differential-mode interference path. The capacitance of the positive busbar to ground and the capacitance of the negative busbar to ground reflect the electric field coupling between the positive and negative busbars and the outer casing ground, respectively, and are key parameters of the common-mode interference path.

[0066] S3: Decouple and verify the extracted parasitic parameter set to determine the equivalent circuit model parameters of the DC busbar. The equivalent circuit model parameters include busbar loop inductance, positive busbar branch inductance, negative busbar branch inductance, inter-busbar parasitic capacitance, positive busbar to ground capacitance, and negative busbar to ground capacitance. S4: Determine at least one target suppression frequency based on the out-of-standard frequency band data, and use the busbar circuit inductance and the parasitic capacitance between the busbars as the first reference parameter; S5: Based on the first reference parameter, calculate the X capacitor value corresponding to each target suppression frequency using the LC series resonance principle, and verify the self-resonant frequency of each calculated X capacitor value. Determine the X capacitor combination circuit for suppressing differential mode interference based on the verification results and the preset installation space constraints. S6: Based on the positive busbar branch inductance, the negative busbar branch inductance, the positive busbar to ground capacitance, and the negative busbar to ground capacitance as second reference parameters, the positive side Y capacitor value and the negative side Y capacitor value corresponding to each target suppression frequency are calculated using the LC series resonance principle. The calculated Y capacitor values ​​are then checked for self-resonance frequency and safety energy. Based on the check results and the preset installation space constraints, the Y capacitor combination circuit for suppressing common-mode interference is determined. S7: Based on the X-capacitor combination circuit and the Y-capacitor combination circuit, generate a filter circuit design scheme that includes the specific parameter configurations of the X and Y capacitors. In this way, the differential-mode filter circuit and the common-mode filter circuit correspond to two different types of electromagnetic interference. After being designed separately, they are integrated to comprehensively cover the full-band electromagnetic interference exceeding the standard caused by the parasitic parameters of the DC busbar, constructing a complete electromagnetic interference suppression system.

[0067] As can be seen, this invention proposes a filter circuit design method based on DC bus parasitic parameters and electromagnetic interference (EMC) exceeding the standard frequency. The method provides a DC bus parasitic parameter extraction method and a decoupling circuit model for DC bus parasitic parameters. It simplifies the filter circuit design by replacing all inductors and some capacitors with bus parasitic parameters. A quantitative calculation model for the capacitance value and quantity of filter capacitors based on bus parasitic parameters and EMC exceeding the standard frequency band is established. The X and Y capacitor values ​​required to suppress target frequency EMC are calculated using the LC series resonance principle, ultimately completing the combined filter circuit design. This invention overcomes the shortcomings of traditional methods that rely on experience to select filter capacitor parameters and passive trial-and-error. It can achieve precise suppression of exceeding the standard frequency band and forms an engineeringable filter capacitor calculation model, effectively shortening the EMC rectification cycle and reducing rectification costs.

[0068] In some specific embodiments, based on step S3, the following will provide a possible embodiment and describe its specific implementation in a non-limiting manner.

[0069] S31: Calculate the analytical values ​​of the parallel busbar loop inductance and busbar parasitic capacitance based on the busbar effective length, positive and negative busbar spacing, busbar effective width and busbar effective thickness in the structural dimension parameter table; The parallel busbar loop inductance obtained by analysis is compared with the busbar loop inductance extracted by simulation. The parasitic capacitance of the busbar obtained by analysis is compared with the parasitic capacitance between the busbars extracted by simulation. If the comparison deviation is within the preset tolerance range, the parasitic parameter set extracted by simulation is confirmed to be valid, and the parasitic parameter set is written into the parameter table to be decoupled. If the comparison deviation exceeds the preset tolerance range, then the mesh density or boundary condition settings of the finite element simulation model are corrected, and step S2 is re-executed to extract the parasitic parameter set.

[0070] S32: Read from the inductor matrix , and MBased on the matrix order reduction relationship between the busbar circuit inductance, self-inductance, and mutual inductance, calculate the inductance of the positive busbar branch and the negative busbar branch.

[0071] For differential mode interference current, the inductance of the positive busbar branch = - M Inductance of negative busbar branch = - M .

[0072] For common-mode interference current, the inductance of the positive busbar branch = + M Inductance of negative busbar branch = + M Write the calculated positive busbar branch inductance and negative busbar branch inductance into the branch inductance field.

[0073] S33: Write the busbar circuit inductance, positive busbar branch inductance, negative busbar branch inductance, busbar inter-branch parasitic capacitance, positive busbar to ground capacitance, and negative busbar to ground capacitance into the equivalent circuit model parameter table according to the fields.

[0074] It should be noted that the parasitic parameter set includes four parameters: busbar loop inductance, inter-busbar parasitic capacitance, positive busbar-to-ground capacitance, and negative busbar-to-ground capacitance. The structural dimension parameter table includes the effective length of the busbar. l Spacing between positive and negative busbars d Effective width of busbar w and busbar effective thickness t Call the analytical calculation module to calculate the effective length of the busbar. l Spacing between positive and negative busbars d Effective width of busbar w and busbar effective thickness t Input the analytical calculation module to calculate the inductance of the parallel busbar circuit. L s The parsed value is calculated as follows:

[0075] In the formula, μ 0 is the permeability of free space. μ 0 = 4π × 10 -7 . L o It is an external inductor, dominated by loop flux. L i Internal inductance is the magnetic flux inside the conductor.

[0076] Calculate the inductance of the laminated busbar circuit.

[0077] Interbus parasitic capacitance The calculation method is as follows

[0078] The calculation method for busbar-to-ground capacitance is as follows:

[0079] In the formula, A GND The effective area of ​​the mother row to the ground; d GND This refers to the distance between the busbar and the ground. The vacuum permittivity, is the relative permittivity of the insulating medium between busbars; The inductance of the parallel busbar circuit obtained by analytical method The numerical values ​​of the busbar circuit inductance extracted from the simulation are compared, and the deviation between the two is calculated. The inter-busbar parasitic capacitance calculated analytically The values ​​are compared with the parasitic capacitance between busbars extracted by simulation, and the deviation between the two is calculated. Set the preset tolerance range to ±15%; if the comparison deviation of the busbar circuit inductance and the comparison deviation of the inter-busbar parasitic capacitance are both within ±15%, then confirm that the parasitic parameter set extracted by simulation is valid, and write the busbar circuit inductance, inter-busbar parasitic capacitance, positive busbar to ground capacitance and negative busbar to ground capacitance into the decoupling parameter table. If any comparison deviation exceeds ±15%, return to step S2, correct the mesh density or boundary condition settings of the finite element simulation model, and then re-extract the parasitic parameter set.

[0080] It should be noted that the parallel busbar circuit inductance L s The calculation method treats the busbars as parallel conductors, neglecting the uneven distribution of current across the conductor cross-section and the magnetic field distortion at the ends and bends of the busbars. However, actual busbars exhibit edge effects, with the magnetic field spreading outwards from the ends, resulting in an equivalent loop inductance that is larger than the analytical value. When calculating the parasitic capacitance between busbars, the parallel busbar loop inductance... L s The calculation method uses a parallel plate model, neglecting the outward diffusion of the electric field at the busbar edge. The actual electric field distribution exceeds the geometric boundary of the busbar, resulting in an overestimation of the equivalent capacitance ratio. The deviation introduced by the edge effect is in the range of 10% to 15%.

[0081] The inductance matrix in this embodiment of the invention is calculated by the finite element method and is in the form of: [ L 11 L 12 ] [ L 21 L22 ] In the formula, L 11 The positive DC busbar has its own inductance. L 22 The negative DC busbar has its own inductance. L 12 and L 21 Busbar mutual inductance M ,and L 12 = L 21 = M Read the positive DC bus inductance from the inductance matrix. L 11 Negative DC busbar self-inductance L 22 Mutual inductance with busbar M ; Call the matrix reduction operation to calculate the busbar circuit inductance. L s Positive busbar branch inductance Negative busbar branch inductance ; The calculation method is as follows: For differential mode interference current

[0082] The calculated busbar circuit inductance is compared with the busbar circuit inductance in the parameter table to be decoupled; if they match, the inductance is calculated from the positive DC busbar. L 11 Subtract busbar mutual inductance M Calculate the inductance of the positive busbar branch: Positive busbar branch inductance = L 11 - M Subtract the busbar mutual inductance from the negative DC busbar. M Calculate the inductance of the negative busbar branch: Negative busbar branch inductance = L 22 - M Write the calculated positive busbar branch inductance and negative busbar branch inductance into the branch inductance field; if they are inconsistent, mark the inductance matrix data as abnormal and return to step S2 to extract the inductance matrix again.

[0083] For common-mode interference current, the inductance of each branch

[0084] Positive busbar branch inductance = L 11 +M From the negative DC busbar, add the busbar mutual inductance M Calculate the inductance of the negative busbar branch: Negative busbar branch inductance = L 22 + M Write the calculated positive busbar branch inductance and negative busbar branch inductance into the branch inductance field; if they are inconsistent, mark the inductance matrix data as abnormal and return to step S2 to extract the inductance matrix again.

[0085] Furthermore, the busbar parasitic parameter decoupling circuit model in step S33 needs to include both differential-mode interference path parameters and common-mode interference path parameters. The busbar loop inductance and the inter-busbar parasitic capacitance constitute the LC resonant circuit for differential-mode interference. The positive busbar branch inductance and the positive busbar-to-ground capacitance constitute the positive-side common-mode interference path, and the negative busbar branch inductance and the negative busbar-to-ground capacitance constitute the negative-side common-mode interference path. Integrating these six parameters into the equivalent circuit model parameter table allows differential-mode filtering calculations and common-mode filtering calculations to extract the required parameters from the same data source, maintaining consistency in parameter source.

[0086] In some specific embodiments, based on step S4, the following will provide a possible embodiment and describe its specific implementation in a non-limiting manner.

[0087] S41: Extract the start and end frequencies and envelope peak frequency of the out-of-standard frequency band from the electromagnetic interference test data table; write the start and end frequencies of the out-of-standard frequency band into the out-of-standard frequency band interval table, and write the envelope peak frequency into the initial peak frequency table.

[0088] S42: Traverse each envelope peak frequency in the initial peak frequency table and compare each envelope peak frequency with the electromagnetic interference amplitude of the adjacent frequency points; if the electromagnetic interference amplitude of a certain envelope peak frequency is greater than the amplitude of its left and right adjacent frequency points, then retain the envelope peak frequency as an effective peak frequency; write the filtered effective peak frequencies into the target suppression frequency table, and each effective peak frequency in the target suppression frequency table is the target suppression frequency.

[0089] S43: Read the equivalent circuit model parameters determined in step S3, extract the busbar loop inductance from the equivalent circuit model parameters, and write the busbar loop inductance into the first field of the first reference parameter table.

[0090] S44: Read the equivalent circuit model parameters determined in step S3, and extract the inter-busbar parasitic capacitance from the equivalent circuit model parameters; write the inter-busbar parasitic capacitance into the second field of the first reference parameter table; output the first reference parameter table to step S5, wherein the first reference parameter table includes busbar loop inductance and inter-busbar parasitic capacitance.

[0091] It should be noted that the electromagnetic interference test data table includes the start and end frequencies and envelope peak frequencies of the out-of-standard frequency bands; the start and end frequencies include the lower limit frequency and upper limit frequency of the out-of-standard frequency bands; the extracted lower limit frequency and upper limit frequency of each out-of-standard frequency band are written into the out-of-standard frequency band interval table in order of frequency band number. The envelope peak frequency is extracted row by row from the electromagnetic interference test data table, and the envelope peak frequency is the frequency point where the electromagnetic interference amplitude reaches a local maximum value in each out-of-standard frequency band. In step S42, the electromagnetic interference amplitude curve obtained by the spectrum analyzer has measurement noise and local fluctuations, and not all envelope peak frequencies correspond to the actual electromagnetic interference energy concentration points. By comparing the amplitude of each envelope peak frequency with the amplitude of its left and right adjacent frequency points, only when the amplitude of the current frequency point is greater than the amplitudes of the two adjacent frequency points at the same time, is the frequency point confirmed as a true local peak, thereby eliminating false peak frequencies caused by measurement noise or spectrum leakage.

[0092] Further, in step S44, the inter-busbar parasitic capacitance and the busbar loop inductance together form an LC resonant circuit for differential-mode interference. In the calculation of the filter X capacitor value, the inter-busbar parasitic capacitance, as an existing capacitance component in the circuit, needs to be subtracted from the calculated total resonant capacitance to determine the additional filter X capacitor value required. The value of the inter-busbar parasitic capacitance is determined by the busbar structural dimensions and the characteristics of the insulating medium. The inter-busbar parasitic capacitance and the busbar loop inductance are used together as the first reference parameter to establish a complete parameter set for differential-mode filtering calculation.

[0093] In some specific embodiments, based on step S5, the following will provide a possible embodiment and describe its specific implementation in a non-limiting manner.

[0094] S51: Read the first reference parameter table output in step S43, and extract the busbar loop inductance and inter-busbar parasitic capacitance from the first reference parameter table; read the target suppression frequency from the target suppression frequency table output in step S42. f 1, f 2,..., f n Based on different target suppression frequencies f 1, f 2,..., f n The corresponding X capacitors are respectively C x1 , C x2 , ... , C xn Calculate the capacitance value of capacitor X corresponding to the current target suppression frequency:

[0095] In the formula, For the nth target suppression frequency The corresponding X capacitor values ​​are calculated and written into the X capacitor value table according to the corresponding target suppression frequency.

[0096] It should be noted that, as Figure 6 As shown, electromagnetic interference tests were conducted, and the frequency bands where the electromagnetic interference amplitude exceeded the standard were obtained. f A ~ f B Determine multiple envelope peak frequencies in the middle of the frequency band exceeding the standard. f 1, f 2,..., f n , as the target suppression frequency.

[0097] S52: The self-resonant frequency of the current X capacitor is calculated based on the capacitance value and parasitic inductance of each X capacitor in the following manner.

[0098] In the formula, For the nth X capacitor C xn The self-resonant frequency, Let X be the parasitic inductance of the nth X capacitor; read the target suppression frequency corresponding to the current X capacitor. ; to the self-resonant frequency With 1.5 times the target suppression frequency Perform numerical comparisons; like Greater than If the current capacitance value of X is marked as valid, then the verification is passed; if Not greater than If necessary, replace the X capacitor with one of lower parasitic inductance and recalculate the self-resonant frequency until the desired frequency is achieved. Greater than Write the capacitance value and self-resonant frequency of each X capacitor that has passed the verification into the X capacitor table after verification.

[0099] S53: Read the capacitance values ​​of each X capacitor in the verified X capacitor table; read the preset installation space constraint parameters, which include the available area of ​​the filter circuit and the maximum allowable height of the X capacitor element; Find the package size corresponding to each X capacitor value, and mark the X capacitor values ​​whose package size exceeds the installation space constraints as restricted items; Determine if the number of restricted items is zero; if the number of restricted items is zero, connect all the X capacitor values ​​in the verified X capacitor table in parallel to form an X capacitor combination circuit. If the number of restricted items is not zero, remove the X capacitor value corresponding to the middle frequency from the X capacitor table after verification, retain the X capacitor value corresponding to the edge frequency, connect the retained X capacitor values ​​in parallel to form an X capacitor combination circuit; output the X capacitor combination circuit to step S7.

[0100] It can be seen that step 51 directly calculates the X capacitor value using the busbar circuit inductance and inter-busbar parasitic capacitance as known quantities, and independently calculates the corresponding X capacitor value for each target suppression frequency, ensuring that each out-of-range frequency has a targeted filter capacitor configuration. In S52, the actual X capacitor element has parasitic inductance. When the operating frequency increases to the self-resonant frequency At the same time, the capacitive reactance and parasitic inductive reactance of the X capacitor cancel each other out, and the component exhibits purely resistive characteristics. When the operating frequency exceeds the self-resonant frequency, the X capacitor exhibits inductive characteristics and loses its filtering function. The self-resonant frequency verification here ensures that the selected X capacitor is still in the effective operating frequency band at the target suppression frequency, avoiding capacitor failure at the target frequency. Step S53 is based on the parallel connection of multiple X capacitors, where the total capacitance is the sum of the capacitance values ​​of each X capacitor. Each X capacitor provides resonance suppression for different target suppression frequencies, and the combined circuit after parallel connection can form a low-impedance path at multiple frequency points simultaneously. When installation space is limited, the contribution of the X capacitor corresponding to the middle frequency to the overall filtering effect is relatively small, because the X capacitor corresponding to the edge frequency has covered the main range of the out-of-range frequency band. Removing the X capacitor corresponding to the middle frequency can meet the space constraints while maintaining the core filtering capability.

[0101] In some specific embodiments, based on step S6, the following will provide a possible embodiment and describe its specific implementation in a non-limiting manner.

[0102] S61: Read the equivalent circuit model parameter table output in step S33, and extract the positive busbar branch inductance, negative busbar branch inductance, positive busbar-to-ground capacitance, and negative busbar-to-ground capacitance from the equivalent circuit model parameter table. The capacitance value of the positive-side Y capacitor corresponding to the current target suppression frequency is calculated using the following method.

[0103] The capacitance value of the negative-side Y capacitor corresponding to the current target suppression frequency is calculated using the following relationship:

[0104] In the formula, The nth target suppression frequency of the positive busbar The corresponding Y capacitor value, The nth target suppression frequency of the negative electrode busbar The corresponding Y capacitor value, For the positive busbar branch inductance, For the negative busbar branch inductance, This is the positive busbar capacitance to ground. The capacitance of the negative busbar to ground is denoted as ; the calculated capacitance values ​​of the Y capacitors on each positive and negative side are written into the Y capacitor value table according to the corresponding target suppression frequency.

[0105] S62: Read the capacitance values ​​of each positive-side Y capacitor and each negative-side Y capacitor from the Y capacitor capacitance value table; read the parasitic inductance parameters corresponding to each Y capacitor, which are provided by the datasheet of the selected Y capacitor element; calculate the self-resonant frequency of the current positive-side Y capacitor based on the current positive-side Y capacitor capacitance value and parasitic inductance in the following manner.

[0106] For each negative-side Y-capacitor value, the self-resonant frequency of the current negative-side Y-capacitor is calculated based on the current negative-side Y-capacitor value and parasitic inductance. The calculation method is as follows:

[0107] In the formula, The nth Y capacitor of the positive busbar The self-resonant frequency, The nth Y capacitor of the negative busbar The self-resonant frequency, Let be the parasitic inductance of the nth Y capacitor on the positive busbar. The parasitic inductance of the nth Y capacitor in the negative busbar; Read the target suppression frequency corresponding to the current Y capacitor. ; the self-resonant frequency on the positive side With 1.5 Numerical comparisons were performed, and the self-resonant frequency on the negative electrode side was determined. With 1.5 Perform numerical comparisons; if Greater than 1.5 ,and Greater than 1.5 If the value of the Y capacitor corresponding to the current target suppression frequency is marked as "self-resonance verification passed", then the self-resonance verification is passed. If the self-resonant frequency on either side is not greater than 1.5 Then replace the Y capacitor with one of smaller parasitic inductance on that side, and recalculate the self-resonant frequency until both sides meet the requirements. Greater than 1.5 and Greater than 1.5 ; Write the capacitance values ​​of the positive and negative Y capacitors that have passed the self-resonance test into the Y capacitor table after the self-resonance test.

[0108] S63: Read the capacitance values ​​of each positive-side Y capacitor in the Y capacitor table after self-resonance verification. and the capacitance values ​​of the Y capacitors on each negative side The total capacitance of the Y capacitor is calculated based on the following formula.

[0109] In the formula, Let Y be the capacitance value on the positive side corresponding to the i-th target suppression frequency. Here, n represents the capacitance value of the negative-side Y capacitor corresponding to the i-th target suppression frequency, and n is the total number of target suppression frequencies; read the supply voltage of the target power electronic equipment. U The total energy stored in the Y capacitor is calculated using the following formula. E=

[0110] In the formula, E is the total energy stored in the Y capacitor. This represents the total capacitance of the Y capacitor. U This refers to the power supply voltage. The total energy stored in the Y capacitor, E, is numerically compared with 0.2 joules; If E is less than 0.2 joules, then the total energy stored in the Y capacitor is marked as having passed the safety verification. If E is not less than 0.2 joules, remove the Y capacitance value pair corresponding to the intermediate frequency from the Y capacitance table after self-resonance verification, recalculate the total capacitance value and total energy storage, and repeat this process until E is less than 0.2 joules; write the Y capacitance values ​​of each positive terminal and each negative terminal that have passed the safety verification into the Y capacitance table after safety verification.

[0111] S64: Retrieve the package dimensions corresponding to the Y capacitor values ​​on each positive side and each Y capacitor value on each negative side, and mark the Y capacitor values ​​whose package dimensions exceed the installation space constraints as restricted items. Determine if the number of restricted items is zero; If the number of restricted items is zero, then all positive-side Y capacitors in the Y capacitor table after safety verification are connected in parallel between the positive busbar and ground, and all negative-side Y capacitors are connected in parallel between the negative busbar and ground to form a Y capacitor combination circuit. If the number of restricted items is not zero, remove the Y capacitor value pairs corresponding to the middle frequency from the Y capacitor table after safety verification, retain the positive and negative Y capacitor values ​​corresponding to the edge frequencies, connect the retained positive Y capacitors in parallel between the positive busbar and ground, and connect the retained negative Y capacitors in parallel between the negative busbar and ground to form a Y capacitor combination circuit; output the Y capacitor combination circuit to step S7.

[0112] It should be noted that the capacitance values ​​of the Y capacitors on the positive and negative sides are calculated separately to accommodate differences in branch inductance and capacitance to ground caused by asymmetry in the positive and negative busbar structure. The self-resonant frequencies of the Y capacitors on both the positive and negative sides are checked separately to accommodate situations where different types of components may be used on each side. The verification is considered successful only if both sides simultaneously meet a 1.5 times safety margin to avoid incomplete common-mode filtering due to failure on one side.

[0113] The Y capacitor is connected between a live conductor and ground. When the equipment is powered off, the charge stored in the Y capacitor is released through the human body. Excessive total energy storage may pose a risk of electric shock. Electromagnetic compatibility (EMC) safety standards stipulate that the total energy storage of the Y capacitor must not exceed 0.2 joules to limit the risk of electric shock after power failure. The total capacitance value is obtained by summing all the Y capacitors on both the positive and negative sides. The total energy storage is calculated based on the total capacitance value and the supply voltage. Limiting the upper limit of the total energy storage ensures that the filter circuit meets safety requirements. The positive and negative Y capacitors are connected in parallel between their respective busbars and ground, allowing independent filtering of common-mode interference paths on both sides, preventing interference. When space is limited, Y capacitors corresponding to edge frequencies are prioritized to ensure effective common-mode suppression at both ends of the out-of-range frequency band, maintaining the main function of the filter circuit. The positive and negative sides of the Y capacitor combination circuit are configured with separate outputs to facilitate the generation of the filter circuit design scheme in step S7.

[0114] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0115] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A filter circuit design method, characterized in that, The methods include: S1: Obtain the structural dimension parameters of the DC busbar in the target power electronic equipment, and obtain the electromagnetic interference amplitude and out-of-standard frequency band data of the equipment in the electromagnetic interference test; S2: Based on the structural dimension parameters of the DC busbar, extract the parasitic parameter set of the DC busbar through simulation; S3: Decouple and verify the extracted parasitic parameter set to determine the equivalent circuit model parameters of the DC busbar. The equivalent circuit model parameters include busbar loop inductance, positive busbar branch inductance, negative busbar branch inductance, inter-busbar parasitic capacitance, positive busbar to ground capacitance, and negative busbar to ground capacitance. S4: Determine at least one target suppression frequency based on the out-of-standard frequency band data, and use the busbar circuit inductance and the parasitic capacitance between the busbars as the first reference parameter; S5: Based on the first reference parameter, calculate the X capacitor value corresponding to each target suppression frequency using the LC series resonance principle, and verify the self-resonant frequency of each calculated X capacitor value. Determine the X capacitor combination circuit for suppressing differential mode interference based on the verification results and the preset installation space constraints. S6: Based on the positive busbar branch inductance, the negative busbar branch inductance, the positive busbar to ground capacitance, and the negative busbar to ground capacitance as the second reference parameters, the positive side Y capacitor value and the negative side Y capacitor value corresponding to each of the target suppression frequencies are calculated using the LC series resonance principle. The calculated Y capacitor values ​​are then checked for self-resonance frequency and safety energy. Based on the check results and the preset installation space constraints, the Y capacitor combination circuit for suppressing common-mode interference is determined. S7: Based on the X capacitor combination circuit and the Y capacitor combination circuit, generate a filter circuit design scheme that includes the specific parameter configurations of the X capacitor and the Y capacitor.

2. The filter circuit design method according to claim 1, characterized in that, S2 specifically includes the following steps: A three-dimensional electromagnetic simulation model of the DC busbar was established based on the structural dimension parameters. The material properties of the positive and negative busbars and the dielectric constant of the insulation layer were set. The grid was then refined after the controller shell was set as the boundary of the grounded solution domain. In the three-dimensional electromagnetic simulation model, current excitation is applied to the positive busbar and the negative busbar respectively. The self-inductance of the positive busbar, the self-inductance of the negative busbar and the mutual inductance are extracted by solving the inductance matrix. Then, the busbar loop inductance, the positive busbar branch inductance and the negative busbar branch inductance are calculated by matrix reduction. In the three-dimensional electromagnetic simulation model, voltage excitation is applied between the positive busbar and the negative busbar, between the positive busbar and the controller housing, and between the negative busbar and the controller housing. The parasitic capacitance between the busbars, the capacitance of the positive busbar to ground, and the capacitance of the negative busbar to ground are extracted by solving the capacitance matrix.

3. The filter circuit design method according to claim 1, characterized in that, S3 specifically includes the following steps: The busbar circuit inductance and inter-busbar parasitic capacitance calculated by analytical method are compared with the corresponding parameters extracted by simulation. If the deviation is within the preset tolerance range, the parasitic parameter set is confirmed to be valid; otherwise, the simulation model is corrected and the parameters are extracted again. Read the positive busbar inductance, negative busbar inductance and mutual inductance from the inductance matrix. Subtract the mutual inductance from the positive busbar inductance to obtain the positive busbar branch inductance. Subtract the mutual inductance from the negative busbar inductance to obtain the negative busbar branch inductance. Write the busbar circuit inductance, positive busbar branch inductance, negative busbar branch inductance, inter-busbar parasitic capacitance, positive busbar to ground capacitance, and negative busbar to ground capacitance into the equivalent circuit model parameter table.

4. The filter circuit design method according to claim 2, characterized in that, S4 specifically includes the following steps: Extract the start and end frequencies and envelope peak frequency of the out-of-standard frequency band from the electromagnetic interference test data table; write the start and end frequencies of the out-of-standard frequency band into the out-of-standard frequency band interval table, and write the envelope peak frequency into the initial peak frequency table; Iterate through each envelope peak frequency in the initial peak frequency table and compare each envelope peak frequency with the electromagnetic interference amplitude of adjacent frequency points; If the electromagnetic interference amplitude of a certain envelope peak frequency is greater than the amplitude of its left and right adjacent frequency points, then the envelope peak frequency is retained as an effective peak frequency; the selected effective peak frequencies are written into the target suppression frequency table, and each effective peak frequency in the target suppression frequency table is the target suppression frequency; Read the equivalent circuit model parameters determined in step S3, extract the busbar loop inductance from the equivalent circuit model parameters, and write the busbar loop inductance into the first field of the first reference parameter table; Read the equivalent circuit model parameters determined in step S3, and extract the inter-busbar parasitic capacitance from the equivalent circuit model parameters; write the inter-busbar parasitic capacitance into the second field of the first reference parameter table; output the first reference parameter table to step S5, wherein the first reference parameter table includes busbar loop inductance and inter-busbar parasitic capacitance.

5. The filter circuit design method according to claim 4, characterized in that, S5 specifically includes the following steps: Read the busbar loop inductance and inter-busbar parasitic capacitance from the first reference parameters, and calculate the X capacitor value corresponding to each target suppression frequency based on the X capacitor value calculation method. Read the parasitic inductance corresponding to each X capacitor value and calculate the self-resonant frequency. Compare the self-resonant frequency with 1.5 times the target suppression frequency and select the X capacitor values ​​that satisfy the self-resonant frequency being greater than 1.5 times the target suppression frequency. Based on the installation space constraints, determine whether the package size of each X capacitor value exceeds the available space. If it does, remove the X capacitor value corresponding to the middle frequency and retain the X capacitor value corresponding to the edge frequency. Connect the retained X capacitor values ​​in parallel to form an X capacitor combination circuit.

6. The filter circuit design method according to claim 1, characterized in that, S6 specifically includes the following steps: Based on the positive busbar branch inductance, negative busbar branch inductance, positive busbar to ground capacitance and negative busbar to ground capacitance, calculate the positive side Y capacitance value and negative side Y capacitance value corresponding to each target suppression frequency. Calculate the self-resonant frequency for each positive-side Y capacitor and each negative-side Y capacitor. Mark the Y capacitor value whose self-resonant frequency is greater than 1.5 times the target suppression frequency as having passed the self-resonance verification. The total capacitance value is obtained by summing up all the Y capacitor values ​​that have passed the self-resonance test. The total energy storage is calculated by combining the supply voltage. The Y capacitor value pairs corresponding to the intermediate frequency are repeatedly eliminated until the total energy storage is less than 0.2 joules. Based on the installation space constraints, the Y capacitor values ​​corresponding to the intermediate frequencies are eliminated, while the Y capacitor values ​​corresponding to the edge frequencies are retained. The retained positive-side Y capacitors are connected in parallel between the positive busbar and ground, and the negative-side Y capacitors are connected in parallel between the negative busbar and ground, forming a Y capacitor combination circuit.

7. The filter circuit design method according to claim 1, characterized in that, S1 specifically includes the following steps: Read the design drawing file of the DC busbar in the target power electronic equipment and write the data in the design drawing file into the structural dimension parameter table; Use a spectrum analyzer to scan the electromagnetic interference signals of the target power electronic equipment in a preset frequency band and record the electromagnetic interference amplitude at each frequency point. The electromagnetic interference amplitude corresponding to each frequency point is compared with the electromagnetic compatibility standard limit, and the frequency points whose electromagnetic interference amplitude exceeds the standard limit are selected as non-standard frequency points; the continuously distributed non-standard frequency points are aggregated into non-standard frequency bands, the envelope peak frequency in each non-standard frequency band is extracted, and the envelope peak frequency and the start and end frequencies of the corresponding non-standard frequency band are written into the electromagnetic interference test data table.

8. A filter circuit, characterized in that, The filter circuit is designed based on the filter circuit design method according to any one of claims 1 to 7; the circuit includes: a first capacitor C yn_P Second capacitor C yn_N Third capacitor C y2_P Fourth capacitor C y2_N Fifth capacitor C y1_P And multiple sixth capacitors C connected in parallel xn ; First capacitor C yn_P The first end is connected to the positive busbar of the DC busbar (3), and the first capacitor C yn_P The second terminal is grounded; Second capacitor C yn_N The first end is connected to the negative busbar of the DC busbar (3), and the second capacitor C yn_N The second terminal is grounded; Third capacitor C y2_P The first end is connected to the positive busbar of the DC busbar (3), and the third capacitor C y2_P The second terminal is grounded; Fourth capacitor C y2_N The first end is connected to the negative busbar of the DC busbar (3), and the fourth capacitor C y2_N The second terminal is grounded; Fifth capacitor C y1_P The first end is connected to the positive busbar of the DC busbar (3), and the fifth capacitor C y1_P The second terminal is grounded; Each sixth capacitor C xn The first end is connected to the positive busbar of the DC busbar (3), and the sixth capacitor C xn The second end is connected to the negative busbar of the DC busbar (3); All Y capacitors are connected to the same grounding plane, which is connected to the metal casing of the equipment.

9. The filter circuit according to claim 8, characterized in that, Sixth capacitor C xn The configuration is as an X capacitor; the X capacitor is connected in parallel between the positive and negative terminals of the DC bus (3), and the circuit parasitic inductance of the DC bus (3) is also connected. L s Multiple LC series resonant branches are formed; to address differential-mode interference, since the differential-mode interference currents are in the same direction and the magnetic flux cancels each other out, the busbar circuit inductance... L s = L 11 + L 22 -2 M First capacitor C yn_P Third capacitor C y2_P Fifth capacitor C y1_P Configured as a positive-side Y capacitor, the positive-side Y capacitor is connected in parallel between the positive busbar and ground, and the parasitic inductance of the positive branch of the DC busbar (3) is related to the inductance of the DC busbar (3). L 11 + M Resonance provides a low-impedance path from the positive terminal to ground for common-mode current; For common-mode interference, the inductance of the busbar branch is equal to the sum of its own inductance and mutual inductance. Since the common-mode interference currents are in the same direction, the magnetic flux is mutually reinforcing. Second capacitor C yn_N Fourth capacitor C y2_N Configured as a negative-side Y capacitor, the negative-side Y capacitor is connected in parallel between the negative busbar and ground, and the parasitic inductance of the negative branch of the DC busbar (3) is also connected to it. L 22 + M The resonance provides a return path for the common-mode current from ground to the negative terminal.

10. An electric drive system for a new energy vehicle, characterized in that, The system includes: a PDU board (1), a filter circuit (2), a DC busbar (3), an MCU board (4), and three magnetic rings (5); The high voltage DC output terminal of the PDU board (1) is connected to the input terminal of the filter circuit (2); The output terminal of the filter circuit (2) is connected to the input terminal of the DC bus (3); The output terminal of the DC bus (3) is connected to the input terminal of the MCU board (4); The three-phase AC output terminals of the MCU board (4) are connected to one end of each of the three magnetic rings (5), and the other end of each magnetic ring (5) is connected to the motor via a power cable.

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