A design method and system of a radiation-resistant gallium nitride driving circuit

Abstract

The application discloses a design method and system of an anti-radiation gallium nitride driving circuit, and the system comprises a first signal processing module, a second signal processing module, a signal detection module, a switch control module and a data selector module. The first signal processing module receives an external input signal and outputs a first driving signal; the signal detection module identifies whether there is an alternating current component in the external input signal, and outputs a low-level signal if there is the alternating current component, and outputs a high-level signal if there is no alternating current component; the data selector module selects the first driving signal under the low-level signal; the switch control module feeds the external input signal into the second signal processing module under the high-level signal, and the data selector module selects a second driving signal; and the input end of the second signal processing module is clamped to zero potential when the second signal processing module is not enabled, and a transistor for determining a flip threshold is in zero gate bias. The application can be used for gate driving in a space radiation environment.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and specifically to a design method and system for a radiation-resistant gallium nitride driving circuit. Background Technology

[0002] Gallium nitride high electron mobility transistors (HEMTs) have promising applications in aerospace power systems due to their advantages such as high breakdown voltage, low on-resistance, and high switching frequency. However, high-energy particles in the space irradiation environment generate a large number of electron-hole pairs inside the device, and some charge carriers are captured by defects and traps, causing irreversible drift of the threshold voltage with cumulative dose. For GaN-driven logic circuits, positive threshold voltage drift raises the low level, causing false turn-on, while negative drift leads to failure to turn off or even burnout. Existing research shows that this degradation rate depends not only on the cumulative dose but also on the bias state of the device during irradiation: the higher the gate-source voltage and the stronger the electric field in the gate region, the more severe the threshold voltage drift; while when the device is in the off state with zero gate-source voltage, the threshold voltage drift is significantly smaller.

[0003] To address logic distortion caused by radiation, Schmitt triggers, with their hysteresis characteristics, are used in GaN driver circuits. When placed in the preamplifier stage, they can shape noise-affected or edge-degraded input signals into steep square waves, preventing malfunctions in subsequent logic gates. When placed in the postamplifier stage, they can restore the logic swing attenuated by radiation, ensuring complete signal transmission in multi-stage driver chains. Furthermore, traditional radiation-hardened designs employ device hardening, process optimization, and functional redundancy, adding spare units to maintain system functionality and improve the reliability of aerospace electronic systems.

[0004] However, existing solutions have significant shortcomings. Schmitt triggers are themselves composed of GaN HEMTs, and under irradiation, their switching point also shifts with threshold drift. In severe cases, the output gets stuck at a fixed level, completely losing its shaping function. In traditional redundant structures, the primary and backup cells are exposed to the same irradiation environment. If the bias conditions are identical, the backup channel will degrade synchronously with the primary channel, failing to extend its lifespan. Furthermore, most existing Schmitt triggers are CMOS structures, lacking optimized designs for GaN devices, and fail to systematically integrate bias control strategies into the driver chain redundancy architecture, making it difficult to achieve zero-gate bias protection and automatic switching of the backup channel in standby mode. Summary of the Invention

[0005] This invention proposes a design method and system for a radiation-resistant gallium nitride driving circuit, which solves the problem that existing technologies cannot achieve differentiated degradation and automatic redundancy switching of primary and backup channels through bias control, leading to synchronous failure of primary and backup units.

[0006] To solve the above-mentioned technical problems, the present invention provides a radiation-resistant gallium nitride driving circuit system, comprising: a first signal processing module, a second signal processing module, a signal detection module, a switch control module, and a data selector module; The input terminal of the first signal processing module receives an external input signal and outputs a first drive signal; The signal detection module is used to identify whether there is an AC component in the first driving signal. When there is an AC component, it outputs a low-level control signal; otherwise, it outputs a high-level control signal. The first data input terminal of the data selector module is connected to the output terminal of the first signal processing module, the second data input terminal of the data selector module is connected to the output terminal of the second signal processing module, and the selection control terminal of the data selector module is connected to the output terminal of the signal detection module; when the signal detection module outputs a low-level control signal, the data selector module selects to output the first driving signal. The control terminal of the switch control module is connected to the output terminal of the signal detection module, the input terminal receives the external input signal, and the output terminal is connected to the input terminal of the second signal processing module. When the signal detection module outputs a high-level control signal, the switch control module enables the second signal processing module and inputs the external input signal into the second signal processing module. The output terminal of the second signal processing module outputs a second drive signal, and the data selector module selects to output the second drive signal. The second signal processing module includes a first-stage gallium nitride enhancement transistor. When the second signal processing module is not enabled, the input terminal of the second signal processing module is clamped to zero potential, so that the first-stage gallium nitride enhancement transistor is in zero gate bias.

[0007] Preferably, the first signal processing module and the second signal processing module each include an identical Schmitt trigger. Each Schmitt trigger includes an input resistor, a first load resistor, a second load resistor, a positive feedback resistor, a first-stage gallium nitride enhancement-mode transistor (GaN-EMT), and a second-stage GaN-EMT. One end of the input resistor serves as the input terminal of the Schmitt trigger, and the other end of the input resistor is connected to the gate of the first-stage GaN-EMT. The source of the first-stage GaN-EMT is grounded, and the drain of the first-stage GaN-EMT is connected to the power supply via the first load resistor. The drain of the first-stage GaN-EMT serves as the output terminal of the Schmitt trigger. The gate of the second-stage GaN-EMT is connected to the drain of the first-stage GaN-EMT, the source of the second-stage GaN-EMT is grounded, and the drain of the second-stage GaN-EMT is connected to the power supply via the second load resistor. The positive feedback resistor is connected between the drain of the second-stage GaN-EMT and the gate of the first-stage GaN-EMT.

[0008] Preferably, the signal detection module includes a high-pass filter branch, a voltage doubler rectifier branch, and an inverting and shaping branch; the high-pass filter branch is used to filter out the DC component in the first drive signal output by the first signal processing module and output an AC coupled signal; the voltage doubler rectifier branch converts the AC coupled signal into a DC detection voltage; the inverting and shaping branch compares the DC detection voltage with the inherent flip threshold of the inverting shaper in the inverting and shaping branch to generate the low-level control signal or the high-level control signal.

[0009] Preferably, the voltage doubler rectifier branch includes a first capacitor, a second capacitor, a first diode, a second diode, and a discharge resistor; one end of the first capacitor is connected to the output terminal of the high-pass filter branch, and the other end is connected to the cathode of the first diode and the anode of the second diode; the anode of the first diode is grounded; the cathode of the second diode is connected to one end of the second capacitor and serves as the output terminal of the voltage doubler rectifier branch, and the other end of the second capacitor is grounded; the discharge resistor is connected in parallel with the second capacitor, one end of the discharge resistor is connected to the cathode of the second diode, and the other end is grounded.

[0010] Preferably, both the first diode and the second diode are gate-source Schottky diodes, obtained by shorting the gate and drain of a gallium nitride enhancement-mode transistor.

[0011] Preferably, the switch control module includes a gallium nitride enhancement transistor (GaN-Enhanced Transistor), the gate of which is electrically connected to the output terminal of the signal detection module, the drain of which is used to receive external input signals, and the source of which is electrically connected to the input terminal of the second signal processing module; a pull-down resistor is connected between the input terminal of the second signal processing module and ground, and when the GaN-Enhanced Transistor is turned off, the input terminal of the second signal processing module is clamped to zero potential.

[0012] Preferably, the data selector module includes three sets of NAND gate logic circuits. The first input terminal of the first NAND gate logic circuit is connected to the output terminal of the first signal processing module, the second input terminal of the first NAND gate logic circuit is connected to the output terminal of the voltage doubler rectifier branch, and the output terminal of the first NAND gate logic circuit is connected to the first input terminal of the third NAND gate logic circuit. The first input terminal of the second NAND gate logic circuit is connected to the output terminal of the signal detection module as the selection control terminal, the second input terminal of the second NAND gate logic circuit is connected to the output terminal of the second signal processing module, and the output terminal of the second NAND gate logic circuit is connected to the second input terminal of the third NAND gate logic circuit. The output of the third NAND gate logic circuit is the total output of the data selector module.

[0013] Preferably, each NAND gate logic circuit includes two gallium nitride enhancement-mode transistors connected in series and a pull-up resistor connected to the power supply; the initial threshold voltage of the gallium nitride enhancement-mode transistor whose gate is connected to the output terminal of the voltage doubler rectifier branch in the first NAND gate logic circuit is lower than the inherent flip-flop threshold of the inverter shaper, and the initial threshold voltage of the other five gallium nitride enhancement-mode transistors in the data selector module is half of the power supply voltage.

[0014] This invention also provides a design method for a radiation-resistant gallium nitride (GaN) drive circuit, based on the aforementioned radiation-resistant GaN drive circuit system, comprising the following steps: Step S1: The data selector module selects the second drive signal and switches to the first drive signal after a preset delay. The signal detection module continuously monitors the waveform of the first drive signal. Step S2: When the signal detection module detects that there is a continuous AC component in the first drive signal, it outputs a low-level control signal. After receiving the low-level control signal, the data selector module outputs the first drive signal. Step S3: When the signal detection module detects that the first drive signal becomes a constant DC signal with no AC component, the signal detection module outputs a high-level control signal after a preset delay; the switch control module turns on the second signal processing module and inputs the external input signal into the second signal processing module, while the data selector module outputs the second drive signal.

[0015] Preferably, the signal detection module in step S3 includes a high-pass filter branch, and the cutoff frequency of the high-pass filter branch satisfies the following expression: ; In the formula, This is the cutoff frequency of the high-pass filter branch; The lowest operating frequency for external input signals; This is the resistance value of the filter resistor in the high-pass filter branch; This is the capacitance value of the filter capacitor in the high-pass filter branch.

[0016] The advantages of this invention include at least the following: 1. When the second signal processing module is not enabled, its input terminal is pulled down to zero potential, the gate of the first stage transistor has no bias voltage, and the degradation rate of the circuit that determines the switching threshold in the standby channel is lower than that of the continuously running main channel during standby, and the consumption rate of the threshold margin is reduced accordingly. 2. The signal detection module determines the main channel status by identifying the presence of an AC component in the first drive signal. This eliminates the need for complex physical parameter monitoring circuits; failure detection can be achieved solely through the signal's inherent characteristics. When the main channel's output locks to a DC level due to irradiation, the detection module immediately outputs a high-level control signal, triggering the switch control module to activate the second signal processing module and seamlessly switching to the backup output via a data selector. Channel switching is completed in the order of first connecting the backup branch and then disconnecting the main branch. The output maintains a consistent logic level throughout the switching process, without interruption, high impedance, or logical indeterminacy. The switching process requires no external intervention, enabling autonomous fault recovery of the drive channel. 3. The first signal processing module and the second signal processing module adopt a Schmitt trigger structure optimized for gallium nitride devices. The gate bias state of the first-stage transistor in the backup channel is directly controlled by the survival state of the main channel through the switching control signal. Compared with traditional process optimization or simple unit parallel connection, this design is more systematic and can effectively deal with the signal swing attenuation and logic disorder problems in multi-level logic chains. 4. The first-stage transistor of the backup channel is in a zero-gate bias state, which not only suppresses the threshold drift caused by irradiation, but also eliminates the electric field stress borne by the gate of this stage during standby. This makes the switching threshold margin of the backup channel stable during standby, improving the long-term reliability of the gallium nitride drive circuit in the space irradiation environment. Attached Figure Description

[0017] Figure 1 This is a system structure block diagram according to an embodiment of the present invention; Figure 2 This is a system circuit schematic diagram according to an embodiment of the present invention; Figure 3 This is a circuit schematic diagram of the first signal processing module in an embodiment of the present invention; Figure 4 This is a circuit schematic diagram of the signal detection module in an embodiment of the present invention; Figure 5 This is a circuit schematic diagram of the data selector module in an embodiment of the present invention; Figure 6 This is a circuit diagram of the switch control module in an embodiment of the present invention; Figure 7 This is a circuit schematic diagram of the second signal processing module in an embodiment of the present invention; Figure 8 This is a waveform timing diagram of key nodes during the operation of an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0019] Example 1 like Figure 1 and Figure 2 As shown, an embodiment of the present invention provides a radiation-resistant gallium nitride (GaN) driving circuit system, comprising a first signal processing module 100, a second signal processing module 200, a signal detection module 300, a switch control module 400, and a data selector module 500. All active devices are enhancement-mode N-channel GaN high electron mobility transistors, and all resistors are GaN two-dimensional electron gas resistors. The power supply voltage is... Take 8V. The first signal processing module 100 constitutes the main drive channel during normal operation, the second signal processing module 200 constitutes the backup drive channel in standby mode, the signal detection module 300 is responsible for identifying the existence status of the main drive channel, the switch control module 400 is responsible for enabling the backup drive channel after the main drive channel fails, and the data selector module 500 is responsible for completing the output selection between the two drive channels.

[0020] In terms of signal flow, the external input signal Vin is simultaneously connected to the input terminals of both the first signal processing module 100 and the switch control module 400. The output terminal of the first signal processing module 100 generates a first drive signal Vout1, which is sent to both the input terminal of the signal detection module 300 and the first data input terminal of the data selector module 500. The signal detection module 300 detects the first drive signal Vout1 and outputs a switching control signal S, which is simultaneously connected to both the control terminal of the switch control module 400 and the selection control terminal of the data selector module 500. The output terminal of the switch control module 400 is connected to the input terminal of the second signal processing module 200, which generates a second drive signal Vout2 and sends it to the second data input terminal of the data selector module 500. The output terminal Y of the data selector module 500 is the final output Vout of the entire drive circuit, directly driving the subsequent gallium nitride power device. Therefore, the working state of the main drive channel is converted into a switching control signal S by the signal detection module 300. The switching control signal S simultaneously determines whether the backup drive channel is fed with an external input signal and which drive signal is selected at the output. Both actions are uniformly governed by the same criterion and do not require external command intervention.

[0021] In this embodiment, the external input signal Vin is a periodic square wave signal with a duty cycle of 50%, an amplitude of 0V to 5V, and a minimum operating frequency of 1kHz. The minimum frequency of the external input signal is limited by the cutoff frequency of the high-pass filter branch in the signal detection module 300. The input signal frequency must be much higher than this cutoff frequency to ensure that the amplitude attenuation of the AC coupling signal is small enough, thereby ensuring that the voltage doubler rectifier branch outputs a sufficiently high DC detection voltage. The maximum frequency of the external input signal is limited by the switching speed of the gallium nitride high electron mobility transistor and the propagation delay of the resistor transistor logic gate. The design should be optimized according to the device speed of the process used.

[0022] like Figure 3As shown, the first signal processing module 100 adopts a resistive transistor logic Schmitt trigger structure, consisting of an input resistor R4, a first-stage gallium nitride enhancement-mode transistor M1, a second-stage gallium nitride enhancement-mode transistor M2, and three resistors R1, R2, and R3. One end of the input resistor R4 serves as the input terminal of the Schmitt trigger and receives the external input signal Vin, while the other end is connected to the gate of the first-stage transistor M1. The source of M1 is grounded, and its drain is connected to the power supply voltage VDD through the first load resistor R1. This drain also serves as the output terminal of the first signal processing module 100, outputting the first drive signal Vout1. The gate of the second-stage transistor M2 is connected to the drain of M1, and its source is grounded. The drain is connected to the power supply voltage VDD through the second load resistor R2. The positive feedback resistor R3 is connected between the drain of M2 and the gate of M1, forming a hysteresis loop. In this embodiment, resistors R1, R2, and R3 are all 10kΩ, and the input resistor R4 is 5kΩ.

[0023] Let the threshold voltage of transistor M1 be VTH. Then, when the external input signal rises from low level to high level, the flip-up point of the first signal processing module 100 is: .

[0024] When the external input signal falls from high level to low level, its down-flipping point is: .

[0025] The above two equations show that both the upper and lower flip points change linearly with the threshold voltage VTH of the first-stage transistor. Therefore, the threshold drift caused by irradiation will simultaneously shift the upper and lower boundaries of the hysteresis window. Substituting the parameters of this embodiment, taking the initial threshold voltage VTH as 2.5V, the upper flip point is approximately 3.75V, the lower flip point is approximately 1.125V, and the hysteresis window width is approximately 2.625V. Since the high level of the external input signal is 5V and the low level is 0V, the hysteresis window falls completely within the high and low level range of the external input signal. The first signal processing module 100 can reliably flip once for each input edge, outputting a complete square wave that is inversely phase to the external input signal.

[0026] It is important to note that the width variation of the hysteresis window itself does not constitute a failure criterion for the first signal processing module 100. Under irradiation conditions, the hysteresis window may shrink, widen, or shift entirely. As long as the upper flip point remains below the high level of the external input signal and the lower flip point remains above the low level of the external input signal, the first signal processing module 100 can still be driven by the input edge and flip normally. The first driving signal Vout1 remains a square wave carrying an AC component, and the main driving channel has not yet failed. Only when the threshold drift accumulates to the point where the upper flip point is higher than the high level of the external input signal, or the lower flip point is lower than the low level of the external input signal, will the input edge no longer be able to trigger flipping, and the output logic will be stuck. Therefore, in this embodiment, the failure mode of the main driving channel is clearly defined as the first driving signal Vout1 being stuck at a constant DC level.

[0027] Using the parameters of this embodiment, the above-mentioned failure process can be quantitatively explained. When irradiation causes the threshold voltage VTH to drift positively to 3.5V, the upper inversion point rises to approximately 5.25V, which is higher than the high level of the external input signal 5V. The input signal can no longer push M1 past the upper inversion point, and the first drive signal Vout1 is stuck at the high level corresponding to the power supply voltage VDD. When irradiation causes the threshold voltage VTH to drift negatively to 1.5V, the lower inversion point drops to approximately -0.125V, which is lower than the low level of the external input signal 0V. The input signal can no longer push M1 back to the lower inversion point, and the first drive signal Vout1 is stuck at the low level corresponding to the ground potential. In both of these cases, the first drive signal Vout1 loses its effective AC component and degenerates into a DC level, which is precisely the target state that the signal detection module 300 aims to identify. By combining the above two equations with the high and low levels of the external input signal, the maximum threshold drift margin allowed by the first signal processing module 100 can also be deduced. In this embodiment, the positive drift margin is about 0.83V and the negative drift margin is about 0.9V.

[0028] like Figure 4 As shown, the signal detection module 300 includes three parts: a high-pass filter branch, a voltage doubler rectifier branch, and an inverting and shaping branch. Its function is to convert the dynamic characteristic of whether the output waveform of the main drive channel carries an AC component into a stable DC level criterion, and then generate a switching control signal S. The reason for using an AC component as the criterion is that the failure of the first signal processing module 100 will inevitably manifest as the output being stuck at a constant DC level, while its normal operation will inevitably cause the output to periodically flip with the external input signal. The two states show a definite difference in the presence or absence of an AC component, and this criterion is not affected by small changes in the output swing or the drift of the hysteresis window.

[0029] The high-pass filter branch, consisting of filter capacitor C3 and filter resistor R5, forms a passive high-pass RC network. Its input is connected to the output of the first signal processing module 100, used to filter out the DC component in the first drive signal Vout1 and output an alternating positive and negative AC coupled signal. When the first drive signal Vout1 is a normal square wave, the high-pass filter branch outputs a reasonably large AC coupled signal; when the first drive signal Vout1 is stuck at a DC level, the output of the high-pass filter branch tends to zero. The cutoff frequency of this branch satisfies: ; In the formula, This is the cutoff frequency of the high-pass filter branch; The lowest operating frequency for external input signals; This is the resistance value of the filter resistor; This refers to the capacitance value of the filter capacitor. This constraint ensures that the amplitude attenuation of the AC-coupled signal is sufficiently small at the lowest operating frequency, thereby guaranteeing that the output voltage amplitude of the voltage doubler rectifier branch is always higher than the switching threshold of the inverting shaping branch. In this embodiment, C3 is set to 100nF and R5 to 100kΩ, with a cutoff frequency of approximately 16Hz. The lowest frequency of the external input signal is 1kHz, which is much higher than ten times the cutoff frequency, satisfying the above constraint. Designers can configure the capacitor according to the lowest signal frequency of the actual application, following the principle that the lowest operating frequency should not be lower than ten times the cutoff frequency. and The value of .

[0030] The voltage doubler rectifier branch consists of a first capacitor C1, a first diode D1, a second diode D2, a second capacitor C2, and a discharge resistor R6. It is used to convert the AC coupled signal into a DC detection voltage. One end of the first capacitor C1 is connected to the output terminal of the high-pass filter branch, which is the connection node between R5 and C3. The positive terminal of the first diode D1 is grounded, and the negative terminal is connected to the other end of the first capacitor C1 and the positive terminal of the second diode D2. The negative terminal of the second diode D2 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is grounded. The discharge resistor R6 is connected in parallel with the second capacitor C2, with one end connected to the negative terminal of the second diode D2 and the other end grounded. The negative terminal of the second diode D2 serves as the output terminal of the voltage doubler rectifier branch. During the negative half-cycle, the AC-coupled signal clamps the right-hand node of the first capacitor C1 to a negative potential approximately equal to the forward voltage drop of a diode, charging C1. During the positive half-cycle, the superposition of the charge on C1 and the signal raises the node potential to near the peak-to-peak value of the AC-coupled signal. This charge is then transferred to C2 via D2. This process repeats until a DC detection voltage, VDD, is established on C2, approximately equal to the peak-to-peak value of the AC-coupled signal minus the forward voltage drops of the two diodes. 2.Vf. Since this DC detection voltage depends on the peak-to-peak value of the AC coupling signal rather than the peak value on one side, its value does not change when the duty cycle of the external input signal deviates from 50%. Therefore, this detection scheme is also applicable to pulse width modulation drive applications with variable duty cycles.

[0031] Both the first diode D1 and the second diode D2 are constructed from gallium nitride enhancement-mode transistors (GaN transistors). Specifically, the gate and drain of the transistor are shorted together to serve as the positive terminal, while the source serves as the negative terminal. Unidirectional conduction is achieved using the Schottky barrier between the gate and source. The significance of this implementation is that all rectifier devices can be directly derived from the same transistor unit in a standard GaN process, without introducing any additional diode process steps or requiring P-channel devices. The forward voltage drop Vf of the gate-source junction Schottky diode depends on the gate Schottky barrier height and specific process conditions, typically ranging from 1.0V to 1.5V. With a power supply voltage VDD of 8V and a forward voltage drop Vf of 1.5V, the swing of the first drive signal Vout1 ranges from 0V to 8V, its AC coupling component peak value is approximately 4V, and the output DC detection voltage of the voltage doubler rectifier branch is approximately 5V.

[0032] Furthermore, the second capacitor C2 is charged only once per input cycle via the second diode D2 within one half-cycle of the AC coupled signal. Between these two charges, it continuously discharges through the discharge resistor R6. Therefore, the DC detection voltage inevitably carries a ripple with the same period as the external input signal. To prevent the valley of this ripple from crossing the flip-flop threshold of the inverting shaping branch and misjudging a normal state as a failure state, the discharge time constant must satisfy the ripple constraint: ; In the formula, This is the resistance value of the discharge resistor; This is the capacitance value of the second capacitor; This is the lowest operating frequency for the external input signal. Because the flip threshold of the inverter M3 is based on... The configuration is exactly the DC detection voltage. Half of the above constraint has a mathematical critical value of 1 / 2. This constraint is approximately 6.9 times greater, providing an additional margin for M3 threshold drift caused by irradiation and short-term jitter of the input signal. In this embodiment, the lowest operating frequency of the external input signal is 1kHz. The discharge resistor R6 is set to 100kΩ, the second capacitor C2 to 100nF, and the discharge time constant to 10ms, reaching ten times the lowest operating cycle of 1ms, thus satisfying the above constraint. At this point, the ripple valley value of the DC detection voltage is approximately 4.5V, still far higher than the 2.5V switching threshold. In this embodiment, the first capacitor C1 is set to 100nF, which is equivalent to the capacitance of the second capacitor.

[0033] The inverting shaping branch consists of an inverting shaper M3, its load resistor R8, and a gate series resistor R7. M3 and R8 together form a resistive transistor logic inverter. The source of M3 is grounded, and its drain is connected to the power supply voltage VDD through R8, serving as the output of the signal detection module 300. The gate is connected to the output of the voltage doubler rectifier branch through R7. The inverting shaping branch compares the DC detection voltage with the inherent flip-flop threshold of the inverting shaper M3, thereby generating a low-level control signal or a high-level control signal. To maximize the threshold drift margin, the initial threshold voltage of M3 should be set at the midpoint between the DC detection voltage and ground potential, i.e., satisfying: .

[0034] In this embodiment, the initial threshold voltage is approximately 2.5V. When the first signal processing module 100 is working normally, the DC detection voltage is approximately 5V, which is higher than the toggle threshold of M3. M3 is turned on, and its drain is pulled down to a low level, resulting in a low level for the switching control signal S. When the first signal processing module 100 fails, causing the first drive signal Vout1 to be stuck at a DC level, the AC coupling signal disappears, the second capacitor C2 discharges through the discharge resistor R6, and the DC detection voltage gradually decreases. Once it falls below the toggle threshold of M3, M3 is turned off, and its drain is pulled up to the power supply voltage VDD by the load resistor R8, resulting in a high level for the switching control signal S. It can be seen that the switching control signal S is low during normal operation and high when the main drive channel fails.

[0035] The above configuration provides a large detection margin for the inverting shaping branch. With a DC detection voltage of approximately 5V and a flip-flop threshold of approximately 2.5V, the detection margin is approximately 2.5V. Even if the threshold voltage of the inverting shaping unit M3 itself drifts by ±1V under irradiation, its flip-flop point remains well within the range defined by the DC detection voltage and ground potential, and the detection function is unaffected. This margin relationship can be uniformly expressed as: ; In the formula, This represents the threshold voltage drift caused by irradiation. This constraint quantifies the matching relationship between the power supply voltage, the forward voltage drop of the diode, and the irradiation degradation of the inverting shaping branch. Furthermore, the value of the gate series resistor R7 should be much smaller than the discharge resistor R6 to ensure that the gate of M3 can obtain a driving voltage that is essentially the same as the voltage across C2 during discharge. Since the gate of M3 has a high-impedance input, the current flowing through R7 in steady state is extremely small, and the voltage drop across R7 can be ignored. The main function of R7 is to limit the transient charging and discharging current of the gate. In this embodiment, R7 is 1kΩ and R6 is 100kΩ, which differs by two orders of magnitude, satisfying the constraint. Since the main body of the signal detection module 300 is composed of passive devices, only the transistor of the inverting shaping unit M3 is in an active state, and its input DC detection voltage is approximately 5V while the flip threshold is only 2.5V. The detection margin is much greater than the threshold drift that may occur under irradiation. Therefore, the cumulative irradiation dose required for the signal detection module 300 to fail is much higher than the logic failure dose of the first signal processing module 100.

[0036] like Figure 5 As shown, the data selector module 500 consists of three sets of resistor-transistor NAND gates. Each NAND gate consists of two series-connected gallium nitride enhancement-mode transistors and a pull-up resistor. The two transistors are connected in series, and the drain of the first transistor is connected to the power supply voltage through the pull-up resistor. The source of the first transistor is connected to the drain of the second transistor, and the source of the second transistor is grounded. The gates of the first and second transistors serve as the first and second input terminals of the NAND gate, respectively, and the drain of the first transistor serves as the output terminal of the NAND gate. Specifically, the first NAND gate is composed of transistors M6 and M7 and pull-up resistor R13, the second NAND gate is composed of transistors M9 and M10 and pull-up resistor R15, and the third NAND gate is composed of transistors M8 and M11 and pull-up resistor R14.

[0037] The connection relationship of the three NAND gates is as follows: the first input of the first NAND gate is connected to the output Vout1 of the first signal processing module 100, the second input is connected to the output of the voltage doubler rectifier branch, the level of this node is denoted as ~S, and its output is connected to the first input of the third NAND gate; the first input of the second NAND gate is connected to the switching control signal S output by the signal detection module 300, the second input is connected to the output Vout2 of the second signal processing module 200, and its output is connected to the second input of the third NAND gate; the output of the third NAND gate is the total output Y of the data selector module 500. Therefore, the logic function implemented by the data selector module 500 is to AND the first driving signal with ~S, AND the second driving signal with S, and then OR them. That is, when the switching control signal S is low, the output Y follows the first driving signal Vout1, and when the switching control signal S is high, the output Y follows the second driving signal Vout2.

[0038] It is worth noting that the second input of the first NAND gate is not directly taken from the output of the inverter M3, but from the output of the voltage doubler rectifier branch. This arrangement allows the enable level of the first selection branch to be directly provided by the DC detection voltage, which is naturally complementary to the switching control signal S in terms of level. There is no need to set up an additional inverter stage, which reduces the number of transistors in the active bias state and avoids the threshold drift of the additional inverter itself from introducing new failure points. When the first signal processing module 100 is working normally, the DC detection voltage is approximately 5V, therefore ~S is at a logic high level, the switching control signal S is at a logic low level, the first NAND gate outputs the inverted value of the first drive signal, the second NAND gate outputs a constant logic high level, and the third NAND gate reconstructs the first drive signal accordingly. The output terminal Y is equal to Vout1. When the first signal processing module 100 fails, the DC detection voltage drops to zero, therefore ~S is at a logic low level, the switching control signal S is pulled up to the power supply voltage and becomes a logic high level, the first NAND gate outputs a constant logic high level, the second NAND gate outputs the inverted value of the second drive signal, and the third NAND gate reconstructs the second drive signal accordingly. The output terminal Y is equal to Vout2.

[0039] The radiation tolerance of the data selector module 500 is determined by the initial threshold voltage of its internal transistors. In this embodiment, except for the input transistor M7 connected to the output of the doubler rectifier branch in the first NAND gate, the initial threshold voltage of the other NAND gate transistors is set to half the power supply voltage, i.e., 4V. The swing of the nodes connected to the gates of these transistors is from 0V to the power supply voltage. This value makes the allowable ranges of positive and negative drift symmetrical and simultaneously reach their maximum, which can be uniformly expressed as: ; In the formula, This is the initial threshold voltage of the transistor inside the NAND gate. For logic nodes with a swing of 0V to 8V, the tolerance range for both positive and negative drift is 4V.

[0040] The gate of input transistor M7 is connected to the ~S node, and its logic high level is the DC detection voltage output from the doubler rectifier branch. Instead of the power supply voltage, which is approximately 5V in this embodiment, its initial threshold voltage should be configured separately and must meet the following requirements: .

[0041] This constraint ensures that the moment ~S falls below the first NAND gate's toggle threshold is later than the moment the switching control signal S is pulled up, causing the two selection branches to overlap rather than discontinuously during channel switching, preventing both outputs from being simultaneously turned off. In this embodiment, the initial threshold voltage of M7 is 2V, lower than the toggle threshold of the inverter M3 (2.5V), and a 0.5V margin is left for their irradiation drift. At this time, the high-level decision margin of the ~S node is 3V, and the low-level decision margin is 2V, which is more balanced than the 1V and 4V when 4V is used. During normal operation, the gates of M7 and M3 are subjected to a DC detection voltage of approximately 5V, with the same bias conditions. The threshold drift direction and amplitude under irradiation are related, and the threshold order of the two is maintained during the degradation process.

[0042] like Figure 6 As shown, the switch control module 400 is implemented by an N-type gallium nitride enhancement-mode transistor Msw. The gate of Msw is connected to the output of the signal detection module 300 and receives the switching control signal S. The drain is connected to the external input signal Vin, and the source is connected to the input of the second signal processing module 200, i.e., node X. Node X is also connected in parallel with a pull-down resistor R16, the other end of which is grounded, to clamp the potential of node X to 0V when Msw is turned off.

[0043] When the first signal processing module 100 is working normally, the switching control signal S is low, the gate-source voltage of Msw is zero and it is in the off state, the transmission of external input signals to the backup drive channel is cut off, and the input terminal of the second signal processing module 200 is clamped to 0V by the pull-down resistor R16. When the first signal processing module 100 fails, the switching control signal S is pulled up to the power supply voltage VDD, Msw is turned on, and the external input signal Vin is directly transmitted to the input terminal of the second signal processing module 200 through Msw. The backup drive channel then starts working and outputs the second drive signal Vout2.

[0044] To ensure that external input signals can be reliably transmitted to the second signal processing module 200 when Msw is turned on, two constraints need to be met. First, Msw itself should be fully turned on when the switching control signal is high and reliably turned off when the switching control signal is low. This requirement can be expressed as follows: .

[0045] Secondly, the actual output voltage of the Msw source should be higher than the upper flip point of the second signal processing module 200 to ensure that the backup drive channel can be triggered and flipped normally. This requirement can be expressed as follows: ; In the formula, and These represent the high and low levels of the external input signal, respectively. The threshold voltage of Msw; This represents the Msw threshold voltage drift caused by irradiation. The conduction current of Msw; Let Msw be the on-resistance; This is the flip-over point for the second signal processing module. In this embodiment, the power supply voltage VDD is 8V, and the external input signal high level is 5V, with a difference of 3V. The threshold voltage of Msw is 1.5V. This threshold voltage should be as small as possible during design. In this embodiment, the value leaves a margin of approximately 1.5V for the small threshold drift caused by irradiation. The on-resistance of gallium nitride high electron mobility transistors is in the tens to hundreds of milliohms range, and the on-current is in the milliampere range. Therefore, the on-voltage drop is negligible relative to the amplitude of the external input signal. The source voltage of Msw is approximately 5V, which is much higher than the flip-over point of approximately 3.75V for the second signal processing module 200. Designers should design and verify according to the above two formulas based on the actual parameters of the process used.

[0046] Regarding irradiation degradation, for most of the normal operation of the first signal processing module 100, the gate-source voltage of the switch control module 400 is zero, and the drain-source voltage varies between 0V and 5V with the external input signal, placing it in a zero-gate bias off state. Based on the physical law described above that the irradiation degradation rate of gallium nitride devices is highly dependent on the bias electric field, the threshold voltage drift rate of Msw in this state is much lower than that of the transistor in the active bias state. Therefore, the cumulative irradiation dose required to reach failure is higher than the logic failure dose of the first signal processing module 100.

[0047] like Figure 7As shown, the second signal processing module 200 and the first signal processing module 100 adopt the same resistive transistor logic Schmitt trigger topology and the same component parameters, consisting of an input resistor R9, a first-stage gallium nitride enhancement-mode transistor M4, a second-stage gallium nitride enhancement-mode transistor M5, and three resistors R10, R11, and R12. One end of the input resistor R9 serves as the input terminal of this module and is connected to the output terminal of the switch control module 400, while the other end is connected to the gate of M4. The source of M4 is grounded, and its drain is connected to the power supply voltage VDD through the first load resistor R10. This drain serves as the output terminal of the second signal processing module 200 and outputs the second drive signal Vout2. The gate of M5 is connected to the drain of M4, its source is grounded, and its drain is connected to the power supply voltage VDD through the second load resistor R11. The positive feedback resistor R12 is connected between the drain of M5 and the gate of M4. Since the topology and parameters of the two drive channels are completely identical, the second drive signal output after the backup drive channel takes over is consistent with the first drive signal in terms of phase, swing and edge characteristics, and no adaptation is required for the subsequent power devices.

[0048] The core of this invention lies in the bias state of the second signal processing module 200 when it is not enabled. During standby, Msw in the switch control module 400 is turned off, and the input terminal of the second signal processing module 200 is clamped to 0V by the pull-down resistor R16. Therefore, the gate potential of the first-stage transistor M4, which determines the switching threshold, is zero, its source is grounded, and the gate-source voltage is zero. At the same time, the drain is connected to the power supply voltage through the load resistor R10. M4 is thus in a zero-gate bias off state. In this state, the two-dimensional electron gas concentration in the channel of M4 is maintained at a very low level, the electric field intensity near the gate region and the heterojunction interface is significantly reduced, and the capture probability of irradiated induced carriers in the gate edge and buffer layer traps decreases accordingly. The drift rate of the threshold voltage is therefore lower than that of M1 in the continuously active first signal processing module 100.

[0049] Meanwhile, during standby, the output Vout2 of the second signal processing module 200 is pulled up to the power supply voltage VDD by the load resistor R10. The gate of the second-stage transistor M5 thus withstands the power supply voltage and remains on for an extended period, resulting in bias stress in the gate-source and drain-source directions. This causes a certain degree of degradation in parameters such as transconductance and on-resistance. However, the switching threshold of the Schmitt trigger is dominated by the threshold voltage of the first-stage transistor. The second-stage transistor primarily performs the output driving function, and its transconductance decrease and on-resistance change, within a fairly wide range, do not alter the switching criterion of the first-stage transistor, thus preventing the Schmitt trigger's logic switching function from failing. Therefore, the conclusion of near-zero bias under low electric field is valid for the first-stage transistor M4 and the MSw in the switch control module 400. The threshold margin of the backup drive channel is solely dominated by the first-stage transistor M4, and the zero-gate bias standby state of M4 is sufficient to ensure that the backup drive channel still has sufficient threshold margin when the main drive channel fails.

[0050] To quantitatively characterize the aforementioned differentiated degradation process, let the expression for the threshold voltage drift of a gallium nitride high electron mobility transistor under irradiation conditions be: ; In the formula, This represents the cumulative irradiation dose. and These are the gate-source voltage and drain-source voltage, respectively. Irradiation time, The operating temperature is [value]. Applying this function to the main drive channel and the standby drive channel respectively, we get: ; ; In the formula, the subscripts m and b represent the main drive channel and the standby drive channel, respectively. Since the gate-source voltage of the first-stage transistor in the standby drive channel is approximately zero during standby, i.e. Approximately zero and significantly smaller than the main drive channel Therefore, under the same cumulative irradiation dose conditions, we have: .

[0051] This results in a differentiated degradation process between the two drive channels. Further, let Vmargin be the maximum threshold drift margin allowed by the drive logic circuit. The cumulative irradiation dose corresponding to when the main drive channel reaches the failure threshold. If the cumulative irradiation dose corresponding to the failure threshold of the backup drive channel is given, then the failure condition of the main drive channel is: ; The conditions under which the backup drive channel can reliably take over are: ; That is, requirements Greater than Therefore, the lifetime extension factor is defined as follows: .

[0052] A lifetime extension factor greater than one indicates that the backup drive channel still maintains effective functional margin even when the main drive channel has reached the failure dose.

[0053] The specific value of the lifetime extension factor depends on the dose drift profile of the device under the process conditions used. Under the same cumulative irradiation dose, the threshold drift of a zero-gate bias off-state device is significantly smaller than that of an on-state device with a positive gate-source voltage, and the threshold drift exhibits a non-linear saturation variation with cumulative dose. Therefore, the cumulative dose required for the backup drive channel to reach its maximum threshold drift margin is... Higher than the main drive channel Lifetime extension factor Greater than one. Designers should take values ​​point by point according to the dose drift curve obtained by actual measurement of the device under actual process conditions, and calculate accordingly. , and The specific values ​​are given, where the dosage unit is the absorbed dose of the silicon material.

[0054] Based on the above bias control mechanism, the radiation resistance characteristics of each main module in this embodiment can be summarized as follows. In the working state, the first signal processing module 100's internal transistors continuously withstand gate-source and drain-source voltages, resulting in a long-term establishment of a two-dimensional electron gas channel. The gate edge and buffer layer traps continuously participate in the carrier capture process. Therefore, it is most prone to threshold voltage drift during total dose irradiation and is the fastest degrading component in the entire driving circuit. During standby, the second signal processing module 200's first-stage transistors maintain a zero-gate bias cutoff state. Its threshold voltage drift amplitude is smaller than that of the continuously operating first signal processing module 100. Under the same cumulative dose, it still maintains sufficient threshold margin and can serve as an alternative driving path after the main driving channel fails. The signal detection module 300 is mainly composed of passive devices, is less affected by irradiation, and its output amplitude of the voltage doubler rectifier branch is much higher than the switching threshold of the inverting shaping branch, giving it excellent tolerance for threshold voltage drift. When the first signal processing module 100 is operating normally, the switch control module 400 is in a zero-gate bias off state, the transistor is cut off, and the threshold voltage drift is much smaller than in the active operating state. The data input and selection control terminals of the data selector module 500 are both at a defined logic level in steady state. The logic high level of each NAND gate output is passively achieved by pull-up resistors, and the logic low level is achieved by pull-down transistors in series. Furthermore, the output path is only changed at the moment of switching. By setting the initial threshold voltage to half the power supply voltage, it can be ensured that the threshold drift of a single transistor will not cause logic function errors within a wide range.

[0055] The preceding sections provide specific parameter values ​​for each module. However, for those skilled in the art, the parameter selection for each module is not independent but rather constrained by system-level quantitative co-design rules. These rules collectively ensure that the entire drive circuit can still perform the complete function from fault detection to standby switching even when the threshold voltage of the gallium nitride high electron mobility transistor experiences irradiation drift. Overall, the system needs to meet the following requirements: ; In the formula, , , and These are the cumulative irradiation doses corresponding to the failures of the signal detection module 300, switch control module 400, second signal processing module 200, and first signal processing module 100, respectively. The physical meaning of these constraints is that when the main drive channel fails due to irradiation degradation, the signal detection module must still be able to complete fault identification, the switch control module must still be able to perform conduction, and the backup drive channel must still have sufficient threshold margin to take over the drive function; if any component fails before the main drive channel, the entire redundant system cannot complete an effective switchover. Therefore, this embodiment does not reinforce a single module in isolation, but rather uses four methods—bias state control, detection margin design, logic threshold configuration, and switching timing design—to uniformly raise the failure dose of all auxiliary components to above the failure dose of the main drive channel.

[0056] To achieve the above constraints, this embodiment ensures the irradiation lifetime of each stage through the following methods. During standby, the second signal processing module 200 is placed in a zero-gate bias off state via a pull-down resistor, and its irradiation degradation rate is much lower than that of the actively operating main drive channel, thereby ensuring... Greater than The switch control module 400 is also in a zero-gate bias off state when the first signal processing module 100 is working normally, the transistor is cut off, and its threshold drift amplitude is much smaller than that of the active working state, thereby ensuring Greater than The signal detection module 300 is quantitatively designed using the output voltage constraint of the rectifier unit and the cutoff frequency constraint of the filter branch, as described above. This ensures that the flip point of the inverting shaper remains far from the decision interval boundary defined by the DC detection voltage and ground potential within a threshold drift range of ±1V, thereby ensuring... Greater than The data selector module 500 sets the initial threshold voltage of its internal transistors to half the power supply voltage, thus ensuring that the allowable drift range in both the positive and negative directions is half the power supply voltage. The input transistor M7, which receives the output of the voltage doubler rectifier branch, has its gate swing upper limit set to the DC detection voltage rather than the power supply voltage, and its initial threshold voltage is set separately to VTH(M7). <VDD / 2 The Vf configuration expands the decision margin of this node and ensures that channel switching is completed in the order of on-the-fly, thus maintaining correct logic gating function throughout the switching process. Furthermore, the switching action must also meet the detection response timing constraint, that is, the delay time between signal detection and output switching must be shorter than the maximum duration of the error level allowed by the subsequent circuitry. This constraint will be given in the next section in conjunction with specific timing details.

[0057] like Figure 8As shown, in conjunction with the specific circuits of the aforementioned modules, the complete working process of this embodiment can be described in four stages: power-on initialization, normal operation, fault detection, and channel switching.

[0058] During the power-on initialization phase, the second capacitor C2 has not yet built up charge, the output of the voltage doubler rectifier branch is zero, the inverter M3 is cut off, and the switching control signal S is pulled up to the power supply voltage, thus presenting a high level. Therefore, the data selector module 500 briefly selects the output of the second signal processing module 200. As the external input signal is shaped by the first signal processing module 100 and coupled through the high-pass filter branch for the first few cycles, the second capacitor C2 is quickly charged to about 5V. The switching control signal S flips to a low level, the switch control module 400 is turned off, and the data selector module 500 then switches to select the first drive signal, and the main drive channel enters normal operation. This transient process requires several cycles of the external input signal, and its duration mainly depends on the capacitance ratio of the first capacitor to the second capacitor and the frequency of the external input signal. It is usually several times the period of the external input signal, and in this embodiment, it is about several milliseconds. Since the output logic of the two signal processing modules is completely consistent, this transient process will not have a substantial impact on the subsequent power devices.

[0059] exist Figure 8 During the period from 0 to t0, the first signal processing module 100 operates normally, the first drive signal Vout1 outputs a square wave that is out of phase with the external input signal Vin, the switching control signal S output by the signal detection module 300 remains at a low level, the Msw in the switch control module 400 is turned off, the input terminal of the second signal processing module 200 is pulled down to 0V and is in a zero-gate bias standby state, and the output terminal Y of the data selector module 500 follows the first drive signal Vout1.

[0060] At time t0, cumulative irradiation causes a severe positive drift in the threshold voltages of M1 and M2 within the first signal processing module 100, raising the flip point above the high level of the external input signal. The first drive signal Vout1 is stuck at the high level corresponding to the power supply voltage VDD. If the threshold voltage experiences a severe negative drift, the first drive signal Vout1 is stuck at ground potential. From this moment onward, the signal detection module 300 begins to identify abnormal outputs from the main drive channel.

[0061] During the period from t0 to t1, the DC level of the first drive signal is zero after passing through the high-pass filter branch. The second capacitor C2 discharges through the discharge resistor R6, and the output voltage of the double voltage rectifier branch gradually decreases. That is, the gate input voltage of the inverting shaper M3 gradually decreases, and the drain output voltage of M3, i.e., the switching control signal S, gradually increases.

[0062] At time t1, the voltage across the second capacitor C2, i.e., ~S, drops below the toggling threshold of the inverting shaper M3. M3 is turned off, and its drain is pulled up by the load resistor R8. The switching control signal S rises rapidly and successively surpasses the threshold voltage of Msw in the switching control module 400 and the toggling threshold of M9 in the data selector module 500. Msw turns on, and the external input signal Vin is fed into the second signal processing module 200. The backup drive channel then starts to output a square wave Vout2 that is inverted from the external input signal. At the same time, the second NAND gate is selected and starts to output the inverted value of the second drive signal.

[0063] During the time interval t1 to t2, although ~S is lower than the toggle threshold of M3, it is still higher than the toggle threshold of the input transistor M7 in the first NAND gate. The first NAND gate has not yet been turned off and is still outputting the inverted value of the first drive signal. At this time, the two selection branches are in an overlapping conduction state, and the output of the third NAND gate is the logical OR of the first drive signal and the second drive signal. Since the first drive signal is stuck at the high level corresponding to the power supply voltage, the output terminal Y continues to remain at a high level.

[0064] At time t2, ~S drops below the toggling threshold of M7, the input transistor of the first NAND gate is cut off, and the output of the first NAND gate is a constant logic high level. The third NAND gate then reconstructs the second drive signal, and the output Y returns to a normal square wave, thus restoring the drive function. Therefore, channel switching is completed in the order of first connecting the backup branch and then disconnecting the main branch. The output maintains a definite logic level throughout the switching process, without interruption, high impedance, or level clamping caused by simultaneous shutdown of both channels. If the first signal processing module 100 causes the first drive signal to be stuck at ground potential due to a negative threshold voltage drift, then the output Y will be equal to the second drive signal during the time interval t1 to t2, and the output will recover earlier. The above conclusion also holds true.

[0065] Regarding the quantitative design of the switching delay, in this embodiment, the second capacitor C2 is 100nF, and the discharge resistor R6 is 100kΩ, forming a discharge circuit with a discharge time constant of 10ms. During normal operation, the voltage across the second capacitor C2 is approximately 5V. After the main drive channel fails, this voltage decays exponentially from 5V. The switching threshold of the inverter M3 is 2.5V. Therefore, the time required from the occurrence of the fault to the activation of the backup drive channel is approximately 6.9ms, and the time required for the output to fully switch to the second drive signal is approximately 9.2ms. These two can be described as detection response timing constraints: ; ; In the formula, The delay time between signal detection and output switching; This is the maximum allowed error level duration for the subsequent circuitry. During this delay, the output Y initially remains high following the locked first drive signal Vout1. After ~S drops below the data selector's toggle threshold, it switches to following the second drive signal. Both phases are defined logic levels, not high-impedance states, and the gate potential of the subsequent power devices remains constant. Designers can adjust the ripple constraint based on the maximum allowed error level duration for the subsequent circuitry. Reduce discharge resistance within the allowable range With the second capacitor The value of is used to shorten the switching delay; by combining the ripple constraint and the above detection response timing constraint, we can obtain . In this embodiment, approximately In other words, the switching delay of this scheme has a lower limit that is linked to the minimum operating frequency of the external input signal. Therefore, when the maximum duration of the error level allowed by the subsequent circuit is short, the minimum operating frequency of the external input signal should be increased accordingly. Conversely, when the subsequent circuit is more tolerant of the error level, the values ​​of both can be appropriately increased to improve the immunity to short-term loss of input signal.

[0066] As can be seen from the above working process, the threshold drift state of the first signal processing module 100 is read by the signal detection module 300 via the AC component of the first drive signal and converted into a switching control signal. This switching control signal determines whether the switch control module 400 feeds an external input signal to the backup drive channel, and also determines the selection path of the data selector module 500. Whether the backup drive channel is fed an input signal, in turn, determines whether its first-stage transistor maintains zero gate bias during standby, and thus determines the irradiation degradation rate of the backup drive channel itself. It is precisely because the bias state of the backup drive channel is always dominated by the existence state of the main drive channel that the threshold margin of the backup drive channel is no longer consumed synchronously with the main drive channel as the cumulative dose increases, and the effective working life of the drive system can exceed the simple sum of the lifespans of the two channels.

[0067] Example 2 This embodiment provides a parameter configuration suitable for low power supply voltage and high switching frequency applications. Its circuit topology and connections are identical to those in Embodiment 1, the only difference being that the component parameter values ​​are adjusted accordingly based on the power supply voltage and operating frequency. In this embodiment, the power supply voltage VDD is 6V, the external input signal Vin is a pulse width modulation signal with a variable duty cycle, an amplitude ranging from 0V to 3.3V, and a switching frequency of 100kHz.

[0068] In the first signal processing module 100 and the second signal processing module 200, resistors R1, R2, R3, R10, R11, and R12 are all 8.2kΩ, input resistors R4 and R9 are both 4.7kΩ, and the initial threshold voltage of the first-stage transistor is 1.7V. From the expressions for the upper and lower flip points, the upper flip point is approximately 2.67V, the lower flip point is approximately 0.47V, and the hysteresis window width is approximately 2.20V, falling entirely within the external input signal level range of 0V to 3.3V. The main drive channel can reliably flip at each input edge.

[0069] In the signal detection module 300, since the lowest operating frequency of the external input signal is 100kHz, according to the principle that the cutoff frequency should not be higher than one-tenth of the lowest operating frequency, the cutoff frequency should not be higher than 10kHz. In this embodiment, the filter capacitor C3 is 1nF and the filter resistor R5 is 100kΩ, and the cutoff frequency is approximately 1.6kHz, which satisfies the above constraint. The forward voltage drop of the gate-source junction Schottky diode is assumed to be 1.0V, the DC detection voltage of the voltage doubler rectifier branch is approximately 4V, and the initial threshold voltage of the inverting shaper M3 is set to 2V, which is half of the power supply voltage minus the forward voltage drop, with a detection margin of approximately 2V. The first capacitor C1 is 10nF, the second capacitor C2 is 10nF, the discharge resistor R6 is 10kΩ, and the discharge time constant is 0.1ms, which is ten times the 10μs period of the 100kHz input signal, satisfying the ripple constraint. The delay time from the occurrence of the fault to the completion of the switching control signal is about 69μs, which is suitable for situations where the maximum allowable error level duration of the subsequent circuit is on the order of hundreds of microseconds. The gate series resistor R7 is 100Ω, which is also two orders of magnitude different from the discharge resistor R6.

[0070] In the switch control module 400, the threshold voltage of Msw is 1.2V, and the difference between the power supply voltage and the high level of the external input signal is 2.7V, which is about 1.5V higher than the threshold voltage, leaving a margin for threshold drift caused by irradiation. When Msw is turned on, its source voltage is about 3.3V, which is about 2.67V higher than the upper flip point of the second signal processing module 200. In the data selector module 500, except for the input transistor in the first NAND gate that receives the output of the doubler rectifier branch, the initial threshold voltage of the transistors inside each NAND gate is half of the power supply voltage, i.e., 3V. The initial threshold voltage of the input transistor is 1.5V, which is lower than the 2V flip threshold of the inverter M3, and its high and low level decision margins are 2.5V and 1.5V, respectively. The time from the occurrence of the fault to the activation of the backup drive channel is about 69μs, and the time to the complete switching of the output is about 98μs. The working process of this embodiment is completely the same as that of Embodiment 1. The difference is that all time parameters are shortened proportionally, and the ratio of switching delay to switching cycle is maintained at a level comparable to that of Embodiment 1.

[0071] Example 3 This embodiment provides a parameter configuration suitable for applications with high power supply voltage, low operating frequency, and where the subsequent circuitry is relatively tolerant of error levels. Its circuit topology and connections are identical to those in Embodiment 1. In this embodiment, the power supply voltage VDD is 10V, the external input signal Vin is a clock signal with a 50% duty cycle, an amplitude of 0V to 5V, and an operating frequency of 100Hz.

[0072] In the first signal processing module 100 and the second signal processing module 200, resistors R1, R2, R3, R10, R11, and R12 are all 20kΩ, and input resistors R4 and R9 are both 10kΩ. The initial threshold voltage of the first-stage transistor is 2.8V. Therefore, the upper flip point is approximately 4.2V, the lower flip point is approximately 1.0V, and the hysteresis window width is approximately 3.2V, falling entirely within the 0V to 5V level range of the external input signal. Compared to Embodiment 1, this embodiment has a wider hysteresis window and stronger suppression capability against superimposed noise in the input signal. However, the margin between the upper flip point and the high level of the external input signal is correspondingly reduced to approximately 0.8V, thus placing higher demands on the process consistency of the initial threshold voltage of the first-stage transistor.

[0073] In the signal detection module 300, the minimum operating frequency of the external input signal is 100Hz. According to the aforementioned principle, the cutoff frequency should not exceed 10Hz. In this embodiment, the filter capacitor C3 is 220nF and the filter resistor R5 is 100kΩ, resulting in a cutoff frequency of approximately 7.2Hz, which meets the constraints. The forward voltage drop of the gate-source junction Schottky diode is assumed to be 1.5V. The DC detection voltage of the voltage doubler rectifier branch is approximately 7V. The initial threshold voltage of the inverter M3 is set to 3.5V, resulting in a detection margin of approximately 3.5V, the largest among the three embodiments. The first capacitor C1 is 1μF, the second capacitor C2 is 1μF, and the discharge resistor R6 is 100kΩ. The discharge time constant is approximately 100ms, which is ten times the 10ms period of the 100Hz input signal, meeting the ripple constraints. The delay time from the occurrence of a fault to the completion of the switching control signal's flip is approximately 69ms, suitable for low-frequency drive applications where the subsequent circuit allows for error levels lasting tens of milliseconds.

[0074] In the switch control module 400, the threshold voltage of Msw is 2V, and the difference between the power supply voltage and the high level of the external input signal is 5V, exceeding this threshold voltage by 3V. When Msw is turned on, its source voltage is approximately 5V, exceeding the approximately 4.2V flip-over point of the second signal processing module 200. In the data selector module 500, except for the input transistor in the first NAND gate that receives the output of the doubler rectifier branch, the initial threshold voltage of the transistors inside each NAND gate is 5V. For logic nodes with a swing range of 0V to 10V, the allowable drift range for both positive and negative directions reaches 5V. The initial threshold voltage of this input transistor is 3V, lower than the 3.5V flip-over threshold of the inverter M3, and the 7V high level output of the doubler rectifier branch has a 4V margin relative to this threshold. The time from the occurrence of a fault to the activation of the backup drive channel is approximately 69ms, and the time to complete switching at the output is approximately 85ms.

[0075] In the three embodiments described above, the initial threshold voltage values ​​of the transistors within different modules are different. For example, the initial threshold voltage of the first-stage transistor in the signal processing module is not equal to the initial threshold voltage of the NAND gate transistor in the data selector module. On the same gallium nitride process platform, different equivalent flip-flop thresholds can be achieved by adjusting the etching depth of the gate trench, adjusting the thickness and magnesium doping concentration of the pGaN gate layer, or setting a voltage divider resistor network at the gate front end, etc., without introducing additional masks or process steps.

[0076] Example 4 This embodiment provides a design method for a radiation-resistant gallium nitride drive circuit, including the following steps: Step S1: The data selector module connects to the second signal processing module and switches to the first signal processing module after a preset delay. The signal detection module continuously monitors the waveform of the first signal processing module. This step corresponds to the circuit power-on initialization process. At the moment of power-on, the second capacitor in the voltage doubler rectifier branch has not yet built up charge, its output is zero, the inverting shaper is cut off, and the switching control signal is high. Therefore, the data selector module first selects the output of the second signal processing module. As the first few cycles of the external input signal are shaped by the first signal processing module and coupled through the high-pass filter branch, the second capacitor is charged to a level close to the power supply voltage minus the forward voltage drop of the two diodes. The switching control signal flips to low, and the data selector module switches to the first signal processing module. This preset delay is determined by the capacitance ratio of the first capacitor to the second capacitor and the frequency of the external input signal, and is usually several times the period of the external input signal.

[0077] Step S2: When the signal detection module detects a continuous AC component in the first drive signal, it outputs a low-level control signal. Upon receiving this low-level control signal, the data selector module outputs the first drive signal. This step corresponds to the steady-state process of the main drive channel during normal operation. At this time, the switch control module remains off, the input of the second signal processing module is clamped to zero potential by a pull-down resistor, and its first-stage transistor maintains a zero-gate bias off state. The threshold margin of the backup drive channel is hardly consumed during this period.

[0078] Step S3: When the signal detection module detects that the first drive signal has become a constant DC signal without any AC component, the signal detection module outputs a high-level control signal after a preset delay. The switch control module then turns on the second signal processing module and inputs the external input signal into it. Simultaneously, the data selector module outputs the second drive signal. The preset delay in this step is determined by the second capacitor and the discharge resistor of the voltage doubler rectifier branch. Its expression is the aforementioned detection response timing constraint, and its value should be shorter than the maximum allowed duration of the error level in the subsequent circuit. Throughout the switching process, the output of the drive circuit maintains a valid logic level output without interruption or high impedance.

[0079] In step S3, the signal detection module includes a high-pass filter branch. The cutoff frequency of this high-pass filter branch satisfies the aforementioned cutoff frequency constraint, namely, the cutoff frequency is not higher than one-tenth of the lowest operating frequency of the external input signal. This constraint ensures that the amplitude attenuation of the AC coupling signal is sufficiently small at the lowest operating frequency, thereby ensuring that the output voltage amplitude of the voltage doubler rectifier branch is always higher than the switching threshold of the inverting shaping branch, and preventing the normal operating state from being mistakenly judged as a failure state.

[0080] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described; only preferred embodiments of the present invention are illustrated. The descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. As long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0081] It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of this invention. Therefore, the scope of protection of this invention should be determined by the appended claims.

Claims

1. A radiation-resistant gallium nitride driving circuit system, characterized in that, include: The system comprises a first signal processing module, a second signal processing module, a signal detection module, a switch control module, and a data selector module. The input terminal of the first signal processing module receives an external input signal and outputs a first drive signal; The signal detection module is used to identify whether there is an AC component in the first driving signal. When there is an AC component, it outputs a low-level control signal; otherwise, it outputs a high-level control signal. The first data input terminal of the data selector module is connected to the output terminal of the first signal processing module, the second data input terminal of the data selector module is connected to the output terminal of the second signal processing module, and the selection control terminal of the data selector module is connected to the output terminal of the signal detection module; when the signal detection module outputs a low-level control signal, the data selector module selects to output the first driving signal. The control terminal of the switch control module is connected to the output terminal of the signal detection module, the input terminal receives the external input signal, and the output terminal is connected to the input terminal of the second signal processing module. When the signal detection module outputs a high-level control signal, the switch control module enables the second signal processing module and inputs the external input signal into the second signal processing module. The output terminal of the second signal processing module outputs a second drive signal, and the data selector module selects to output the second drive signal. The second signal processing module includes a first-stage gallium nitride enhancement transistor. When the second signal processing module is not enabled, the input terminal of the second signal processing module is clamped to zero potential, so that the first-stage gallium nitride enhancement transistor is in zero gate bias.

2. The radiation-resistant gallium nitride driving circuit system according to claim 1, characterized in that: The first signal processing module and the second signal processing module each include an identical Schmitt trigger. Each Schmitt trigger includes an input resistor, a first load resistor, a second load resistor, a positive feedback resistor, a first-stage gallium nitride enhancement-mode transistor (GaN-EMT), and a second-stage GaN-EMT. One end of the input resistor serves as the input terminal of the Schmitt trigger, and the other end of the input resistor is connected to the gate of the first-stage GaN-EMT. The source of the first-stage GaN-EMT is grounded, the drain of the first-stage GaN-EMT is connected to the power supply via the first load resistor, and the drain of the first-stage GaN-EMT serves as the output terminal of the Schmitt trigger. The gate of the second-stage gallium nitride enhancement-mode transistor is connected to the drain of the first-stage gallium nitride enhancement-mode transistor, the source of the second-stage gallium nitride enhancement-mode transistor is grounded, and the drain of the second-stage gallium nitride enhancement-mode transistor is connected to the power supply through the second load resistor. The positive feedback resistor is connected between the drain of the second-stage gallium nitride enhancement transistor and the gate of the first-stage gallium nitride enhancement transistor.

3. The radiation-resistant gallium nitride driving circuit system according to claim 1, characterized in that: The signal detection module includes a high-pass filter branch, a voltage doubler rectifier branch, and an inverting and shaping branch. The high-pass filter branch is used to filter out the DC component in the first drive signal output by the first signal processing module and output an AC coupled signal. The voltage doubler rectifier branch converts the AC coupled signal into a DC detection voltage. The inverting and shaping branch compares the DC detection voltage with the inherent flip threshold of the inverting shaper in the inverting and shaping branch to generate the low-level control signal or the high-level control signal.

4. The radiation-resistant gallium nitride driving circuit system according to claim 3, characterized in that: The voltage doubler rectifier branch includes a first capacitor, a second capacitor, a first diode, a second diode, and a discharge resistor; one end of the first capacitor is connected to the output terminal of the high-pass filter branch, and the other end is connected to the cathode of the first diode and the anode of the second diode; the anode of the first diode is grounded; the cathode of the second diode is connected to one end of the second capacitor and serves as the output terminal of the voltage doubler rectifier branch, and the other end of the second capacitor is grounded; the discharge resistor is connected in parallel with the second capacitor, one end of the discharge resistor is connected to the cathode of the second diode, and the other end is grounded.

5. The radiation-resistant gallium nitride driving circuit system according to claim 4, characterized in that: Both the first diode and the second diode are gate-source Schottky diodes, which are obtained by shorting the gate and drain of a gallium nitride enhancement-mode transistor.

6. The radiation-resistant gallium nitride driving circuit system according to claim 1, characterized in that: The switch control module includes a gallium nitride enhancement transistor (GaN-Enhanced Transistor). The gate of the GaN-Enhanced Transistor is electrically connected to the output terminal of the signal detection module, the drain is used to receive external input signals, and the source is electrically connected to the input terminal of the second signal processing module. A pull-down resistor is connected between the input terminal of the second signal processing module and ground. When the GaN-Enhanced Transistor is turned off, the input terminal of the second signal processing module is clamped to zero potential.

7. The radiation-resistant gallium nitride driving circuit system according to claim 3, characterized in that: The data selector module includes three sets of NAND gate logic circuits. The first input terminal of the first NAND gate logic circuit is connected to the output terminal of the first signal processing module. The second input terminal of the first NAND gate logic circuit is connected to the output terminal of the voltage doubler rectifier branch. The output terminal of the first NAND gate logic circuit is connected to the first input terminal of the third NAND gate logic circuit. The first input terminal of the second NAND gate logic circuit is connected to the output terminal of the signal detection module as the selection control terminal, the second input terminal of the second NAND gate logic circuit is connected to the output terminal of the second signal processing module, and the output terminal of the second NAND gate logic circuit is connected to the second input terminal of the third NAND gate logic circuit. The output of the third NAND gate logic circuit is the total output of the data selector module.

8. The radiation-resistant gallium nitride driving circuit system according to claim 7, characterized in that: Each NAND gate logic circuit includes two gallium nitride enhancement transistors connected in series and a pull-up resistor connected to the power supply; the initial threshold voltage of the gallium nitride enhancement transistor whose gate is connected to the output terminal of the voltage doubler rectifier branch in the first NAND gate logic circuit is lower than the inherent flip-flop threshold of the inverter shaper, and the initial threshold voltage of the other five gallium nitride enhancement transistors in the data selector module is half of the power supply voltage.

9. A design method for a radiation-resistant gallium nitride (GaN) drive circuit, implemented based on a radiation-resistant GaN drive circuit system as described in any one of claims 1-8, characterized in that, Includes the following steps: Step S1: The data selector module selects the second drive signal and switches to the first drive signal after a preset delay. The signal detection module continuously monitors the waveform of the first drive signal. Step S2: When the signal detection module detects that there is a continuous AC component in the first drive signal, it outputs a low-level control signal. After receiving the low-level control signal, the data selector module outputs the first drive signal. Step S3: When the signal detection module detects that the first drive signal becomes a constant DC signal with no AC component, the signal detection module outputs a high-level control signal after a preset delay; the switch control module turns on the second signal processing module and inputs the external input signal into the second signal processing module, while the data selector module outputs the second drive signal.

10. The design method of a radiation-resistant gallium nitride driving circuit according to claim 9, characterized in that: The signal detection module in step S3 includes a high-pass filter branch, and the cutoff frequency of the high-pass filter branch satisfies the following expression: ； In the formula, This is the cutoff frequency of the high-pass filter branch; The lowest operating frequency for external input signals; This is the resistance value of the filter resistor in the high-pass filter branch; This is the capacitance value of the filter capacitor in the high-pass filter branch.

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