Chip simulation verification method, device, equipment, storage medium and program product

Abstract

Embodiments of the present application disclose a chip simulation verification method, device, equipment, storage medium and program product, comprising: determining a power intent description model of a three-dimensional stacked chip based on design parameters of the three-dimensional stacked chip; wherein the power intent description model is used to describe a first power intent of a functional unit of each die in the three-dimensional stacked chip and a second power intent of a test unit of each die, the test unit comprising an on-die test unit and a cross-die test unit; constructing a state constraint condition of a functional power of each die and a test power of each die in time sequence based on the power intent description model; wherein the functional power is used to power the functional unit of the corresponding die; the test power is used to power the on-die test unit and the cross-die test unit of the corresponding die; and performing simulation verification of a test path of at least one die under at least one power state combination of each functional power according to the state constraint condition to obtain a simulation verification result.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of simulation verification technology, and in particular to a chip simulation verification method, chip simulation verification device, equipment, storage medium, and program product. Background Technology

[0002] In chip simulation and verification scenarios, the DFT (Design for Test) hardware circuits and their test logic inserted into the chip can be verified based on the chip's power supply intent description. In related technologies, when performing DFT verification on a 3D stacked chip including multiple stacked dies, each die is typically verified individually in a single test scenario where all dies are powered normally.

[0003] However, in 3D stacked chips, each die is interconnected with the others via TSV (Through-Silicon Via) for power and signal. This means that any change in the power state of any die will be coupled to other dies through the TSV power supply channel, causing signal anomalies in cross-die test paths. Under the condition of using relevant technical verification methods, it is impossible to verify the correctness and reliability of cross-die test paths under different power supply test scenarios, thus affecting the yield and reliability of mass production testing of 3D stacked chips. Summary of the Invention

[0004] This application provides at least one chip simulation verification method, chip simulation verification device, equipment, storage medium, and program product.

[0005] The technical solution of this application embodiment is implemented as follows: On one hand, embodiments of this application provide a chip simulation verification method, including: determining a power intention description model of the three-dimensional stacked chip based on the design parameters of the three-dimensional stacked chip; wherein, the power intention description model is used to describe the first power intention of the functional units of each die in the three-dimensional stacked chip, and the second power intention of the test units of each die, the test units including on-chip test units and cross-die test units; based on the power intention description model, constructing the timing state constraints of the functional power supply and the test power supply of each die; wherein, the functional power supply is used to supply power to the functional units of the corresponding die; the test power supply is used to supply power to the on-chip test units and cross-die test units of the corresponding die; according to the state constraints, performing simulation verification of the test path on at least one die under at least one power supply state combination of each functional power supply, and obtaining simulation verification results.

[0006] Secondly, embodiments of this application provide a chip simulation verification apparatus for simulating and verifying a three-dimensional stacked chip, the three-dimensional stacked chip including multiple stacked dies, the apparatus comprising: a determination module, used to determine a power intention description model of the three-dimensional stacked chip based on the design parameters of the three-dimensional stacked chip; wherein, the power intention description model is used to describe the first power intention of the functional units of each die in the three-dimensional stacked chip, and the second power intention of the test units of each die, the test units including on-chip test units and cross-die test units; a construction module, used to construct the timing state constraints of the functional power supply and the test power supply of each die based on the power intention description model; wherein, the functional power supply is used to supply power to the functional units of the corresponding die; the test power supply is used to supply power to the on-chip test units and cross-die test units of the corresponding die; a verification module, used to perform simulation verification of the test path of at least one die under at least one power supply state combination of each functional power supply according to the state constraints, and obtain simulation verification results.

[0007] Thirdly, embodiments of this application provide an electronic device, including a memory and a processor. The memory stores a computer program that can run on the processor, and the processor executes the program to implement the method provided in the first aspect of embodiments of this application.

[0008] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method provided in the first aspect of embodiments of this application.

[0009] Fifthly, embodiments of this application provide a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements the method provided in the first aspect of embodiments of this application.

[0010] This application provides a chip simulation verification method. Based on the design parameters of a three-dimensional stacked chip, a power intention description model is determined. This model describes the first power intention of the functional units of each die in the three-dimensional stacked chip, and the second power intention of the test units of each die. The test units include on-chip test units and cross-die test units. Based on the power intention description model, timing constraints are constructed for the functional power supplies and test power supplies of each die. The functional power supplies power the functional units of the corresponding die, and the test power supplies power the on-chip test units and cross-die test units of the corresponding die. According to the state constraints, simulation verification of the test path is performed on at least one die under at least one power supply state combination of the functional power supplies to obtain simulation verification results. In this way, by using a power intent description model that includes power intent across die test units, the timing dependency between the functional power supply and the test power supply of each die during the test process is constructed. This allows for the simulation verification of cross-die test paths for at least one die under different power supply state combinations of its functional power supply. This not only enables DFT verification of 3D stacked chips under test scenarios with different power supply state combinations, but also enables collaborative verification of the signal integrity of test paths across die test units under test scenarios with different power supply state combinations. This improves the correctness and reliability of cross-die test paths, thereby improving the yield and reliability of mass production testing of 3D stacked chips.

[0011] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this application. Attached Figure Description

[0012] Figure 1 This is a flowchart illustrating the implementation of a chip simulation and verification method provided in an embodiment of this application. Figure 2 This is a schematic diagram of a chip simulation and verification device provided in an embodiment of this application; Figure 3 This is a flowchart of a power-aware 3D DFT verification method for 3D stacked chips provided in an embodiment of this application; Figure 4 This is a schematic diagram of the hardware entity of an electronic device provided in an embodiment of this application.

[0013] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0015] In the following description, references to "some embodiments" refer to a subset of all possible embodiments. It is understood that "some embodiments" may be the same or different subsets of all possible embodiments and may be combined with each other without conflict. The terms "first / second / third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to be limiting of this application.

[0017] Figure 1 This is a flowchart illustrating the implementation of a chip simulation and verification method provided in an embodiment of this application. Figure 1 As shown, the method includes steps S101 to S103.

[0018] Step S101: Based on the design parameters of the three-dimensional stacked chip, determine the power supply intention description model of the three-dimensional stacked chip.

[0019] The power intent description model is used to describe the first power intent of the functional units of each die in the three-dimensional stacked chip, and the second power intent of the test units of each die. The test units include on-chip test units and cross-die test units.

[0020] In this embodiment, a three-dimensional stacked chip can refer to an integrated circuit in which multiple dies are stacked vertically using three-dimensional stacking technology, and power and signal interconnection between the dies is achieved through vertical interconnect structures such as TSV.

[0021] For example, the three-dimensional stacked chip can be a homogeneous stacked chip composed of multiple layers of memory dies, or a heterogeneous stacked chip composed of a mixture of different types of dies such as logic dies, memory dies, and interconnect dies. The number of stacked layers in the three-dimensional stacked chip can be two or more. Each die in the three-dimensional stacked chip can be at least one of logic dies, memory dies, and interconnect dies, or any combination of the above types of dies; this application does not limit this.

[0022] The design parameters of a 3D stacked chip can refer to the structured parameters that are determined during the design phase and can reflect the stacking architecture, power domain partitioning, test circuit structure, and low-power strategies of the 3D stacked chip.

[0023] Power intent can refer to a formal description of the power management strategy of each circuit module in chip design. Power intent includes at least power domain partitioning, power state definition, power state switching rules, cross-power domain signal transmission strategy, and power control timing constraints.

[0024] In some embodiments, the first power intent may refer to a set of information describing the power management strategies of functional units in each die. The first power intent includes at least the functional power domain to which each functional unit belongs, the power supply states supported by each functional power domain (e.g., normal power supply, state hold, complete power failure), and the isolation and level transition strategies between functional power domains. The first power intent corresponds to the power supply requirement description of each die in a functional mode. The second power intent may refer to a set of information describing the power management strategies of test units in each die. The second power intent includes at least the DFT test power domain to which each test unit belongs, the power supply states supported by each DFT test power domain (e.g., test power supply, test sleep), and the power attribute description of each cross-die test unit. The second power intent corresponds to the power supply requirement description of each die in a test mode.

[0025] Given the existence of the UPF 2.0+ (IEEE 1801) standard in related technologies, this standard, as an industry standard for low-power integrated circuit design, provides a structured language for defining power domains, power supply networks, power switches, isolation, state retention, level transitions, and power states. However, the existing UPF 2.0+ standard is natively geared towards single-die design, and its power intent describes the power supply behavior of functional circuits used in functional modes under scenarios such as multiple voltages, shutdown, and state retention.

[0026] Therefore, in this step, when determining the power intention description model of the three-dimensional stacked chip, we can extend the UPF 2.0+ standard to be more oriented towards the three-dimensional stacked chip. Based on the design parameters of the three-dimensional stacked chip, we can determine the power intention description model of the three-dimensional stacked chip.

[0027] For example, the power management information of each die functional unit and the power management information of each die test unit can be extracted from the design parameters of the 3D stacked chip. The power management information of each die functional unit can refer to information such as the functional power domain division and functional power status of each die functional unit, while the power management information of each die test unit can refer to information such as the DFT test power domain division, test unit type and location, and power attributes across die test units.

[0028] Then, a first power intent can be constructed within the UPF 2.0+ standard framework. UPF standard commands can be used to describe the functional power domain to which each die functional unit belongs, and the power supply states supported by each functional power domain, thus constituting the first power intent. A second power intent can then be extended within the UPF 2.0+ standard framework. Based on the existing UPF command system, the DFT test power domain to which each test unit (on-chip test unit and cross-die test unit) belongs, the power supply states supported by each DFT test power domain, and the power attributes of cross-die test units can be defined.

[0029] Finally, the first power intent and the second power intent can be merged to obtain a power intent description model of the three-dimensional stacked chip.

[0030] Step S102: Based on the power supply intent description model, construct the timing state constraints of the functional power supply and test power supply of each die.

[0031] The functional power supply is used to power the functional units of the corresponding die; the test power supply is used to power the on-chip test units and cross-die test units of the corresponding die.

[0032] In this embodiment, state constraints refer to the timing coordination rules that each die's functional power supply and test power supply must follow during the testing process. These state constraints may include, but are not limited to, power state transition rules, interlocking conditions, and waiting mechanisms.

[0033] For example, power state transition rules can be used to define the transition rules between the functional power state and the test power state of each die; interlock conditions can be used to define the mutual exclusion or interlock relationship between the functional power state and the test power state to avoid illegal state combinations; and waiting mechanisms can be used to define the stable waiting time before power state switching to ensure that the next operation is performed after the power state switching is completed.

[0034] In one possible implementation, state constraints can be implemented using a joint state machine.

[0035] A joint state machine can be constructed based on the first and second power intentions in the power intention description model. It is used to uniformly manage the functional power states and test power states of each die and automatically execute jump rules, interlock conditions, and waiting mechanisms. The input of the joint state machine can be the current power supply state of the functional power supply and the test mode request of each die. The output can be the power supply state of the test power supply that matches the current power supply state of the functional power supply of the die; or the next power supply state of the functional power supply to be switched to on the die, and the power supply state of the test power supply that matches the next power supply state of the functional power supply.

[0036] Step S103: Based on the state constraints, perform simulation verification of the test path for at least one die under at least one power supply state combination of each functional power supply, and obtain the simulation verification results.

[0037] The test path can include a cross-die test path, which can be formed by physically connecting the on-chip test units of each die through cross-die test units.

[0038] In this embodiment, the power supply state combinations to be verified are first determined based on the joint state machine constructed in step S102. Secondly, for each power supply state combination, a simulation tool is invoked to perform dynamic simulation of the cross-die test path based on state constraints.

[0039] Considering that in related technologies, due to the lack of coordination constraints between functional power supplies and test power supplies, under certain power supply combinations, cross-die test paths may be broken due to power supply mismatch, abnormal signal levels, or lack of isolation, making the DFT circuit untestable in this scenario.

[0040] Therefore, in this embodiment, by constructing the timing state constraints of the functional power supply and the test power supply of each die, that is, by constructing the cooperative relationship between the functional power supply state and the test power supply state, the test path can be simulated and verified under at least one combination of power supply states of each functional power supply, and the simulation verification results can be obtained.

[0041] For example, in the actual operation of 3D stacked chips, each die can independently switch its functional power state according to power management requirements. The functional power state of a die can be switched from normal power supply to a state-holding mode or completely powered down. When the functional power state of a die switches, the joint state machine can determine the test power state that matches the functional power state based on preset jump rules, interlock conditions, and / or waiting mechanisms. For instance, when the functional power supply switches to a power-down state, the joint state machine can control the test power supply of the corresponding test unit to maintain power supply while isolating the test path, or synchronously adjust the test voltage, thereby ensuring that the power state switching process conforms to the design intent and does not interfere with the testing of other dies.

[0042] During simulation verification, multiple power supply state combinations can be actively traversed based on the state constraints in the joint state machine. These combinations include various pairings of each die's functional power supply under different power supply states (such as normal power supply, state holding, and complete power failure). Under each power supply state combination, the joint state machine can drive the test power supply to make a response that matches the current functional power supply state, thereby detecting the connectivity and signal integrity of the cross-die test path during power state changes.

[0043] In some implementations, when the above-mentioned at least one power supply state combination includes power supply state combinations corresponding to low-power scenarios such as partial die power loss, partial die in state-holding mode, and / or partial die switching to a lower voltage, simulation verification can be performed under the at least one power supply state combination by establishing a state constraint relationship between the functional power supply and the test power supply, thus covering the test path verification under low-power scenarios.

[0044] By adopting the above technical solution, a power intent description model including cross-die test power intent is used to construct the timing dependency relationship between the functional power supply and the test power supply during the test process. This allows for the simulation verification of cross-die test paths for at least one die under different power supply state combinations of its functional power supply. Not only can DFT verification be performed under different power supply test scenarios, but the signal integrity of the cross-die test path under different power supply conditions can also be collaboratively verified. This avoids the cross-die power coupling effect caused by the TSV power supply channel being excluded from the verification scope, improves the correctness and reliability of the cross-die test path, and thus improves the yield and reliability of mass production testing of 3D stacked chips.

[0045] In some embodiments, step S103 can be implemented by steps S1031 to S1033.

[0046] Step S1031: Obtain the test circuit structure of the test unit in the three-dimensional stacked chip, and the power supply network structure of the three-dimensional stacked chip.

[0047] In this step, the test circuit structure of the test unit can refer to the netlist file of the DFT circuits that have been inserted on each die in the three-dimensional stacked chip, including at least the circuit connection relationship and logical function description of test circuit modules such as scan chain, MBIST (Memory Build-In-Self Test) and on-chip JTAG (Internal Test Access Port).

[0048] The power supply network structure of a 3D stacked chip can refer to the circuit model of the power / ground (PG) network of each die in the 3D stacked chip, including at least the electrical parameters and topology connection relationships of the local PG network, TSV power supply channel, and micro-bump interconnect structure of each die.

[0049] Step S1032: The test circuit structure, power supply network structure, and power supply intention description model are merged to obtain a joint simulation platform.

[0050] Since cross-die test paths are formed by physically connecting the on-chip test cells of each die through cross-die test cells, the test circuit structure of the test cells (i.e., the DFT netlist) can be used to provide the physical carrier of the cross-die test paths. Only with the test circuit structure obtained can the test paths to be verified, as well as the application points of the test stimuli and the observation points of the test responses, be determined.

[0051] The power supply network structure (i.e., the 3D PG netlist) serves as the physical carrier for power transmission. The power supply status of the functional and test power supplies ultimately needs to be reflected in the specific voltage and current on the PG network. Therefore, a power supply network structure is also required to simulate the actual voltage distribution of each die under different power supply states and reflect the cross-die coupling effect of the TSV power supply channel.

[0052] The power intent description model provides the rules and constraints for power management, while the test circuit structure and power supply network structure provide the circuit carrier and power supply carrier to be verified, respectively. Without the test circuit structure, the simulation cannot perform test operations; without the power supply network structure, the simulation cannot simulate a real power supply environment; and without the power intent description model, the simulation cannot learn about the power state switching rules and cross-domain processing strategies.

[0053] Therefore, the test circuit structure, power supply network structure, and power intent description model can be merged to obtain a joint simulation platform, which can realize the simulation verification of cross-die test paths based on power intent constraints in a real test circuit and real power supply environment.

[0054] Step S1033: Based on the state constraints, the test path of at least one die is simulated and verified using a co-simulation platform under at least one power supply state combination of various functional power supplies, and the simulation verification results are obtained.

[0055] In this embodiment, based on state constraints, a co-simulation platform can automatically traverse at least one power supply state combination. For each power supply state combination, the co-simulation platform calls the power supply state definition in the power intent description model, controls the power supply network output in the 3D PG netlist to output the corresponding voltage and current, performs corresponding test operations on the DFT netlist, and monitors the signal integrity on the cross-die test path to obtain simulation verification results.

[0056] By adopting the above technical solution, a comprehensive simulation verification of cross-die test paths can be carried out under various power supply test scenarios based on a unified co-simulation platform, ensuring the accuracy and reliability of the verification results.

[0057] In some embodiments, step S1033 above can be implemented in the following ways: For at least one power supply state combination, under the power supply state combination, the unknown state signal at the through-silicon via test port of the first die and the unknown state signal in the test path of the second die can be detected firstly by using a co-simulation platform based on the state constraints.

[0058] The power supply for the first bare die is in a power-off state.

[0059] In this embodiment, the power supply state combination can be selected by the joint state machine according to the test mode request. The power supply state combination can include at least one or more of the following: partial die power loss, partial die state maintenance, or multiple die voltage switching.

[0060] For each selected power supply state combination, the joint state machine can output a power supply state control command that matches the power supply state combination, so as to control the joint simulation platform to call the power supply network structure to apply the corresponding power supply voltage to each die according to the power supply state control command, and call the test circuit structure to perform the corresponding test operation.

[0061] When the power supply to the first die is lost, its internal test circuit outputs an uncertain logic value, i.e., an unknown state, due to the loss of power. This unknown state signal will appear at the through-silicon via (TSV) test port of the first die. Therefore, a co-simulation platform can be used to monitor the signal at the TSV test port of the first die to detect whether the port outputs an unknown state signal.

[0062] The second die can refer to a die adjacent to the first die and interconnected via a TSV (Through Silicon Via), whose functional power supply is in a normal operating state. Since the first and second dies are interconnected via TSVs, unknown state signals generated at the through-silicon via (TSV) test ports of the first die can propagate to the test path of the second die via the TSV. A co-simulation platform can be used to monitor the signal in the test path of the second die to detect whether unknown state signals propagating from the first die appear in the test path.

[0063] If an unknown state signal is detected at the through-silicon via test port of the first die and in the test path of the second die under any power supply state combination, then it is determined that the simulation verification results characterize that there is an unknown state propagation anomaly in the test path of the three-dimensional stacked chip.

[0064] By adopting the above technical solution, under different power supply state combinations, based on state constraints, the propagation of unknown states on the cross-die test path can be accurately detected through a joint simulation platform, and the test path can be determined to be abnormal based on the detection results, thereby realizing the completeness of DFT verification of three-dimensional stacked chips under various power supply test scenarios.

[0065] In some embodiments, the power supply intention description model may define power supply operation information under at least one combination of power supply states for each functional power supply.

[0066] Among them, power operation information can refer to the signal behavior characteristics of the through-silicon via test ports of each die under the corresponding power state, which are predefined in the power intention description model for each combination of power supply states.

[0067] For example, if a three-dimensional stacked chip comprises three layers of dies: a top-level logic die, a middle-level interconnect die, and a bottom-level memory die, then for the power supply state combination of "bottom-level memory die powered down, top-level logic die powered on normally," the power supply operation information can be defined as follows: The signal behavior characteristics of the TSV test port of the underlying memory die in the power-down state are: output unknown state (X state); where the type label of the unknown state is a reasonable unknown state generated by normal power management behavior; the propagation control strategy of the unknown state is that it needs to be absorbed and should not propagate to the test path of the top-level logic die.

[0068] Therefore, power operation information can include whether the signal output by the TSV test port of a certain die is in an unknown state (X state) when the functional power supply of a die is in a power-off state. Power operation information can also include whether the unknown state is a reasonable unknown state generated by normal power management behavior, or an abnormal unknown state caused by test defects.

[0069] In one possible implementation, the first through-silicon via (TSV) test port of each die under a power supply state combination can be determined based on power supply operation information. The first TSV test port generates an unknown-state signal under the power supply behavior of the corresponding die's functional power supply.

[0070] After identifying the first through-silicon via (TSV) test port to be subjected to unknown state absorption, an unknown state absorption unit can be inserted into the co-simulation platform to obtain an updated co-simulation platform. The unknown state absorption unit is used to filter unknown state signals. Finally, based on state constraints, the updated co-simulation platform can be used to detect unknown state signals at the TSV test port of the first die under power supply state combinations, as well as unknown state signals in the test path of the second die.

[0071] In this implementation, the first through-silicon via (TSV) test port can refer to a TSV test port that is determined based on power supply operation information, generates an unknown state signal under a specific power supply state combination, and the unknown state signal needs to be absorbed.

[0072] In the implementation process, when the power supply operation information indicates that the unknown state signal output by the TSV test port of a die under a specific power supply state combination is an abnormal unknown state (i.e., an unknown state caused by a test defect, rather than a reasonable unknown state generated by normal power management behavior), the TSV test port is determined as the first through-silicon via (TSV) test port; or, when the power supply operation information indicates that the unknown state signal output by the TSV test port of a die under a specific power supply state combination is a reasonable unknown state, but the unknown state may propagate to other dies through the cross-die test path and cause simulation false alarms, the TSV test port is also determined as the first TSV test port.

[0073] An unknown state absorption unit can be a circuit unit used to filter unknown state signals. It can clamp the input unknown state signal to a known logic value (e.g., logic 0 or logic 1), thereby preventing the unknown state from continuing to propagate in the test path.

[0074] In the updated co-simulation platform, when an unknown state signal is detected from the first through-silicon via test port, the unknown state signal can be clamped to a preset logic value by the unknown state absorption unit, thereby blocking the propagation of the unknown state to the adjacent die test path.

[0075] Based on this, simulation verification can be performed using the updated co-simulation platform, based on state constraints.

[0076] In one possible implementation, a joint state machine can be used to combine and output power state control commands based on the current power supply state, call the power supply network structure to apply the corresponding power supply voltage to each die, and call the test circuit structure to execute the corresponding test operations.

[0077] During the simulation, the co-simulation platform can simultaneously perform the following checks: The unknown state signal at the through-silicon via test port of the first die is detected to monitor whether the port outputs an unknown state signal; The unknown state signal in the test path of the second die is detected to monitor whether an unknown state signal propagating from the first die appears in the test path.

[0078] If an unknown state signal is detected at the through-silicon via (TSV) test port of the first die and also detected in the test path of the second die, then the simulation verification results indicate that there is an unknown state propagation anomaly in the test path of the 3D stacked chip. If an unknown state signal is detected at the TSV test port of the first die but not detected in the test path of the second die, then the simulation verification results indicate that there is no unknown state propagation anomaly in the test path of the 3D stacked chip.

[0079] By adopting the above technical solution, reasonable unknown states and abnormal unknown states can be identified based on power supply operation information, and unknown state absorption units can be inserted at the TSV test ports that need to be absorbed. This accurately blocks the cross-die propagation of abnormal unknown states during simulation verification, avoids misjudging normal power management behavior as test defects, and significantly improves the accuracy and reliability of simulation verification.

[0080] In some embodiments, each power supply state combination has a corresponding verification scenario.

[0081] The verification scenarios may include low-power scenarios. A combination of power states in a three-dimensional stacked chip where at least one die is not in a fully voltage-normal power supply state can correspond to a low-power scenario. These low-power scenarios may include, but are not limited to, test scenarios where some dies are completely powered down, some dies are in a state-holding mode, and multiple dies are switching voltages.

[0082] In this embodiment, the resource consumption costs required for simulation verification vary depending on the power supply state combination. The resource consumption costs required for simulation verification in low-power scenarios are lower than those required for simulation verification in normal scenarios.

[0083] Therefore, according to the resource consumption cost required for simulation verification in the corresponding verification scenario from low to high, for each power supply state combination, according to the state constraints, at least one die can be simulated and verified for the test path under the power supply state combination to obtain the simulation verification results under the power supply state combination.

[0084] The order of resource consumption costs required for simulation verification of each power supply state combination can be used to characterize the execution order of each power supply state combination during simulation verification on the co-simulation platform. Resource consumption costs may include, but are not limited to, simulation runtime, computational resource usage, complexity of power supply state switching, and the number of activations across die test paths.

[0085] On the one hand, the varying scale of the circuits and power supply networks involved in the simulation under different power supply state combinations leads to different computational resource consumption. For example, in a power supply state combination where all dies are powered normally, all die test units are activated, requiring simulation of the complete test path and power supply network, resulting in a large network scale. On the other hand, in power supply state combinations where some dies are powered down or in low-power scenarios such as state-holding mode, the test units of the powered-down dies are not working, which can simplify the simulation model for this part (e.g., by using an equivalent macro model), reduce the simulation network scale, and lower the computational resource consumption.

[0086] On the other hand, the simulation runtime varies due to the different power supply state switching complexities under different power supply state combinations. For example, when multiple dies are switching voltages, multiple voltage switching operations are required followed by waiting for stabilization, resulting in a longer simulation runtime; when all dies are powered normally, no switching is needed, leading to a shorter simulation runtime.

[0087] On the other hand, the number of activated cross-die test paths varies under different power supply state combinations. The verification complexity of cross-die test paths differs under different power supply state combinations. For example, when some dies are powered down, X-state blocking verification and dual detection are required, which is highly complex; when the entire die is powered on normally, only signal transmission connectivity needs to be verified, which is relatively less complex.

[0088] In some embodiments, the lower the resource consumption cost, the higher the priority of the power supply state combination to be simulated and verified; the higher the resource consumption cost, the lower the priority of the power supply state combination to be simulated and verified.

[0089] In this way, by executing simulation verification in the order of resource consumption cost of each power supply state combination during the simulation verification, the joint simulation platform can prioritize the verification of basic scenarios to quickly discover basic test path faults under limited simulation resources, and then gradually delve into the verification of complex scenarios to investigate potential test failure risks. This significantly improves the overall efficiency of simulation verification while ensuring verification coverage and avoids the waste of resources caused by blindly traversing all power supply state combinations.

[0090] In one possible implementation, at least one power supply state combination includes a first power supply state combination, a second power supply state combination, and a third power supply state combination, which sequentially increase the resource consumption cost required for simulation verification in the corresponding verification scenario.

[0091] In this implementation, under the first power supply state combination, the functional power supply of the third die located at the top layer of the three-dimensional stacked chip is in a normal power supply state, while the functional power supply of the fourth die (excluding the third die) in the three-dimensional stacked chip is in a power-down state. This combination can correspond to deep low-power scenarios, where only a single die works and the rest are powered down. Under the second power supply state combination, the functional power supply of the fifth die located in the middle layer of the three-dimensional stacked chip is in a normal power supply state, while the functional power supply of the sixth die (excluding the third die) in the three-dimensional stacked chip is in a hold state. This combination can correspond to moderate low-power scenarios, where some dies are in a low-voltage hold mode. Under the third power supply state combination, the functional power supplies of all dies in the three-dimensional stacked chip are in a normal power supply state, and at least one die's functional power supply supports voltage switching. This combination can correspond to a full power supply scenario.

[0092] In actual implementation, the first power supply state combination only requires a single die to be powered normally, necessitating single-die DFT testing without cross-die interaction. This results in the smallest simulation network size and the lowest resource consumption. The second power supply state combination involves cross-die interaction, requiring dynamic simulation using a co-simulation platform. This increases the simulation network size and operational complexity compared to the first power supply state combination, placing its resource consumption in the middle range. Finally, the third power supply state combination, with all dies powered normally, involves not only cross-die interaction but also has the largest simulation network size and operational complexity, resulting in the highest resource consumption.

[0093] In this way, by prioritizing the verification of the first power supply state combination (i.e., the deep low-power scenario), the correctness of the single-die DFT test can be quickly confirmed; secondly, verifying the second power supply state combination (i.e., the medium low-power scenario) can verify the connectivity and isolation effectiveness of the test path in cross-die interaction scenarios; finally, verifying the third power supply state combination (i.e., the full power supply scenario) can thoroughly investigate the test failure risks in complex scenarios such as voltage switching. This allows for prioritizing the basic scenario verification of the first power supply state combination with limited simulation resources, then gradually progressing to the cross-die interaction scenario verification of the second power supply state combination, and finally to the complex scenario verification of the third power supply state combination, thus improving the overall efficiency of simulation verification while ensuring verification coverage.

[0094] In some embodiments, the simulation verification results may include sub-simulation verification results corresponding to each power supply state combination under the design for testability test mode. The chip simulation verification method may further include the following steps S104 to S106: Step S104: Extract the first fluctuation index of the operating current of the test unit of each bare die under the corresponding power supply state combination from the sub-simulation verification results corresponding to each power supply state combination.

[0095] The first fluctuation index is a set of parameters used to characterize the current fluctuation characteristics exhibited by each die's test unit under corresponding power supply state combinations and in the design for testability test mode. Current fluctuation characteristics may include one or more of the following parameters: peak current of the test unit, dynamic current waveform amplitude, current surge duration, current fluctuation range, etc.

[0096] Peak current can refer to the maximum instantaneous current value reached by the test unit during test mode operation (such as scan shift, MBIST operation, IJTAG test, etc.); dynamic current waveform amplitude can refer to the fluctuation amplitude of dynamic current relative to static bias current during test mode operation; current surge duration can refer to the length of time the current exceeds a preset threshold during test mode operation; current fluctuation range can refer to the difference between the maximum and minimum current values ​​during test mode operation.

[0097] For example, taking the scan shift test mode as an example, when the scan chain performs a shift operation, the synchronous flipping of each trigger will generate a large transient current surge in a very short time. From the sub-simulation verification results corresponding to this power supply state combination, the peak current, transient current change rate, and current surge duration of the scan chain during the shift can be extracted as the first fluctuation index of the scan chain under this power supply state combination.

[0098] In this embodiment, the process of extracting the first fluctuation index from the sub-simulation verification results corresponding to each power supply state combination can be automatically executed based on preset extraction rules. These extraction rules may include, but are not limited to, setting corresponding current sampling windows and feature extraction algorithms for each test mode (e.g., scan-shift mode, MBIST operation mode, IJTAG test mode) to automatically identify and extract the aforementioned physical quantities from the simulation waveforms.

[0099] Step S105: For each power supply state combination, the first fluctuation index of the operating current of the test unit of each die under the power supply state combination is back-annotated to the power supply network structure of the three-dimensional stacked chip, and power supply disturbance simulation is performed on the updated power supply network structure of the three-dimensional stacked chip to obtain the second fluctuation index of the operating voltage of the test unit of each die under the corresponding power supply state combination.

[0100] The second fluctuation index is a set of parameters used to characterize the voltage fluctuation characteristics caused by power supply disturbances resulting from the back-annotation of the operating current to the power supply network structure during DFT simulation verification. Voltage fluctuation characteristics may include, but are not limited to, voltage drop distribution.

[0101] In this embodiment, for each power supply state combination, the first fluctuation index can first be back-annotated to the power supply network structure of the three-dimensional stacked chip. For example, in the 3D PG netlist, the current source corresponding to each die test unit is replaced with a time-varying current source with the characteristics of the first fluctuation index to realistically simulate the dynamic current consumption of the DFT circuit under different test modes such as scan shift, MBIST operation, and IJTAG test.

[0102] Then, power disturbance simulation can be performed on the reverse-annotated power supply network structure. The power disturbance simulation is based on dynamic IR-drop simulation performed by a dynamic IR-drop simulation engine.

[0103] During the simulation, the voltage drop distribution of each die local PG network under the action of DFT dynamic current can be calculated, as well as the peak voltage drop and voltage fluctuation range on the TSV power supply channel. The voltage transfer characteristics on the cross-die PG interconnect structure (micro-bumps) can also be calculated.

[0104] Step S106: Based on the second fluctuation index of the operating voltage of each die's test path under at least one power supply state combination, identify the test failure risk points caused by power supply noise in the test path of each die.

[0105] Among them, the test failure risk point can refer to the physical location or circuit unit in the test path of each die under at least one power supply state combination, where the power supply disturbance caused by the back-labeling of the DFT working current to the power supply network structure causes the second fluctuation index of its working voltage to exceed the preset threshold, which may cause abnormal test function.

[0106] In this embodiment, a second fluctuation index of the operating voltage of the test unit of each die under the corresponding power supply state combination can be extracted from the power supply disturbance simulation results, so as to determine the real impact of the power supply noise caused by the DFT operating current on the power supply quality of the test unit based on the second fluctuation index.

[0107] In the process of implementation, when analyzing the second fluctuation index to determine the real impact of power supply noise caused by the DFT operating current on the power supply quality of the test unit, the impact of power supply noise caused by the DFT operating current on the DFT test circuit and functional circuit can be evaluated by comparing the second fluctuation index with the preset voltage tolerance threshold, and the test failure risk points caused by power supply noise can be accurately located.

[0108] For example, if the second fluctuation index (such as peak voltage drop) of a die test unit exceeds a preset threshold, it indicates that the test unit has a risk of test failure due to power supply noise under the corresponding power supply state combination; if the second fluctuation index of a TSV power supply channel exceeds a preset threshold, it indicates that the power supply quality across the die test path does not meet the test requirements; if the second fluctuation index of all test units is within the preset threshold range, it indicates that there is no risk of test failure due to power supply noise under the corresponding power supply state combination, and the verification is successful.

[0109] In one possible implementation, dynamic voltage drop simulation can be performed on the updated power supply network structure of the three-dimensional stacked chip to obtain the voltage drop distribution of the power supply channel of the through-silicon via test port of each die, and / or the voltage fluctuation distribution of the power supply network of the test unit.

[0110] By adopting the above technical solution, the dynamic current surge during the operation of the DFT circuit can be back-labeled to the power supply network structure, and the second fluctuation index on the voltage side can be obtained through power supply disturbance simulation. Based on the second fluctuation index, the impact of power supply noise on DFT testing can be determined, thereby realizing the collaborative simulation of DFT operating current and 3D PG network. This allows for early identification of test failure risk points, avoidance of test mistests and failures caused by high DFT current, and improvement of mass production test yield and tape-out success rate of 3D stacked chips.

[0111] In some embodiments, the power supply network structure may include the power supply network of each die and the power supply channel model of through-silicon vias (TSVs). Step S105 above can be implemented through steps S1051 and S1052: Step S1051: Construct an equivalent macro model for the updated power supply network of each die.

[0112] In this model, the port characteristics of the equivalent macro model are consistent with the port characteristics of the updated power supply network of the corresponding die. The equivalent macro model can refer to a simplified equivalent model of a complex system / device. Its core is to significantly reduce the complexity of the model and improve the analysis efficiency while ensuring that the port characteristics are approximately consistent with the original system.

[0113] In this embodiment, for each die, its updated power supply network (i.e., the PG network portion corresponding to the die in the 3D PG netlist) is constructed as an equivalent macromodel. The input / output port characteristics of this equivalent macromodel are consistent with the port characteristics of the original updated power supply network to ensure that the external electrical behavior of the die's power supply network is equivalent to the original network during top-level simulation. For example, the port impedance characteristics, port voltage-current relationship, transient response characteristics, and other parameters of this equivalent macromodel are consistent with the corresponding parameters of the original updated power supply network.

[0114] In the process of constructing the equivalent macro model, the port equivalence simplification of the PG network of each die can be performed, retaining the key electrical parameters at the TSV power supply channel interface, and the complex RC network inside the die can be equivalent to a simplified lumped parameter model or a reduced-order model, so that the macro model can accurately characterize the electrical characteristics of the die power supply network with a low computational cost in the top-level simulation.

[0115] Step S1052: Call the equivalent macro model and through-silicon via power supply channel model of each die to perform top-level power supply disturbance simulation, and obtain the second fluctuation index of the operating voltage of the test unit of each die under the corresponding power supply state combination.

[0116] The through-silicon via (TSV) power supply channel model is the equivalent circuit model of the power supply channel of the TSV test port. Top-level power disturbance simulation can refer to treating each die as a component of a complete system and performing power disturbance simulation on the overall power supply topology after stacking.

[0117] In this embodiment, the first fluctuation index of the test unit of each die extracted in step S104 under the corresponding power supply state combination can be back-annotated to the power supply node corresponding to each test unit in the top-level equivalent simulation network as a time-varying current source. Then, each die can be regarded as a component of a complete system, and power supply disturbance simulation can be performed on the overall power supply topology after stacking.

[0118] Finally, a second fluctuation index of the operating voltage of the test unit of each die under the corresponding power supply state combination can be extracted from the simulation results.

[0119] By adopting the above technical solution, an equivalent macro model is constructed for the PG network of each die. The top-level simulation only needs to call the macro model and the TSV power supply channel model, without having to process the complete RC network inside each die. This greatly improves the simulation efficiency while ensuring the simulation accuracy, and achieves a balance between simulation efficiency and simulation accuracy.

[0120] In this embodiment, simulation verification is used to verify the correctness and reliability of the test path. For example, simulation verification can be used to verify one or more of the following: the connectivity, isolation and level transition effectiveness, unknown state propagation controllability, and the impact of power supply noise caused by DFT operating current on test paths such as scan chain, MBIST, and IJTAG under various power supply state combinations.

[0121] In one possible implementation, under the conditions that there is no test path breakage, no abnormal unknown state propagation across the die, and none of the second fluctuation indicators exceed the preset voltage tolerance threshold, it can be determined that the simulation verification results meet the expected conditions.

[0122] In another possible implementation, if at least one of the following conditions exists: test path breakage, abnormal unknown state propagation across the die, or the second fluctuation index exceeds the preset voltage tolerance threshold, the simulation verification result can be considered not to meet the expected conditions.

[0123] For example, the expected conditions may include, but are not limited to, at least one of the following verification objectives corresponding to simulation verification: The connectivity of the test path is normal under various power supply state combinations, which can be used to verify that the physical connection of the cross-die test path has not been broken when the power state changes; the effectiveness of isolation and level conversion is normal, which can be used to verify that the cross-die test isolation unit and the cross-die test level conversion unit can correctly perform isolation and level conversion functions under the corresponding power supply state; the controllability of unknown state propagation is normal, which can be used to verify that the reasonable unknown state generated by the power-down die has been effectively blocked and has not propagated to the test path of adjacent dies; the impact of power supply noise caused by DFT operating current on the test path is within an acceptable range, which can be used to verify that the operating voltage fluctuation of each test unit does not exceed its normal operating voltage tolerance threshold.

[0124] In some embodiments, if it is determined that the simulation verification result does not meet the expected conditions, the following steps S107 to S109 can be repeated until it is determined that the updated simulation verification result meets the expected conditions.

[0125] Step S107: Adjust at least one of the design parameters to be optimized in the three-dimensional stacked chip to obtain the updated design parameters of the three-dimensional stacked chip.

[0126] Among them, at least one of the following is included: a second power supply intention of at least one die test unit, a test circuit structure of at least one die test unit, and a power supply network structure of a three-dimensional stacked chip.

[0127] In this step, the failure type of the simulation verification can be determined first if the simulation verification results do not meet the expected conditions. The failure type can include at least one of the following: DFT test path breakage, unknown state abnormal propagation, and exceeding the limit of the second fluctuation index.

[0128] Then, the corresponding optimization items in the design parameters of the 3D stacked chip can be adjusted according to the failure type.

[0129] In some embodiments, if the failure type is a DFT test path break, it indicates that the test path failed to maintain the expected connectivity under the corresponding power supply state combination. The cause of a DFT test path break can be at least one of the following: 1. Inappropriate isolation strategy for cross-die test isolation units leads to incorrect clamping of test signals; 2. Inappropriate configuration of the conversion threshold and power supply noise margin of the cross-die test level conversion unit leads to test signal distortion; 3. Inaccurate definition of power state constraints for the TSV test port causes the test port to fail to maintain the correct high impedance state or on state during functional power switching. IV. The topology distribution of the scan chain / IJTAG test link in the DFT architecture causes the test path to be physically disconnected under some power supply state combinations.

[0130] Therefore, based on the reasons mentioned above that lead to the breakage of the DFT test pathway, at least one item to be optimized can be identified.

[0131] In one possible implementation, the second power supply intent of at least one die test unit can be adjusted. For example, when the cross-die test unit in the test unit includes a cross-die test isolation unit, the power supply domain binding or isolation enable signal power dependency in the second power supply intent of the cross-die test isolation unit can be adjusted to ensure that the cross-die test path of the power-down die is correctly isolated and does not affect the DFT test of other dies. When the cross-die test unit in the test unit includes a test level conversion unit, the attributes of the test level conversion unit can be adjusted, redefining its input / output power domain, conversion threshold, and power noise margin to ensure correct conversion of the test signal between different voltage domains. When the cross-die test unit in the test unit includes a TSV test port, the power state constraint definition of the TSV test port can be adjusted to clarify the signal transmission rules of the TSV test port under different functional power states, avoiding path breakage caused by signal interference.

[0132] In another possible implementation, the test circuit structure of at least one die test unit can be adjusted.

[0133] For example, the scan chain can be segmented and reconstructed to ensure that the cross-die test path remains connected even when some dies are powered down or the voltage is switched; the IJTAG test link can be redundantly designed to add backup test access paths; and the MBIST can be optimized for grouped testing to ensure the reachability of the MBIST controller on the cross-die test path.

[0134] In another possible implementation, the power supply network structure of the three-dimensional stacked chips can be adjusted.

[0135] For example, the routing of the TSV power supply channel can be optimized. For example, the number of TSVs can be increased or the via area can be increased to reduce the power supply resistance and ensure that the cross-die test isolation unit and the cross-die test level conversion unit receive a stable power supply during testing, thereby avoiding path breakage due to insufficient power supply.

[0136] In other embodiments, if the failure type is unknown state anomaly propagation, it indicates that under the corresponding power supply state combination, the unknown state signal generated by the power-down die (first die) due to the loss of power supply to the functional power source is not effectively controlled by the isolation mechanism, absorption mechanism, or port constraints in the cross-die test path. This causes the unknown state signal to pass through the cross-die test isolation unit and propagate to the test path of the adjacent die (second die) via TSV, thereby interfering with the DFT test operation of the normally powered die, resulting in the simulation verification results indicating an unknown state propagation anomaly in the test path. Therefore, at least one item to be optimized can also be adjusted.

[0137] In some embodiments, if the failure type is an excessive second fluctuation index, this indicates that under the corresponding power supply state combination, the dynamic current surge generated when the test unit is operating, after being reflected back to the power supply network structure, causes power disturbances exceeding the expected tolerance. Specifically, the peak voltage drop of the TSV power supply channel, the voltage fluctuation range across the die PG network, or the voltage fluctuation at the power supply pin of the test unit exceeds the preset voltage tolerance threshold, leading to test failure risks for test paths such as the scan chain, MBIST, and IJTAG due to degraded power supply quality. Therefore, at least one item to be optimized can also be adjusted.

[0138] Step S108: Based on the updated design parameters, determine the updated power intention description model of the three-dimensional stacked chip, and based on the updated power intention description model, construct the updated state constraints in timing for the functional power supply and test power supply of each die.

[0139] For the implementation method in this step, please refer to step S102.

[0140] Step S109: Based on the updated state constraints, perform simulation verification of the test path for at least one die under at least one power supply state combination of each functional power supply to obtain the updated simulation verification results.

[0141] For the implementation method in this step, please refer to step S103.

[0142] By adopting the above technical solution, the power intention description model, test circuit structure and / or power supply network structure of the three-dimensional stacked chip can be dynamically adjusted according to the simulation verification results, so that the simulation verification can be gradually adapted to the multi-die and multi-power domain characteristics of the three-dimensional stacked chip until the DFT verification requirements under all power supply state combinations are met.

[0143] In some embodiments, the second power supply is intended to describe the power supply dependency information of the cross-die test cells of each die; the above step S102 can be implemented by the following steps S1021 and S1022.

[0144] Step S1021: Extract the first power supply state set supported by the functional power supply of each die and the second power supply state set supported by the test power supply of each die from the power supply intent description model, and extract the power supply dependency information across die test units.

[0145] The first power supply state set may include, but is not limited to, normal power supply state, hold state, and power-off state; the second power supply state set may include, but is not limited to, test power supply state and test sleep state.

[0146] The power dependency information across die test units can include power domain affiliation, power supply timing dependency, power dependency of isolation enable signals, and power noise tolerance for level transitions in test modes.

[0147] Step S1022: Based on the first power supply state set of each die, the second power supply state set of each die, and the power supply dependency information, determine the timing state constraints of the functional power supply and the test power supply of each die.

[0148] State constraints refer to the timing coordination rules that each die's functional power supply and the test power supply must follow during testing. These state constraints may include, but are not limited to, power state transition rules, interlocking conditions, and waiting mechanisms.

[0149] In one possible implementation, the power state transition rules can be determined based on the first power state set of each die, the second power state set of each die, and power dependency information.

[0150] Among them, the state constraints can include, in the design for testability test mode, the test power supply of the seventh die located in the middle layer is in a normal power supply state, and the test power supply of the eighth die located in the top layer, the test power supply of the ninth die located in the bottom layer, and the functional power supply of each die switch power supply states according to test requirements.

[0151] In actual execution, when DFT testing is initiated, the test power supply of the seventh die located in the middle layer can be switched from test sleep state to test power supply state, and the functional power supply switches to the corresponding mode according to the test requirements. After the test is completed, the test power supply switches from test power supply state to test sleep state, and the functional power supply returns to the specified state in the functional mode. When low-power scenario verification is required, the functional power supply of some dies is allowed to switch to power-down or state-holding mode, while the test power supply of the die maintains the test power supply state or switches to test sleep state according to the power dependency information of the cross-die test unit. When voltage switching verification is performed, the test power supply remains unchanged during the voltage switching process of the functional power supply, and is adjusted according to the test requirements after the voltage switching is completed.

[0152] State constraints may also include the following: when the functional power supply of the tenth die is in a power-off state, the test power supply of the tenth die is in a normal power supply state, the test isolation unit of the tenth die is powered by the test power supply of the tenth die, and the isolation enable signal of the test isolation unit of the tenth die is valid.

[0153] In actual operation, when the functional power supply of a die is completely powered down, the test power supply of that die must not be in test power supply mode, unless the cross-die test unit of that die still needs to communicate with other dies through the TSV test port (in which case the test power supply can remain in test power supply mode, but the cross-die test isolation unit must be enabled to block the propagation of unknown states); when the functional power supply of a die is in the process of voltage switching, the test power supply of that die should remain unchanged in its current state, and be adjusted according to the test requirements after the voltage switching is completed, so as to avoid the test signal being distorted due to power supply voltage mismatch; when the test power supply of a die is in test power supply mode, the functional power supply of that die must not switch to a state incompatible with the test scenario (e.g., when the test requires the functional unit of the die to provide a reference voltage, the functional power supply must not be powered down).

[0154] State constraints may also include that, when the functional power supply of the eleventh die is in the powered state, the supply voltage of the test power supply of the eleventh die is compatible with the supply voltage of the functional power supply of the eleventh die.

[0155] In actual operation, when the functional power supply of a die switches from a power-down state to a normal power supply state, the voltage can be stabilized before the test power supply can be switched to the test power supply state; when the test power supply of a die switches from a test sleep state to a test power supply state, the power supply must be stabilized before starting the DFT test operation; and when the functional power supply of a die switches voltage, the voltage must be stabilized before signal transmission across die test units can be allowed.

[0156] By adopting the above technical solution and determining the state constraints, a clear timing control basis can be provided for the coordinated operation of the functional power supply and the test power supply of the three-dimensional stacked chip in test mode.

[0157] In some embodiments, the cross-die test unit includes at least one of a test isolation unit, a test level conversion unit, and a through-silicon via (TSV) test port.

[0158] In this embodiment, when the cross-die test unit includes a test isolation unit, the power supply dependency information of the test isolation unit includes the power supply domain affiliation information of the test isolation unit and the isolation power supply dependency relationship of the isolation enable signal; the isolation enable signal is a control signal used to control the test isolation unit to be turned on or off; the isolation power supply dependency relationship is used to characterize the power supply state on which the isolation enable signal depends.

[0159] In the case where the cross-die test unit includes a test level shifting unit, the power supply dependency information includes the input power domain, output power domain, shift threshold, and power supply noise margin of the test level shifting unit.

[0160] When the cross-die test unit includes a through-silicon via (TSV) test port, the power dependency information includes the power domain binding information of the TSV test port and the signal transmission rules.

[0161] In this way, by defining the power dependence information for different types of cross-die test units, the power intent description model can accurately describe the power characteristics of the three-dimensional stacked chips in the cross-die test scenario, thus providing a precise basis for the subsequent construction of the state constraints of functional power supplies and test power supplies.

[0162] Based on the above embodiments, this application also proposes a chip simulation and verification device. Figure 2 This is a schematic diagram of a chip simulation and verification device provided in an embodiment of this application, as shown below. Figure 2 As shown, the chip simulation verification device 200 includes a determination module 201, a construction module 202, and a verification module 203.

[0163] The determination module 201 is used to determine the power intention description model of the three-dimensional stacked chip based on the design parameters of the three-dimensional stacked chip; wherein, the power intention description model is used to describe the first power intention of the functional unit of each die in the three-dimensional stacked chip, and the second power intention of the test unit of each die, and the test unit includes on-chip test unit and cross-die test unit. The construction module 202 is used to construct the timing state constraints of the functional power supply and the test power supply of each die based on the power supply intent description model; wherein, the functional power supply is used to power the functional unit of the corresponding die; the test power supply is used to power the on-chip test unit and cross-die test unit of the corresponding die. The verification module 203 is used to perform simulation verification of the test path of at least one die under at least one power supply state combination of various functional power supplies according to the state constraints, and obtain the simulation verification results.

[0164] The description of the above device-side embodiments is similar to the description of the above method embodiments, and has similar beneficial effects. For technical details not disclosed in the device embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0165] The following describes the application of the chip simulation verification method provided in the embodiments of this application in a real-world scenario, mainly involving a power-aware DFT verification method for 3D stacked chips.

[0166] The 3D IC (three-dimensional integrated circuit) power intent description scheme is a description scheme based on the IEEE 1801 standard UPF (Unified Power Format) to complete power intent modeling. However, this standard is originally designed for single die design and can only define the basic power interconnection relationship between dies at the top level of the 3D IC chip. It has not been extended for cross-die test scenarios, and cannot describe the power characteristics of cross-die test isolation, level conversion and TSV through-silicon via test ports. It also does not establish the association rules between the DFT power domain in the die and the top-level cross-die power network.

[0167] In related technologies, 3D IC DFT verification schemes can be implemented in the following two ways: Method 1 follows the DFT verification method for 2D chips, independently designing scan chains, MBIST, and IJTAG (Internal JTAG) test circuits for each die of the 3D IC, and performing DFT functional verification within a single die. However, this method does not consider the impact of different power states of multiple dies on cross-die test paths.

[0168] Method 2 involves building a basic 3D PG (power / ground) network simulation environment, performing static voltage drop simulation analysis only on the local PG network (power supply network) and TSV power supply channel of the bare die. However, this method does not incorporate cross-die power supply noise collaborative analysis based on the dynamic current surges during DFT circuit operation.

[0169] Method 3: Perform individual DFT verification on each die under a single test scenario where all dies are powered normally. However, this method does not establish a collaborative verification mechanism between the functional power supply and the DFT test power supply. It only covers a single test scenario where all dies are powered normally, and does not verify low-power scenarios such as some dies losing power, maintaining their state, and voltage switching.

[0170] In summary, the relevant technologies are essentially simple transfers of single-die DFT verification methods to the 3D IC field. They only realize the independent verification of each die DFT circuit and the basic simulation of 3D IC power networks, but fail to achieve deep integration of DFT verification with the multi-power domain characteristics of 3D ICs and cross-die power interconnects.

[0171] The embodiments proposed in this application have at least the following technical effects: First, addressing the issue that the existing Unified Power Format (UPF) standard is natively designed for single-die designs and cannot adapt to cross-die design testability (DFT) testing of three-dimensional integrated circuits (3D ICs), this application can extend the UPF model to achieve an accurate description of power characteristics related to cross-die testing, thereby improving the technical defect of poor power state adaptability.

[0172] Secondly, to address the issue of insufficient robustness of cross-die test paths under different power supply conditions, this application can effectively verify DFT paths in multi-power supply combination scenarios, thereby improving the connectivity and signal integrity of cross-die test paths in three-dimensional stacked chips under various power supply conditions.

[0173] Furthermore, regarding the issue that cross-die power supply noise caused by DFT dynamic current is not analyzed, this application can accurately locate the test failure risk caused by power supply noise and fully consider the impact of power supply noise on the DFT test path to improve verification coverage.

[0174] Finally, to address the issue of low verification coverage in 3D IC DFT, this application can build a collaborative simulation platform to achieve comprehensive coverage of low-power scenarios, improve verification integrity, and reduce tape-out risks.

[0175] The purpose of the embodiments proposed in this application is to overcome the shortcomings of the related technologies in 3D stacked chip DFT verification, such as poor power state adaptability, insufficient verification coverage, and insufficient consideration of the impact of power noise. It provides a power-aware 3D DFT verification method for 3D stacked chips, which is based on UPF unified power intent and PG power network simulation to realize the completeness and robustness verification of DFT circuits under multiple dies and multiple power domains, thereby improving the 3D IC DFT coverage and tape-out success rate.

[0176] Figure 3 This is a flowchart of a power-aware 3D DFT verification method for 3D stacked chips provided in an embodiment of this application, as shown below. Figure 3 As shown, the method includes the following steps S301 to S306.

[0177] Step S301: Construct the UPF extended model of the 3D stacked chip.

[0178] In this step, an extended power intent description related to cross-die testing can be built based on the UPF 2.0+ standard.

[0179] Power intent descriptions corresponding to cross-die test isolation units and cross-die test level conversion units (i.e., the test level conversion units in the above embodiments) can be added to the UPF model of related technologies to obtain the UPF extended model of the 3D stacked chip, namely the power intent description model in the above embodiments. The cross-die test isolation units and cross-die test level conversion units can be existing hardware in 3D DFT.

[0180] For cross-die test isolation units, a power supply intent description can be added to the UPF model. Cross-die test isolation units are set between any two adjacent dies. In the UPF, the power supply domain of the cross-die test isolation unit is defined as the DFT test power domain; that is, the cross-die test isolation unit is powered by the power signal in the DFT test power domain. Simultaneously, the isolation enable signal of the cross-die test isolation unit is defined to depend on the power state of the DFT test control signal; that is, the power domain of the isolation enable signal is associated with the DFT test power domain, ensuring that the isolation enable signal is only effective when the DFT test power supply is in a normal power supply state, thereby controlling the cross-die test isolation unit to correctly perform isolation or conduction operations.

[0181] For cross-die test level conversion units, their power supply intent descriptions can be added to the UPF model. Cross-die test level conversion units are set between any two adjacent dies. In the UPF model, the input power domain of the cross-die test level conversion unit is defined as the functional power domain of the corresponding die, and the output power domain is defined as the DFT test power domain. Simultaneously, the conversion threshold and power supply noise margin of the cross-die test level conversion unit are clearly defined to ensure that the test signal can correctly complete the level conversion when crossing multiple voltage domains and maintain the integrity of the converted signal within the specified power supply noise margin.

[0182] It should be noted that a power intent description for the TSV test port can also be added to the UPF model. The TSV test port is defined as a cross-layer power-aware port and bound to the DFT test power domain. In the UPF, the TSV test port is defined to transmit test signals only when the DFT test power is normally powered; when the functional power state switches, the TSV test port remains in a high-impedance state to avoid signal interference.

[0183] Step S302: Construct the joint state machine.

[0184] In this step, the functional power states (normal power supply, hold, complete power failure) and DFT test power states (test power supply, test sleep) of each die can be extracted from the extended UPF model to construct a joint state machine.

[0185] During implementation, the following jump rules can be defined: When initiating DFT testing, the DFT test power supply of the intermediate layer interconnect die is given priority. The top-level logic die and the bottom-level memory die switch to test power supply state according to test requirements. During the test, if the bottom-level memory die does not need to be tested, its functional power supply can be switched to hold state, and its DFT test path can be isolated by the cross-die test isolation unit to avoid affecting the test of the top-level logic die. When the voltage is switched, the operating voltage of the DFT test circuit is adjusted synchronously to ensure that the test signal matches the voltage and avoid test signal distortion.

[0186] Step S303: Build a co-simulation platform.

[0187] In this step, DFT netlists, 3D PG netlists, and UPF extended models can be integrated to build a co-simulation platform.

[0188] The DFT netlist contains the scan chain, IJTAG controller, and MBIST module for each die; the 3D PG netlist contains the circuit model of the PG network, TSV power supply channel, and micro-bump interconnect structure for each die.

[0189] In one possible implementation, a hierarchical macromodel approach can be used to construct an equivalent macromodel for the PG network of each bare die, thereby improving simulation efficiency.

[0190] Step S304: Perform DFT simulation in low-power mode.

[0191] In this step, a variety of typical power supply combination scenarios can be automatically traversed based on a joint state machine. A power supply combination scenario refers to a combination of power states of various die functionalities. Adaptive DFT tests are performed under each of the multiple scenarios, with the complexity of the test logic increasing sequentially for each scenario. The multiple typical power supply combination scenarios can include at least the following scenarios 1 to 3.

[0192] For scenario 1, some dies are powered normally while the rest are powered down; only a single die is powered normally, so only the DFT test of a single die is required, and there is no cross-die interaction. The test is relatively simple and can use the same DFT verification logic as ordinary 2D.

[0193] For scenario 2, the intermediate layer interconnect die is powered normally, while the other dies are in a hold mode; at least one die is powered normally, and the other dies may be powered normally. When cross-die interaction is involved, a co-simulation platform is used for dynamic simulation; when cross-die interaction is not involved, only the DFT test of a single die is required. Since cross-die interaction is not involved, the test is simpler and the ordinary 2D DFT verification logic can be used.

[0194] For scenario 3, all dies are under normal power supply and voltage switching is performed; cross-die interaction is involved and voltage switching is required; dynamic simulation is performed on DFT circuits such as scan chain, MBIST, and IJTAG to verify the integrity of scan chain shift, the test accuracy of MBIST, and the control effectiveness of IJTAG.

[0195] In this case, the TSV-level X-state propagation strategy defined in the UPF extended model can be used to detect whether the X-state (i.e., the unknown state in the above embodiment) generated when the die is powered off will be injected into the scan chain of the adjacent die through the TSV test port. The X-state propagation can be blocked by the inserted X-sink unit (i.e., the unknown state absorption unit in the above embodiment) to avoid simulation false alarms.

[0196] Step S305: Back-calibrate the DFT operating current and perform PG power supply noise analysis.

[0197] In this step, the peak current during scan chain shift and the dynamic current waveform during MBIST operation can be extracted from the simulation results obtained in step S304, back-annotated to the 3D PG netlist, and dynamic IR-drop simulation can be performed.

[0198] For example, by using dynamic IR-drop simulation, the peak voltage drop of the TSV power supply channel and the voltage fluctuation range across the die PG network can be obtained, thereby assessing the degree of interference of power supply noise on the DFT test signal; at the same time, it can be used to locate whether there is an IR-drop problem and identify it as a local power supply noise problem caused by DFT current surge.

[0199] Step S306: Verification result feedback and optimization.

[0200] In this step, addressing the excessive IR-drop issue identified in step S305, the DFT architecture can be adjusted by splitting the scan chain of the top-level logic die into two segments to reduce current surges in a single scan chain segment. Simultaneously, the routing of the TSV power supply channels in the 3D PG netlist is optimized by increasing the number of TSVs and reducing the power supply resistance. After adjustment, the above steps are repeated, and simulation verification is performed again. The peak voltage drop of the TSV power supply channels is reduced to 78mV, and the local IR-drop of the scan chain is reduced to 92mV, until the verification requirements are met, thus completing the 3DDFT verification.

[0201] The embodiments of this application, through the above technical solutions, can realize the integrity and robustness verification of DFT circuits under multiple bare dies and multiple power domains of 3D stacked chips, effectively avoiding the risk of DFT test failure and improving the chip tape-out success rate.

[0202] The embodiments of this application can expand the power intent description range of UPF, and can incorporate the power characteristics of cross-die test isolation, level conversion, and TSV test ports into the UPF model. This solves the problem that existing UPF cannot adapt to cross-die DFT testing of 3D stacked chips, and achieves accurate matching between power intent and DFT architecture, providing a foundation for power-aware DFT verification.

[0203] A joint state machine for functional power supply and DFT test power supply was constructed, which can fully cover some low-power scenarios such as die power loss, hold, and voltage switching. The robustness of DFT circuit under different power states is verified by dynamic simulation, ensuring the connectivity and signal integrity of the test path and significantly improving the DFT verification coverage.

[0204] It also realizes the co-simulation of DFT operating current and 3D PG netlist, back-annotates the current surge during DFT testing to the PG network, accurately analyzes the impact of dynamic IR-drop and power supply noise on DFT testing, locates test failure risk points in advance, avoids test mistests and failures caused by high DFT current, and improves the chip tape-out success rate.

[0205] In summary, the entire verification process forms a closed loop. Through verification result feedback and optimization, the UPF model and DFT architecture can be dynamically adjusted to adapt to the multi-die and multi-power domain characteristics of 3D stacked chips. It has strong versatility and scalability and is suitable for different types of 3D stacked chips and chiplet / chip products.

[0206] It should be noted that the descriptions of the above device embodiments are similar to those of the above method embodiments, and have similar beneficial effects. For technical details not disclosed in the device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0207] Figure 4 This is a hardware entity diagram of an electronic device provided in an embodiment of this application, such as... Figure 4 As shown, the hardware entity of the electronic device 400 includes a processor 401 and a memory 402, wherein the memory 402 stores a computer program that can run on the processor 401, and the processor 401 executes the program to implement the steps in the method of any of the above embodiments.

[0208] The memory 402 stores computer programs that can run on the processor. The memory 402 is configured to store instructions and applications that can be executed by the processor 401. It can also cache data to be processed or already processed by the processor 401 and various modules in the computer device 400 (e.g., image data, audio data, voice communication data and video communication data). It can be implemented by flash memory or random access memory (RAM).

[0209] The processor 401 implements the steps of the above method when executing the program. The processor 401 typically controls the overall operation of the computer device 400.

[0210] This application provides a computer storage medium that stores one or more programs, which can be executed by one or more processors to implement the steps of the above method.

[0211] It should be noted that the descriptions of the storage medium and device embodiments above are similar to the descriptions of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0212] The aforementioned processor can be at least one of the following: Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), Digital Signal Processing Device (DSPD), Programmable Logic Device (PLD), Field Programmable Gate Array (FPGA), Central Processing Unit (CPU), Controller, Microcontroller, and Microprocessor. It is understood that other electronic devices can also implement the functions of the aforementioned processor, and this application does not specifically limit the specific implementation.

[0213] The aforementioned computer storage media / memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM), etc.; or it can be various terminals that include one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0214] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0215] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0216] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0217] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0218] Furthermore, in the various embodiments of this application, all functional units can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units. Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0219] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0220] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A chip simulation and verification method, characterized in that, include: Based on the design parameters of the three-dimensional stacked chip, a power intention description model of the three-dimensional stacked chip is determined; wherein, the power intention description model is used to describe the first power intention of the functional unit of each die in the three-dimensional stacked chip, and the second power intention of the test unit of each die, wherein the test unit includes on-chip test unit and cross-die test unit. Based on the power supply intent description model, the timing state constraints of the functional power supply and the test power supply of each die are constructed; wherein, the functional power supply is used to power the functional unit of the corresponding die; the test power supply is used to power the on-chip test unit and the cross-die test unit of the corresponding die. Based on the state constraints, at least one of the bare dies is subjected to simulation verification of the test path under at least one power supply state combination of each of the functional power supplies, and the simulation verification results are obtained.

2. The method according to claim 1, characterized in that, The step involves simulating and verifying the test path of at least one of the bare dies under at least one power supply state combination of each of the functional power supplies, based on the state constraints, to obtain simulation verification results, including: Obtain the test circuit structure of the test unit in the three-dimensional stacked chip, and the power supply network structure of the three-dimensional stacked chip; The test circuit structure, the power supply network structure, and the power supply intention description model are merged to obtain a joint simulation platform; Based on the state constraints, the test path of at least one of the bare dies is simulated and verified using the co-simulation platform under at least one power supply state combination of each of the functional power supplies, and the simulation verification results are obtained.

3. The method according to claim 2, characterized in that, The three-dimensional stacked chip includes at least a first die and a second die located in adjacent layers; based on the state constraints, the simulation verification of at least one die under at least one power supply state combination of each of the functional power supplies is performed using the co-simulation platform to obtain simulation verification results, including: For at least one of the power supply state combinations, under the power supply state combination, based on the state constraints, the unknown state signal at the through-silicon via test port of the first die and the unknown state signal in the test path of the second die are detected through the co-simulation platform, and the functional power supply of the first die is in a power-off state. If, under any power supply state combination, an unknown state signal is detected at the through-silicon via test port of the first die and the unknown state signal is detected in the test path of the second die, then it is determined that the simulation verification result characterizes an unknown state propagation anomaly in the test path of the three-dimensional stacked chip.

4. The method according to claim 3, characterized in that, The power supply intention description model defines power supply operation information under at least one combination of power supply states for each of the functional power supplies; Under the power supply state combination, based on the state constraints, the co-simulation platform is used to detect unknown state signals at the through-silicon via (TSV) test port of the first die and to detect unknown state signals in the test path of the second die, including: Based on the power operation information, the first through-silicon via (TSV) test port of each die is determined under the power supply state combination; the first TSV test port generates an unknown state signal under the power supply behavior of the functional power supply of the corresponding die; In the co-simulation platform, an unknown state absorption unit is inserted into the first through-silicon via test port to obtain an updated co-simulation platform; the unknown state absorption unit is used to filter unknown state signals. Based on the aforementioned state constraints, the updated co-simulation platform is used to detect the unknown state signals at the through-silicon via test ports of the first die under the aforementioned power supply state combinations, and to detect the unknown state signals in the test paths of the second die.

5. The method according to claim 1, characterized in that, Each of the aforementioned power supply state combinations has a corresponding verification scenario; The step involves simulating and verifying the test path of at least one of the bare dies under at least one power supply state combination of each of the functional power supplies, based on the state constraints, to obtain simulation verification results, including: According to the order of resource consumption cost required for simulation verification in the corresponding verification scenario from low to high, for each power supply state combination, according to the state constraints, at least one die is subjected to simulation verification of the test path under the power supply state combination to obtain the simulation verification result under the power supply state combination.

6. The method according to claim 5, characterized in that, The at least one power supply state combination includes a first power supply state combination, a second power supply state combination, and a third power supply state combination, in which the resource consumption cost required for simulation verification in the corresponding verification scenario increases sequentially, wherein: Under the first power supply state combination, the functional power supply of the third die located at the top layer of the three-dimensional stacked chip is in a normal power supply state, and the functional power supply of the fourth die other than the third die in the three-dimensional stacked chip is in a power-off state. Under the second power supply state combination, the functional power supply of the fifth die located in the middle layer of the three-dimensional stacked chip is in the normal power supply state, and the functional power supply of the sixth die other than the third die in the three-dimensional stacked chip is in the hold state. Under the third power supply state combination, the functional power supply of each die in the three-dimensional stacked chip is in a normal power supply state, and at least one of the die's functional power supplies supports voltage switching.

7. The method according to claim 1, characterized in that, The simulation verification results include sub-simulation verification results corresponding to each of the power supply state combinations under the design for testability test mode; the method further includes: From the sub-simulation verification results corresponding to each of the power supply state combinations, extract the first fluctuation index of the operating current of the test unit of each bare die under the corresponding power supply state combination; For each power supply state combination, the first fluctuation index of the operating current of the test unit of each die under the power supply state combination is back-annotated to the power supply network structure of the three-dimensional stacked chip, and power supply disturbance simulation is performed on the updated power supply network structure of the three-dimensional stacked chip to obtain the second fluctuation index of the operating voltage of the test unit of each die under the corresponding power supply state combination. Based on the second fluctuation index of the operating voltage of the test path of each die under at least one power supply state combination, the test failure risk points caused by power supply noise in the test path of each die are identified.

8. The method according to claim 7, characterized in that, The power supply network structure includes the power supply network of each die and the through-silicon via power supply channel model; The updated power supply network structure of the three-dimensional stacked chips is subjected to power disturbance simulation to obtain a second fluctuation index of the operating voltage of each die's test unit under the corresponding power supply state combination, including: An equivalent macro model is constructed for the updated power supply network of each of the aforementioned dies; wherein the port characteristics of the equivalent macro model are consistent with the port characteristics of the updated power supply network of the corresponding die. The equivalent macro model of each die and the through-silicon via (TSV) power supply channel model are used to perform top-level power supply disturbance simulation to obtain the second fluctuation index of the operating voltage of the test unit of each die under the corresponding power supply state combination; wherein, the TSV power supply channel model is the equivalent circuit model of the power supply channel of the TSV test port.

9. The method according to any one of claims 1 to 8, characterized in that, The method further includes: If the simulation verification result does not meet the expected conditions, repeat the following steps until the updated simulation verification result meets the expected conditions: Adjust at least one of the design parameters of the three-dimensional stacked chip to obtain the updated design parameters of the three-dimensional stacked chip; the at least one of the following includes at least one of the following: the second power supply intention of at least one test unit of the die, the test circuit structure of at least one test unit of the die, and the power supply network structure of the three-dimensional stacked chip; Based on the updated design parameters, an updated power intention description model for the three-dimensional stacked chip is determined, and based on the updated power intention description model, updated state constraints in timing are constructed for the functional power supply and test power supply of each die. Based on the updated state constraints, simulation verification of the test path is performed on at least one of the bare dies under at least one power supply state combination of each of the functional power supplies to obtain the updated simulation verification results.

10. The method according to any one of claims 1 to 8, characterized in that, The second power supply is intended to describe the power supply dependency information of the cross-die test units of each of the dies; The step of constructing the timing-related state constraints for the functional power supply and test power supply of each die based on the power supply intent description model includes: From the power intent description model, extract the first power supply state set supported by the functional power supply of each die and the second power supply state set supported by the test power supply of each die, and extract the power supply dependency information of the cross-die test unit. Based on the first power supply state set of each die, the second power supply state set of each die, and the power dependence information, determine the timing state constraints of the functional power supply and the test power supply of each die.

11. The method according to claim 10, characterized in that, The state constraints include at least one of the following: In the design for testability test mode, the test power supply of the seventh die located in the middle layer is in normal power supply state, while the test power supply of the eighth die located at the top layer, the test power supply of the ninth die located at the bottom layer, and the functional power supply of each die switch power supply state according to test requirements. When the functional power supply of the tenth die is in a power-off state, the test power supply of the tenth die is in a normal power supply state, the test isolation unit of the tenth die is powered by the test power supply of the tenth die, and the isolation enable signal of the test isolation unit of the tenth die is valid. When the functional power supply of the eleventh die is in the power supply state, the power supply voltage of the test power supply of the eleventh die is matched with the power supply voltage of the functional power supply of the eleventh die.

12. The method according to claim 10, characterized in that, The cross-die test unit includes at least one of a test isolation unit, a test level conversion unit, and a through-silicon via (TSV) test port. The power dependence information of the cross-die test unit includes: When the cross-die test unit includes a test isolation unit, the power supply dependency information of the test isolation unit includes the power supply domain affiliation information of the test isolation unit and the isolation power supply dependency relationship of the isolation enable signal; the isolation enable signal is a control signal used to control the test isolation unit to be turned on or off; the isolation power supply dependency relationship is used to characterize the power supply state on which the isolation enable signal depends. When the cross-die test unit includes a test level conversion unit, the power supply dependency information includes the input power domain, output power domain, conversion threshold, and power supply noise margin of the test level conversion unit. When the cross-die test unit includes a through-silicon via (TSV) test port, the power dependency information includes the power domain binding information and signal transmission rules of the TSV test port.

13. A chip simulation and verification device, characterized in that, The apparatus is used to simulate and verify a three-dimensional stacked chip, the three-dimensional stacked chip comprising multiple stacked dies, and the apparatus includes: A determination module is used to determine the power intent description model of the three-dimensional stacked chip based on the design parameters of the three-dimensional stacked chip; wherein, the power intent description model is used to describe the first power intent of the functional unit of each die in the three-dimensional stacked chip, and the second power intent of the test unit of each die, the test unit including on-chip test unit and cross-die test unit; A construction module is used to construct the timing state constraints of the functional power supply and the test power supply of each of the dies based on the power intent description model; wherein, the functional power supply is used to power the functional unit of the corresponding die; the test power supply is used to power the on-chip test unit and the cross-die test unit of the corresponding die. The verification module is used to perform simulation verification of the test path for at least one of the bare dies under at least one power supply state combination of each of the functional power supplies, based on the state constraints, and to obtain the simulation verification results.

14. An electronic device comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that, When the processor executes the program, it implements the method of any one of claims 1-12.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 12.

16. A computer program product, said computer program product comprising a non-transitory computer-readable storage medium storing a computer program, characterized in that, When the computer program is read and executed by a computer, it implements the method described in any one of claims 1 to 12.

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