A method for parallel acceleration of static timing analysis

Abstract

The application discloses a method for parallel acceleration of static timing analysis, and belongs to the field of electronic design automation, and comprises the following steps: RCTree network extraction and data structure initialization; RCTree topology sorting based on breadth-first search, all nodes are divided into different levels and rearranged; the rearranged data is transmitted to GPU memory; GPU parallel calculation of downstream capacitance; GPU parallel calculation of interconnection line delay; calculation result feedback and timing diagram update. The application eliminates the strong data dependency between nodes in the RCTree network, reasonably divides and maps the serial interconnection line delay calculation task to the GPU thread model, so that efficient parallel calculation of the interconnection line delay is realized.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, and in particular to a method for parallel acceleration of static timing analysis. Background Technology

[0002] In advanced process node integrated circuit (IC) design, static timing analysis (STA) is a core step in verifying whether the chip's timing performance meets the standards. As process dimensions continue to shrink, the proportion of delay caused by interconnects in the total path delay is increasing, becoming a key factor determining the chip's maximum operating frequency.

[0003] To accurately calculate interconnect delays, industry typically uses the RTree (Resistor-Capacitor Tree) model to model interconnects. In traditional STA tools, RTree delay calculations usually employ the Elmore delay model or higher-order moment-matching methods (such as D2M, AWE, etc.). However, traditional RTree delay calculation methods have the following technical drawbacks: Strong data dependencies lead to serial computation: RTree is essentially a tree graph structure. When calculating the latency or downstream capacitance of a node, it must rely on the calculation results of its parent node or even the entire subtree. This upstream and downstream data dependency means that traditional CPUs can only use depth-first search (DFS) or breadth-first search (BFS) for serial traversal during computation, and cannot take advantage of the multi-core parallelism of modern processors.

[0004] CPU computing power bottleneck: Modern very large-scale integrated circuit (VLSI) designs often involve billions of transistors and hundreds of millions of R-Tree networks. Faced with such a massive computing scale, traditional CPU-based serial computing methods encounter a severe computing power bottleneck, resulting in extremely long runtimes for STA tools and significantly slowing down chip design iteration cycles.

[0005] GPU parallelization is challenging: GPUs have tens of thousands of computing cores, making them ideal for handling highly parallel tasks. However, due to the implicit data dependencies in R-Tree computation (such as the need for the parent node's state to compute child node latency), directly porting existing serial algorithms to GPUs leads to a large amount of thread idle waiting (i.e., thread divergence and synchronization overhead), which not only fails to achieve speedup but may even be slower than CPU computation.

[0006] Therefore, how to break the data dependency in RCTree computation and transform it into a data structure and execution logic suitable for large-scale parallel computing on GPUs has become a pressing technical problem to be solved in order to improve the performance of static time series analysis. Summary of the Invention

[0007] The purpose of this invention is to provide a method for parallel acceleration of static timing analysis to solve the current problems of serial computing bottlenecks and difficulties in GPU parallelization.

[0008] To address the aforementioned technical problems, this invention provides a method for parallel acceleration of static timing analysis, comprising the following steps: Step S1: RCTree network extraction and data structure initialization; Step S2: Based on breadth-first search, perform topological sorting of the RTree, divide all nodes into different levels, and rearrange them. Step S3: Transfer the rearranged data to the GPU memory; Step S4: The GPU performs parallel computation of the downstream capacitor; Step S5: GPU parallel computing interconnect latency; Step S6: Calculation results are fed back and timing diagram is updated.

[0009] In one implementation, the RCTree network extraction and data structure initialization include: During static timing analysis, the parasitic parameter file of interconnects extracted from the layout is read, and the RCRTree graph data structure is constructed. Define the set of nodes for an RCTree ,in The driving source node; the edge set Each edge represents a resistor R, and each node represents a capacitance C to ground.

[0010] In one embodiment, step S2 includes: Taking advantage of the acyclic nature of RCTree, to drive the source node Using the root node, perform a breadth-first search topological sort; root node Defined as Level 0; If node The parent node at the 1st Layers, then nodes Classified to the The level, or Level k+1; Record the level ID of each node, as well as the number of nodes and the list of node indices in each level, to generate a level mapping table; Based on the mapping table, the original tree-linked node data is linearly and continuously rearranged in memory according to the hierarchical order to construct a flattened array suitable for continuous reading by the GPU; wherein, the node data includes resistance value, capacitance value, and parent node pointer.

[0011] In one implementation, the transfer of the rearranged data to GPU memory includes: The linearly rearranged RTree hierarchy data, node capacitor array, edge resistor array, and hierarchy mapping table are copied from CPU main memory to GPU global memory via the PCIe bus.

[0012] In one implementation, the GPU parallel computation of downstream capacitance employs a bottom-up reverse traversal approach. A kernel function is initiated on the GPU side, and based on a topologically sorted hierarchical mapping table, the downstream equivalent capacitance of each node is computed in parallel from the highest level to the 0th level. : Fully parallel within a layer: Within the same layer, since the nodes are not parent-child relationships, each node is allocated a GPU thread to execute... The calculation; where, It is a node The downstream equivalent capacitance, It is a node Its own capacitance to ground. It is a node The j-th child node; Inter-layer synchronization: After all threads in the current layer have completed their calculations, the GPU's native synchronization barrier ensures that the results are written to the video memory before starting the kernel function calculation for the next layer.

[0013] In one implementation, the GPU parallel computing interconnect latency is achieved using a top-down forward traversal approach, with downstream equivalent capacitance... After all calculations are complete, the kernel function is started again on the GPU to calculate the latency of each node in parallel from level 0 to the maximum level based on topological sorting: Delay at level 0 ; Fully parallel within a layer: for the first layer Layer nodes, Each node is assigned an independent GPU thread, which executes the formula in parallel based on the latency of its parent node and the resistance of the connected edges: ; in, It is a node The parent node, The signal comes from the driver source. propagation to nodes The interconnect delay experienced, This represents the equivalent resistance value of the edge connecting parent node u and child node v. It is a node The downstream equivalent capacitance; Inter-layer synchronization: Also relying on the hierarchical synchronization mechanism, after the delay of the parent node layer is calculated and synchronized, the delay of the child node layer is calculated in parallel.

[0014] In one implementation, step S6 includes: After the GPU completes the latency calculation for all nodes, it copies the latency results of the leaf nodes in the highest level from the GPU memory back to the CPU main memory. The upper-level logic of the static timing analysis tool reads these interconnect latency, adds them to the corresponding timing arc, and continues to complete the subsequent standard cell latency calculation and timing path convergence check.

[0015] In one implementation, the GPU's mesh configuration is as follows: a mapping strategy of using one thread block to process one RTree network and one thread to process one node; if the number of nodes at a certain level of one of the RTrees exceeds the maximum number of threads in a single thread block, then multiple thread blocks are used to process different node segments at the same level in parallel; for extremely small RTrees, fine-grained parallelism at the thread bundle level or multiple small RTrees are merged into one thread block for processing is used to mask the latency overhead of GPU kernel function startup.

[0016] The present invention provides a method for parallel acceleration of static timing analysis, which has the following beneficial effects: (1) Break through the serial bottleneck and greatly improve the computing speed: The original serial traversal with a time complexity of O(N) is transformed into a hierarchical parallel computing with a time complexity of O(H) (H is the height of the tree). For an RTree network containing millions of nodes, this can bring a speedup of tens or even hundreds of times. (2) Extremely low thread synchronization overhead: By pre-dividing the layers through topological sorting, the GPU kernel function only needs to perform one lightweight synchronization between the layers, avoiding the locking mechanism or atomic operation between threads in traditional methods, which greatly improves the utilization of GPU resources. (3) Friendly memory access mode: Combined with the topology sorting results, the resistor and capacitor parameters of RCTree are continuously rearranged in memory, enabling GPU threads to perform merged memory access and hiding memory access latency. (4) Seamless compatibility with existing EDA processes: This invention only replaces the underlying interconnect delay calculation engine, and the upper-level timing graph traversal and constraint analysis logic does not need to be changed, making it easy to integrate into existing commercial or open-source STA tools. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the method for parallel accelerated static timing analysis provided by the present invention.

[0018] Figure 2 This is a schematic diagram of the steps for calculating timing delays in parallel units provided by the present invention. Detailed Implementation

[0019] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a method for parallel acceleration of static timing analysis proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise scales, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0020] This invention provides a method for parallel acceleration of static timing analysis, the overall process of which is as follows: Figure 1 As shown, the specific implementation steps are as follows: Step S1: RCTree network extraction and data structure initialization; During static timing analysis, interconnect parasitic parameter files (such as SPEF (Standard Parasitic Exchange Format)) output by layout extraction tools (such as Cadence Quantus, Synopsys StarRC, etc.) are read. These files are industry-standard files in integrated circuit design, used to store the parasitic parameters of interconnects: the capacitance of each node in the file corresponds to the interconnect (extracted from the capacitance structure in the layout), and the resistance of each edge corresponds to the interconnect segment (calculated from parameters such as resistivity, length, and width of the metal conductors in the layout).

[0021] Based on the node-edge relationships in the file, construct the RTCTree graph data structure: define the node set of the RTCTree. ,in The driving source node; the edge set Each edge represents a resistor R, and each node represents a capacitance C to ground.

[0022] Step S2: RCRTree topology sorting (hierarchical partitioning) based on breadth-first search; Taking advantage of the acyclic nature of RCTree, to drive the source node Using the root node, perform a breadth-first search (BFS) topological sort to divide all nodes into different levels: root node Defined as Level 0; If node The parent node at the 1st Layer, then node Classified to the Level (Level k+1); Record the Level ID of each node, as well as the number of nodes and the list of node indices in each level, to generate a "level mapping table"; Based on this mapping table, the original tree-linked node data (including its own capacitance value and parent node pointer) and edge data (resistance value corresponding to each edge) are linearly and continuously rearranged in memory according to the hierarchical order to construct a flattened array suitable for continuous reading by the GPU.

[0023] Step S3: Data is transferred to GPU memory; The linearly rearranged RTree hierarchy data, node capacitor array, edge resistor array, and hierarchy mapping table are copied from CPU main memory to GPU global memory via the PCIe bus.

[0024] The steps for parallel units to calculate timing delay are as follows: Figure 2 As shown; Step S4: GPU performs parallel computation of downstream capacitors (bottom-up reverse traversal). On the GPU, a kernel function is launched to compute the downstream equivalent capacitance of each node in parallel, based on a topologically sorted hierarchical mapping table, working backward from the highest level (the level where the leaf nodes are located) to the 0th level (the root node). : Fully parallel within a layer: Within the same layer, since the nodes are not parent-child relationships, each node is allocated a GPU thread to execute... The calculation; where, It is a node The downstream equivalent capacitance, It is a node Its own capacitance to ground. It is a node The j-th child node; Inter-layer synchronization: After all threads in the current layer have completed their calculations, the results are written to the GPU memory through the GPU's native synchronization barriers (such as __syncthreads() or stream synchronization) before the kernel function of the next layer (i.e., the parent node layer) is started.

[0025] GPU mesh configuration: A mapping strategy of one block (thread block) processes one RTree network and one thread (thread) processes one node is adopted. If the number of nodes at a certain level of an RTree exceeds the maximum number of threads in a single block, multiple blocks are used to process different node segments at the same level in parallel. For very small RTrees (e.g., number of nodes <32), fine-grained parallelism at the CUDA Warp level or multiple small RTrees can be merged into one block for processing to mask the latency overhead of GPU kernel function startup.

[0026] Step S5: GPU parallel computing interconnect latency (top-down forward traversal); Downstream capacitors After all calculations are complete, the kernel function is started again on the GPU to calculate the latency of each node in parallel from level 0 to the maximum level based on topological sorting (taking Elmore latency as an example): Delay at level 0 (root node) ; Fully parallel within a layer: for the first layer layer( Each node is assigned an independent GPU thread to execute the formula in parallel, based on the latency of its parent node and the resistance of the connecting edges. ; in, It is a node The parent node, The signal comes from the driver source. propagation to nodes The interconnect delay experienced, This represents the equivalent resistance value of the edge connecting parent node u and child node v. It is a node The downstream equivalent capacitance; Inter-layer synchronization: Also relying on the hierarchical synchronization mechanism, after the delay of the parent node layer is calculated and synchronized, the delay of the child node layer is calculated in parallel.

[0027] Step S6: Calculation results are fed back and timing diagram is updated; After the GPU completes the latency calculation for all nodes, it copies the latency results of the leaf nodes (i.e., the sink pins of the RCTree) from the GPU memory back to the CPU main memory. The upper-level logic of the STA tool reads the interconnect latency of these sinks, adds it to the corresponding timing arc, and continues to complete the subsequent standard cell latency calculation and timing path convergence check.

[0028] This invention breaks node-level data dependencies. After topological sorting, nodes within the same level are physically and electrically independent (they belong to different branches and have no shared resistance paths). Therefore, it is not necessary to wait for the entire tree to be calculated; once all nodes at the same level have been calculated, it is safe to proceed to the next level. Fine-grained node locks or atomic operations are elevated to coarse-grained hierarchical synchronization barriers. All threads within the same level can run in parallel without conflict, and only one low-overhead global synchronization is performed between layers, improving the utilization of the GPU's SIMT (Single Instruction Multithreaded) architecture. GPU threads can achieve merged memory access when processing the same level. Using the result of topological sorting as an index, scattered node data (R, C, pointers, etc.) is unfolded into a continuous one-dimensional array in memory hierarchically.

[0029] This invention transforms tree-structured computation into hierarchical computation by performing topological sorting on the RTree network. Utilizing the mathematical characteristic of RTree where nodes at the same level are independent and undependent, nodes at the same level are assigned to different threads on the GPU for parallel processing. By replacing the node-to-node synchronization mechanism with an inter-level synchronization mechanism, the parallelism of the GPU is maximized while maintaining computational accuracy.

[0030] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for parallel acceleration of static timing analysis, characterized in that, Includes the following steps: Step S1: RCTree network extraction and data structure initialization; Step S2: Based on breadth-first search, perform topological sorting of the RTree, divide all nodes into different levels, and rearrange them. Step S3: Transfer the rearranged data to the GPU memory; Step S4: The GPU performs parallel computation of the downstream capacitor; Step S5: GPU parallel computing interconnect latency; Step S6: Calculation results are fed back and timing diagram is updated.

2. The method for parallel acceleration of static timing analysis as described in claim 1, characterized in that, The RTree network extraction and data structure initialization include: During static timing analysis, the parasitic parameter files of interconnects output by the layout extraction tool are read. These files are industry standard files in integrated circuit design and are used to store the parasitic parameters of interconnects: each node in the file corresponds to the capacitance of the interconnect, and each edge corresponds to the resistance of the interconnect segment. Construct the RCTree graph data structure based on the node-edge relationships in the file; Define the set of nodes for an RCTree ,in The driving source node; the edge set Each edge represents a resistor R, and each node represents a capacitor C.

3. The method for parallel acceleration of static timing analysis as described in claim 2, characterized in that, Step S2 includes: Taking advantage of the acyclic nature of RCTree, to drive the source node Using the root node, perform a breadth-first search topological sort; root node Defined as Level 0; If node The parent node at the 1st Layers, then nodes Classified to the The level, or Level k+1; Record the level ID of each node, as well as the number of nodes and the list of node indices in each level, to generate a level mapping table; Based on the mapping table, the original tree-linked node data is linearly and continuously rearranged in memory according to the hierarchical order to construct a flattened array suitable for continuous reading by the GPU; wherein, the node data includes resistance value, capacitance value, and parent node pointer.

4. The method for parallel acceleration of static timing analysis as described in claim 3, characterized in that, The process of transferring the rearranged data to GPU memory includes: The linearly rearranged RTree hierarchy data, node capacitor array, edge resistor array, and hierarchy mapping table are copied from CPU main memory to GPU global memory via the PCIe bus.

5. The method for parallel accelerated static timing analysis as described in claim 4, characterized in that, The GPU parallel computation of downstream capacitance adopts a bottom-up reverse traversal approach. A kernel function is started on the GPU side, and based on a topologically sorted hierarchical mapping table, the downstream equivalent capacitance of each node is computed in parallel from the highest level to the 0th level. : Fully parallel within a layer: Within the same layer, since the nodes are not parent-child relationships, each node is allocated a GPU thread to execute... The calculation; where, It is a node The downstream equivalent capacitance, It is a node Its own capacitance to ground. It is a node The j-th child node; Inter-layer synchronization: After all threads in the current layer have completed their calculations, the GPU's native synchronization barrier ensures that the results are written to the video memory before starting the kernel function calculation for the next layer.

6. The method for parallel acceleration of static timing analysis as described in claim 5, characterized in that, The GPU parallel computing interconnect latency is achieved using a top-down forward traversal method, with downstream equivalent capacitance... After all calculations are complete, the kernel function is started again on the GPU to calculate the latency of each node in parallel from level 0 to the maximum level based on topological sorting: Delay at level 0 ; Fully parallel within a layer: for the first layer Layer nodes, Each node is assigned an independent GPU thread, which executes the formula in parallel based on the latency of its parent node and the resistance of the connected edges: ； in, It is a node The parent node, The signal comes from the driver source. propagation to nodes The interconnect delay experienced, This represents the equivalent resistance value of the edge connecting parent node u and child node v. It is a node The downstream equivalent capacitance; Inter-layer synchronization: Also relying on the hierarchical synchronization mechanism, after the delay of the parent node layer is calculated and synchronized, the delay of the child node layer is calculated in parallel.

7. The method for parallel accelerated static timing analysis as described in claim 6, characterized in that, Step S6 includes: After the GPU completes the latency calculation for all nodes, it copies the latency results of the leaf nodes in the highest level from the GPU memory back to the CPU main memory. The upper-level logic of the static timing analysis tool reads these interconnect latency, adds them to the corresponding timing arc, and continues to complete the subsequent standard cell latency calculation and timing path convergence check.

8. The method for parallel acceleration of static timing analysis as described in claim 7, characterized in that, The GPU's mesh configuration is as follows: a mapping strategy of using one thread block to process one RTree network and one thread to process one node; if the number of nodes at a certain level of one RTree exceeds the maximum number of threads in a single thread block, then multiple thread blocks are used to process different node segments at the same level in parallel; for extremely small RTrees, fine-grained parallelism at the thread bundle level or multiple small RTrees are merged into one thread block for processing is used to mask the latency overhead of GPU kernel function startup.

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