A chip multi-physical field collaborative optimization method based on current vortex regulation, a chip layout structure and an integrated circuit chip

Abstract

The application discloses a chip multi-physical field collaborative optimization method based on current vortex regulation, a chip layout structure and an integrated circuit chip, wherein the chip multi-physical field collaborative optimization method is used for synchronously improving at least two types of physical defects of the chip, and comprises the following steps: obtaining vortex characteristics of current distribution in a chip interconnection structure; constructing a reverse vortex field which is opposite to an original vortex direction and matches the strength according to the vortex characteristics; and applying the reverse vortex field in the chip interconnection layer to offset the original vortex and inhibit current turbulent loss; wherein the synchronously improved physical defects include dynamic power consumption, interconnection crosstalk, device leakage, hot spot temperature rise and PVT parameter drift. The application has the following beneficial effects: the steady-state current base is used to inhibit dynamic flip loss, the long line uniform shunt is used to weaken high-frequency additional loss, and the overall dynamic comprehensive power consumption of chip data transport and interconnection is reduced by 80%-90%.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit chip technology, and in particular to a chip multi-physics field collaborative optimization method based on current eddy current control, chip layout structure, and integrated circuit chip. Background Technology

[0002] Existing AI in-memory computing and high-speed integrated circuit optimization solutions all employ single-point independent compensation architectures, which can only improve a single indicator such as power consumption, crosstalk, leakage current, or thermal effects, without a unified underlying mechanism. Interconnect optimization relies solely on differential traces and shielding layers to cancel crosstalk; bias circuits only statically correct the operating point; memory medium improvements only reduce static tunneling leakage current; and thermal management solutions only provide passive heat dissipation. These solutions are independent of each other and cannot break the positive feedback loop of "eddy current-temperature rise-leakage current-PVT drift." Existing EDA simulation tools can only perform post-optimization performance verification and cannot actively construct reverse eddy fields during the layout design stage to achieve simultaneous suppression of multiple defects. No complete solution based on the simultaneous optimization of multiple physical defects using interconnect four-field coupling current eddy currents has been found in existing ISSCC and IEDM publications. Summary of the Invention

[0003] According to a first aspect of the present invention, a chip multi-physics field collaborative optimization method based on current eddy current control is provided for simultaneously improving at least two types of physical defects in a chip, comprising the following steps: Obtain the eddy current characteristics of the current distribution in the chip interconnect structure; Based on the characteristics of vorticity, a reverse vorticity field is constructed that is opposite in direction and matches the intensity of the original vorticity. A reverse vortex field is applied to the chip interconnect layer to counteract the original vortices and suppress current turbulence loss. Among the physical defects that need to be improved simultaneously are dynamic power consumption, interconnect crosstalk, device leakage, hot spot temperature rise, and PVT parameter drift.

[0004] Furthermore, vorticity characteristics include at least one of current density curl, turbulence intensity, and local vortex distribution.

[0005] Furthermore, the methods for applying a reverse vortex field include: using a staggered via structure, using traces with gradually varying widths, setting spiral or serpentine traces, and inserting at least one of magnetic or dielectric shielding structures between interconnect layers.

[0006] Furthermore, it also includes: configuring a global steady-state bias circuit around the signal path of the chip to provide a steady-state reference current to constrain the current jump during the signal level switching process.

[0007] Furthermore, the amplitude ratio of the steady-state reference current to the signal current is maintained at 0.15 to 0.6; the steady-state bias circuit includes a zero-point calibration sub-circuit, and the static power consumption increment introduced by it is controlled within 0.1% to 5%.

[0008] Furthermore, it also includes: using a layered multi-channel current-guiding structure for long interconnects with a length greater than 150μm within the chip to evenly distribute the concentrated current in order to suppress high-frequency turbulence losses.

[0009] Furthermore, it also includes: setting a three-layer gradient thin-film dielectric structure for the chip's memory cells, with an outer high-resistivity current-limiting layer, a middle functional dielectric layer, and an inner buffer adapter layer to suppress leakage and temperature drift.

[0010] Furthermore, the materials of the three-layer gradient thin film dielectric structure are HfO2, TaOx and TiN, respectively, with a thickness ratio of (1.5~2.5):(4.5~5.5):(2.5~3.0).

[0011] Furthermore, it also includes: embedding passive equalization units at uniform intervals within the memory array in units of subarrays to compensate for global current distortion caused by array edge effects and process deviations, thereby converging PVT parameter drift.

[0012] Furthermore, the passive equalization unit uses a 16×16 subarray as the smallest deployment unit, without changing the original array's operational architecture, read / write logic, and control timing.

[0013] Furthermore, the method can be applied to AI in-memory computing chips, RF differential inductor chips, power management chips, or high-speed serial interface circuits.

[0014] According to a second aspect of the present invention, a chip layout structure based on current eddy current control is provided for generating a reverse eddy current cancellation effect in the chip interconnect structure, comprising: Adjacent conductive channels are configured with currents rotating in opposite directions to form reverse-coupled vortex fields; In the multi-channel array, the central region adopts an alternating reverse arrangement of rows, the edge region adopts a gradually rotating arrangement, and the cross nodes are equipped with isolation media.

[0015] Furthermore, the reverse-coupled vortex field is achieved through a staggered through-hole structure, and the lateral offset of the staggered through-hole is 0.4 to 0.6 times the corresponding metal linewidth.

[0016] Furthermore, the reverse-coupled vortex field is achieved through at least one of the following: a tapered trace, a spiral or serpentine trace, or an interlayer shielding structure.

[0017] Furthermore, the conductive channels include metal interconnects, multilayer vias, power inductors, or power interconnects.

[0018] According to a third aspect of the present invention, an integrated circuit chip is provided, the integrated circuit chip being configured with a chip layout structure according to the second aspect.

[0019] Furthermore, it also includes a global steady-state bias circuit, which is coupled to the chip's global data bus, word lines, and bit lines to provide a steady-state reference current to maintain a constant current base for the signal path.

[0020] Furthermore, the global steady-state bias circuit includes a zero-temperature drift bandgap reference source, a common-source cascode current mirror, and a zero-point calibration sub-circuit; the amplitude ratio of the steady-state reference current to the signal current is maintained at 0.15 to 0.6, and the static power consumption increment introduced by the zero-point calibration sub-circuit is controlled within 0.1% to 5%.

[0021] Furthermore, it also includes a layered multi-channel current-guiding structure, which is applied to interconnects or clock lines with a length greater than 150μm within the chip to uniformly shunt concentrated current in order to suppress high-frequency turbulence losses.

[0022] Furthermore, it also includes a three-layer gradient thin-film dielectric structure, which is disposed in the storage cell and consists of an outer high-resistivity current-limiting layer, an intermediate functional dielectric layer, and an inner buffer adapter layer.

[0023] Furthermore, the materials of the three-layer gradient thin film dielectric structure are HfO2, TaOx and TiN, respectively, with a thickness ratio of (1.5~2.5):(4.5~5.5):(2.5~3.0).

[0024] Furthermore, it also includes passive equalization units, which are uniformly embedded in the memory array at subarray intervals to dynamically compensate for global current distortion caused by array edge effects and process deviations, and to converge PVT parameter drift.

[0025] Furthermore, the passive equalization unit uses a 16×16 subarray as the smallest deployment unit, without changing the original array's operational architecture, read / write logic, and control timing.

[0026] Furthermore, the integrated circuit chips are manufactured using standard CMOS processes ranging from 28nm to 3nm.

[0027] A chip multi-physics field collaborative optimization method based on current eddy current control, according to an embodiment of the present invention, has the following beneficial effects: 1. Significant power consumption optimization and energy efficiency improvement: By suppressing dynamic switching losses through steady-state current substrate and reducing high-frequency additional losses through long-line uniform current shunting, in a typical simulation embodiment, the overall dynamic power consumption of chip data transfer and interconnection is reduced by 80%.

[0028] 2. Excellent crosstalk suppression and high computational accuracy: Through the reverse electromagnetic field cancellation mechanism of staggered vias, the crosstalk suppression rate of high-density parallel array interconnection can reach more than 70%, and the overall array computational error is controlled within 1%.

[0029] 3. Excellent leakage current suppression and strong thermal stability: The gradient composite dielectric structure effectively blocks micro leakage current channels, reducing the overall static leakage current of the unit by 30% to 45%, and lowering the hot spot junction temperature of the active area of ​​the chip by 12 to 15℃.

[0030] 4. Strong PVT robustness and good mass production adaptability: After verification by more than 500 sets of Monte Carlo process deviation simulations, the present invention reduces the maximum relative drift of chip PVT parameters from 18.2% in the traditional scheme to 7.1%.

[0031] 5. Significant cross-domain application effects: In RF chip differential inductors, the Q value is improved by 15% to 25%; in power management chips, the conversion efficiency is improved by 5% to 8%, and the voltage overshoot at switching nodes is reduced by more than 30%.

[0032] 6. It has strong engineering feasibility and is compatible with 28nm to 3nm full-gradient standard CMOS mass production processes, with no additional process barriers.

[0033] 7. The global steady-state bias circuit relies on a four-field coupling model to constrain instantaneous eddy current fluctuations, which significantly reduces dynamic turbulence losses and is the core support for reducing overall interconnect power consumption by 80%~90%. 8. The staggered alternating vias and gradient traces counteract the vortex field of adjacent channels, achieving an array interconnect crosstalk suppression rate of up to 70.8%, and controlling the overall computational error to within 1%. 9. The three-layer gradient dielectric structure suppresses eddy-induced micro-leakage from the device itself, and the layered flow guiding structure simultaneously weakens long-line turbulent heating, resulting in a 12~15℃ decrease in the junction temperature of the active region of the chip. 10. The array-distributed passive equalization unit compensates for global vortex distortion in real time, and the maximum relative drift of PVT in Monte Carlo simulation converges from 18.2% to 7.1%.

[0034] It should be understood that both the foregoing general description and the following detailed description are exemplary and intended to provide further illustration of the claimed technology. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of current eddy current distribution (irregular turbulence) in a traditional chip interconnect structure.

[0036] Figure 2 This is a schematic diagram illustrating the ordered laminar / spiral flow distribution of the current after applying a reverse vortex field according to an embodiment of the present invention.

[0037] Figure 3This is a partial structural schematic diagram of how misaligned through-holes achieve vorticity cancellation according to an embodiment of the present invention.

[0038] Figure 4 This is a schematic diagram illustrating how vorticity cancellation is achieved by gradually varying the width of adjacent traces according to an embodiment of the present invention.

[0039] Figure 5 This is a schematic diagram illustrating the application of a differential inductor in a radio frequency chip according to an embodiment of the present invention.

[0040] Figure 6 This is a schematic diagram illustrating the application of power management chip power stage interconnection according to an embodiment of the present invention.

[0041] Figure 7 This is a schematic diagram of the overall array integration architecture according to an embodiment of the present invention.

[0042] Figure 8 This is a flowchart of a chip multiphysics field collaborative optimization method based on current eddy current control, according to an embodiment of the present invention.

[0043] Figure 9 This is a logic block diagram of the four-field coupled electric field-eddy current-thermal field-leakage current mechanism according to an embodiment of the present invention.

[0044] Figure 10 The waveform diagrams are simulation comparisons of turbulent loss under the condition of current eddy current optimization according to an embodiment of the present invention.

[0045] Figure 11 This is a Monte Carlo PVT parameter distribution statistical histogram according to an embodiment of the present invention. Detailed Implementation

[0046] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, further illustrating the present invention.

[0047] First, combine Figures 2-11 This invention describes a chip multi-physics field collaborative optimization method based on current eddy current control according to a first aspect of an embodiment of the present invention, which is used in chips and has a wide range of applications.

[0048] like Figure 8 As shown in the figure, an embodiment of the present invention provides a chip multi-physics field collaborative optimization method based on current eddy current control, which is used to simultaneously improve at least two types of physical defects in a chip, and includes the following steps: like Figure 8 As shown, in S1, the eddy current characteristics of the current distribution in the chip interconnect structure are obtained.

[0049] like Figure 8 As shown, in S2, based on the vorticity characteristics, a reverse vorticity field is constructed that is opposite in direction and matches the intensity of the original vorticity.

[0050] like Figure 8 As shown, in S3, a reverse vortex field is applied to the chip interconnect layer to counteract the original vortices and suppress current turbulence loss. Among the physical defects that need to be improved simultaneously are dynamic power consumption, interconnect crosstalk, device leakage, hot spot temperature rise, and PVT parameter drift.

[0051] Furthermore, in this embodiment, the vorticity characteristics include at least one of current density curl, turbulence intensity, and local vortex distribution.

[0052] Furthermore, in this embodiment, the method of applying the reverse eddy field includes: using a staggered via structure, using traces with gradually varying widths, setting spiral or serpentine traces, and inserting at least one of magnetic or dielectric shielding structures between interconnect layers.

[0053] Furthermore, in this embodiment, a chip multi-physics field collaborative optimization method based on current eddy current control further includes: configuring a global steady-state bias circuit around the signal path of the chip to provide a steady-state reference current to constrain current jumps during signal level switching. Specifically, a dedicated steady-state bias circuit is deployed around the signal paths of the chip's global data bus, memory array word lines, and bit lines. This circuit is integrated with a zero-temperature drift bandgap reference source, a high-matching common-source cascode current mirror, and a high-precision zero-point calibration sub-circuit. The amplitude ratio of the reference current to the signal current is controlled to be stably maintained between 0.15 and 0.6, ensuring that the signal path always has a constant steady-state current base. This constrains the instantaneous jump amplitude and direction fluctuations of the current during signal level switching, suppressing dynamic switching power consumption and turbulent additional power consumption from the source. The zero-point calibration sub-circuit is used to offset the reference current offset introduced by process and temperature, and the static power consumption increment it introduces is controlled within 0.1% to 5%.

[0054] Furthermore, in this embodiment, a chip multi-physics field collaborative optimization method based on current eddy current control also includes: employing a layered multi-channel current guiding structure for long interconnects with a length greater than 150 μm within the chip to uniformly distribute concentrated current and suppress high-frequency turbulence losses. Specifically, for word lines, bit lines, global clock lines, and backbone data lines with a metal layer length greater than 200 μm within the chip, a layered current guiding structure separated by multiple insulating media is adopted to decompose the traditional single-channel concentrated large current into a multi-channel uniform current distribution; smoothing out the current density gradient across the long line cross-section, suppressing the current skin effect and non-uniform turbulence losses under high-frequency operation.

[0055] Furthermore, in this embodiment, a chip multiphysics field collaborative optimization method based on current eddy current control further includes: setting a three-layer gradient thin-film dielectric structure for the chip's memory cell, with an outer high-resistivity current-limiting layer, a middle functional dielectric layer, and an inner buffer adapter layer to suppress leakage current and temperature drift. The materials of the three-layer gradient thin-film dielectric structure are HfO2, TaOx, and TiN, respectively, with a thickness ratio of (1.5~2.5):(4.5~5.5):(2.5~3.0).

[0056] Furthermore, in this embodiment, a chip multiphysics field collaborative optimization method based on current eddy current control further includes: embedding passive equalization units at uniform intervals within the in-memory array, using subarrays as units, to compensate for global current distortion caused by array edge effects and process deviations, and to converge PVT parameter drift. The passive equalization units use 16×16 subarrays as the smallest deployment unit and do not change the original array's operational architecture, read / write logic, or control timing. The in-memory array includes at least one of RRAM, SRAM, PCM, and Flash.

[0057] Furthermore, the chip multi-physics collaborative optimization method based on current eddy current regulation can be applied to AI in-memory computing chips, RF differential inductor chips, power management chips, or high-speed serial interface circuits.

[0058] The circuits and structures corresponding to each step are coupled to form a closed-loop control system. A steady-state bias circuit constructs a globally stable operating base; misaligned vias cancel crosstalk, improving signal transmission quality through structural regularity; a layered current-guiding structure addresses the bottleneck of global long-line transmission loss; a gradient dielectric structure suppresses leakage current and thermal drift from the device end; and a distributed equalization unit converges global process and operating condition deviations. These five modules work together to break the positive feedback coupling chain of "power surge - hotspot temperature rise - leakage current amplification - parameter drift deterioration," forming a complete, mutually coupled, and synergistic chip collaborative optimization system.

[0059] To better understand this technical solution, the following specific embodiments are used for explanation: like Figure 3 As shown, Example 1: Application of reverse vorticity field based on misaligned through-holes (AI chip in-memory computing array) At the connection points of the upper and lower metal layers in the high-density parallel interconnect of the chip, a staggered via structure is adopted. The lateral offset of the staggered via is preferably 1 / 2 of the corresponding metal linewidth, so that the current rotation direction and electromagnetic field direction of adjacent traces are reversed. The high-density region in the center of the array is arranged alternately in opposite directions, while the edge region is arranged with a gradual transition. The line intersection nodes are filled with isolation dielectric. The principle of reverse electromagnetic field cancellation is used to maximize the suppression of crosstalk in parallel interconnects. Simulation results show that this embodiment achieves an interconnect crosstalk suppression rate of ≥70% and an array operation comprehensive error of ≤0.9%. At the same time, combined with the steady-state bias circuit (reference current to signal current amplitude ratio of 1 / 3), layered current guiding structure (double-layer insulation), gradient composite dielectric (HfO2 / TaOx / TiN three layers, thickness ratio 2:5:3), and distributed equalization unit (16×16 spacing), the overall power consumption is reduced by 82% to 88%, leakage current is reduced by 32% to 42%, junction temperature is reduced by 12 to 14℃, and PVT drift is reduced to 7.1%.

[0060] like Figure 4 As shown, Example 2: Eddy canceling structure based on gradually varying metal wire width (equivalent replacement) As an equivalent replacement for staggered vias, this embodiment employs a width-gradient structure of adjacent parallel metal lines to achieve a reverse eddy field. Specifically, the width of the first metal line gradually changes from W1 to W2, and the width of the second metal line gradually changes from W2 to W1, so that the current density gradients of the two lines are in opposite directions, thereby generating a eddy cancellation effect. This structure can also effectively suppress crosstalk and turbulence losses, and is suitable for process layers where staggered vias cannot be used. Those skilled in the art should understand that any structural design that can reverse the eddy currents of adjacent channels is an equivalent replacement of this invention.

[0061] like Figure 5 As shown, Example 3: Application in Differential Inductors of RF Chips (Cross-domain) The method of this invention is also applicable to differential inductors and transmission line structures in radio frequency chips. By obtaining the eddy current distribution in the differential inductor, and applying a reverse eddy current field by inserting a grounding shield of a specific shape between the inductor coils or adjusting the gradual spacing of the coils, inductor crosstalk and eddy current losses can be significantly reduced, thereby improving the Q value. Simulation results show that the Q value of the differential inductor increases by 15% to 25% after applying this invention.

[0062] like Figure 6 As shown, Example 4: Application in power stage interconnection of power management chips (cross-domain) Power stage interconnects in power management chips typically carry high currents and high-frequency switching, resulting in severe skin effect and eddy current losses. This invention suppresses high-frequency turbulent losses and reduces switching noise by detecting current eddy currents in the power stage interconnects and applying a reverse eddy current field using multi-layered staggered vias and a tapered width structure. Experimental results show that applying this invention improves power conversion efficiency by 5%–8% and reduces switching node voltage overshoot by more than 30%.

[0063] Overall verification To verify the effectiveness, stability, and versatility of the technical solution of this invention, multiple sets of comparative simulation tests were conducted based on mainstream commercial CMOS processes of 28nm and 14nm. The standard test conditions were a 1GHz operating frequency, a room temperature of 25℃, and a conventional process angle. The test results were consistent with the beneficial effects. This invention can be adapted to 28nm to 3nm full-gradient nanometer processes, and the core optimization mechanism can be reused simply by fine-tuning the via size, dielectric thickness, and layering parameters according to the corresponding process rules.

[0064] The above combined with the appendix Figure 8 A chip multiphysics collaborative optimization method based on current eddy current control is described according to an embodiment of the present invention. Furthermore, the present invention can also be applied to a chip layout structure based on current eddy current control.

[0065] According to a second aspect of the present invention, a chip layout structure based on current eddy current control is provided for generating a reverse eddy current cancellation effect in the chip interconnect structure, comprising: Adjacent conductive channels are configured with currents rotating in opposite directions to form reverse-coupled vortex fields; In the multi-channel array, the central region adopts an alternating reverse arrangement of rows, the edge region adopts a gradually rotating arrangement, and the cross nodes are equipped with isolation media.

[0066] Furthermore, in this embodiment, the reverse-coupled vortex field is achieved through a staggered via structure, and the lateral offset of the staggered via is 0.4 to 0.6 times the corresponding metal linewidth. Specifically, for the high-density parallel interconnect metal layer of the chip, a staggered via connection structure is adopted between upper and lower layers to change the circumferential current circulation pattern of a single metal trace, so that the current rotation direction of adjacent parallel traces is opposite and the electromagnetic fields are coupled in reverse. For the in-memory array, a partitioned differentiated arrangement strategy is adopted. The high-density area in the center of the array adopts a row-by-row alternating reverse arrangement, and the transition area at the edge of the array adopts a gradually changing rotation direction arrangement. The dense nodes where the lines cross are filled with an isolation dielectric structure.

[0067] Furthermore, in this embodiment, the reverse-coupled vortex field is achieved through at least one of the following: a tapered trace, a spiral or serpentine trace, or an interlayer shielding structure.

[0068] Furthermore, in this embodiment, the conductive channel includes a metal interconnect, a multilayer via, a power inductor, or a power interconnect.

[0069] The above describes a chip layout structure based on current eddy current control according to an embodiment of the present invention. Furthermore, the present invention can also be applied to an integrated circuit chip based on current eddy current control.

[0070] According to a third aspect of the present invention, an integrated circuit chip is provided, wherein the integrated circuit chip is configured with a chip layout structure according to the second aspect.

[0071] Furthermore, in this embodiment, an integrated circuit chip also includes a global steady-state bias circuit. This circuit is coupled to the chip's global data bus, word lines, and bit lines to provide a steady-state reference current to maintain a constant current base for the signal path. The global steady-state bias circuit includes a zero-temperature drift bandgap reference source, a cascode current mirror, and a zero-point calibration sub-circuit. The amplitude ratio of the steady-state reference current to the signal current is maintained between 0.15 and 0.6, ensuring that the signal path always has a constant steady-state current base. This constrains the instantaneous jump amplitude and direction fluctuations of the current during signal level transitions, suppressing dynamic switching power consumption and turbulent additional power consumption from the source. The static power consumption increment introduced by the zero-point calibration sub-circuit is controlled within 0.1% to 5%, used to offset the reference current offset introduced by process and temperature.

[0072] Furthermore, in this embodiment, an integrated circuit chip also includes a layered multi-channel current-guiding structure. The layered multi-channel current-guiding structure is applied to interconnects or clock lines with a length greater than 150μm within the chip to uniformly shunt concentrated current in order to suppress high-frequency turbulence losses.

[0073] Furthermore, in this embodiment, an integrated circuit chip further includes a three-layer gradient thin-film dielectric structure. This three-layer gradient thin-film dielectric structure is disposed in the memory cell and consists of an outer high-resistivity current-limiting layer, an intermediate functional dielectric layer, and an inner buffer adapter layer. This effectively reduces the static leakage current of the cell and mitigates device parameter drift caused by temperature and voltage fluctuations. The materials of the three-layer gradient thin-film dielectric structure are HfO2, TaOx, and TiN, with a thickness ratio of (1.5–2.5):(4.5–5.5):(2.5–3.0).

[0074] Furthermore, in this embodiment, an integrated circuit chip further includes a passive equalization unit. The passive equalization unit is uniformly embedded within the in-memory array at sub-array intervals to dynamically compensate for global current distortion caused by array edge effects and process deviations, thereby converging PVT parameter drift. The passive equalization unit uses a 16×16 sub-array as the smallest deployment unit and does not change the original array's operational architecture, read / write logic, or control timing. The in-memory array includes at least one of RRAM, SRAM, PCM, and Flash.

[0075] Furthermore, the integrated circuit chips are manufactured using standard CMOS processes ranging from 28nm to 3nm.

[0076] It should be noted that, in this specification, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0077] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A chip multi-physics collaborative optimization method based on current eddy current control, characterized in that, Includes the following steps: Obtain the eddy current characteristics of the current distribution in the chip interconnect structure; Based on the vorticity characteristics, a reverse vorticity field with opposite direction and matching intensity to the original vorticity is constructed. The reverse eddy field is applied to the chip interconnect layer to counteract the original eddies, suppress current turbulence loss, and simultaneously improve at least two types of physical defects of the chip. The physical defects that are being synchronously improved include dynamic power consumption, interconnect crosstalk, device leakage, hot spot temperature rise, and PVT parameter drift.

2. The chip multi-physics collaborative optimization method based on current eddy current control according to claim 1, characterized in that, The vorticity characteristics include at least one of current density curl, turbulence intensity, and local vortex distribution.

3. The chip multi-physics collaborative optimization method based on current eddy current control according to claim 1, characterized in that, The methods for applying the reverse vortex field include: using a staggered via structure, using traces with gradually varying widths, setting spiral or serpentine traces, and inserting at least one of magnetic or dielectric shielding structures between interconnect layers.

4. The chip multi-physics collaborative optimization method based on current eddy current control according to claim 1, characterized in that, Also includes: A global steady-state bias circuit is configured around the signal path of the chip to provide a steady-state reference current to constrain the current jump during the signal level switching process.

5. The chip multi-physics collaborative optimization method based on current eddy current control according to claim 4, characterized in that, The amplitude ratio of the steady-state reference current to the signal current is maintained at 0.15 to 0.6; the steady-state bias circuit includes a zero-point calibration sub-circuit, and the static power consumption increment introduced by it is controlled within 0.1% to 5%.

6. The chip multi-physics collaborative optimization method based on current eddy current control according to claim 1, characterized in that, Also includes: For long interconnects with a length greater than 150μm within the chip, a layered multi-channel current-guiding structure is adopted to evenly distribute the concentrated current to suppress high-frequency turbulence loss.

7. The chip multi-physics collaborative optimization method based on current eddy current control according to claim 1, characterized in that, It also includes: setting a three-layer gradient thin-film dielectric structure for the chip's memory cells, with an outer high-resistivity current-limiting layer, a middle functional dielectric layer, and an inner buffer adapter layer to suppress leakage and temperature drift.

8. The chip multi-physics collaborative optimization method based on current eddy current control according to claim 7, characterized in that, The materials of the three-layer gradient thin film dielectric structure are HfO2, TaOx and TiN, respectively, and the thickness ratio is (1.5~2.5):(4.5~5.5):(2.5~3.0).

9. The chip multi-physics collaborative optimization method based on current eddy current control according to claim 1, characterized in that, Also includes: Passive equalization units are embedded at uniform intervals within the memory array, in units of subarrays, to compensate for global current distortion caused by array edge effects and process deviations, thereby converging PVT parameter drift.

10. The chip multi-physics collaborative optimization method based on current eddy current control according to claim 9, characterized in that, The passive equalization unit uses a 16×16 subarray as the smallest deployment unit and does not change the original array's computing architecture, read / write logic, and control timing.

11. The chip multi-physics collaborative optimization method based on current eddy current control according to claim 1, characterized in that, The method is applied to AI in-memory computing chips, RF differential inductor chips, power management chips, or high-speed serial interface circuits.

12. A chip layout structure based on current eddy current control, used to generate a reverse eddy current cancellation effect in the chip interconnect structure, characterized in that, include: Adjacent conductive channels are configured with currents rotating in opposite directions to form reverse-coupled vortex fields; In the multi-channel array, the central region adopts an alternating reverse arrangement of rows, the edge region adopts a gradually rotating arrangement, and the cross nodes are equipped with isolation media.

13. The chip layout structure according to claim 12, characterized in that, The reverse coupled vortex field is achieved through a staggered through-hole structure, and the lateral offset of the staggered through-hole is 0.4 to 0.6 times the corresponding metal linewidth.

14. The chip layout structure according to claim 12, characterized in that, The reverse-coupled vortex field is achieved through at least one of the following: a tapered trace, a spiral or serpentine trace, or an interlayer shielding structure.

15. The chip layout structure according to claim 12, characterized in that, The conductive channels include metal interconnects, multilayer vias, power inductors, or power interconnects.

16. An integrated circuit chip, characterized in that, The integrated circuit chip is configured with the chip layout structure as described in any one of claims 12 to 15.

17. The integrated circuit chip according to claim 16, characterized in that, It also includes a global steady-state bias circuit, which is coupled to the chip’s global data bus, word lines and bit lines to provide a steady-state reference current to maintain a constant current base for the signal path.

18. The integrated circuit chip according to claim 17, characterized in that, The global steady-state bias circuit includes a zero-temperature drift bandgap reference source, a common-source cascode current mirror, and a zero-point calibration sub-circuit; the amplitude ratio of the steady-state reference current to the signal current is maintained at 0.15 to 0.6, and the static power consumption increment introduced by the zero-point calibration sub-circuit is controlled within 0.1% to 5%.

19. The integrated circuit chip according to claim 16, characterized in that, It also includes a layered multi-channel current-guiding structure, which is applied to interconnects or clock lines with a length greater than 150μm within the chip to uniformly shunt concentrated current in order to suppress high-frequency turbulence losses.

20. The integrated circuit chip according to claim 16, characterized in that, It also includes a three-layer gradient thin-film dielectric structure, which is disposed in the storage unit and consists of an outer high-resistivity current-limiting layer, an intermediate functional dielectric layer, and an inner buffer adapter layer.

21. The integrated circuit chip according to claim 20, characterized in that, The materials of the three-layer gradient thin film dielectric structure are HfO2, TaOx and TiN, respectively, and the thickness ratio is (1.5~2.5):(4.5~5.5):(2.5~3.0).

22. The integrated circuit chip according to claim 16, characterized in that, It also includes passive equalization units, which are uniformly embedded in the memory array at subarray intervals to dynamically compensate for global current distortion caused by array edge effects and process deviations, and to converge PVT parameter drift.

23. The integrated circuit chip according to claim 22, characterized in that, The passive equalization unit uses a 16×16 subarray as the smallest deployment unit and does not change the original array's computing architecture, read / write logic, and control timing.

24. The integrated circuit chip according to any one of claims 16 to 23, characterized in that, The integrated circuit chip is manufactured using a standard CMOS process of 28nm to 3nm.

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