A method and system for analog circuit maximum common sub-circuit matching

Abstract

The application discloses a kind of method and system for analog circuit maximum public subcircuit matching, belong to analog integrated circuit design automation field.The method includes: two analog circuits to be matched are converted into undirected bipartite graph respectively;Device is simplified to be combined in bipartite graph, and series-parallel connection similar device is combined as equivalent single node;Extract K jump neighborhood subtree in each node of simplified graph, and filter candidate matching pair by subtree isomorphism detection, and sort based on heuristic rule;Maximum public subcircuit is searched using branch and bound strategy, including bidirectional domain grouping management, upper bound pruning and iterative expansion.System includes circuit diagram representation module, subtree heuristic search module embedded with electrical behavior pre-check unit and branch and bound search module.The application greatly reduces search space by fusing hierarchical simplification strategy and customized pruning mechanism of analog circuit characteristics, with the advantages of high matching efficiency, high solution quality, strong adaptability and the like.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit design automation, and more specifically to a method and system for matching the maximum common subcircuit of analog circuits. Background Technology

[0002] In analog integrated circuit design, subcircuit matching is a key technology for achieving design reuse, shortening product launch cycles, and improving design efficiency. With the continuous evolution of integrated circuit process nodes and the dramatic increase in design complexity, analog circuit design exhibits significant modularity. Designers typically build hierarchical structures based on validated functional modules (such as operational amplifiers, comparators, bandgap references, and phase-locked loops), adapting them to different application requirements through parameter adjustments and local structural modifications. In this context, new design versions often evolve from older versions, requiring frequent subcircuit consistency checks during layout iteration to confirm whether modifications affect the integrity of core functional modules. Simultaneously, design reuse scenarios demand the rapid retrieval of candidate circuits with similar structures to the target functional block from a vast existing circuit library. However, traditional subcircuit matching methods mostly rely on precise subgraph isomorphism algorithms, which require the subcircuit to be matched to be completely identical in topology to the candidate subgraphs in the target circuit, allowing no differences in devices or connections. While this rigid matching strategy can guarantee the accuracy of the matching results under ideal conditions, it cannot meet the real needs of actual engineering. During design iterations, the addition, deletion, or parameter adjustment of a small number of components is inevitable. The precise subgraph isomorphism method completely fails when faced with such minute differences, failing to provide any meaningful matching results. To address this issue, Maximum Common Subcircuit (MCSC) matching has gradually become a more practical alternative. Its core objective is to find the largest subcircuit with the same structure in two circuit diagrams, thus allowing for non-common parts between the two circuits to tolerate local variations during design iterations. However, existing MCSC matching methods still have many shortcomings. First, the MCSC problem is essentially an NP-hard problem. Existing methods are mostly based on general graph matching strategies, simply abstracting the circuit into a general graph structure for searching. This fails to fully utilize the inherent modular design characteristics of analog circuits (i.e., circuits are constructed from reusable functional block hierarchies) and the regularity of device connections (such as the equivalent transformation of passive device series-parallel connections, the structural patterning of differential pairs and current mirrors, etc.), leading to an excessively enlarged search space and a sharp increase in computational cost. Secondly, existing methods are extremely inefficient in medium- to large-scale analog circuits. Strategies based on constraint programming or maximum clique solving often require tens of minutes or even hours of computation time when processing circuits with thousands of nodes, far from meeting the real-time response and rapid iteration requirements of industrial-grade EDA tools. Thirdly, existing methods are prone to getting trapped in local optima in complex circuit topologies, making it difficult to guarantee the finding of the true global maximum common subcircuit, thus limiting matching quality and directly affecting the accuracy of design reuse and consistency checks. Therefore, there is an urgent need in this field for a maximum common subcircuit matching method that can fully utilize the inherent characteristics of analog circuits and possess both high efficiency and high-quality solution capabilities. Summary of the Invention

[0003] To address the shortcomings of existing technologies, the present invention aims to provide a method and system for matching the maximum common subcircuit of analog circuits. This method solves the problems of low search efficiency, failure to utilize inherent circuit characteristics, and insufficient matching accuracy in existing maximum common subcircuit matching methods. By integrating a heuristic strategy based on analog circuit characteristics with a customized branch-bound framework, the present invention achieves efficient and high-precision maximum common subcircuit matching.

[0004] To achieve the above objectives, the embodiments of this invention provide the following technical solutions:

[0005] This application provides a method for matching the maximum common sub-circuit of analog circuits, comprising the following steps: S1, converting the first analog circuit and the second analog circuit to be matched into undirected bipartite graphs, wherein the nodes of the undirected bipartite graphs include device nodes and network nodes, and the edges represent the connection relationship between device nodes and network nodes; S2, simplifying the undirected bipartite graphs of the first analog circuit and the second analog circuit by merging devices, merging similar devices connected in series and parallel into equivalent single nodes; S3, processing each of the two simplified undirected bipartite graphs... S4. Extract K-hop neighborhood subtrees from each node, filter node pairs with subtree isomorphism as candidate matching pairs through subtree isomorphism detection, and sort the candidate matching pairs based on heuristic rules; S5. Search for the maximum common subcircuit using a branch and bound strategy, including: initializing the current solution to be empty, establishing bidirectional domain groups to group unmatched nodes, iteratively adding candidate matching pairs to the current solution and updating the bidirectional domain groups in the order of sorted candidate matching pairs, calculating the upper bound of the current path, and performing pruning if the upper bound is not greater than the current optimal solution, otherwise continuing to explore until the maximum common subcircuit is found.

[0006] Furthermore, the device merging simplification in S2 includes: for passive devices, if two or more similar passive devices are connected in series and share the same network node, they are merged into a single equivalent device node; for active devices, if two or more similar active devices share a gate and their source and drain are connected in series, they are merged into a single equivalent device node; the device merging simplification also includes: by detecting transistor groups controlled by the same bias voltage in the undirected bipartite graph, identifying the transistor groups as hierarchical functional blocks of current mirrors or differential pairs, and encapsulating the hierarchical functional blocks as a supernode to participate in subsequent matching, so as to improve the matching granularity from the device level to the functional block level.

[0007] Furthermore, before extracting the K-hop neighborhood subtree in step S3, an electrical behavior pre-detection step is also included: extracting the equivalent transconductance and impedance characteristics under the DC operating point of each device node as electrical behavior labels. Only when the relative error of the electrical behavior labels of two device nodes is within the preset behavior error threshold range is the subtree isomorphism detection process allowed; if the relative error of the electrical behavior labels is not within the preset behavior error threshold range, all subsequent matching attempts of the device node pair are directly blocked, with electrical function consistency as a prerequisite for matching admission.

[0008] Furthermore, the subtree isomorphism detection in S3 employs the Weisfeiler-Lehman test, specifically including: assigning prime numbers as initial color codes to each device node in the undirected bipartite graph based on the device pin type to generate node features; refining the color codes of each node through Weisfeiler-Lehman iteration, hashing and aggregating the color codes of the node itself with the color codes of all its neighboring nodes in each iteration to obtain updated color codes; and comparing the subtree features formed by the final color codes of each node after a preset number of iterations to determine the subtree isomorphism between the two nodes.

[0009] Furthermore, in the color refinement process of the Weisfeiler-Lehman iteration, each device node is assigned a feature vector based on the device physical model. The feature vector includes the channel width-to-length ratio, gate oxide thickness, or capacitance density. The feature vector is then embedded into the color coding aggregation process after hash mapping, so that nodes with similar physical parameters but slightly different topologies are assigned similar color codes, thereby incorporating the similarity of device physical parameters into the determination criteria for subtree isomorphism detection.

[0010] Furthermore, the heuristic rule in S3 includes: calculating the subtree isomorphism size, node encoding similarity, and network node connectivity for each candidate matching pair; assigning different weight coefficients to the subtree isomorphism size, node encoding similarity, and network node connectivity, and then weighting and summing them to obtain a priority score; wherein, a negative weight coefficient is assigned to the network node connectivity, so that the higher the connectivity of the network node, the lower its priority score, so as to prioritize matching network nodes with low connectivity and their associated devices; the negative weight strategy is based on the prior knowledge that the topological ambiguity introduced by high connectivity network nodes in analog circuits in sub-circuit matching is higher than that of signal path nodes, and actively suppresses the matching priority of highly ambiguous nodes.

[0011] Furthermore, the upper bound in S4 is calculated as follows: assuming the current solution contains... For each matched node pair, for each bidirectional domain group, count the number of unmatched nodes in the first analog circuit domain and the second analog circuit domain respectively, and take the smaller of the two values. Sum the smaller values ​​of all bidirectional domain groups to obtain the result. Then the upper bound of the current path ;like If the size is not greater than the current optimal solution size, pruning is performed. A dynamic relaxation factor is introduced during the pruning process in S4. This dynamic relaxation factor adaptively adjusts the tightness of the upper bound based on the current search depth. In the early stages of the search, a tight upper bound is used for aggressive pruning, while in the later stages, the upper bound is gradually relaxed to prevent the omission of deeper optimal solutions. A time-aware adaptive switching mechanism based on matching progress is introduced during the branch-and-bound search process in S4: when the search time does not exceed a preset search time threshold, a depth-first exploration strategy is used to quickly find feasible solutions; when the search time exceeds the preset search time threshold, a breadth-first exploration strategy is automatically switched to and parallel threads are enabled. Each bidirectional domain group is solved independently and in parallel for sub-problems, and the solutions to each sub-problem are merged and their union is taken as the maximum common sub-circuit.

[0012] Furthermore, in step S4, after pruning occurs, the candidate matching pairs corresponding to the pruning path are recorded in the global conflict set. The global conflict set records the device type sequence and connectivity sequence involved in the pruned candidate matching pairs as topological fingerprints. In subsequent search paths, if it is detected that the candidate matching pair to be expanded is isomorphic to any topological fingerprint in the global conflict set in the local topological structure, the candidate matching pair is skipped directly without repeating the upper bound calculation, so that the pruning information can be horizontally transferred and reused between different search branches.

[0013] Accordingly, this application also provides a system for matching the maximum common subcircuit of an analog circuit, comprising: a circuit diagram representation module for converting the analog circuit into an undirected bipartite graph, wherein the nodes of the undirected bipartite graph include device nodes and network nodes, and edges represent the connection relationship between devices and networks; a subtree heuristic search module for extracting a K-hop neighborhood subtree for each node in the circuit and performing a Weisfeiler-Lehman test to determine the subtree isomorphism to identify potential matching node pairs, and combining prime number encoding based on device pin type and device merging to simplify and optimize the candidate matching set; and a branch and bound search module for searching the maximum common subcircuit through bidirectional domain grouping management, heuristic path selection, and upper bound pruning mechanism; wherein the bidirectional domain grouping management will identify unmatched subcircuit nodes. The matching nodes are grouped according to their connection mode with the currently matched sub-circuit, and new matching pairs are only allowed between nodes within the same group; the heuristic path selection sorts candidate matching pairs based on subtree isomorphism size, node encoding similarity, and network node connectivity; the upper bound pruning calculates the maximum possible matching size of the current path as the upper bound, and terminates the current path if the upper bound is not greater than the current optimal solution; the subtree heuristic search module embeds an electrical behavior pre-detection unit, which is used to extract the equivalent transconductance and impedance characteristics of each device node under the DC operating point as electrical behavior labels before subtree isomorphism detection. Subtree isomorphism detection is only allowed when the relative error of the electrical behavior labels of two nodes is within the preset behavior error threshold range; otherwise, the matching attempt of the node pair is directly blocked.

[0014] Furthermore, the branch-bound search module also includes: a taboo memory unit, used to record the topological fingerprints of failed candidate matching pairs that lead to pruning, the topological fingerprints including the device type sequence and connectivity sequence involved in the failed candidate matching pairs; when a local structure matching the topological fingerprint reappears in a subsequent search path, the historical pruning decision result is directly reused to skip the path; a dynamic relaxation unit, used to adaptively adjust the tightness of the upper bound according to the current search depth, using aggressive pruning with a tight upper bound in the early stage of the search, and gradually relaxing the upper bound in the later stage of the search to prevent missing deep optimal solutions; and bidirectional domain compatibility. The pre-detection unit is used to count the number of remaining adjacent edges of candidate nodes in the first and second analog circuits in each group after each bidirectional domain grouping is completed. If the absolute value of the difference between the two is greater than a preset edge number deviation threshold, the redundant candidate node on the side with the larger number of remaining adjacent edges is deleted from the group. The time-aware scheduling unit is used to monitor the running time of the branch and bound search. When it has not exceeded the preset search time threshold, it schedules the depth-first search strategy. When it exceeds the preset search time threshold, it automatically switches to the breadth-first search strategy and enables parallel threads to solve independent subproblems for each bidirectional domain group.

[0015] The beneficial effects of this invention are as follows: A dual-layer compression strategy combining device merging simplification and hierarchical functional block encapsulation, coupled with pre-screening based on subtree isomorphism, achieves multi-dimensional reduction of the search space; simultaneously, dynamic relaxation pruning and global conflict set reuse mechanisms further amplify pruning benefits and significantly reduce computational costs; a subtree encoding mechanism based on electrical behavior pre-detection and physical parameter embedding upgrades from pure topology matching to multi-dimensional matching encompassing topology, electrical, and physical aspects, avoiding mismatches due to topological isomorphism but functionally dissimilar relationships; and a heuristic sorting mechanism with negative weights for high-connectivity network nodes and a time-aware adaptive switching mechanism balances fast solution and global optimum. Attached Figure Description

[0016] Figure 1 A flowchart illustrating a method for matching the maximum common sub-circuit of an analog circuit, provided in an embodiment of this application;

[0017] Figure 2 A schematic flowchart illustrating the overall framework of the maximum common sub-circuit provided in the embodiments of this application;

[0018] Figure 3 A schematic diagram illustrating the heuristic rules provided in the embodiments of this application;

[0019] Figure 4 A schematic diagram illustrating subtree isomorphism detection provided in an embodiment of this application;

[0020] Figure 5 This is a schematic diagram of a system for matching the maximum common sub-circuit of an analog circuit, provided as an embodiment of this application. Detailed Implementation

[0021] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.

[0022] In this invention, the terms "system" and "network" are used interchangeably. "Multiple" refers to two or more; therefore, in this invention, "multiple" can also be understood as "at least two." "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, it should be understood that in the description of this invention, terms such as "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or order.

[0023] Example 1:

[0024] like Figures 1-4 As shown, this application provides a method for matching the maximum common sub-circuit of analog circuits, including the following steps: S1, converting the first analog circuit and the second analog circuit to be matched into undirected bipartite graphs, where the nodes of the undirected bipartite graphs include device nodes and network nodes, and the edges represent the connection relationship between device nodes and network nodes; S2, simplifying the undirected bipartite graphs of the first analog circuit and the second analog circuit by merging devices, merging similar devices connected in series and parallel into equivalent single nodes; S3, processing the simplified undirected bipartite graphs... For each node, extract a K-hop neighborhood subtree, filter nodes with isomorphic subtrees as candidate matching pairs through subtree isomorphism detection, and sort the candidate matching pairs based on heuristic rules; S4, use a branch and bound strategy to search for the maximum common subcircuit, including: initializing the current solution to be empty, establishing bidirectional domain groups to group unmatched nodes, iteratively adding candidate matching pairs to the current solution and updating the bidirectional domain groups in the order of sorted candidate matching pairs, calculating the upper bound of the current path, and performing pruning if the upper bound is not greater than the current optimal solution, otherwise continuing to explore until the maximum common subcircuit is found.

[0025] In another possible embodiment, the first and second analog circuits to be matched are first converted into undirected bipartite graph representations. Here, an undirected bipartite graph refers to a special graph structure where nodes are divided into two categories: device nodes and network nodes, and there are no connecting edges between nodes of the same type. Device nodes correspond one-to-one with physical components such as transistors, resistors, capacitors, and inductors in the circuit, while network nodes correspond to electrical connection networks directly connected by wires in the circuit. Edges exist only between device nodes and network nodes, corresponding to the physical connection relationship between device pins and the electrical network, thus completing the standardization conversion of the circuit data. Next, the two undirected bipartite graphs are simplified by merging devices, merging series and parallel devices of the same type into equivalent single nodes, reducing the total size of the nodes and edges in the graph. Then, a K-hop neighborhood subtree is extracted from each node in the simplified two undirected bipartite graphs. Here, a K-hop neighborhood subtree refers to a subtree with the target node as the root node. The algorithm starts with a central node and extends outwards to form a subgraph structure consisting of all nodes and edges within a K-hop connection range. Subtree isomorphism detection filters out nodes with isomorphic subtrees as candidate matching pairs. Heuristic rules prioritize all candidate matching pairs to pre-determine high-potential matching paths. Finally, a branch-and-bound strategy is used to search for the maximum common subcircuit. The current matching solution is initialized to empty, and a bidirectional domain grouping mechanism is established to group unmatched nodes. Here, the bidirectional domain refers to groups based on the connection patterns between unmatched nodes and the current matching subcircuit. Then, candidate matching pairs are iteratively added to the current solution according to the sorted candidate matching pair order, and the bidirectional domain grouping is updated synchronously. After each expansion, the upper bound of the matching scale of the current search path is calculated. If the upper bound is not greater than the scale of the currently found optimal solution, pruning is performed to terminate the path; otherwise, the exploration continues downwards until all valid paths are traversed and the maximum common subcircuit is obtained.

[0026] Through a hierarchical and progressive solution process, the circuit is first represented as a standardized undirected bipartite graph. Then, the graph size is compressed by simplifying the circuit. Next, the candidate range is narrowed down by heuristic screening. Finally, the solution is accurately obtained through branch and bound, achieving a step-by-step optimization from coarse to fine, while taking into account both solution efficiency and matching accuracy.

[0027] In this embodiment, the device merging simplification in S2 includes: for passive devices, if two or more similar passive devices are connected in series and share the same network node, they are merged into a single equivalent device node; for active devices, if two or more similar active devices share a gate and their source and drain are connected in series, they are merged into a single equivalent device node; the device merging simplification also includes: by detecting transistor groups controlled by the same bias voltage in the undirected bipartite graph, identifying the transistor groups as hierarchical functional blocks of current mirrors or differential pairs, and encapsulating the hierarchical functional blocks as a supernode to participate in subsequent matching, so as to improve the matching granularity from the device level to the functional block level.

[0028] In another possible embodiment, the process first involves merging passive devices by traversing all nodes of passive devices such as resistors, capacitors, and inductors in the undirected bipartite graph. If two or more passive devices of the same type are detected in series and adjacent devices share the same network node, or if multiple passive devices of the same type are connected in parallel to the same two network nodes at both ends, then the series-parallel devices are merged into a single equivalent device node. Next, the process involves merging active devices by traversing all methods used for matching the maximum common subcircuit of analog circuits, including NMOS and PMOS methods. The matching method involves active device nodes. If two or more active devices of the same type are detected sharing the same gate connection network, and the source and drain are connected in series to form a stacked structure, then the group of active devices is merged into a single equivalent device node. Finally, hierarchical functional block identification and encapsulation are carried out. By detecting transistor groups controlled by the same bias voltage in the undirected bipartite graph, the group is identified as a hierarchical functional block of current mirror or differential pair according to the connection topology within the group. The entire hierarchical functional block is encapsulated as a supernode to participate in subsequent matching, thereby improving the matching granularity from the device level to the functional block level and further compressing the graph structure scale.

[0029] By employing simplification strategies such as passive device merging, active device merging, and hierarchical functional block supernode encapsulation, the graph size is compressed layer by layer from the device level to the functional block level. This fully leverages the inherent characteristics of the connection regularity and modular design of analog circuit devices, maximizing the reduction of the undirected bipartite graph size and fundamentally shrinking the search space for subsequent matching.

[0030] In this embodiment of the application, before extracting the K-hop neighborhood subtree in step S3, an electrical behavior pre-detection step is also included: extracting the equivalent transconductance and impedance characteristics under the DC operating point of each device node as electrical behavior labels. Only when the relative error of the electrical behavior labels of two device nodes is within the preset behavior error threshold range is the subtree isomorphism detection process allowed; if the relative error of the electrical behavior labels is not within the preset behavior error threshold range, all subsequent matching attempts of the device node pair are directly blocked, with electrical function consistency as a prerequisite for matching admission.

[0031] In another possible embodiment, the equivalent transconductance and impedance characteristics at the DC operating point of each device node are first extracted as electrical behavior labels. The equivalent transconductance characterizes the current control capability of the transistor and is a core parameter reflecting the electrical function of the device. The impedance characteristics reflect the port electrical characteristics of the device. The two types of parameters together constitute the functional identity of the device. Next, for the device node pair to be matched across two circuits, the relative error between their electrical behavior labels is calculated. The relative error is calculated by dividing the absolute value of the difference between the two values ​​by the larger of the two values. Finally, it is determined whether the relative error is within the preset behavior error threshold range. If it is within the threshold range, the node pair is allowed to enter the subtree isomorphism detection process. If it is not within the threshold range, all subsequent matching attempts of the device node pair are directly blocked, thereby achieving pre-screening at the electrical function level.

[0032] By using electrical functional consistency as a prerequisite for matching admission, node pairs with mismatched electrical behaviors are filtered out in advance before subtree isomorphism detection. This not only significantly reduces the computational load of subsequent subtree detection, but also ensures the validity of the matching results from a functional perspective, avoiding mismatches caused by topological isomorphism and functional differences.

[0033] In this embodiment, the subtree isomorphism detection in S3 uses the Weisfeiler-Lehman test, specifically including: assigning prime numbers as initial color codes to each device node in the undirected bipartite graph based on the device pin type to generate node features; refining the color codes of each node through Weisfeiler-Lehman iteration, hashing and aggregating the color codes of the node itself with the color codes of all its neighboring nodes in each iteration to obtain updated color codes; after a preset number of iterations, comparing the subtree features formed by the final color codes of each node to determine the subtree isomorphism between the two nodes.

[0034] In another possible embodiment, firstly, for each device node in the undirected bipartite graph, prime numbers are assigned as initial color codes based on the device pin types. For example, in the NMOS method for maximum common subcircuit matching in analog circuits, the drain, gate, source, and substrate pins correspond to prime numbers 3, 5, 7, and 11, respectively; and in the PMOS method, the corresponding pins correspond to prime numbers 13, 17, 19, and 23, respectively. The initial color code for the device node is generated by multiplying the prime number weights of all pins of a single device, using the mathematical properties of prime numbers to ensure that the initial codes of devices with different pin combinations are not repeated. Then, the Weisfeil method for maximum common subcircuit matching in analog circuits is used. The er-Lehman method for matching the maximum common subcircuit of analog circuits iteratively refines the color codes of each node. In each iteration, each node collects the current color codes of all its neighboring nodes, concatenates its own code with the sorted codes of all its neighbors, and then maps the concatenation result to a new color code using a hash function, completing one round of feature refinement. Each iteration expands the neighborhood range of the corresponding subtree by one hop. Finally, after a preset number of iterations corresponding to the hop depth of the subtree for matching the maximum common subcircuit of analog circuits, the final color codes of each node are compared as subtree features. If the final color codes of two nodes are completely identical, then their hop neighborhood subtrees are determined to be isomorphic.

[0035] By using prime number initial encoding based on device pin type and leveraging the non-divisibility property of prime numbers to ensure the uniqueness of encoding for different device types, and then combining iterative hash aggregation refinement with multiple rounds of the Weisfeiler-Lehman method for matching the maximum common subcircuits of analog circuits, high-precision encoding of subtree topological features is achieved, improving the accuracy of subtree isomorphism determination.

[0036] In this embodiment of the application, during the color refinement process of the Weisfeiler-Lehman iteration, each device node is also assigned a feature vector based on the device physical model. The feature vector includes the channel width-to-length ratio, gate oxide thickness, or capacitance density. The feature vector is then embedded into the color encoding aggregation process after hash mapping, so that nodes with similar physical parameters but slightly different topologies are assigned similar color codes, thereby incorporating the similarity of device physical parameters into the determination criteria for subtree isomorphism detection.

[0037] In another possible embodiment, firstly, during the color refinement process of the Weisfeiler-Lehman method for matching the maximum common subcircuit of analog circuits, each device node is assigned a feature vector based on the device physical model. The feature vector of transistor devices includes parameters such as channel width-to-length ratio and gate oxide thickness, while the feature vector of passive devices includes parameters such as capacitance density and resistance density. Then, the above feature vectors are hashed into numerical values ​​and embedded into the aggregation process of each round of color coding. They participate in the hash calculation together with the node's own topological coding and the coding of neighboring nodes to generate updated color codes. Finally, through multiple rounds of iteration, subtree feature codes that integrate physical parameter information are obtained, so that nodes with similar physical parameters but slightly different topological structures are assigned similar color codes, thereby incorporating the similarity of device physical parameters into the determination criteria for subtree isomorphism detection.

[0038] By embedding the feature vector hash of the device physical model into the iterative color refinement process of the Weisfeiler-Lehman method for matching the maximum common subcircuits of analog circuits, the similarity of physical parameters is incorporated into the determination criteria for subtree isomorphism. This allows nodes with similar physical parameters to obtain similar codes even if their topologies differ slightly. The final matching result takes into account both topological consistency and physical parameter consistency, which is more in line with the actual needs of industrial design reuse.

[0039] In this embodiment, the heuristic rule in S3 includes: calculating the subtree isomorphism size, node encoding similarity, and network node connectivity for each candidate matching pair; assigning different weight coefficients to the subtree isomorphism size, node encoding similarity, and network node connectivity, and then weighting and summing them to obtain a priority score; wherein, a negative weight coefficient is assigned to the network node connectivity, so that the higher the connectivity of the network node, the lower its priority score, so as to prioritize matching network nodes with low connectivity and their associated devices; the negative weight strategy is based on the prior knowledge that the topological ambiguity introduced by high connectivity network nodes in analog circuits in sub-circuit matching is higher than that of signal path nodes, and actively suppresses the matching priority of highly ambiguous nodes.

[0040] In another possible embodiment, the values ​​of three dimensions—subtree isomorphism size, node encoding similarity, and network node connectivity—are first calculated for each candidate matching pair. The subtree isomorphism size corresponds to the total number of nodes in the subtree of the matching pair (using the maximum common subcircuit matching method K for analog circuits). The node encoding similarity corresponds to the degree of matching between the final color codes of the two nodes. The network node connectivity corresponds to the number of connecting edges between the network nodes associated with the matching pair. Next, different weight coefficients are assigned to the above three dimensions, and a weighted sum is obtained to obtain a priority score. A negative weight coefficient is assigned to the network node connectivity, so that the higher the connectivity of a network node, the lower its priority score. Finally, the candidate matching pairs are sorted from high to low priority scores, so that the branch-and-bound search process prioritizes matching network nodes with low connectivity and their associated devices, actively suppressing the matching priority of highly ambiguous nodes.

[0041] By employing a reverse heuristic strategy that assigns negative weights to the connectivity of network nodes, the matching priority of highly ambiguous nodes is actively suppressed, and signal path nodes with low connectivity and strong topological uniqueness are matched first. This breaks the technical inertia of general graph matching, reduces the probability of mismatch from the source of the search, and significantly reduces invalid backtracking in the search process.

[0042] In this embodiment of the application, the upper bound in step S4 is calculated as follows: assuming the current solution contains... For each matched node pair, for each bidirectional domain group, count the number of unmatched nodes in the first analog circuit domain and the second analog circuit domain respectively, and take the smaller of the two values. Sum the smaller values ​​of all bidirectional domain groups to obtain the result. Then the upper bound of the current path ;like If the size is not greater than the current optimal solution size, pruning is performed. A dynamic relaxation factor is introduced during the pruning process in S4. This dynamic relaxation factor adaptively adjusts the tightness of the upper bound based on the current search depth. In the early stages of the search, a tight upper bound is used for aggressive pruning, while in the later stages, the upper bound is gradually relaxed to prevent the omission of deeper optimal solutions. A time-aware adaptive switching mechanism based on matching progress is introduced during the branch-and-bound search process in S4: when the search time does not exceed a preset search time threshold, a depth-first exploration strategy is used to quickly find feasible solutions; when the search time exceeds the preset search time threshold, a breadth-first exploration strategy is automatically switched to and parallel threads are enabled. Each bidirectional domain group is solved independently and in parallel for sub-problems, and the solutions to each sub-problem are merged and their union is taken as the maximum common sub-circuit.

[0043] In another possible implementation, first calculate the upper bound of the matching size of the current path, assuming that the current solution contains... For each matched node pair, iterate through all bidirectional domain groups, count the number of unmatched nodes in the first and second analog circuit domains within each group, and take the smaller of the two values. Sum the smaller values ​​of all bidirectional domain groups to obtain the result. Then the basic bound of the current path If used for the method of maximum common subcircuit matching in analog circuits If the size is not greater than the current optimal solution size, pruning is performed. Then, a dynamic relaxation factor is introduced during the pruning process. This dynamic relaxation factor is a coefficient used to adjust the tightness of the upper bound, ranging from method 0 to method 1 for matching the maximum common subcircuit of the analog circuit. The value is adaptively adjusted based on the current search depth. In the early stages of the search, a smaller relaxation coefficient is used to tighten the upper bound, performing pruning aggressively and quickly eliminating many invalid paths. In the later stages of the search, the relaxation coefficient is gradually increased to relax the upper bound, preventing the omission of deeper optimal solutions due to over-pruning. Finally, a time-aware adaptive switching mechanism based on matching progress is introduced during the branch and bound search process. When the search time does not exceed a preset search time threshold, a depth-first exploration strategy is used to quickly find feasible solutions, providing a higher baseline for pruning. When the search time exceeds the preset search time threshold, it automatically switches to a breadth-first exploration strategy and enables parallel threads to solve subproblems independently and in parallel for each bidirectional domain group. The solutions to each subproblem are merged, and the union is taken as the maximum common subcircuit.

[0044] By calculating the precise upper bound of the summation of the minimum nodes in the bidirectional domain, and combining the dynamic relaxation factor to adaptively adjust the tightness with the search depth, a balance is achieved between aggressive pruning in the early stage and ensuring optimality in the later stage. Furthermore, with the adaptive switching of the time-aware search strategy, the solution speed and global optimality are taken into account within a limited time, which can adapt to the solution needs of circuits of different sizes.

[0045] In this embodiment of the application, in step S4, after pruning occurs, the candidate matching pair corresponding to the pruning path is recorded in the global conflict set. The global conflict set records the device type sequence and connectivity sequence involved in the pruned candidate matching pair as a topological fingerprint. In subsequent other search paths, if it is detected that the candidate matching pair to be expanded is isomorphic to any topological fingerprint in the global conflict set in the local topological structure, the candidate matching pair is skipped directly without repeating the upper bound calculation, so that the pruning information can be horizontally transferred and reused between different search branches.

[0046] In another possible embodiment, firstly, after pruning occurs, the candidate matching pairs corresponding to the pruned path are recorded in the global conflict set. The device type sequence and connectivity sequence involved in the pruned candidate matching pairs are extracted and encoded as the topological fingerprint of the local structure, serving as a storage entry in the conflict set. Then, during the expansion of other search paths, for each candidate matching pair to be expanded, its corresponding topological fingerprint is extracted and compared with all topological fingerprints in the global conflict set for local topological isomorphism. Finally, if it is detected that the candidate matching pair to be expanded is isomorphic to any topological fingerprint in the global conflict set in the local topological structure, the candidate matching pair is skipped directly, and the upper bound calculation and subsequent exploration are not repeated, enabling the pruning information to be horizontally transferred and reused between different search branches.

[0047] By recording the local structural features of the pruning path through topological fingerprinting, a global conflict set is constructed to enable cross-branch reuse of pruning experience, avoid redundant calculations of similar topologies, and allow the benefits of one pruning to be reused in all search paths of similar structures, further amplifying the efficiency gain of pruning.

[0048] Example 2:

[0049] Reference Figure 5 In this application embodiment, the application also provides a system for matching the maximum common subcircuit of an analog circuit, comprising: a circuit diagram representation module for converting the analog circuit into an undirected bipartite graph, wherein the nodes of the undirected bipartite graph include device nodes and network nodes, and edges represent the connection relationship between devices and networks; a subtree heuristic search module for extracting a K-hop neighborhood subtree for each node in the circuit and performing a Weisfeiler-Lehman test to determine the subtree isomorphism to identify potential matching node pairs, and combining prime number encoding based on device pin type and device merging to simplify and optimize the candidate matching set; and a branch and bound search module for searching the maximum common subcircuit through bidirectional domain grouping management, heuristic path selection, and upper bound pruning mechanism; wherein the bidirectional domain grouping management... Unmatched nodes are grouped according to their connection patterns with the currently matched subcircuit, and new matching pairs are only allowed between nodes within the same group. The heuristic path selection sorts candidate matching pairs based on subtree isomorphism size, node encoding similarity, and network node connectivity. The upper bound pruning calculates the maximum possible matching size of the current path as an upper bound. If the upper bound is not greater than the current optimal solution, the current path is terminated. The subtree heuristic search module embeds an electrical behavior pre-detection unit, which is used to extract the equivalent transconductance and impedance characteristics of each device node under the DC operating point as electrical behavior labels before subtree isomorphism detection. Subtree isomorphism detection is only allowed when the relative error of the electrical behavior labels of two nodes is within the preset behavior error threshold range; otherwise, the matching attempt of the node pair is directly blocked.

[0050] In another possible embodiment, the circuit diagram representation module first receives the circuit netlist input and converts the analog circuit into an undirected bipartite graph structure. The nodes of the undirected bipartite graph include device nodes and network nodes, and the edges represent the connection relationships between devices and networks, completing the standardization transformation of the input data. Next, the subtree heuristic search module extracts the maximum common subcircuit matching method K for each node in the circuit, performs a neighborhood subtree hopping test, and executes the Weisfeiler-Lehman maximum common subcircuit matching method test to determine subtree isomorphism and identify potential matching node pairs. Simultaneously, it combines prime number encoding based on device pin types and device merging to simplify and optimize the candidate matching set. An embedded electrical behavior pre-detection unit is also included. Before subtree isomorphism detection, the equivalent transconductance and impedance characteristics of each device node under the DC operating point are extracted as electrical behavior labels. Subtree isomorphism detection is only allowed when the relative error of the electrical behavior labels of two nodes is within the preset behavior error threshold range; otherwise, the matching attempt of the node pair is directly blocked. Finally, the branch and bound search module searches for the maximum common subcircuit through bidirectional domain grouping management, heuristic path selection, and upper bound pruning mechanism. Bidirectional domain grouping management groups unmatched nodes according to their connection mode with the currently matched subcircuit, and only allows new matching pairs to be formed between nodes in the same group. Heuristic path selection sorts candidate matching pairs based on subtree isomorphism size, node encoding similarity, and network node connectivity. Upper bound pruning calculates the maximum possible matching size of the current path as the upper bound. If the upper bound is not greater than the current optimal solution, the current path is terminated.

[0051] In this embodiment, the branch-bound search module further includes: a taboo memory unit, used to record the topological fingerprints of failed candidate matching pairs that lead to pruning, the topological fingerprints including the device type sequence and connectivity sequence involved in the failed candidate matching pairs; when a local structure matching the topological fingerprint reappears in a subsequent search path, the historical pruning decision result is directly reused to skip the path; a dynamic relaxation unit, used to adaptively adjust the tightness of the upper bound according to the current search depth, using aggressive pruning with a tight upper bound in the early stage of the search, and gradually relaxing the upper bound in the later stage of the search to prevent missing deep optimal solutions; and a bidirectional domain. The compatibility pre-detection unit is used to count the number of remaining adjacent edges of candidate nodes in the first and second analog circuits in each group after each bidirectional domain grouping is completed. If the absolute value of the difference between the two is greater than a preset edge number deviation threshold, the redundant candidate node on the side with the larger number of remaining adjacent edges is deleted from the group. The time-aware scheduling unit is used to monitor the running time of the branch and bound search. When it has not exceeded the preset search time threshold, it schedules the depth-first search strategy. When it exceeds the preset search time threshold, it automatically switches to the breadth-first search strategy and enables parallel threads to solve independent subproblems for each bidirectional domain group.

[0052] In this embodiment, the subtree-inspired search module further includes: a physical parameter embedding unit, used to assign a feature vector based on the device physical model to each device node, the feature vector including channel aspect ratio, gate oxide thickness or capacitance density, and embed the feature vector into the Weisfeiler-Lehman iterative color refinement process after hash mapping; and a hierarchical packaging unit, used to identify the group of transistors controlled by the same bias voltage as hierarchical functional blocks of current mirrors or differential pairs, and encapsulate the hierarchical functional blocks as supernodes to participate in subsequent matching.

[0053] In another possible embodiment, a physical parameter embedding unit and a hierarchical encapsulation unit are first set in the subtree heuristic search module. The physical parameter embedding unit assigns a feature vector based on the device physical model to each device node. The feature vector includes the channel width-to-length ratio, gate oxide thickness, or capacitance density. After hash mapping, the feature vector is embedded into the color refinement process of the Weisfeiler-Lehman method for matching the maximum common subcircuit of analog circuits. The hierarchical encapsulation unit identifies the group of transistors controlled by the same bias voltage as hierarchical functional blocks of current mirrors or differential pairs by detecting them, and encapsulates the hierarchical functional blocks as supernodes to participate in subsequent matching. Next, a bidirectional domain compatibility pre-detection unit and a dynamic relaxation unit are set in the branch and bound search module. After each bidirectional domain group is completed, the bidirectional domain compatibility pre-detection unit counts the number of remaining adjacent edges of the candidate nodes in the first and second analog circuits in each group. If the absolute value of the difference between the two is large, the system will determine the next step. If the edge count deviation threshold is met, redundant candidate nodes on the side with the larger number of remaining adjacent edges are removed from the group. The search width is compressed in advance at the domain level. The dynamic relaxation unit adaptively adjusts the tightness of the upper bound according to the current search depth. Aggressive pruning with a tight upper bound is adopted in the early stage of the search, and the upper bound is gradually relaxed in the later stage of the search to prevent the omission of deep optimal solutions. Finally, a taboo memory unit and a time-aware scheduling unit are set in the branch and bound search module. The taboo memory unit records the topological fingerprint of the failed candidate matching pairs that caused pruning. The topological fingerprint includes the device type sequence and connectivity sequence involved in the failed candidate matching pairs. When a local structure matching the topological fingerprint reappears in the subsequent search path, the historical pruning judgment result is directly reused to skip the path. The time-aware scheduling unit monitors the running time of the branch and bound search. When it does not exceed the preset search time threshold, the depth-first exploration strategy is scheduled. When it exceeds the preset search time threshold, the breadth-first exploration strategy is automatically switched and parallel threads are enabled to solve independent subproblems for each bidirectional domain group.

[0054] By setting up multiple refined functional units in the subtree heuristic search module and the branch and bound search module, deep optimization is achieved in every stage of the search. The system performance is comprehensively improved from multiple dimensions, including domain-level candidate compression, dynamic adjustment of pruning intensity, cross-branch reuse of pruning experience, and adaptive scheduling of search strategy, so as to ensure the solution efficiency and result quality under ultra-large-scale circuits.

[0055] The optional embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention.

[0056] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the embodiments of the present invention will not describe the various possible combinations separately.

[0057] Furthermore, various different implementations of the present invention can be combined arbitrarily, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed in the present invention.

Claims

1. A method for matching the maximum common subcircuit in analog circuits, characterized in that, Includes the following steps: S1. Convert the first analog circuit and the second analog circuit to be matched into undirected bipartite graphs respectively. The nodes of the undirected bipartite graph include device nodes and network nodes, and the edges represent the connection relationship between device nodes and network nodes. S2. Perform device merging and simplification on the undirected bipartite graphs of the first analog circuit and the second analog circuit respectively, merging similar devices connected in series and parallel into an equivalent single node; S3. Extract K-hop neighborhood subtrees for each node in the two simplified undirected bipartite graphs, filter node pairs with subtree isomorphism as candidate matching pairs by subtree isomorphism detection, and sort the candidate matching pairs based on heuristic rules. S4. Use the branch and bound strategy to search for the maximum common sub-circuit, including: initializing the current solution to be empty, establishing bidirectional domain groups to group unmatched nodes, iteratively adding candidate matching pairs to the current solution and updating the bidirectional domain groups in the sorted candidate matching pairs, calculating the upper bound of the current path, and performing pruning if the upper bound is not greater than the current optimal solution, otherwise continuing to explore until the maximum common sub-circuit is found.

2. The method for matching the maximum common sub-circuit of an analog circuit according to claim 1, characterized in that, The device merging simplification in S2 includes: For passive devices, if two or more passive devices of the same type are connected in series and share the same network node, they are merged into a single equivalent device node. For active devices, if two or more active devices of the same type share a gate and their source and drain are connected in series, they are merged into a single equivalent device node. The device merging simplification also includes: identifying transistor groups controlled by the same bias voltage in an undirected bipartite graph as hierarchical functional blocks of current mirrors or differential pairs, and encapsulating the hierarchical functional blocks as supernodes to participate in subsequent matching, so as to improve the matching granularity from the device level to the functional block level.

3. The method for matching the maximum common sub-circuit of an analog circuit according to claim 1, characterized in that, Before extracting the K-hop neighborhood subtree, step S3 also includes an electrical behavior pre-detection step: The equivalent transconductance and impedance characteristics at the DC operating point of each device node are extracted as electrical behavior labels. Only when the relative error of the electrical behavior labels of two device nodes is within the preset behavior error threshold range, the subtree isomorphism detection process is allowed. If the relative error of the electrical behavior label is not within the preset behavior error threshold range, all subsequent matching attempts for that device node pair will be directly blocked, with electrical function consistency as a prerequisite for matching admission.

4. The method for matching the maximum common sub-circuit of an analog circuit according to claim 1, characterized in that, The subtree isomorphism detection in S3 uses the Weisfeiler-Lehman test, specifically including: For each device node in the undirected bipartite graph, a prime number is assigned as the initial color code based on the device pin type to generate node features; The color code of each node is refined through Weisfeiler-Lehman iteration. In each iteration, the color code of the node itself is hashed and aggregated with the color codes of all its neighboring nodes to obtain the updated color code. After a preset number of iterations, the subtree features formed by the final color codes of each node are compared to determine the subtree isomorphism between the two nodes.

5. The method for matching the maximum common sub-circuit of an analog circuit according to claim 4, characterized in that, In the Weisfeiler-Lehman iterative color refinement process, each device node is assigned a feature vector based on the device physical model. The feature vector includes the channel aspect ratio, gate oxide thickness, or capacitance density. After hash mapping, the feature vector is embedded into the color coding aggregation process, so that nodes with similar physical parameters but slightly different topologies are assigned similar color codes, thereby incorporating the similarity of device physical parameters into the determination criteria for subtree isomorphism detection.

6. The method for matching the maximum common sub-circuit of an analog circuit according to claim 1, characterized in that, The heuristic rules in S3 include: For each candidate matching pair, calculate the subtree isomorphism size, node encoding similarity, and network node connectivity. Assign different weight coefficients to the subtree isomorphism size, node encoding similarity, and network node connectivity, and then sum them up to obtain the priority score. Specifically, a negative weighting coefficient is assigned to the connectivity of the network nodes, so that the higher the connectivity of the network node, the lower its priority score, so as to prioritize the matching of network nodes with low connectivity and their associated devices. The negative weighting strategy is based on the prior knowledge that the topological ambiguity introduced by high connectivity network nodes in analog circuits in sub-circuit matching is higher than that of signal path nodes, and actively suppresses the matching priority of highly ambiguous nodes.

7. The method for matching the maximum common sub-circuit of an analog circuit according to claim 1, characterized in that, The upper bound in S4 is calculated as follows: assuming the current solution contains... For each matched node pair, for each bidirectional domain group, count the number of unmatched nodes in the first analog circuit domain and the second analog circuit domain respectively, and take the smaller of the two values. Sum the smaller values ​​of all bidirectional domain groups to obtain the result. Then the upper bound of the current path ;like If the size is not greater than the current optimal solution size, then pruning is performed; The S4 pruning process introduces a dynamic relaxation factor, which adaptively adjusts the tightness of the upper bound according to the current search depth. In the early stage of the search, a tight upper bound is used for aggressive pruning, and in the later stage of the search, the upper bound is gradually relaxed to prevent the omission of deep optimal solutions. The branch-bound search process of S4 introduces a time-aware adaptive switching mechanism based on matching progress: when the search time does not exceed the preset search time threshold, a depth-first exploration strategy is adopted to quickly find feasible solutions. When the search time exceeds the preset search time threshold, the system automatically switches to a breadth-first exploration strategy and enables parallel threads to solve sub-problems independently and in parallel for each bidirectional domain group. The solutions to each sub-problem are then merged and the union is taken as the maximum common sub-circuit.

8. The method for matching the maximum common sub-circuit of an analog circuit according to claim 7, characterized in that, In step S4, after pruning occurs, the candidate matching pairs corresponding to the pruning path are recorded in the global conflict set. The global conflict set records the device type sequence and connectivity sequence involved in the pruned candidate matching pairs as topological fingerprints. In subsequent search paths, if it is detected that the candidate matching pair to be expanded is isomorphic to any topological fingerprint in the global conflict set in the local topological structure, the candidate matching pair is skipped directly without repeating the upper bound calculation, so that the pruning information can be horizontally transferred and reused between different search branches.

9. A system for matching the maximum common subcircuit of analog circuits, characterized in that, The method for matching the maximum common subcircuit of an analog circuit as described in any one of claims 1-8 includes: The circuit diagram representation module is used to convert analog circuits into undirected bipartite graphs, wherein the nodes of the undirected bipartite graphs include device nodes and network nodes, and the edges represent the connection relationships between devices and networks. The subtree-inspired search module is used to extract the K-hop neighborhood subtree for each node in the circuit and perform the Weisfeiler-Lehman test to determine the subtree isomorphism in order to identify potential matching node pairs. It also combines prime number encoding based on device pin type and device merging to simplify and optimize the candidate matching set. The branch-bound search module is used to search for the maximum common sub-circuit through bidirectional domain grouping management, heuristic path selection, and upper bound pruning mechanism. The bidirectional domain grouping management groups unmatched nodes according to their connection patterns with the currently matched sub-circuit, allowing only nodes within the same group to form new matching pairs. The heuristic path selection sorts candidate matching pairs based on subtree isomorphism size, node encoding similarity, and network node connectivity. The upper bound pruning calculates the maximum possible matching size of the current path as the upper bound, and terminates the current path if the upper bound is not greater than the current optimal solution. The subtree heuristic search module embeds an electrical behavior pre-detection unit, which is used to extract the equivalent transconductance and impedance characteristics of each device node under the DC operating point as electrical behavior labels before subtree isomorphism detection. Subtree isomorphism detection is only allowed when the relative error of the electrical behavior labels of two nodes is within the preset behavior error threshold range; otherwise, the matching attempt of the node pair is directly blocked.

10. The system for matching the maximum common sub-circuit of analog circuits according to claim 9, characterized in that, The branch delimitation search module also includes: The taboo memory unit is used to record the topological fingerprint of the failed candidate matching pairs that lead to pruning. The topological fingerprint includes the device type sequence and connectivity sequence involved in the failed candidate matching pairs. When a local structure that matches the topological fingerprint appears again in a subsequent search path, the historical pruning judgment result is directly reused to skip the path. The dynamic relaxation unit is used to adaptively adjust the tightness of the upper bound according to the current search depth. In the early stage of the search, it adopts aggressive pruning with a tight upper bound, and in the later stage of the search, it gradually relaxes the upper bound to prevent missing deep optimal solutions. The bidirectional domain compatibility pre-detection unit is used to count the number of remaining adjacent edges of the candidate node in the first analog circuit and the second analog circuit in each group after the bidirectional domain grouping is completed. If the absolute value of the difference between the two is greater than the preset edge number deviation threshold, the redundant candidate node on the side with the larger number of remaining adjacent edges is deleted from the group. The time-aware scheduling unit is used to monitor the running time of the branch and bound search. When the time limit is not exceeded, the depth-first search strategy is scheduled. When the time limit is exceeded, the breadth-first search strategy is automatically switched and parallel threads are enabled to solve the independent subproblems of each bidirectional domain group. The subtree-inspired search module also includes: The physical parameter embedding unit is used to assign a feature vector based on the device physical model to each device node. The feature vector includes the channel width-to-length ratio, gate oxide thickness or capacitance density, and the feature vector is embedded into the Weisfeiler-Lehman iterative color refinement process after hash mapping. A hierarchical packaging unit is used to identify a group of transistors controlled by the same bias voltage as a hierarchical functional block of current mirror or differential pair, and to encapsulate the hierarchical functional block as a supernode to participate in subsequent matching.

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