Large language model driven low noise amplifier automatic design method

Abstract

The application discloses a large language model driven low noise amplifier automatic design method, and belongs to the technical field of radio frequency integrated circuit automatic design. The method comprises the following steps: a large language model is used to analyze design requirements to generate a structured task and select a circuit structure; design variables of a schematic diagram are determined to perform circuit simulation iteration; according to optimization results of the schematic diagram, layout structures of inductors and transformers are selected, placement information is determined, and electromagnetic simulation ports are configured; according to a passive device association relationship and a calculation resource budget, optimization groups are adaptively divided; parameterized layouts are generated according to groups, electromagnetic field simulation is called to obtain an S parameter network model, and a schematic diagram corresponding device model is replaced; group-level local optimization is performed in the order of input matching, inter-stage matching and output matching; finally, all passive layout variables are jointly optimized, and a result is output. The method realizes full-process automation of a low noise amplifier from a design requirement to a layout electromagnetic model verification, and reduces manual intervention and electromagnetic simulation times.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency integrated circuit automated design technology, specifically relating to a large language model-driven automated design method for low-noise amplifiers. Background Technology

[0002] Low-noise amplifiers (LNAs) are typically located at the front end of an RF receiver, and their performance directly affects the receiver's sensitivity and dynamic range. LNA performance is related to the adjustable components and network parameters in the schematic, as well as the layout, geometry, and process-related parameters of passive components such as on-chip inductors and transformers, and the resulting parasitic effects and electromagnetic coupling. The parameters that play a major role in performance differ under different circuit structures and process conditions.

[0003] Traditional LNA design typically begins with schematic optimization using ideal inductors, ideal transformers, or lumped parameter models. Designers then select the inductor or transformer layout based on experience, determine the placement, location, and orientation of passive components within the chip, set up electromagnetic simulation ports, and use electromagnetic field simulation tools to obtain S-parameter files, which are then integrated into the circuit simulation environment. This process requires repeated operations between circuit simulation tools, layout tools, and electromagnetic simulation tools, and the design result is heavily influenced by the designer's experience.

[0004] For multi-stage LNAs containing multiple inductors and transformers, there are interrelationships between the input matching, inter-stage matching, and output matching networks. If the layout parameters of all passive components are treated as variables at once, the optimization dimensionality is high, requiring extensive electromagnetic simulations in each iteration. Optimizing each inductor or transformer individually, while lowering the dimensionality per search, still results in a long design time due to the increasing number of iterations and tool calls as the number of components increases. Using fixed groupings may separate strongly correlated components or unnecessarily group weakly correlated components together.

[0005] Existing automated design methods mostly focus on transistor size optimization, schematic passive parameter optimization, or individual passive device layout optimization. Circuit structure, passive layout structure, device placement, port positions, parameter ranges, and optimization sequence still need to be determined manually. Simply using large language models to generate scripts or calling electronic design automation tools cannot automatically complete the entire process from natural language indicators to schematic convergence, from target inductor parameters to layout structure and port configuration, from passive device correlation evaluation to grouped electromagnetic model replacement, and finally to global post-layout convergence. Summary of the Invention

[0006] To address the aforementioned technical issues, this invention proposes a large language model-driven automated design method for low-noise amplifiers. This method automates the entire process from natural language design requirements to schematic convergence, passive device layout generation, and electromagnetic model verification, thereby reducing manual intervention and the number of electromagnetic simulations required.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] In a first aspect, the present invention provides an automated design method for low-noise amplifiers driven by a large language model, comprising the following steps:

[0009] S1. Obtain the natural language design requirements of the low-noise amplifier, use a large language model to parse the design requirements, and generate a structured design task that includes performance indicators, process constraints and layout constraints.

[0010] S2. Based on the structured design task, determine the target circuit structure from the candidate low-noise amplifier circuit structures, establish the corresponding schematic diagram, and determine one or more schematic diagram design variables based on the target circuit structure, the structured design task, and the circuit performance response. Obtain the schematic diagram optimization result through circuit simulation iteration. The large language model is responsible for determining or adjusting the variable set and its range, selecting optimization strategies, explaining the reasons for index defaults, and judging whether the termination conditions are met in this process.

[0011] S3. Based on the schematic optimization results, select the layout structure for the inductors and transformers in the schematic, determine the placement area, position, rotation angle and direction of each inductor and transformer in the target low noise amplifier layout, and automatically set the position and port attributes of the electromagnetic simulation port according to the mapping relationship between the schematic network nodes and the layout leads.

[0012] S4. Establish passive device association relationships based on at least two of the following: circuit connection relationships between inductors and transformers, performance sensitivity correlation, layout space coupling, and computational resource budget. Based on the association relationships, automatically determine the number of optimization groups and the passive devices included in each optimization group. Each optimization group includes one or more inductors or transformers.

[0013] S5. Generate a parameterized layout for the current optimization group. Based on the selected layout structure, device target characteristics, process constraints and layout performance response, determine one or more adjustable layout parameters in the group as layout design variables. Call the electromagnetic field simulation tool to obtain one or more S-parameter network models corresponding to the current optimization group.

[0014] S6. Replace the inductor or transformer model corresponding to the current optimization group in the schematic diagram with the S-parameter network model, take the layout design variables in the current optimization group as the main adjustment object, and fine-tune other circuit parameters related to the performance of the current optimization group within the constraints of the structured design task based on the circuit performance feedback of the low noise amplifier.

[0015] S7. Following the order of input matching region, inter-level matching region, and output matching region, repeat the parametric layout generation, electromagnetic simulation, model replacement, and circuit performance evaluation for each optimization group to complete the group-level local optimization.

[0016] S8. After the target optimization group completes the group-level local optimization, release all or the passive device layout design variables in the preset set, and re-execute electromagnetic simulation and whole-system circuit evaluation for each candidate layout to complete the joint optimization, and output the schematic diagram of the low-noise amplifier, the passive device layout, the S-parameter network model and the performance verification results.

[0017] Preferably, the structured design task in S2 includes circuit performance targets, design constraints, and process-related information obtained from the analysis of the design requirements; the candidate low-noise amplifier circuit structure is one or more circuit topologies adapted to the structured design task.

[0018] Preferably, the schematic design variables in S2 are one or more adjustable parameters determined based on the target circuit structure, design requirements, circuit constraints, and circuit performance response. The specific parameter types and value forms are dynamically determined according to the current design task. Passive devices in the schematic optimization stage adopt circuit models that can characterize their electrical characteristics and support parameter adjustment.

[0019] Preferably, the inductor layout structure in S3 includes at least one of a single-layer planar spiral structure, a multi-layer stacked structure, a differential structure, and a center-tapped structure; the transformer layout structure includes at least one of a side-by-side, interleaved, stacked, differential, and center-tapped structure; the placement information includes the placement area, center coordinates, rotation angle, mirror state, device spacing, and lead orientation; the port attributes include port number, port direction, port polarity, port type, and reference conductor.

[0020] Preferably, in step S4, the correlation degree between devices is calculated based on whether passive devices are located in the same matching network, whether they share or are adjacent to circuit nodes, whether their sensitivity to changes in the target performance index is related, the layout placement distance, and the estimated mutual inductance or spatial electromagnetic coupling strength. The calculated correlation degree is used as the basis for clustering or graph partitioning, and then combined with the allowed active variable dimension, the time consumed in a single electromagnetic simulation, the parallel computing capability, the maximum running time, or the total simulation budget, the number of optimization groups and the number of devices in each group are determined.

[0021] Preferably, the layout design variables in S5 are one or more adjustable layout parameters determined based on the selected passive device layout structure, target electrical characteristics, process constraints, layout constraints, and electromagnetic simulation results. The specific parameter types and value forms are dynamically determined according to the current optimization task. For passive devices within a group whose spatial electromagnetic coupling does not meet the preset conditions, corresponding S-parameter network models are generated respectively. For multiple passive devices whose spatial electromagnetic coupling meets the preset conditions, they are set in the same electromagnetic simulation area and a joint multi-port S-parameter network model is generated.

[0022] Preferably, in S6 and S7, the current optimization group adopts an S-parameter network model generated by the candidate layout, the preceding optimization group that has completed group-level local optimization adopts a locked S-parameter network model, and the subsequent optimization group that has not yet entered group-level local optimization adopts a schematic parameter model or an initial S-parameter network model, so as to form a hybrid model circuit that changes with the optimization stage.

[0023] Preferably, in step S7, the group-level local optimization of the input matching region, inter-stage matching region, and output matching region determines one or more indicators as optimization targets from the performance indicators to be optimized based on the structured design task, the current circuit performance, and the matching region, and sets other performance indicators that need to be maintained as constraints; during any group-level local optimization process, the layout design variables of one or more passive devices in the current optimization group are used as the main active variables, and other relevant circuit parameters are fine-tuned within the constraints of the structured design task based on performance feedback.

[0024] Preferably, in step S7, during the group-level local optimization process, subsequent optimization groups are re-merged, split, or adjusted based on the actual convergence speed, index changes, inter-group coupling, and electromagnetic simulation time. When the current optimization group causes the already satisfied performance index to exceed the allowable range, at least one operation is performed in advance, such as narrowing the variable range, re-dividing the optimization groups, or performing joint optimization of multiple optimization groups in advance.

[0025] Secondly, the present invention provides a large language model-driven automated design system for low-noise amplifiers, comprising:

[0026] The requirement analysis and structure selection module is used to obtain the natural language design requirements of the low noise amplifier and generate a structured design task by parsing with a large language model, and to determine the target circuit structure from the candidate circuit structures according to the structured design task.

[0027] The schematic optimization module is used to determine the schematic design variables based on the target circuit structure and the structured design task, and obtain the schematic optimization result through circuit simulation iteration;

[0028] The passive layout planning and port configuration module is used to select the layout structure and determine the placement information for inductors and transformers based on the schematic optimization results, and to set the electromagnetic simulation port according to the mapping relationship between the schematic network nodes and the layout leads.

[0029] An adaptive grouping module is used to establish relationships based on the circuit connection relationship, performance sensitivity correlation, layout space coupling and computing resource budget between passive devices, and to determine the number of optimization groups and the passive devices included in each optimization group based on the relationships.

[0030] The electromagnetic model generation and replacement module is used to generate a parameterized layout for the current optimization group and call the electromagnetic field simulation tool to obtain the S-parameter network model, and replace the corresponding inductor or transformer model in the schematic diagram with the S-parameter network model.

[0031] The group matching optimization module is used to perform group-level local optimization on each optimization group in the order of input matching region, inter-level matching region and output matching region.

[0032] The joint optimization module is used to release all or a preset set of passive device layout design variables for joint optimization after group-level local optimization is completed.

[0033] Compared with the prior art, the beneficial effects of the present invention are:

[0034] (1) This invention uses a large language model to convert natural language design requirements into executable circuit structure selection and optimization tasks, reducing the workload of manually establishing processes and repeatedly setting parameters;

[0035] (2) The present invention automatically selects the passive device layout structure based on the schematic optimization results, plans the device placement and configures the electromagnetic simulation port, and can maintain the consistency of schematic network nodes, layout leads and S-parameter model ports;

[0036] (3) The present invention automatically determines the number of optimization groups and the number of devices in the group based on the correlation of passive devices and the computational budget, avoiding too many stages generated by fixed device-by-device iteration, and also avoiding excessively high search dimensionality caused by releasing all layout variables at once;

[0037] (4) The present invention first performs local optimization of input matching, inter-level matching and output matching, and then performs joint optimization of all passive layout variables, which can take into account both local convergence efficiency and overall system performance. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments are briefly introduced below.

[0039] Figure 1This is a schematic diagram of the overall process of the low-noise amplifier automated design method of the present invention;

[0040] Figure 2 This is a schematic diagram of the full-variable optimization process of the present invention.

[0041] Figure 3 This is a schematic diagram showing the selection, placement, and port configuration of the passive device layout structure of the present invention;

[0042] Figure 4 This is a schematic diagram of the passive device correlation evaluation and adaptive grouping process of the present invention;

[0043] Figure 5 This is a schematic diagram of the S-parameter network model group replacement and hybrid model circuit of the present invention;

[0044] Figure 6 This is a schematic diagram of the group-level optimization process for input matching, inter-level matching, and output matching in this invention;

[0045] Figure 7 This is a schematic diagram of the joint optimization process for all passive layout variables in this invention. Detailed Implementation

[0046] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the following embodiments are for illustrative purposes only and are not intended to limit the scope of protection of the present invention. Equivalent substitutions made to circuit structures, optimization algorithms, electromagnetic simulation tools, or parametric layout generation methods without departing from the inventive concept can all be used to implement the present invention.

[0047] like Figure 1 As shown in this embodiment, the automated design method for low-noise amplifiers driven by a large language model includes the following steps:

[0048] S1. Requirements Analysis and Structure.

[0049] The system receives LNA design requirements from the user, which can be given in natural language, such as specifying the target operating frequency band, minimum gain, maximum noise figure, input / output return loss, power consumption limit, supply voltage, process platform, and chip area. The large language model converts these requirements into structured tasks, checks for missing or conflicting metrics, and prioritizes hard constraints, soft constraints, and optimization objectives. These structured tasks can be stored in JSON, XML, or database record format, containing a list of performance metrics (each metric includes name, target value, weight, and constraint type), process constraints (available metal layers, minimum linewidth, minimum spacing), and layout constraints (area limit, differential symmetry requirements), facilitating parsing and execution by downstream modules.

[0050] S2. Circuit structure selection and schematic optimization.

[0051] Based on the structured task, the large language model filters candidate structures from the circuit template library that meet the requirements of frequency band, power supply, and single-ended or differential form. For narrowband low-noise applications, an inductor source degradation cascode structure can be selected; for broadband applications, a resistor feedback or noise cancellation structure can be selected. The system generates initial schematics for the candidate structures, uses small-scale pre-simulation to eliminate candidate structures that do not meet the stability, power consumption, or gain requirements, and then determines the target circuit structure.

[0052] like Figure 2 As shown, in the schematic optimization stage, the system selects one or more adjustable parameters that can affect the target performance from the target schematic to form a set of schematic design variables. These variables can come from active devices, passive devices, bias networks, coupling structures, or other adjustable parts of the circuit. The specific parameter types, quantities, and values ​​are dynamically determined based on the selected circuit structure, design requirements, circuit constraints, and circuit performance response. The numerical optimizer adopts an appropriate search method based on the value attributes (continuous or discrete) of different variables. For example, gradient descent or Bayesian optimization can be used for continuous variables, while enumeration or genetic algorithms can be used for discrete variables. For each set of candidate variables, the circuit simulator calculates the corresponding circuit performance (including S-parameters, noise figure, stability factor, and power consumption) until the hard constraints are met and the schematic stage termination condition is reached. The large language model is responsible for determining or adjusting the variable set and its range, selecting optimization strategies, interpreting the reasons for index violations, and determining whether the termination condition is met during this process.

[0053] S3. Selection, placement, and port configuration of passive component layout.

[0054] After schematic optimization, the system reads the target inductance, coupling coefficient, operating frequency, number of ports, differential or single-ended attributes, and allowable area for each inductor or transformer. For example... Figure 3 As shown, structures that meet the target parameters are selected from the parametric passive layout library. Candidate inductor layout structures include single-layer planar spiral structures, multi-layer stacked structures, differential structures, and center-tapped structures; candidate transformer layout structures include side-by-side, interleaved, stacked, differential, and center-tapped structures. The selection criteria include target inductance, target coupling coefficient, quality factor, self-resonant frequency, number of ports, available metal layers, allowable area, and manufacturability constraints.

[0055] Based on the position of passive components in the input matching, inter-stage matching, or output matching network, the target placement area of ​​each component in the chip layout is determined. The system further determines the center coordinates, rotation angle, mirror image state, component spacing, and lead orientation of each component based on the RF signal flow direction, the position of adjacent transistors or capacitors, the differential symmetry axis, and the shortest interconnect requirement.

[0056] For each passive device, the system reads the network node and port attributes from the schematic diagram and establishes a mapping relationship between inductor or transformer identifiers, network nodes, layout cells, layout leads, electromagnetic simulation ports, and S-parameter model ports. For example, the two network nodes of a two-port inductor are mapped to the inner and outer ends of a spiral inductor, respectively; the center node of a center-tapped inductor is mapped to the center-tapped lead; and the primary, secondary, and center-tapped nodes of a transformer are mapped to their corresponding winding ends. The system sets port markers at the layout leads and automatically generates port numbers, port directions, port polarities, port types, and reference conductors, ensuring that the port sequence output by the electromagnetic simulation matches the connection sequence in the schematic diagram and satisfies the port spacing and boundary constraints of the electromagnetic simulation tool.

[0057] S4. Passive device correlation evaluation and adaptive grouping.

[0058] like Figure 4 As shown, the system performs a correlation evaluation on all inductors and transformers to be optimized. The correlation evaluation is calculated based on the following factors: whether passive devices are located in the same matching network, whether they share or are adjacent to circuit nodes, whether their sensitivity changes to the same target performance index are correlated, the layout spacing, and the estimated mutual inductance or spatial electromagnetic coupling strength. The system constructs a device correlation matrix based on the above factors, where the value of each element in the matrix represents the correlation strength between corresponding device pairs.

[0059] The correlation matrix is ​​used as input for clustering or graph partitioning. Combined with the allowed dimension of active variables, the estimated time for a single electromagnetic simulation, parallel computing capability, maximum runtime, and total simulation budget, the system automatically determines the number of optimization groups, members of each group, and execution order. The grouping strategy prioritizes highly correlated passive devices into the same optimization group. An optimization group can contain only one passive device or multiple inductors or transformers. The number of optimization groups is not predetermined but dynamically determined by the system based on the actual design status.

[0060] Examples of grouping results are as follows: When an input matching inductor and a source degradation inductor have a strong correlation with the noise figure and input return loss, they are grouped into the same optimization group; when the circuit effects of two devices are independent and their layouts are far apart, they are set up as independent optimization groups or evaluated simultaneously if parallel computing resources allow; if a transformer has significant spatial coupling with its neighboring inductor, they are placed in the same electromagnetic simulation region and a joint multiport model is generated.

[0061] S5, Electromagnetic Model Generation and Hybrid Model Circuit.

[0062] For the current optimization group, the parametric layout generator generates candidate layouts based on the selected layout structure template and placement information. Then, based on the selected layout structure, device target characteristics, process constraints, layout constraints, and electromagnetic simulation feedback, it determines the currently active layout variable from adjustable layout parameters. The specific parameter types (such as the number of spiral turns, linewidth, line spacing, outer diameter, and inner diameter) and quantities of the active layout variable are dynamically determined according to the current optimization task and are not limited to a pre-fixed set of geometric parameters.

[0063] For passive devices within a group whose spatial electromagnetic coupling does not reach the preset threshold, S-parameter network models for their respective ports are generated. For multiple passive devices whose spatial electromagnetic coupling reaches the preset threshold, their actual relative positions and orientations are preserved in the layout, placed in the same electromagnetic simulation area, and a joint multi-port S-parameter network model is generated. After updating the corresponding layout and port configuration based on candidate variables, the parametric layout generator automatically calls EMX or other electromagnetic field simulation tools to obtain S-parameter files in Touchstone format or other network parameter formats.

[0064] S6, S-parameter model replacement and hybrid model circuit.

[0065] like Figure 5 As shown, the model replacement module, based on a pre-established mapping relationship, connects the S-parameter network model of the current optimization group to and replaces the corresponding inductor or transformer model in the schematic diagram. Precursor optimization groups that have completed group-level local optimization use the locked final S-parameter network model, the current optimization group uses the S-parameter network model generated from the candidate layout, and subsequent optimization groups that have not yet entered group-level local optimization use the schematic parameter model or the initial S-parameter network model, thus forming a hybrid model circuit that changes with the optimization stage.

[0066] This approach focuses on updating the layout and model corresponding to the current optimization group in each iteration, avoiding repeated electromagnetic simulations of the pre-optimized groups and preventing unprocessed subsequent groups from prematurely consuming computational resources. At the same time, it allows for constrained fine-tuning of other circuit parameters related to the performance of the current optimization group based on the feedback from the whole-system circuit simulation within the constraints of the structured design task, in order to compensate for impedance mismatch caused by model replacement.

[0067] S7, Group-level Local Optimization

[0068] like Figure 6 As shown, the system performs group-level local optimization in the order of input matching region, inter-level matching region, and output matching region.

[0069] Each group-level local optimization, based on the structured design task, current circuit performance, and the matching region, determines one or more indicators from the performance indicators to be optimized as the main optimization targets (e.g., input return loss and noise figure are the main targets in the input matching region, and output return loss and gain flatness are the main targets in the output matching region), and sets other performance indicators that need to be maintained as constraints.

[0070] Taking group-level local optimization of the input matching region as an example: the system prioritizes processing one or more optimization groups within that region. Based on design requirements and current performance status, it selects one or more performance indicators related to that region as the primary optimization objectives, while setting constraints on other indicators that need to be maintained (such as stability and power consumption). After the termination condition is met, the optimal layout and S-parameter model of the group are saved and locked. Then, the inter-level matching optimization group and the output matching optimization group are processed in the same manner.

[0071] During group-level local optimization, the system uses the layout design variables of one or more passive devices within the current optimization group as the primary active variables, and allows fine-tuning of other relevant circuit parameters within the constraints of the structured design task based on performance feedback. Preceding optimization groups that have completed group-level local optimization use a locked S-parameter network model, while subsequent optimization groups that have not yet entered group-level local optimization use a schematic parameter model or an initial S-parameter network model.

[0072] The system monitors the actual convergence speed, objective function improvement, inter-group index coupling, and single electromagnetic simulation time of each optimization group, and dynamically adjusts subsequent optimization strategies accordingly: when the scale of the variables to be optimized in an optimization group is too large or the convergence is slow, the group is split into multiple subgroups; when two optimization groups are optimized separately and repeatedly violate each other's already satisfied indices, the two are merged into the same optimization group; when the remaining computational budget is insufficient, the number of candidate layouts for subsequent optimization groups is reduced or multiple groups are entered into joint optimization ahead of schedule.

[0073] When the current optimization group causes the performance indicators that have been satisfied in the previous step to exceed the allowable range, the system rolls back to the previous feasible design point and performs at least one remedial operation, such as narrowing the variable range, re-dividing the optimization group, or performing joint optimization of multiple optimization groups in advance.

[0074] S8, Joint Optimization and Output

[0075] like Figure 7As shown, after the target optimization groups for input matching, inter-level matching, and output matching have all completed group-level local optimization, the system simultaneously releases all or a preset set of passive device layout design variables, and re-executes electromagnetic simulation and overall circuit evaluation for each candidate layout to complete joint optimization. The joint optimizer generates a global candidate variable combination based on the current design state, and each parameterized layout updates and calls the electromagnetic field simulation tool to obtain the corresponding network model. Subsequently, all network models are jointly connected to the low-noise amplifier circuit for overall performance evaluation.

[0076] The objective function of the joint optimization comprehensively considers gain, noise figure, input and output return loss, stability, linearity, power consumption, area, and electromagnetic simulation cost. Through multi-objective optimization, trade-offs are made among various indicators to compensate for the electromagnetic coupling between groups and the mutual constraints of indicators that were not fully considered in the local optimization stage.

[0077] To reduce the computational overhead of the joint optimization phase, the system caches the simulated layout parameter combinations and corresponding S-parameter models. If the candidate parameter combination is the same as the simulated sample or is within a preset similarity range, the existing simulation results are reused. At the same time, parallel electromagnetic simulation (distributing multiple candidate layouts to multiple computing nodes), surrogate models (constructing an approximate model of electromagnetic response using Gaussian processes or neural networks), multi-fidelity optimization (first scanning with a coarse mesh, then performing fine mesh simulation on the preferred candidates), or incremental update methods can be used to accelerate the optimization process.

[0078] The schematic diagram stage, group-level local optimization stage, and joint optimization stage all use at least one of the following as the termination condition: maximum number of simulations, maximum running time, objective function improvement threshold, or satisfaction of all hard constraints.

[0079] After the design is completed, the system outputs the final circuit structure and schematic parameters, passive component layout structure and final layout parameters, placement and port configuration records, optimization group division records, S-parameter files for each electromagnetic simulation, overall system performance verification results, and optimization logs.

[0080] The method is not limited to a single large language model, numerical optimization algorithm, or electromagnetic simulation software, and can be used for the automated design of RF amplifier circuits and other microwave integrated circuits containing multiple on-chip inductors, transformers, or other passive devices with distributed parameters.

Claims

1. A method for automated design of low-noise amplifiers driven by a large language model, characterized in that, Includes the following steps: S1. Obtain the natural language design requirements of the low-noise amplifier, use a large language model to parse the design requirements, and generate a structured design task that includes performance indicators, process constraints and layout constraints. S2. Based on the structured design task, determine the target circuit structure from the candidate low-noise amplifier circuit structures, establish the corresponding schematic diagram, and determine one or more schematic diagram design variables based on the target circuit structure, the structured design task, and the circuit performance response. Obtain the schematic diagram optimization result through circuit simulation iteration. S3. Based on the schematic optimization results, select the layout structure for the inductors and transformers in the schematic, determine the placement area, position, rotation angle and direction of each inductor and transformer in the target low noise amplifier layout, and automatically set the position and port attributes of the electromagnetic simulation port according to the mapping relationship between the schematic network nodes and the layout leads. S4. Establish passive device association relationships based on at least two of the following: circuit connection relationships between inductors and transformers, performance sensitivity correlation, layout space coupling, and computational resource budget. Based on the association relationships, automatically determine the number of optimization groups and the passive devices included in each optimization group. Each optimization group includes one or more inductors or transformers. S5. Generate a parameterized layout for the current optimization group. Based on the selected layout structure, device target characteristics, process constraints and layout performance response, determine one or more adjustable layout parameters in the group as layout design variables. Call the electromagnetic field simulation tool to obtain one or more S-parameter network models corresponding to the current optimization group. S6. Replace the inductor or transformer model corresponding to the current optimization group in the schematic diagram with the S-parameter network model, take the layout design variables in the current optimization group as the main adjustment object, and fine-tune other circuit parameters related to the performance of the current optimization group within the constraints of the structured design task based on the circuit performance feedback of the low noise amplifier. S7. Following the order of input matching region, inter-level matching region, and output matching region, repeat the parametric layout generation, electromagnetic simulation, model replacement, and circuit performance evaluation for each optimization group to complete the group-level local optimization. S8. After completing group-level local optimization in the target optimization groups corresponding to the input matching region, inter-stage matching region and output matching region, release all or preset passive device layout design variables, re-execute electromagnetic simulation and whole-system circuit evaluation for each candidate layout to complete joint optimization, and output the schematic diagram, passive device layout, S-parameter network model and performance verification results of the low-noise amplifier.

2. The automated design method for low-noise amplifiers driven by a large language model according to claim 1, characterized in that: The structured design task in S2 includes circuit performance targets, design constraints, and process-related information obtained from the analysis of the design requirements. The candidate low-noise amplifier circuit structure is one or more circuit topologies adapted to the structured design task.

3. The automated design method for low-noise amplifiers driven by a large language model according to claim 1, characterized in that: In S2, the schematic design variables are one or more adjustable parameters determined based on the target circuit structure, design requirements, circuit constraints, and circuit performance response. The specific parameter types and value forms are dynamically determined according to the current design task. In the schematic optimization stage, passive devices adopt circuit models that can characterize their electrical characteristics and support parameter adjustment.

4. The automated design method for low-noise amplifiers driven by a large language model according to claim 1, characterized in that: The inductor layout structure in S3 includes at least one of a single-layer planar spiral structure, a multi-layer stacked structure, a differential structure, and a center-tapped structure; the transformer layout structure includes at least one of a side-by-side, interleaved, stacked, differential, and center-tapped structure; the placement information includes the placement area, center coordinates, rotation angle, mirror state, device spacing, and lead orientation; the port attributes include port number, port direction, port polarity, port type, and reference conductor.

5. The automated design method for low-noise amplifiers driven by a large language model according to claim 1, characterized in that: In step S4, the correlation between devices is calculated based on whether passive devices are located in the same matching network, whether they share or are adjacent to circuit nodes, whether their sensitivity to changes in the target performance index is related, the layout placement distance, and the estimated mutual inductance or spatial electromagnetic coupling strength. The calculated correlation is used as the basis for clustering or graph partitioning, and then combined with the allowed active variable dimension, the time consumed in a single electromagnetic simulation, the parallel computing capability, the maximum running time, or the total simulation budget, the number of optimization groups and the number of devices in each group are determined.

6. The automated design method for low-noise amplifiers driven by a large language model according to claim 1, characterized in that: The layout design variables in S5 are one or more adjustable layout parameters determined based on the selected passive device layout structure, target electrical characteristics, process constraints, layout constraints, and electromagnetic simulation results. The specific parameter types and value forms are dynamically determined according to the current optimization task. For passive devices within a group whose spatial electromagnetic coupling has not reached the preset threshold, corresponding S-parameter network models are generated respectively. For multiple passive devices whose spatial electromagnetic coupling has reached the preset conditions, they are set in the same electromagnetic simulation area and a joint multi-port S-parameter network model is generated.

7. The automated design method for low-noise amplifiers driven by a large language model according to claim 1, characterized in that: In S6 and S7, the current optimization group adopts the S-parameter network model generated by the candidate layout, the previous optimization group that has completed the group-level local optimization adopts the locked S-parameter network model, and the subsequent optimization group that has not yet entered the group-level local optimization adopts the schematic parameter model or the initial S-parameter network model, so as to form a hybrid model circuit that changes with the optimization stage.

8. The automated design method for low-noise amplifiers driven by a large language model according to claim 1, characterized in that: In S7, the group-level local optimization of the input matching region, inter-stage matching region, and output matching region determines one or more indicators as optimization targets from the performance indicators to be optimized based on the structured design task, the current circuit performance, and the matching region, and sets other performance indicators that need to be maintained as constraints. During any group-level local optimization process, the layout design variables of one or more passive devices in the current optimization group are used as the main active variables, and other relevant circuit parameters are fine-tuned within the constraints of the structured design task based on performance feedback.

9. The automated design method for low-noise amplifiers driven by a large language model according to claim 1, characterized in that: In S7, during the group-level local optimization process, subsequent optimization groups are re-merged, split, or adjusted based on the actual convergence speed, index changes, inter-group coupling, and electromagnetic simulation time. When the current optimization group causes the already satisfied performance index to exceed the allowable range, at least one operation is performed in advance, such as narrowing the variable range, re-dividing the optimization groups, or performing joint optimization of multiple optimization groups in advance.

10. A large language model-driven automated design system for low-noise amplifiers, characterized in that, include: The requirement analysis and structure selection module is used to obtain the natural language design requirements of the low noise amplifier and generate a structured design task by parsing with a large language model, and to determine the target circuit structure from the candidate circuit structures according to the structured design task. The schematic optimization module is used to determine the schematic design variables based on the target circuit structure and the structured design task, and obtain the schematic optimization result through circuit simulation iteration; The passive layout planning and port configuration module is used to select the layout structure and determine the placement information for inductors and transformers based on the schematic optimization results, and to set the electromagnetic simulation port according to the mapping relationship between the schematic network nodes and the layout leads. An adaptive grouping module is used to establish relationships based on the circuit connection relationship, performance sensitivity correlation, layout space coupling and computing resource budget between passive devices, and to determine the number of optimization groups and the passive devices included in each optimization group based on the relationships. The electromagnetic model generation and replacement module is used to generate a parameterized layout for the current optimization group and call the electromagnetic field simulation tool to obtain the S-parameter network model, and replace the corresponding inductor or transformer model in the schematic diagram with the S-parameter network model. The group matching optimization module is used to perform group-level local optimization on each optimization group in the order of input matching region, inter-level matching region and output matching region. The joint optimization module is used to release all or a preset set of passive device layout design variables for joint optimization after group-level local optimization is completed.

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