A thermal-structure dual-domain cooperative charging pile PCB multi-objective layout optimization method

Abstract

The present application relates to charging pile master control PCB board heat design optimization technology, especially to a kind of heat-structure dual-domain collaborative charging pile PCB multi-objective layout optimization method.The optimization method provided by the present application includes the following steps:S101, according to the actual working condition structure of alternating current charging pile master control PCB board, core heating device and weak electric sensitive device are divided, and heat-structure dual-domain constraint is preset simultaneously;S102, the parameter of the device to be laid on the master control PCB board is divided into adjustable optimization variable and non-adjustable fixed variable;S103, generate several groups of parameter combination samples of the device to be laid on the master control PCB board, obtain the temperature peak value, temperature standard deviation and whole board weight distribution offset of each sample by finite element thermal simulation, select the sample meeting heat-structure dual-domain constraint;And using Kriging proxy model is fitted training;S104, heat-structure coupling multi-objective optimization function is constructed using the selected sample;S105, generate PCB board layout scheme from the optimal compromise solution selected from the selected sample.

Description

Technical Field

[0001] This invention relates to thermal design optimization technology for the main control PCB board of charging piles, and in particular to a multi-objective layout optimization method for charging pile PCBs with thermal-structural dual-domain collaboration. Background Technology

[0002] The main control PCB board of electric vehicle charging pile serves as the core control unit, integrating multiple functional components such as high-voltage drive, low-voltage main control, analog sampling, and communication interaction. It undertakes core functions such as charging control, command interaction, electrical protection, and metering and billing. In practical engineering applications, the main control PCB of charging piles faces multiple stringent constraints: 1) Thermal constraints: Extreme outdoor summer temperatures can reach 60℃, natural convection heat dissipation is poor, and concentrated heat sources can easily form local heat islands, accelerating component aging, shortening lifespan, and increasing the risk of failure; 2) Structural constraints: The mounting cavity space, screw hole positions, and interface positions are fixed, and uneven weight distribution can easily lead to PCB bending deformation and stress cracking; 3) Electrical safety constraints: It must strictly meet the national standard GB / T 18487-2015 and 3C certification, and there are mandatory requirements for the insulation distance between high and low voltage and the isolation distance between strong and weak currents; 4) EMC electromagnetic compatibility constraints: Strong electrical interference can easily cause communication abnormalities and sampling distortion, which must be effectively suppressed through layout and grounding design; 5) Engineering implementation constraints: The layout must meet the requirements of being assemblable, wireable, and mass-producible, and avoid problems such as interference, obstruction, and wiring difficulties.

[0003] Traditional charging pile PCB design relies on engineers' experience, first dividing the area into strong and weak current zones, concentrating heat-generating components in the strong current zone and sensitive components in the weak current zone, and then verifying the temperature through conventional thermal simulation, relying on manual fine-tuning to optimize heat dissipation. Currently, while some existing PCB thermal optimization methods introduce basic parametric modeling, they are mostly limited to iterative optimization of single thermal performance indicators, failing to build differentiated models for the special operating conditions of charging pile PCBs with strong and weak current coupling and dense heat sources. Furthermore, they generally rely on traditional finite element simulation for successive calculations, lacking efficient alternatives to surrogate models.

[0004] The core flaw in existing technologies stems from a severe disconnect between thermal domain optimization and structural / constraint optimization, specifically manifested as follows:

[0005] First, the separation of thermal structural constraints prevents the achievement of global optimization. Manual, experience-based layout separates temperature control from constraints such as structural arrangement, weight distribution, and EMC compliance. This inherent "lay out the structure first, then adjust the heat dissipation" approach leads to optimization focusing solely on temperature peaks, neglecting the synergistic requirements of overall board thermal uniformity and weight balance. Concentrated heat sources inevitably create localized heat islands, causing PCB warping and uneven component aging. Simultaneously, it fails to address multiple constraints related to thermal performance, electrical safety, and structural assembly, ultimately resulting in poor reliability and short lifespan in practical engineering. Second, the generalized modeling constraints lack engineering applicability. Existing optimization modeling does not deeply integrate the specific constraints of charging pile PCBs, such as strong / weak current isolation distances, high-voltage safety distances, and thermal isolation zones for sensitive components. Arbitrary optimization variable settings easily lead to solutions that violate national standards GB / T18487, 3C certification, and EMC specifications, making them unsuitable for mass production and resulting in significant waste of design and time costs. Third, the lack of core methodologies and integrated collaborative optimization solutions hinders the development of integrated optimization solutions. Currently, there is no technical solution in the industry that can unify and couple the three core objectives of thermal uniformity, weight distribution, and compliance through modeling and collaborative optimization.

[0006] Therefore, there is an urgent need for a systematic approach to collaboratively optimize solutions that address the disconnect between thermal performance and structural constraints, the inability of traditional optimization methods to balance accuracy and efficiency, and the poor engineering feasibility and adaptability. Summary of the Invention

[0007] To address the aforementioned shortcomings, this invention provides a multi-objective layout optimization method for charging pile PCB boards that integrates thermal and structural domains. This method can simultaneously achieve three core objectives: temperature peak suppression, thermal uniformity control, and weight balance distribution, while also taking into account multiple constraints such as thermal performance, electrical safety, structural assembly, and national standard compliance.

[0008] In a first aspect, the present invention provides a multi-objective layout optimization method for charging pile PCB boards with thermal-structural dual-domain coordination, specifically including the following steps:

[0009] Step S101: Based on the actual working condition structure of the AC / DC charging pile main control PCB board, divide the core heat-generating devices and weak current sensitive devices, and simultaneously preset thermal-structural dual-domain constraints.

[0010] Step S102: Based on the thermal-structural dual-domain constraint, the parameters of the devices to be laid out on the main control PCB are divided into adjustable optimization variables and non-adjustable fixed variables. The adjustable optimization variables include the number of PCB layers and the planar coordinates of each core heat-generating device. The non-adjustable fixed variables remain unchanged during the optimization process.

[0011] Step S103: Using Latin hypercube sampling, several sets of parameter combination samples of the devices to be laid out on the main control PCB are generated. The weight distribution and offset of the whole board are calculated. Based on the actual operating scenario of the main control PCB, the temperature peak, temperature standard deviation and weight distribution offset of the whole board are obtained through finite element thermal simulation. Samples that meet the thermal-structural dual domain constraints are selected. The Kriging surrogate model is used for fitting training.

[0012] Step S104: Construct a thermal-structural coupling multi-objective optimization function using the selected samples, and set thermal-structural coupling constraints and violation penalty terms;

[0013] Step S105: The NSGA-III multi-objective optimization algorithm is used for calculation. Combined with the thermal performance quantitative evaluation index, the optimal compromise solution is selected from the selected samples to generate the PCB board layout scheme, and the output is after verification by finite element thermal simulation.

[0014] In some embodiments, the core heat-generating device includes a DC-DC power conversion chip, a full-bridge module for driving MOSFETs, and a high-power precision sampling resistor; the low-voltage sensitive device includes an MCU main control chip, a CP / CC charging communication circuit, a CAN bus communication module, and an NTC temperature sensing element; the position of the low-voltage sensitive device is fixed throughout the process and does not participate in optimization to avoid signal interference, sampling distortion, and communication abnormalities.

[0015] In some embodiments, the thermal-structural dual-domain constraint includes thermal domain constraint and structural domain constraint. The thermal domain constraint includes: temperature exclusion zone constraint for weak current sensitive devices, minimum thermal insulation distance constraint between core heat-generating devices and weak current sensitive devices, and width and unobstructed constraint of longitudinal ventilation and heat dissipation channels within the PCB board. Through thermal domain constraint, the long-term reliable operation of sensitive devices can be ensured from the thermal management perspective.

[0016] In some preferred embodiments, in the thermal constraint, the temperature limit of the weak current sensitive device is set to ≤65℃, the minimum heat insulation distance between the core heat-generating device and the weak current sensitive device is ≥30mm, and the width of the longitudinal ventilation and heat dissipation channel reserved in the PCB board is ≥15mm, and any device is strictly prohibited from blocking it.

[0017] In some embodiments, the structural domain constraints include isolation spacing constraints for high-voltage sensitive devices and low-voltage sensitive devices, and insulation spacing constraints for high-voltage live components.

[0018] In some preferred embodiments, the structural domain constraints include: setting the isolation distance between high-voltage sensitive devices and low-voltage sensitive devices to be ≥8mm, and the insulation distance between high-voltage live parts to be ≥12mm; the structural domain constraints also include locking the external interface position and mounting screw hole position; high-current wiring maintains the shortest path to reduce losses and heat generation.

[0019] In some embodiments, the adjustable optimization variables include: the number of PCB layers and the coordinate range of each core heat-generating device.

[0020] In some preferred embodiments, the number of PCB layers ranges from 1 to 3; the adjustable range of the X-axis coordinate of each core heat-generating device is 10mm to 210mm, and the adjustable range of the Y-axis coordinate is 15mm to 135mm.

[0021] In some embodiments, the non-adjustable fixed variables include: the minimum safe distance between the installation location of the low-voltage sensitive device and the core heat-generating device, the distance from the core heat-generating device to the edge of the PCB board, the width of the copper foil in the power circuit, the parameters of the heat dissipation vias, the external communication / power interface, the structural positioning holes, and the location of the CP / CC signal and sampling line wiring.

[0022] In some preferred embodiments, the minimum safe distance between the installation location of the low-voltage sensitive device and the core heat-generating device is ≥20mm, the distance from the core heat-generating device to the edge of the PCB board is ≥5mm, the width of the copper foil of the power circuit is fixed at 3mm, the parameters of the heat dissipation vias are 0.8mm in diameter, 2mm in spacing, and 3 holes / cm² in density, and the positions of the external communication / power interface, structural positioning holes, CP / CC signal and sampling line wiring are fixed.

[0023] In some embodiments, thermal domain constraints, structural domain constraints, adjustable optimization variable settings, and non-adjustable fixed variable settings are all set in accordance with the requirements of national standard GB / T 18487, 3C certification, and EMC electromagnetic compatibility specifications.

[0024] In some embodiments, the expression for the Kriging proxy model is:

[0025]

[0026] In the formula: x is an adjustable optimization variable; g(x) is a global trend regression term; Z(x) is a Gaussian stochastic process local correction term, used to fit the nonlinear temperature relationship of the non-uniform heat source in the PCB.

[0027] Accuracy evaluation index (coefficient of determination) for the Kriging surrogate model The formula for calculating ) is:

[0028]

[0029] In the formula, Let i be the temperature of the i-th node; This represents the average temperature of the entire PCB board. The model provides a fitted prediction for the i-th sample; n is the number of samples; the coefficient of determination is used to determine the model's performance. Quantify the model fitting accuracy.

[0030] In some embodiments, the expression for the thermal-structural coupled multi-objective optimization function is:

[0031]

[0032] In the formula:

[0033] To minimize the peak temperature of the PCB board and suppress local heat islands.

[0034] The standard deviation of the overall temperature of the PCB board (to minimize and improve thermal uniformity);

[0035] This represents the overall weight distribution offset of the PCB board (minimize it to ensure structural balance).

[0036] Let x be the j-th inequality constraint function obtained from the design variable x;

[0037] This represents the total number of inequality constraints.

[0038] Let x be the k-th equality constraint function obtained from the design variable x;

[0039] This represents the total number of equality constraints.

[0040] In some embodiments, the quantitative evaluation index of thermal performance is:

[0041] (1) Temperature uniformity index of PCB board :

[0042]

[0043] Where N is the total number of temperature measurement grid nodes on the PCB; Let i be the temperature of the i-th node; This represents the average temperature of the entire plate; the smaller the value, the better the thermal uniformity.

[0044] (2) PCB board weight distribution offset :

[0045]

[0046] in, , The coordinates of the center of gravity of the total weight of all heat-generating devices; , These are the coordinates of the geometric center of the PCB board. The smaller the offset, the more balanced the weight distribution.

[0047] In some embodiments, the thermal-structural coupling constraints include the following conditions: a) no overlapping interference between devices and the high- and low-voltage safety distances meet the standards; b) the high-voltage sensitive devices and the low-voltage sensitive devices are completely within the temperature range; c) the ventilation and heat dissipation channels are unobstructed and the isolation between the high-voltage sensitive devices and the low-voltage sensitive devices meets EMC requirements.

[0048] In some embodiments, the violation penalty item is to automatically remove invalid solutions that do not meet national standards and assembly requirements.

[0049] Beneficial effects

[0050] This invention relies on the bidirectional coupling constraint of the thermal domain and the structural domain to overcome the shortcomings of traditional technologies that rely on single temperature control and the disconnect between thermal performance and structural layout. By optimizing the dual temperature targets and combining them with a balanced and dispersed heat source layout, it eliminates localized heat islands at the source, significantly reduces the temperature difference across the entire board, and effectively avoids problems such as PCB warping and uneven component aging caused by excessive temperature differences. Simultaneously, it achieves a balanced weight distribution across the entire board, balancing heat dissipation performance and structural stability. This solution is perfectly adaptable to the harsh outdoor temperature range of charging piles from -20℃ to 60℃, significantly extending the lifespan of the PCB board and core components, improving the reliability of long-term unattended operation, and meeting heat dissipation requirements solely through natural convection, eliminating the need for additional auxiliary components such as air cooling and heat sinks, effectively saving on equipment raw material and energy costs.

[0051] This invention is based on customized parametric modeling with dual-domain coupling. It pre-locks compliance constraints such as strong and weak current isolation and high-voltage safety distance, and only opens up adjustable variables in the core layout, eliminating invalid iterations and redundant debugging. Combined with Latin hypercube sampling and high-precision Kriging surrogate models, the surrogate models replace the traditional finite element repetitive simulation calculations, compressing the prediction of temperature field for a single set of parameters from hours to seconds. While ensuring model accuracy (R²≥0.95), it achieves an exponential improvement in optimization efficiency, completely solving the problems of long simulation iteration time, high computing cost, and inability to balance accuracy and efficiency in traditional simulations. It significantly reduces the design cycle and lowers labor and computing costs.

[0052] Finally, this invention incorporates mandatory compliance requirements such as national standard GB / T 18487, 3C certification, and EMC electromagnetic compatibility into a thermal-structural dual-domain coupling constraint and optimization algorithm throughout the entire process. This simultaneously avoids assembly interference and reserves ventilation channels. The optimization results require no secondary rectification or retesting and can be directly applied to industrial mass production, fundamentally solving the core problem of non-compliance in traditional optimization schemes. Furthermore, this technology is specifically adapted to the specific operating conditions of charging pile main control PCBs, combining versatility and practicality. It can be adapted to single-layer low-cost PCBs and extended to multi-layer board structures, fully covering AC and DC charging pile design scenarios. In addition, the uniform operating temperature of all components on the board significantly reduces the frequency of subsequent fault repairs, further reducing the overall lifecycle maintenance costs of the equipment and possessing extremely high industrial promotion value. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a traditional PCB layout diagram based on manual experience.

[0055] Figure 2 This is the optimized PCB layout diagram. Detailed Implementation

[0056] To fully verify the feasibility and effectiveness of the charging pile PCB layout optimization method based on thermal-structural dual-domain coupling constraints, this embodiment selects a mainstream 60kW DC charging pile main control 2-layer PCB board as the optimization object. It strictly matches the mass production conditions of commercial charging piles, cavity installation scenarios, and extreme outdoor operating environments. All parameters, constraints, and simulation conditions are calibrated according to national standard GB / T 18487-2015, 3C certification requirements, and engineering measured data, without any idealized assumptions. The specific implementation process is as follows:

[0057] Step 1: Modeling the charging pile PCB board and setting up thermal-structural dual-domain constraints

[0058] This embodiment is based on the actual engineering structure of the main control PCB board of a 60kW DC charging pile. It accurately divides the core heat-generating components and the low-voltage sensitive components, and simultaneously presets thermal-structural dual-domain constraints to lock in compliance boundaries from the source.

[0059] Component definition: The core heat-generating components are locked as DC-DC power conversion chip, full-bridge module for driving MOSFETs, and high-power precision sampling resistor; the low-voltage sensitive components include MCU main control chip, CP / CC charging communication circuit, CAN bus communication module, and NTC temperature measuring element. The installation position of the low-voltage sensitive components is fixed throughout the process and is not involved in optimization to avoid the risk of signal interference and sampling distortion.

[0060] Structural domain constraints: Strictly follow national standard GB / T 18487-2015, 3C certification and EMC electromagnetic compatibility specifications, set the isolation distance between electrically sensitive devices and weakly sensitive devices to be ≥8mm, the insulation distance between high-voltage live parts to be ≥12mm, the external interface position and mounting screw hole position are locked and cannot be changed throughout the process, and constrain the shortest path for high current wiring to ensure electrical safety and structural stability.

[0061] Thermal constraints: Preset temperature exclusion zone for low-voltage sensitive devices (≤65℃), set minimum thermal insulation distance between core heat-generating devices and low-voltage sensitive devices ≥30mm, reserve longitudinal ventilation and heat dissipation channels with a width ≥15mm in the PCB board, and strictly prohibit any device from blocking the heat dissipation channels to ensure the reliability of sensitive devices from a thermal management perspective.

[0062] PCB basic parameters: The substrate is industrial-grade FR-4 epoxy glass cloth board (thermal conductivity 0.35W / (m·K), Tg≥130℃), the board size is 220mm×150mm (precisely matching the main control module cavity installation space), and a double-layer layout is adopted (functional devices are arranged on the top layer, and the bottom layer is a continuous ground plane to achieve the dual functions of uniform heat dissipation and EMC shielding).

[0063] Step 2: Define and classify layout parameterized variables

[0064] Based on thermal-structural dual-domain constraints, a strict distinction is made between adjustable optimization variables and non-adjustable fixed variables to prevent the generation of illegal solutions.

[0065] Adjustable optimization variables: Only the spatial coordinate parameters of the number of PCB layers and the three core heat-generating components are open. The number of PCB layers is 1-3, the adjustable range of the X-axis is 10mm to 210mm, and the adjustable range of the Y-axis is 15mm to 135mm, so as to achieve fine control of the heat source position.

[0066] Non-adjustable fixed variables: minimum safe distance between the installation position of the low-voltage sensitive device and the core heat-generating device ≥20mm, distance from the core heat-generating device to the edge of the PCB board ≥5mm, copper foil width of the power circuit (fixed at 3mm, taking into account both current carrying and heat dissipation), heat dissipation via parameters (hole diameter 0.8mm, hole spacing 2mm, density 3 holes / cm²), external communication / power interface, structural positioning holes, CP / CC signal and sampling line wiring, etc. are all locked throughout to ensure the engineering adaptability of the solution.

[0067] Coupling constraint supplement: Add constraints for single component edge spacing ≥ 5mm and balanced weight distribution of the whole board to avoid PCB load and uneven stress caused by heat source concentration on one side.

[0068] Step 3: Construction of thermal simulation samples and training of Kriging surrogate model

[0069] (1) Thermal simulation boundary conditions (fitting actual extreme working conditions)

[0070] The simulation boundary replicates the actual extreme operating scenario of the outdoor unattended charging pile: the extreme high temperature environment of summer is selected as 60℃, and the natural convection heat dissipation mode is adopted; the convective heat transfer coefficient of the upper surface of the PCB is taken as the measured value of 8W / (m²·K), and the lower surface is directly attached to the aluminum alloy shell of the charging pile (thermal conductivity 12W / (m·K)) to achieve auxiliary heat conduction; the loss of each core heat source is calibrated according to the 60kW full load condition: DC-DC power chip 4.2W, drive MOSFET module 3.8W, high power sampling resistor 2.5W, total heat source loss 10.5W, which fully matches the actual heat generation power.

[0071] (2) Latin Hypercube Sampling (LHS) Sample Construction

[0072] To ensure the uniformity and comprehensiveness of the samples, the Latin hypercube sampling method is adopted. Based on the adjustable coordinate range of the three core heating devices, 100 sets of parameter combination samples are uniformly extracted in layers to fully cover the upper and lower limits and the middle range of the variables. This not only meets the training requirements of the Kriging surrogate model, but also avoids sample redundancy or blank intervals, and eliminates the distortion of optimization results caused by sample bias.

[0073] (3) Thermal simulation data acquisition and Kriging surrogate model training

[0074] One hundred sets of samples were batch-processed using the Comsol Multiphysics thermo-coupling simulation module. Core metrics for each set were collected: peak temperature Tmax, overall board temperature standard deviation Tstd, characterizing thermal uniformity and weight distribution offset Wbias, covering both thermal and structural domain performance. A Kriging surrogate model, adapted to the non-uniform heat source characteristics of PCBs, was selected for fitting and training. This model exhibits better prediction accuracy for small samples and nonlinear data. The coefficient of determination R0 of the trained model was [value missing]. 2 A value ≥0.96 can replace traditional finite element repetitive simulations, reducing the time for predicting a single set of parameter temperature fields from 1.5 hours to 3 seconds, significantly improving optimization efficiency. The expression for the Kriging surrogate model is...

[0075]

[0076] In the formula: x is an adjustable optimization variable; g(x) is a global trend regression term; Z(x) is a Gaussian stochastic process local correction term, used to fit the nonlinear temperature relationship of the non-uniform heat source in the PCB.

[0077] Accuracy evaluation index (coefficient of determination) for the Kriging surrogate model The formula for calculating ) is:

[0078]

[0079] In the formula, Let i be the temperature of the i-th node; This represents the average temperature of the entire PCB board. The model provides a fitted prediction for the i-th sample; n is the number of samples; the coefficient of determination is used to determine the model's performance. Quantify the model fitting accuracy.

[0080] Step 4: Construction of Thermal-Structure Coupled Multi-Objective Optimization Function

[0081] To align with the core optimization requirements of this invention, a thermal-structural coupled multi-objective optimization function is constructed:

[0082]

[0083] In the formula:

[0084] To minimize the peak temperature of the PCB board and suppress local heat islands.

[0085] The standard deviation of the overall temperature of the PCB board (to minimize and improve thermal uniformity);

[0086] This represents the overall weight distribution offset of the PCB board (minimize it to ensure structural balance).

[0087] Let x be the j-th inequality constraint function obtained from the design variable x;

[0088] This represents the total number of inequality constraints.

[0089] Let x be the k-th equality constraint function obtained from the design variable x;

[0090] This represents the total number of equality constraints.

[0091] Synchronous embedding of thermal-structural coupling constraints:

[0092] 1. No overlapping interference between components; high and low voltage safety spacing meets standards.

[0093] 2. Both high-voltage and low-voltage sensitive devices are completely within the temperature limit zone;

[0094] 3. The ventilation and heat dissipation channels are unobstructed, and the isolation between high-voltage and low-voltage sensitive devices meets EMC requirements;

[0095] 4. Added violation penalty items, automatically eliminating invalid solutions that do not meet national standards and assembly requirements, ensuring that the optimization process fully conforms to the dual-domain coupled logic.

[0096] Step 5: Solving for the Pareto optimal solution and outputting and verifying the final layout scheme.

[0097] (1) Multi-objective optimization solution

[0098] The NSGA-III algorithm, adapted to multi-constraint and multi-objective scenarios, was selected for iterative solution. Parameters were set as follows: population size 100, iteration count 200, balancing optimization accuracy and efficiency. Multiple Pareto optimal layout solution sets were generated through iterative computation, and the optimal compromise solution was selected by combining thermal performance quantification metrics.

[0099] The quantitative evaluation index of thermal performance is

[0100] (1) Temperature uniformity index of PCB board :

[0101]

[0102] Where N is the total number of temperature measurement grid nodes on the PCB; Let i be the temperature of the i-th node; This represents the average temperature of the entire plate; the smaller the value, the better the thermal uniformity.

[0103] (2) PCB board weight distribution offset :

[0104]

[0105] in, , The coordinates of the center of gravity of the total weight of all heat-generating devices; , These are the coordinates of the geometric center of the PCB board. The smaller the offset, the more balanced the weight distribution.

[0106] (2) Optimization effect verification and quantitative comparison

[0107] Select a traditional manual layout scheme based on the same working conditions and parameters (see...) Figure 1 As a control group, the comparison of core indicators before and after optimization is shown in Table 1:

[0108] Table 1: Comparison of core indicators before and after optimization

[0109] Key Indicators Traditional manual layout (control group) Optimized scheme of the present invention (experimental group) Optimization and improvement Maximum PCB temperature (°C) 87.3 70.1 Reduced by 17.2℃ (exceeding the preset target of 15℃) Maximum temperature difference across the entire plate (°C) 23.7 11.3 Reduced by 12.4℃ (exceeding the preset target of 10℃) Overall plate weight off-center load percentage (%) 12.7 2.1 Decrease by 10.6 percentage points National Standard / 3C Compliance Some require secondary rectification. 100% compliant No modifications required, ready for mass production Assembly interference / wiring obstruction issues exist none Completely eliminate

[0110] See the optimized PCB layout. Figure 2 .

[0111] (3) Verification conclusion

[0112] The results of this embodiment fully verify that the optimization method based on thermal-structural dual-domain coupling constraints of the present invention can simultaneously achieve the three core objectives of temperature peak suppression, thermal uniformity control, and weight balance distribution. It perfectly balances multiple constraints such as thermal performance, electrical safety, structural assembly, and national standard compliance, and is fully compatible with the design, mass production, and long-term outdoor operation requirements of the 60kW DC charging pile main control 2-layer PCB board, with extremely strong engineering feasibility.

[0113] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0114] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this application, "a plurality of" means at least two, such as two, three, etc., unless otherwise expressly specified.

[0115] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A multi-objective layout optimization method for charging pile PCB boards with thermal-structural dual-domain coordination, characterized in that, Includes the following steps: S101, based on the actual working condition structure of the AC / DC charging pile main control PCB board, divides the core heat-generating devices and weak current sensitive devices, and simultaneously presets thermal-structural dual-domain constraints. S102, Based on thermal-structural dual-domain constraints, the parameters of the devices to be laid out on the main control PCB are divided into adjustable optimization variables and non-adjustable fixed variables. The adjustable optimization variables include the number of PCB layers and the planar coordinates of each core heat-generating device. The non-adjustable fixed variables remain unchanged during the optimization process. S103 uses Latin hypercube sampling to generate several sets of parameter combination samples of the devices to be laid out on the main control PCB board, calculates the weight distribution and offset of the whole board, and obtains the temperature peak, temperature standard deviation and weight distribution offset of the whole board corresponding to each sample through finite element thermal simulation according to the actual operation scenario of the main control PCB board. Samples that meet the thermal-structural dual domain constraints are selected; and Kriging surrogate model is used for fitting training. S104: Construct a thermal-structural coupling multi-objective optimization function using the selected samples, and set thermal-structural coupling constraints and violation penalty terms; S105 uses the NSGA-III multi-objective optimization algorithm for calculation, combined with thermal performance quantitative evaluation index, to select the optimal compromise solution from the selected samples to generate the PCB board layout scheme, and outputs it after verification by finite element thermal simulation.

2. The method according to claim 1, characterized in that, The core heat-generating components include a DC-DC power conversion chip, a full-bridge module for driving MOSFETs, and a high-power precision sampling resistor; the low-voltage sensitive components include an MCU main control chip, a CP / CC charging communication circuit, a CAN bus communication module, and an NTC temperature sensing element.

3. The method according to claim 1, characterized in that, The thermal-structural dual-domain constraint includes thermal domain constraint and structural domain constraint. The thermal domain constraint includes temperature exclusion zone constraint for weak current sensitive devices, minimum thermal insulation distance constraint between core heat-generating devices and weak current sensitive devices, and width constraint of longitudinal ventilation and heat dissipation channels reserved in the PCB board. The structural domain constraint includes isolation distance constraint between strong current sensitive devices and weak current sensitive devices, and insulation distance constraint for high-voltage live components.

4. The method according to claim 1, characterized in that, The adjustable optimization variables include: the number of PCB layers and the coordinate range of each core heat-generating device.

5. The method according to claim 1, characterized in that, The non-adjustable fixed variables include: the minimum safe distance between the installation position of the low-voltage sensitive device and the core heat-generating device, the distance from the core heat-generating device to the edge of the PCB board, the width of the copper foil in the power circuit, the parameters of the heat dissipation vias, the external communication / power interface, the structural positioning holes, and the location of the CP / CC signal and sampling line wiring.

6. The method according to claim 1, characterized in that, The expression for the Kriging proxy model is: In the formula: x is an adjustable optimization variable; g(x) is the global trend regression term; Z(x) is the local correction term of the Gaussian stochastic process; The coefficient of determination in the Kriging agent model The calculation formula is: In the formula, Let i be the temperature of the i-th node; This represents the average temperature of the entire PCB board. is the model's fitted prediction value for the i-th sample; n is the number of samples.

7. The method according to claim 1, characterized in that, The expression for the thermal-structural coupled multi-objective optimization function is: In the formula: This represents the peak temperature of the PCB board. This represents the standard deviation of the overall temperature of the PCB board. This represents the offset of the overall weight distribution of the PCB board. Let x be the j-th inequality constraint function obtained from the design variable x; This represents the total number of inequality constraints. Let x be the k-th equality constraint function obtained from the design variable x; This represents the total number of equality constraints.

8. The method according to claim 1, characterized in that, The thermal performance quantitative evaluation index is as follows: (1) Temperature uniformity index of PCB board : Where N is the total number of temperature measurement grid nodes on the PCB board; Let i be the temperature of the i-th node; This represents the average temperature of the entire plate. (2) PCB board weight distribution offset : in, , The coordinates of the center of gravity of the total weight of all heat-generating devices; , These are the coordinates of the geometric center of the PCB board.

9. The method according to claim 1, characterized in that, In step S104, the thermal-structural coupling constraint conditions include the following conditions: a) no overlapping interference between devices and the high and low voltage safety distances meet the standards; b) the high-voltage sensitive devices and the low-voltage sensitive devices are completely within the temperature range; c) the ventilation and heat dissipation channels are unobstructed and the isolation between the high-voltage sensitive devices and the low-voltage sensitive devices meets EMC requirements.

10. The method according to claim 1, characterized in that, In step S104, the violation penalty item is to automatically remove invalid solutions that do not meet national standards and assembly requirements.

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