Progressive ilp core particle escape routing method and system based on sliding window

Abstract

The application discloses a kind of progressive ILP kernel particle escape wiring method and system based on sliding window, it is related to integrated circuit wiring technical field.The method comprises the following steps: obtaining the information to be wired of chip, updating sliding window by sliding window mechanism, determine the subset of the current window containing to be wired net, dynamically adjust the window range by window shrinkage strategy, until the number of line net meets threshold requirement;Using pre-defined geometric pattern, generate multiple candidate routing paths for each line net in the current sliding window;Construct an integer linear programming model to minimize the total routing cost as the goal, select the optimal path scheme for each line net from the candidate routing path;The line net and its optimal path scheme that have completed routing are solidified, the next line net subset is selected by sliding window, repeat the above steps until all line nets complete path planning, output complete escape routing scheme.Using the present application can improve the completion rate and success rate of wiring.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit wiring technology, and in particular to a progressive ILP chip escape wiring method and system based on a sliding window. Background Technology

[0002] As semiconductor technology continues to evolve, the manufacturing yield of large-scale monolithic integrated circuits is declining while production costs are rising, becoming a major bottleneck restricting the development of advanced chips. Chip-to-chip heterogeneous integration design breaks down the system into multiple functionally independent chips and integrates them using advanced packaging, effectively improving manufacturing yield and reducing R&D and production costs, thus becoming the mainstream implementation method for high-performance integrated circuits.

[0003] In the physical design flow of high-density interconnects, escape routing is a critical step that determines system feasibility and interconnect performance. It is used to efficiently and reliably bring out the chip pin signals to the internal interconnect layer of the package in highly congested and constrained areas around the pins. Due to the high pin density, complex obstacle distribution, and stringent design constraints, escape routing faces extremely high design challenges in large-scale scenarios, placing extremely high demands on the efficiency, quality, and scalability of the algorithms.

[0004] However, existing escape routing methods are ill-suited to the design requirements of high-density and large-scale meshes. Traditional global integer linear programming (ILP) methods exhibit exponential complexity growth with increasing routing scale, resulting in low computational efficiency and difficulty in converging ultra-large-scale netlists within a reasonable timeframe. Pattern-driven or linear search methods, such as VAER, suffer from low routing completion rates, numerous vias, excessive bus lengths, and insufficient scalability and robustness in high-congestion and obstacle-dense scenarios. Furthermore, existing technologies generally fail to effectively combine sliding window divide-and-conquer strategies with pattern-guided ILP optimization, failing to achieve a good balance between routing quality and computational efficiency. Therefore, a mesh escape routing method that balances high routing quality, high completion rate, and high scalability is urgently needed to overcome the design bottlenecks of existing technologies in large-scale, high-congestion, and multi-obstacle scenarios. Summary of the Invention

[0005] To address the technical problems of existing ILP escape routing methods, such as high computational complexity, poor scalability, low completion rate in scenarios with dense obstacles, and insufficient optimization of vias and wire lengths, this invention provides a progressive ILP escape routing method and system based on a sliding window. The technical solution is as follows: On the one hand, a progressive ILP chip escape routing method based on a sliding window is provided, which is implemented by a progressive ILP chip escape routing device based on a sliding window. The method includes: S1. Obtain the routing information of the chip; wherein, the routing information includes net information, obstacle information, routing design constraint information, and available routing track information; S2. Based on the chip's routing information, update the sliding window using a sliding window mechanism to determine the subset of the network to be routed contained in the current window; S3. Based on the subset of nets to be routed in the current window, determine whether the number of nets in the sliding window exceeds the preset threshold. If it does, dynamically adjust the window range through the window shrinking strategy until the number of nets meets the threshold requirement. S4. Using a predefined geometric pattern, generate multiple candidate routing paths for each net within the current sliding window; S5. Construct an integer linear programming model with the goal of minimizing the total wiring cost, select the optimal path scheme for each net from the candidate wiring paths, and satisfy the wiring constraints. S6. Solidify the completed nets and their optimal path schemes in the current net subset to be processed, update the global routing status, and select the next net subset through a sliding window. S7. Repeat steps S2-S6 until all nets have completed path planning, and finally output a complete escape cabling scheme.

[0006] On the other hand, a sliding window-based progressive ILP chip escape routing system is provided, which is applied to the sliding window-based progressive ILP chip escape routing method. The system includes: The acquisition module includes: acquiring the wiring information of the chip; wherein the wiring information includes net information, obstacle information, wiring design constraint information, and available wiring track information; The update module is used to update the sliding window based on the chip's routing information using a sliding window mechanism, and to determine the subset of the nets to be routed contained in the current window. The determination module is used to determine whether the number of nets in the sliding window exceeds a preset threshold based on the subset of nets to be routed in the current window. If it does, the window range is dynamically adjusted through a window shrinking strategy until the number of nets meets the threshold requirement. The generation module is used to generate multiple candidate routing paths for each net within the current sliding window, using a predefined geometric pattern. The selection module is used to construct an integer linear programming model to select the optimal path scheme for each net from the candidate routing paths with the objective of minimizing the total routing cost, while satisfying the routing constraints. The solidification module is used to solidify the completed wiring of the nets and their optimal path schemes in the current net subset to be processed, update the global wiring status, and select the next net subset through a sliding window. The output module is used to repeat the steps until all nets have completed path planning, and finally outputs a complete escape routing scheme.

[0007] On the other hand, a sliding window-based progressive ILP chip escape routing device is provided, the sliding window-based progressive ILP chip escape routing device comprising: a processor; a memory storing computer-readable instructions, which, when executed by the processor, implement any of the methods described above for the sliding window-based progressive ILP chip escape routing method.

[0008] On the other hand, a computer-readable storage medium is provided, wherein at least one instruction is stored therein, the at least one instruction being loaded and executed by a processor to implement any of the above-described progressive ILP core escape routing methods based on sliding windows.

[0009] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following: This invention, by introducing a sliding window mechanism, decomposes the large-scale global escape routing problem into a series of continuous and controllable-scale local subproblems. This effectively avoids the unsolvable problems caused by the explosion of problem size in traditional integer programming methods, achieving linear control of computational complexity and significantly improving the scalability of the algorithm in large-scale scenarios. By combining a preset geometric routing pattern to guide the generation of candidate solutions and formalizing the path selection problem into an integer programming model, high-quality optimization can be achieved within each local window, ensuring the superiority of the overall routing scheme in key indicators such as bus length and via count. In obstacle-dense scenarios, compared with existing methods, this invention significantly improves the routing completion rate while effectively reducing the number of vias and shortening the bus length, ensuring high-quality routing results while possessing good scalability and engineering robustness. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart of a progressive ILP chip escape routing method based on a sliding window provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the wiring structure provided in an embodiment of the present invention; Figure 3This is a schematic diagram of the sliding window initialization and division of the first group of wire mesh provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of updating a set of net routing results and dividing a second set of nets using a sliding window, provided by an embodiment of the present invention. Figure 5 This is a schematic diagram of the second set of net routing results updated and the third set of nets divided by the sliding window, provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of the third group of net routing results updated and the fourth group of nets divided by the sliding window, provided in the embodiment of the present invention. Figure 7 This is a schematic diagram of the wiring result provided in an embodiment of the present invention; Figure 8 This is a block diagram of a progressive ILP core escape routing system based on a sliding window, provided in an embodiment of the present invention. Figure 9 This is a schematic diagram of a progressive ILP core escape cabling device based on a sliding window, provided in an embodiment of the present invention. Detailed Implementation

[0012] The technical solution of the present invention will now be described with reference to the accompanying drawings.

[0013] In embodiments of the present invention, words such as "exemplarily," "for example," etc., are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" in the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present the concept in a concrete manner. Furthermore, in embodiments of the present invention, the meaning expressed by "and / or" can be both, or either one.

[0014] In the embodiments of this invention, the terms "image" and "picture" may sometimes be used interchangeably. It should be noted that, without emphasizing the distinction between them, they convey the same meaning. Similarly, the terms "of," "corresponding (relevant)," and "corresponding" may sometimes be used interchangeably. It should be noted that, without emphasizing the distinction between them, they convey the same meaning.

[0015] In this embodiment of the invention, sometimes a subscript such as W1 may be written in a non-subscript form such as W1. When the difference is not emphasized, the meaning they express is the same.

[0016] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0017] This invention provides a sliding window-based progressive ILP chip escape routing method, which can be implemented by a sliding window-based progressive ILP chip escape routing device, which can be a terminal or a server. Figure 1 The flowchart shown is for a progressive ILP core escape routing method based on a sliding window. The processing flow of this method may include the following steps: S1. Obtain the routing information of the chip; wherein, the routing information includes net information, obstacle information, routing design constraint information and available routing track information.

[0018] Optionally, the net information includes the net name, net source pin coordinates, and net target pin coordinates; The obstacle information includes the obstacle size, obstacle location, and the layer on which the obstacle is located; The routing design constraints include the trace width of different chip layers, the spacing between lines of different chip layers, and the spacing between lines of different chip layers and obstacles. The available track information for wiring includes the horizontal track coordinates and the vertical track coordinates of different metal layers.

[0019] In particular, by acquiring detailed routing data, comprehensive and accurate basic information can be provided for the subsequent routing process. This comprehensive data collection can not only accurately reflect the physical layout of the chip design, but also provide the key constraints required in the routing process, ensuring that process limitations and design requirements are fully considered during routing, thereby optimizing the routing path and improving the success rate and design efficiency of routing.

[0020] Among them, such as Figure 2 The diagram shown is a schematic representation of the wiring structure provided in an embodiment of the present invention; wherein, dashed lines represent horizontal and vertical wiring tracks, black squares represent source pins of the net, and gray dots represent target pins of the net. The letters next to the source pins and target pins represent the net names, so as to clearly indicate the one-to-one correspondence between the source pins and target pins.

[0021] S2. Based on the chip's routing information, update the sliding window using a sliding window mechanism to determine the subset of nets to be routed contained in the current window.

[0022] The sliding window mechanism is used to decompose large-scale routing problems into local subproblems; the coverage of the window is determined by the horizontal coordinate of the net source pin.

[0023] Optionally, the specific implementation process of S2 includes S21-S22: S21. Sort all nets according to the horizontal coordinate position of each net source pin in the routing information of the chip, and obtain the sorting result. S22. Initialize the sliding window based on the sorting result, include the batch of nets with the largest horizontal coordinate of the source pins into the current window, and complete the net routing within the current window; slide the current window along the direction of decreasing horizontal coordinate to determine the subset of nets to be routed contained in the current window.

[0024] Among them, by initializing and updating the sliding window based on the horizontal coordinate of the source pin, the area with the highest routing difficulty can be solved first, avoiding routing failures due to insufficient space in the later stage, while reducing the complexity of global optimization.

[0025] S3. Based on the subset of nets to be routed in the current window, determine whether the number of nets in the sliding window exceeds a preset threshold. If it does, dynamically adjust the window range through a window shrinking strategy until the number of nets meets the threshold requirement.

[0026] The preset threshold is used to control the size of the Integer Linear Programming (ILP) model and ensure solution efficiency.

[0027] Optionally, the specific implementation process of S3 includes: Count the number of wires in the current window and determine if it exceeds a preset threshold; if it does, shrink the window horizontally and vertically using a window shrinking strategy. If the number of cases does not exceed the limit, proceed directly to the path generation step S4.

[0028] When the window is horizontally shrunk, if the current window covers two or more adjacent nets and the total number exceeds a preset threshold, the window will be shrunk to cover only a single column, that is, only a batch of nets with the same horizontal coordinate of the source pins. When shrinking the window vertically, if the number of nets in a single column exceeds a preset threshold, the nets are sorted according to the vertical distance between the source pin and the escape target, and the nets with the smallest vertical distance are retained first, until the number of nets in the window is less than or equal to the preset threshold.

[0029] By dynamically shrinking the window, the solution timeout caused by the excessive size of the ILP model can be avoided while ensuring the quality of the wiring, thus achieving effective control over the computational complexity.

[0030] Among them, such as Figure 3 The diagram shown is a schematic diagram of the initialization of the sliding window and the division of the first group of wire meshes provided in an embodiment of the present invention; wherein, Figure 3The dashed box represents the initial sliding window range, and the gray rectangle represents the final net grouping range determined by the sliding window. Taking a routing scenario containing 10 nets (A to J) as an example, the implementation process of steps S1 and S2 above will be further explained in detail: Based on the "source pin x-coordinate priority" strategy in step S2, the sliding window first covers the net with the largest source pin x-coordinate, i.e., the net closest to the escape boundary. The number of nets within the window must meet a preset threshold (the threshold set in the figure is 3). Since the total number of nets in the two columns initially covered exceeds the limit, it is horizontally shrunk to a single column, intuitively presenting the window initialization logic of "prioritizing high-difficulty areas".

[0031] Among them, such as Figure 4 The diagram shown is a schematic diagram of the updated net routing results and the second net divided by a sliding window, provided by an embodiment of the present invention. Figure 4 As shown, the nets covered by the sliding window still exceed the limit in a single column, so they are sorted by "vertical distance between source pin and escape target," and the three nets with the smallest vertical distance are retained for routing. For example, Figure 5 The diagram shown is a schematic diagram of the second set of net routing results updated and the third set of nets divided by a sliding window, provided by an embodiment of the present invention. Figure 5 The image shows that the sliding window contains the remaining nets in the same column, and the nets are routed.

[0032] S4. Using a predefined geometric pattern, generate multiple candidate routing paths for each net within the current sliding window.

[0033] Optionally, predefined geometric patterns are used to generate diverse paths that conform to the Manhattan routing rules, ensuring the coverage and quality of the candidate set; among which, the predefined geometric patterns include: L-shaped routing pattern, Z-shaped routing pattern and U-shaped routing pattern.

[0034] Among them, the L-shaped routing pattern is a horizontal + vertical geometric pattern; the Z-shaped routing pattern is a horizontal + vertical + horizontal or vertical + horizontal + vertical geometric pattern; the U-shaped routing pattern is a horizontal + vertical + horizontal or vertical + horizontal + vertical geometric pattern; different routing patterns can adapt to different wiring channel requirements.

[0035] Optionally, the specific implementation process of S4 includes S41-S412: S41. Define the Manhattan-compliant geometric pattern; based on each net within the current sliding window, generate multiple candidate paths using the Manhattan-compliant geometric pattern, and calculate the comprehensive cost of each candidate path. The comprehensive cost is expressed by the following formula (1): Cost(p)=LengthCost(p)+λ·TypeCost(p)+ViaCount(p)·ViaCost(1) Wherein, LengthCost(p) represents the penalty for the deviation between the actual length and the Manhattan distance; λ is a scaling factor to amplify the weight of redundant paths; TypeCost(p) is the pattern type penalty, with L-shape < Z-shape < U-shape; ViaCount(p)·ViaCost is the via cost; S42. Controlling the generation proportion of different types of paths through weight parameters, and deciding to enable or disable the single-layer path according to whether the vertical interval overlaps with other pins, so that each net finally retains a preset number of candidate paths with the lowest cost. Wherein, the preset number set in the embodiment of the present invention is 30.

[0036] Wherein, generating diverse candidate paths by predefining geometric patterns and cost models can not only cover different routing requirements, but also guide the optimization direction through cost weights, so as to provide high-quality input for subsequent ILP solving.

[0037] S5. Constructing an integer linear programming model, with the goal of minimizing the total routing cost, selecting the optimal path scheme for each net from the candidate routing paths, and satisfying the routing constraints.

[0038] Wherein, the integer linear programming model is used to select the global optimal solution from the candidate paths, so as to balance the routing cost and constraint satisfaction.

[0039] Optionally, the specific implementation process of S5 includes S51 to S54: S51. Defining a binary decision variable x i,j ∈{0,1}, which indicates whether the net i selects the candidate path j; S52. Constructing the objective function of the integer linear programming model to minimize the total routing cost of all nets; Wherein, the objective function of the integer linear programming model is expressed by the following formula (2): (2) Wherein, represents the cost of the candidate path j of the net i, and N represents the set of all nets to be routed; represents the candidate path set of the net i; S53. Setting routing constraints, including: a single-path constraint that each net must select exactly one path, a topological conflict constraint that two candidate paths cannot coexist if they share routing resources, a spacing constraint that two paths cannot coexist if their spacing does not meet the design rule, and a binary constraint for the binary decision variables; S54. Solving the integer linear programming model by using the Gurobi solver, setting an upper limit of solving time to ensure efficiency, outputting the optimal solution of the objective function, and obtaining the optimal path selected for each net.

[0040] By constructing an integer linear programming model, the wiring problem within a local window can be transformed into a mathematical optimization problem, minimizing the total cost while satisfying constraints, thus achieving the globally optimal path selection.

[0041] S6. Solidify the completed cabling of the nets and their optimal path schemes in the current net subset to be processed, update the global cabling status, and select the next net subset through a sliding window.

[0042] State persistence is used to avoid the reuse of already wired resources and ensure the feasibility of subsequent wiring.

[0043] In one feasible implementation, the specific implementation process of S6 includes S61-S62: S61. Mark the successfully solved net paths in the current window as "routed" and add the routing resources they occupy, such as metal layer segments or via positions, to the obstacle list as no-route zones for subsequent routing. S62. Slide the sliding window in the direction of decreasing horizontal coordinate to cover the next batch of source pins with the second largest horizontal coordinate, and repeat steps S3 to S5.

[0044] Among them, such as Figure 6 The diagram shown is a schematic diagram of the third group of net routing results updated and the fourth group of nets divided by the sliding window, provided in an embodiment of the present invention. Figure 6 As shown, the sliding window slides along the direction of decreasing horizontal coordinate to cover the next batch of source pins with the second largest horizontal coordinate, and then routes this set of nets.

[0045] S7. Repeat steps S2-S6 until all nets have completed path planning, and finally output a complete escape cabling scheme.

[0046] In one feasible implementation, the specific implementation process of S7 includes S71-S72: S71. Repeat steps S2-S6 until all nets are marked as "routed", meaning that there is a valid path from the source pin of all nets to the escape target. S72. Output a complete escape routing scheme, including the path coordinates of each net, the metal layers used, the via locations, and the total length, ensuring that the scheme meets the design rules and is conflict-free.

[0047] Among them, such as Figure 7 The diagram shown is a schematic representation of the wiring result provided in an embodiment of the present invention. Wherein, Figure 7This diagram shows a top-down view of the results in a two-layer routing configuration, with both source and target pins located on metal layer 1. Black squares represent source pins of the nets, gray dots represent target pins, gray dashed lines represent horizontal and vertical tracks, gray solid lines represent traces on metal layer 2, and black solid lines represent traces on metal layer 1. All nets extend from source pins to target pins at escape boundaries, without conflicts and in compliance with design rules.

[0048] In this embodiment of the invention, sequential optimization of local subproblems reduces computational complexity while ensuring wiring quality, thereby improving the wiring efficiency and success rate of high-density core systems in obstacle-dense scenarios.

[0049] This invention, by introducing a sliding window mechanism, decomposes the large-scale global escape routing problem into a series of continuous and controllable-scale local subproblems. This effectively avoids the unsolvable problems caused by the explosion of problem size in traditional integer programming methods, achieving linear control of computational complexity and significantly improving the scalability of the algorithm in large-scale scenarios. By combining a preset geometric routing pattern to guide the generation of candidate solutions and formalizing the path selection problem into an integer programming model, high-quality optimization can be achieved within each local window, ensuring the superiority of the overall routing scheme in key indicators such as bus length and via count. In obstacle-dense scenarios, compared with existing methods, this invention significantly improves the routing completion rate while effectively reducing the number of vias and shortening the bus length, ensuring high-quality routing results while possessing good scalability and engineering robustness.

[0050] Figure 8 This is a block diagram of a progressive ILP chip escape routing system based on a sliding window, provided by an embodiment of the present invention. This system is used in a progressive ILP chip escape routing method based on a sliding window. (Refer to...) Figure 8 The system includes an acquisition module 810, an update module 820, a judgment module 830, a generation module 840, a selection module 850, a solidification module 860, and an output module 870. Among them: The acquisition module 810 includes: acquiring the wiring information of the chip; wherein, the wiring information includes net information, obstacle information, wiring design constraint information, and available wiring track information; The update module 820 is used to update the sliding window according to the chip's routing information through a sliding window mechanism, and to determine the subset of the nets to be routed contained in the current window; The determination module 830 is used to determine whether the number of nets in the sliding window exceeds a preset threshold based on the subset of nets to be routed in the current window. If it exceeds the threshold, the window range is dynamically adjusted through a window shrinking strategy until the number of nets meets the threshold requirement. The generation module 840 is used to generate multiple candidate routing paths for each net within the current sliding window using a predefined geometric pattern. Selection module 850 is used to construct an integer linear programming model to select the optimal path scheme for each net from the candidate routing paths with the goal of minimizing the total routing cost and satisfying the routing constraints. The solidification module 860 is used to solidify the completed wiring of the nets and their optimal path schemes in the current net subset to be processed, update the global wiring status, and select the next net subset through a sliding window. The output module 870 is used to repeat the steps until all nets have completed path planning, and finally outputs a complete escape routing scheme.

[0051] Optionally, the net information includes the net name, net source pin coordinates, and net target pin coordinates; The obstacle information includes the obstacle size, obstacle location, and the layer on which the obstacle is located; The routing design constraints include the trace width of different chip layers, the spacing between lines of different chip layers, and the spacing between lines of different chip layers and obstacles. The available track information for wiring includes the horizontal track coordinates and the vertical track coordinates of different metal layers.

[0052] Optionally, the update module 820 is used for: Based on the horizontal coordinate position of each net source pin in the routing information of the chip, all nets are sorted to obtain the sorting result; The sliding window is initialized based on the sorting results. The batch of nets with the largest x-coordinate of the source pins is included in the current window to complete the net routing within the current window. The current window is then slid along the direction of decreasing x-coordinate to determine the subset of nets to be routed contained in the current window.

[0053] Optionally, the determination module 830 is used for: Count the number of wires in the current window and determine if it exceeds a preset threshold; if it does, shrink the window horizontally and vertically using a window shrinking strategy. When the window is horizontally shrunk, if the current window covers two or more adjacent nets and the total number exceeds a preset threshold, the window will be shrunk to cover only a single column, that is, only a batch of nets with the same horizontal coordinate of the source pins. When shrinking the window vertically, if the number of nets in a single column exceeds a preset threshold, the nets are sorted according to the vertical distance between the source pin and the escape target, and the nets with the smallest vertical distance are retained first, until the number of nets in the window is less than or equal to the preset threshold.

[0054] Optionally, the predefined geometric patterns are used to generate diversified paths complying with Manhattan routing rules, ensuring the coverage and quality of the candidate set; wherein the predefined geometric patterns include an L-shaped routing pattern, a Z-shaped routing pattern, and a U-shaped routing pattern.

[0055] Optionally, the generating module 840 is configured to: Define Manhattan-compliant geometric patterns; for each net in the current sliding window, generate a plurality of candidate paths through the Manhattan-compliant geometric patterns, and calculate the comprehensive cost of each candidate path; Wherein the comprehensive cost is expressed by the following formula (3): Cost(p)=LengthCost(p)+λ·TypeCost(p)+ViaCount(p)·ViaCost (3) Wherein LengthCost(p) represents the penalty for the deviation between the actual length and the Manhattan distance; λ is a scaling factor for amplifying the weight of redundant paths; TypeCost(p) is the pattern type penalty, where L-shape < Z-shape < U-shape; ViaCount(p)·ViaCost is the via overhead; Control the generation proportion of different types of paths through weight parameters, and decide to enable or disable single-layer paths according to whether the vertical interval overlaps with other pins, so that each net finally retains a preset number of candidate paths with the lowest cost.

[0056] Optionally, the selecting module 850 is configured to: Define a binary decision variable x i,j ∈{0,1}, which indicates whether the net i selects the candidate path j; Construct an objective function of an integer linear programming model to minimize the total routing cost of all nets; Wherein the objective function of the integer linear programming model is expressed by the following formula (4): (4) Wherein, represents the cost of the candidate path j of the net i, and N represents the set of all nets to be routed; represents the candidate path set of the net i; Set routing constraints, including: a single-path constraint that each net must select exactly one path, a topological conflict constraint that two candidate paths cannot coexist if they share routing resources, a spacing constraint that two paths cannot coexist if their spacing does not meet the design rule, and a binary constraint for the binary decision variable x i,j ; Solve the integer linear programming model using the Gurobi solver, set an upper limit on the solving time to ensure efficiency, output the optimal solution of the objective function, and obtain the optimal path selected for each net.

[0057] This invention, by introducing a sliding window mechanism, decomposes the large-scale global escape routing problem into a series of continuous and controllable-scale local subproblems. This effectively avoids the unsolvable problems caused by the explosion of problem size in traditional integer programming methods, achieving linear control of computational complexity and significantly improving the scalability of the algorithm in large-scale scenarios. By combining a preset geometric routing pattern to guide the generation of candidate solutions and formalizing the path selection problem into an integer programming model, high-quality optimization can be achieved within each local window, ensuring the superiority of the overall routing scheme in key indicators such as bus length and via count. In obstacle-dense scenarios, compared with existing methods, this invention significantly improves the routing completion rate while effectively reducing the number of vias and shortening the bus length, ensuring high-quality routing results while possessing good scalability and engineering robustness.

[0058] Figure 9 This is a schematic diagram of a progressive ILP core escape cabling device based on a sliding window, as provided in an embodiment of the present invention. Figure 9 As shown, the progressive ILP core escape wiring device based on a sliding window can include the above-mentioned Figure 8 The illustrated progressive ILP chip escape routing system is based on a sliding window. Optionally, the progressive ILP chip escape routing device 910 based on a sliding window may include a first processor 2001.

[0059] Optionally, the progressive ILP core escape wiring device 910 based on a sliding window may also include a memory 2002 and a transceiver 2003.

[0060] The first processor 2001, memory 2002, and transceiver 2003 can be connected via a communication bus.

[0061] The following is combined Figure 9 A detailed introduction to each component of the sliding window-based progressive ILP core escape cabling device 910 is provided below: The first processor 2001 is the control center of the sliding window-based progressive ILP chip escape wiring device 910. It can be a single processor or a collective term for multiple processing elements. For example, the first processor 2001 can be one or more central processing units (CPUs), application-specific integrated circuits (ASICs), or one or more integrated circuits configured to implement embodiments of the present invention, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs).

[0062] Optionally, the first processor 2001 can perform various functions of the sliding window-based progressive ILP core escape wiring device 910 by running or executing software programs stored in the memory 2002 and calling data stored in the memory 2002.

[0063] In a specific implementation, as one example, the first processor 2001 may include one or more CPUs, for example... Figure 9 CPU0 and CPU1 are shown in the diagram.

[0064] In a specific implementation, as one example, the progressive ILP core escape wiring device 910 based on a sliding window may also include multiple processors, for example... Figure 9 The first processor 2001 and the second processor 2004 are shown in the diagram. Each of these processors can be a single-core processor or a multi-core processor. Here, a processor can refer to one or more devices, circuits, and / or processing cores used to process data (such as computer program instructions).

[0065] The memory 2002 is used to store the software program that executes the present invention, and is controlled by the first processor 2001 to execute it. The specific implementation method can be referred to the above method embodiment, and will not be repeated here.

[0066] Optionally, the memory 2002 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory 2002 may be integrated with the first processor 2001 or may exist independently, and may be interfaced through the sliding window-based progressive ILP die escape wiring device 910 interface circuitry. Figure 9 (Not shown in the image) is coupled to the first processor 2001, and this embodiment of the invention does not specifically limit this.

[0067] The transceiver 2003 is used to communicate with network devices or with terminal devices.

[0068] Alternatively, transceiver 2003 may include a receiver and a transmitter. Figure 9 (Not shown separately). The receiver is used to implement the receiving function, and the transmitter is used to implement the transmitting function.

[0069] Alternatively, the transceiver 2003 can be integrated with the first processor 2001 or exist independently, and can be interfaced through the sliding window-based progressive ILP core escape wiring device 910. Figure 9 (Not shown in the image) is coupled to the first processor 2001, and this embodiment of the invention does not specifically limit this.

[0070] It should be noted that, Figure 9 The structure of the sliding window-based progressive ILP chip escape cabling device 910 shown does not constitute a limitation on the router. Actual sliding window-based progressive ILP chip escape cabling devices may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0071] Furthermore, the technical effects of the progressive ILP core escape routing device 910 based on a sliding window can be referred to the technical effects of the progressive ILP core escape routing method based on a sliding window described in the above method embodiments, and will not be repeated here.

[0072] It should be understood that the first processor 2001 in the embodiments of the present invention may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor, or it may be any conventional processor, etc.

[0073] It should also be understood that the memory in the embodiments of the present invention can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0074] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable system. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0075] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0076] In this invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be a single item or multiple items.

[0077] It should be understood that, in various embodiments of the present invention, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0078] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0079] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices, systems, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0080] In the embodiments provided by this invention, it should be understood that the disclosed devices, systems, and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between systems or units may be electrical, mechanical, or other forms.

[0081] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0082] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0083] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0084] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A progressive ILP core escape routing method based on a sliding window, characterized in that, The method includes: S1. Obtain the wiring information of the chip; wherein, the wiring information includes net information, obstacle information, wiring design constraint information, and available wiring track information; S2. Based on the chip's routing information, update the sliding window using a sliding window mechanism to determine the subset of the network to be routed contained in the current window; S3. Based on the subset of nets to be routed in the current window, determine whether the number of nets in the sliding window exceeds the preset threshold. If it does, dynamically adjust the window range through the window shrinking strategy until the number of nets meets the threshold requirement. S4. Using a predefined geometric pattern, generate multiple candidate routing paths for each net within the current sliding window; S5. Construct an integer linear programming model with the goal of minimizing the total wiring cost, select the optimal path scheme for each net from the candidate wiring paths, and satisfy the wiring constraints. S6. Solidify the completed wiring of the nets and their optimal path schemes in the current net subset to be processed, update the global wiring status, and select the next net subset through a sliding window. S7. Repeat steps S2-S6 until all nets have completed path planning, and finally output a complete escape cabling scheme.

2. The progressive ILP core escape routing method based on a sliding window according to claim 1, characterized in that, The net information includes the net name, net source pin coordinates, and net target pin coordinates; The obstacle information includes the obstacle size, obstacle location, and the layer on which the obstacle is located; The routing design constraints include the trace width of different chip layers, the spacing between lines of different chip layers, and the spacing between lines of different chip layers and obstacles. The available track information for wiring includes the horizontal track coordinates and the vertical track coordinates of different metal layers.

3. The progressive ILP core escape routing method based on a sliding window according to claim 1, characterized in that, S2 updates the sliding window based on the chip's routing information using a sliding window mechanism, determining the subset of the network to be routed contained in the current window, including: S21. Sort all nets according to the horizontal coordinate position of each net source pin in the routing information of the chip, and obtain the sorting result. S22. Initialize the sliding window based on the sorting result, include the batch of nets with the largest horizontal coordinate of the source pins into the current window, and complete the net routing within the current window; slide the current window along the direction of decreasing horizontal coordinate to determine the subset of nets to be routed contained in the current window.

4. The progressive ILP core escape routing method based on a sliding window according to claim 1, characterized in that, S3, based on the current window's subset of nets to be routed, determines whether the number of nets within the sliding window exceeds a preset threshold. If it does, the window range is dynamically adjusted using a window shrinking strategy until the number of nets meets the threshold requirement, including: Count the number of wires in the current window and determine if it exceeds a preset threshold; if it does, shrink the window horizontally and vertically using a window shrinking strategy. When the window is horizontally shrunk, if the current window covers two or more adjacent nets and the total number exceeds a preset threshold, the window will be shrunk to cover only a single column, that is, only a batch of nets with the same horizontal coordinate of the source pins. When shrinking the window vertically, if the number of nets in a single column exceeds a preset threshold, the nets are sorted by the vertical distance between the source pin and the escape target, and the nets with the smallest vertical distance are retained first, until the number of nets in the window is less than or equal to the preset threshold.

5. The progressive ILP core escape routing method based on a sliding window according to claim 1, characterized in that, The predefined geometric patterns are used to generate diverse paths that comply with Manhattan routing rules, ensuring the coverage and quality of the candidate set; wherein the predefined geometric patterns include an L-shaped routing pattern, a Z-shaped routing pattern, and a U-shaped routing pattern.

6. The progressive ILP core escape routing method based on a sliding window according to claim 1, characterized in that, The step S4 of generating a plurality of candidate routing paths for each net in the current sliding window by using the predefined geometric patterns comprises: S41. Defining Manhattan-compliant geometric patterns; generating a plurality of candidate paths for each net in the current sliding window through the Manhattan-compliant geometric patterns, and calculating the comprehensive cost of each candidate path; Wherein the comprehensive cost is expressed by the following formula (1): Cost(p)=LengthCost(p)+λ·TypeCost(p)+ViaCount(p)·ViaCost (1) Wherein LengthCost(p) represents a penalty for the deviation of the actual length from the Manhattan distance; λ is a scaling factor for amplifying the weight of redundant paths; TypeCost(p) is a pattern type penalty, where L-shape < Z-shape < U-shape; ViaCount(p)·ViaCost is the via overhead; S42. Controlling the generation proportion of different types of paths through weight parameters, and deciding to enable or disable the single-layer path according to whether the vertical interval overlaps with other pins, so that each net finally retains a preset number of candidate paths with the lowest cost.

7. The progressive ILP core escape routing method based on a sliding window according to claim 1, characterized in that, The step S5 of constructing an integer linear programming model, which aims at minimizing the total routing cost, to select an optimal path scheme for each net from the candidate routing paths and satisfy routing constraints, comprises: S51. Define binary decision variable x i,j ∈{0,1} indicates whether net i selects candidate path j; S52. Constructing an objective function of the integer linear programming model to minimize the total routing cost of all nets; Wherein the objective function of the integer linear programming model is expressed by the following formula (2): （2） in, Let N represent the cost of candidate path j for net i, and N represent the set of all nets to be routed. Represents the set of candidate paths for net i; S53. Set routing constraints, including: a single-path constraint that each net must select one and only one path; a topology conflict constraint that two candidate paths cannot coexist if they share routing resources; a spacing constraint that two paths cannot coexist if the spacing does not meet the design rules; and a binary decision variable x. i,j binary constraints; S54. Solving the integer linear programming model by using a Gurobi solver, and setting an upper limit of solving time to ensure efficiency, outputting the optimal solution of the objective function, and obtaining the optimal path selected for each net.

8. A progressive ILP chip escape routing system based on a sliding window, wherein the progressive ILP chip escape routing system based on a sliding window is used to implement the progressive ILP chip escape routing method based on a sliding window as described in any one of claims 1-7, characterized in that, The system comprises: An acquisition module, configured to acquire to-be-routed information of a chip; wherein the to-be-routed information comprises net information, obstacle information, routing design constraint information, and available track information for routing; An update module, configured to update a sliding window through a sliding window mechanism according to the to-be-routed information of the chip, and determine a to-be-routed net subset included in the current window; A judgment module, configured to judge, based on the to-be-routed net subset in the current window, whether the number of nets in the sliding window exceeds a preset threshold, and if the number exceeds the preset threshold, dynamically adjust the window range through a window shrinking strategy until the number of nets meets the threshold requirement; A generation module, configured to generate a plurality of candidate routing paths for each net in the current sliding window by using predefined geometric patterns; A selection module, configured to construct an integer linear programming model, which aims at minimizing the total routing cost, to select an optimal path scheme for each net from the candidate routing paths and satisfy routing constraints; The solidification module is used to solidify the completed wiring of the nets and their optimal path schemes in the current net subset to be processed, update the global wiring status, and select the next net subset through a sliding window. The output module is used to repeat the steps until all nets have completed path planning, and finally outputs a complete escape routing scheme.

9. A progressive ILP core escape cabling device based on a sliding window, characterized in that, The sliding window-based progressive ILP core escape cabling device includes: processor; A memory storing computer-readable instructions that, when executed by the processor, implement the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium contains program code that can be invoked by a processor to execute the method as described in any one of claims 1 to 7.

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