A register hardening circuit design method against single event upsets
Patent Information
- Application Number
- CN202611084179.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-21
- Publication Date
- 2026-10-13
AI Technical Summary
[0005]2、复杂电路中，采用的控制寄存器非常多，当寄存器数量达到上万个时，如果每个寄存器面积增加到数十倍，将导致芯片面积迅速增加，增加的面积量甚至是不可接受的
[0014]1、本发明通过流片、调试、再设计的方式，删除可固化的功能寄存器，并根据调试结果将各个可固化的寄存器的输出端对应的节点接高电平或低电平，实现寄存器数量的大幅度减少，从而减少版图面积和功耗；
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Figure CN122904840A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuits and relates to a register hardening circuit design method to resist single-event upsets. Background Technology
[0002] With the development of information technology, the requirements for signal acquisition and processing circuits are becoming increasingly stringent. In order to improve the reliability of circuits in space applications, radiation hardening design is required. As process dimensions continue to shrink, CMOS devices are becoming increasingly resistant to total dose, reducing the difficulty of total dose design. However, their resistance to single-event upsets is becoming increasingly weak, especially in digital circuits. Since devices generally use minimum channel length and have small areas, even a small amount of space charge can cause them to flip, resulting in functional interruptions or even failure to function properly. Therefore, it is necessary to harden the control registers in the circuit to resist single-event upsets to ensure normal circuit function.
[0003] Traditional RC filtering can filter out single-event pulses, but it has the following two problems:
[0004] 1. When only RC reinforcement is used, the area of the standard register cell increases by tens of times;
[0005] 2. In complex circuits, a large number of control registers are used. When the number of registers reaches tens of thousands, if the area of each register increases by tens of times, the chip area will increase rapidly, and the increase in area may even be unacceptable. Summary of the Invention
[0006] To address the aforementioned problems in the prior art, this invention employs a register hardening circuit design method resistant to single-event upsets, comprising: designing a register hardening circuit resistant to single-event upsets using a combination of system-level simplification and unit-level hardening; wherein, the system-level simplification method is used to reduce the number of registers, and the unit-level hardening method is used to improve the registers' resistance to single-event upsets.
[0007] The design of register hardening circuits resistant to single-event upsets employs a combination of system-level simplification and unit-level hardening, including:
[0008] S1. Circuit design and fabrication using unhardened registers yield unhardened register circuits; unhardened register circuits include: non-hardened registers and hardened registers;
[0009] S2. Debug the unhardened register circuit and obtain the debugging results of each hardenable register in the unhardened register circuit;
[0010] S3. Using the debugging results of the register that can be hardened, simplify the unhardened register circuit to obtain the simplified unhardened register circuit.
[0011] S4. Perform unit-level hardening on each non-hardened register in the unhardened register circuit to obtain the hardened register unit of each non-hardened register.
[0012] S5. Using the hardened register unit and the simplified unhardened register circuit, circuit design and fabrication are performed to obtain a register hardened circuit resistant to single-event upsets.
[0013] Beneficial effects:
[0014] 1. This invention eliminates the number of registers by tape-out, debugging, and redesign, and connects the corresponding nodes of the output terminals of each register to a high or low level according to the debugging results, thereby significantly reducing the number of registers, thus reducing the layout area and power consumption.
[0015] 2. This invention uses a combination of rising edge suppression unit, falling edge suppression unit and RC filter unit to strengthen the register that must be re-tuned after each tape-out, ensuring the overall circuit's configurability and flexibility. Compared with the traditional method of using only RC filter, it improves the suppression capability of single-particle pulses, thereby improving the register's anti-flip capability.
[0016] 3. Based on the characteristic that the capacitance values of PMOS and NMOS change in opposite directions with voltage, this invention adopts a parallel connection of PMOS and NMOS capacitors to cancel each other out with voltage changes, thus solving the problem of large fluctuations in capacitance value with voltage changes caused by using only PMOS or NMOS capacitors, and improving the stability of register anti-flip capability.
[0017] 4. MOM capacitors use a single-layer metal internal interdigitated fingers, with adjacent metal layers overlapping each other, so that each interdigitated finger is another plate on the top, bottom, left and right, increasing the capacitance density and thus reducing the layout area. Attached Figure Description
[0018] Figure 1 A flowchart of a register hardening circuit design method to resist single-event upsets is provided for an embodiment of the present invention;
[0019] Figure 2 A flowchart of unit-level reinforcement provided in an embodiment of the present invention;
[0020] Figure 3 A schematic diagram of the unit-level reinforcement principle provided in an embodiment of the present invention;
[0021] Figure 4 A schematic diagram of the unit-level reinforcement principle provided in an embodiment of the present invention;
[0022] Figure 5This is a structural diagram of the rising edge suppression unit provided in an embodiment of the present invention;
[0023] Figure 6 This is a structural diagram of the rising edge suppression unit provided in an embodiment of the present invention;
[0024] Figure 7 This is a structural diagram of the rising edge suppression unit provided in an embodiment of the present invention;
[0025] Figure 8 This is a structural diagram of the falling edge suppression unit provided in an embodiment of the present invention;
[0026] Figure 9 This is a structural diagram of the falling edge suppression unit provided in an embodiment of the present invention;
[0027] Figure 10 This is a structural diagram of the falling edge suppression unit provided in an embodiment of the present invention;
[0028] Figure 11 This is a schematic diagram of a single-layer interdigitated capacitor provided in an embodiment of the present invention;
[0029] Figure 12 A schematic diagram of a directly overlapping multilayer interdigitated capacitor provided in an embodiment of the present invention;
[0030] Figure 13 This is a schematic diagram of an interlaced multilayer interdigitated capacitor provided in an embodiment of the present invention. Detailed Implementation
[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0032] like Figure 1 As shown, this embodiment of the invention employs a register hardening circuit design method to resist single-event upsets, including:
[0033] S1. Circuit design and fabrication using unhardened registers yield unhardened register circuits; unhardened register circuits include: non-hardened registers and hardened registers;
[0034] In the initial overall circuit design, all registers in this invention are non-hardened registers, which are then fabricated. The non-hardened registers are the "function registers" and "random error registers" that must be configured, which must be re-tuned after each fabrication. The hardened registers are the "function registers" and "system fixed error registers".
[0035] S2. Debug the unhardened register circuit and obtain the debugging results of each hardenable register in the unhardened register circuit;
[0036] In subsequent designs, the firmware registers can be deleted, and based on the debugging results of the firmware registers, the nodes corresponding to their output terminals can be fixed to high or low levels, thereby reducing the chip area and reducing the number of registers from tens of thousands to thousands, or even hundreds or tens.
[0037] S3. Using the debugging results of the register that can be hardened, simplify the unhardened register circuit to obtain the simplified unhardened register circuit.
[0038] Remove all hardenable registers from the unhardened register circuit, and connect the corresponding nodes of the output terminals of each hardenable register to high or low level according to the debugging results (connect to high level if the debugging result is high level, and connect to low level if the debugging result is low level). This results in a simplified unhardened register circuit, thereby reducing the chip area and reducing the number of registers from tens of thousands to thousands, hundreds, or even tens.
[0039] S4. Perform unit-level hardening on each non-hardened register in the unhardened register circuit to obtain the hardened register unit of each non-hardened register.
[0040] like Figure 2 As shown, cell-level hardening of non-hardware registers includes:
[0041] S41. Disconnect the latch loop of the non-fixable register to obtain two disconnected ports A and A';
[0042] S42. Construct a single-event upset (SOME) circuit. Connect the input and output terminals of the SOME circuit to two disconnected ports A and A', respectively, thereby closing the latch loop of the register and obtaining the register unit. The SOME circuit includes, in sequence, a suppression unit and an RC filter unit.
[0043] The suppression unit can consist of multiple rising edge suppression units connected in series, multiple falling edge suppression units connected in series, or multiple rising edge suppression units and falling edge suppression units connected in series. The sum of the number of rising edge suppression units and falling edge suppression units is even, so as not to change the polarity of the signal; the order of rising edge suppression units and falling edge suppression units can be interchanged.
[0044] Unit-level reinforcement principle as follows Figure 3 or Figure 4 As shown, Figure 3In the process of disconnecting the register's latch loop, before disconnection, A and A' are the same point on the loop. The A' signal is processed sequentially by the falling edge suppression unit, rising edge suppression unit, and RC filter unit before being sent back to point A on the loop; similarly, Figure 4 In the process, the latch loop of the register is disconnected. Before disconnection, B and B' are the same point on the loop. The B' signal is processed by the falling edge suppression unit, rising edge suppression unit, and RC filter unit in sequence and then sent back to point B on the loop.
[0045] One implementation of the rising edge suppression unit, such as Figure 5 As shown, it includes: a PMOS transistor M11 and an NMOS transistor M21; the source of PMOS transistor M11 is connected to the power supply, and the drain of PMOS transistor M21 is connected to the drain of NMOS transistor M21, while the source of NMOS transistor M21 is grounded; the gates of PMOS transistor M11 and NMOS transistor M21 are connected to the input terminals of the rising edge suppression unit, and the drains of PMOS transistor M11 and NMOS transistor M21 are connected to the output terminals of the rising edge suppression unit; wherein, the width-to-length ratio W11 / L11 of PMOS transistor M11 is smaller than the width-to-length ratio W21 / L21 of NMOS transistor M21, therefore the driving capability of PMOS is small, which can suppress its output rising edge.
[0046] One implementation of the rising edge suppression unit, such as Figure 6 As shown, it includes: PMOS transistor M11, NMOS transistor M21 and resistor R1; wherein, the source of PMOS device M11 is connected in series with resistor R1, thereby suppressing its output rising edge.
[0047] One implementation of the rising edge suppression unit, such as Figure 7 As shown, the rising edge of the PMOS transistor M11 can be suppressed by increasing the distance between the source and gate, increasing the distance between the drain and gate, increasing both the distance between the source and gate and the distance between the drain and gate, not increasing either the distance between the source and gate or the distance between the drain and gate, stacking a salicide block layer between the source and gate to further increase the source resistance, stacking a salicide block layer between the drain and gate to further increase the drain resistance, stacking salicide block layers between the source and gate and between the drain and gate to further increase the source and drain resistance, or not stacking a salicide block layer between the source and gate or between the drain and gate.
[0048] The rising edge suppression unit can be implemented using one or more of the above methods.
[0049] One implementation of the falling edge suppression unit, such as Figure 8As shown, it includes: a PMOS transistor M14 and an NMOS transistor M24; the source of the PMOS transistor M14 is connected to the power supply, and the drain of the PMOS transistor M24 is connected to the drain of the NMOS transistor M24, while the source of the NMOS transistor M24 is grounded; the gates of the PMOS transistor M14 and the NMOS transistor M24 are connected to the input terminals of the falling edge suppression unit, and the drains of the PMOS transistor M14 and the NMOS transistor M24 are connected to the output terminals of the falling edge suppression unit; the width-to-length ratio of the PMOS transistor M14 is greater than that of the NMOS transistor M24; wherein the width-to-length ratio W14 / L14 of the PMOS transistor M14 is greater than that of the NMOS transistor M24, W24 / L24, therefore the NMOS has a smaller driving capability, which can suppress its output falling edge.
[0050] One implementation of the falling edge suppression unit, such as Figure 9 As shown, it includes: PMOS transistor M14, NMOS transistor M24 and resistor R2; the source of PMOS transistor M24 is connected in series with resistor R2, thereby suppressing its output falling edge;
[0051] One implementation of the falling edge suppression unit, such as Figure 10 As shown, the following methods can be used to suppress the output falling edge of the NMOS device M24: increasing the distance between the source and gate, increasing the distance between the drain and gate, increasing both the distance between the source and gate and the distance between the drain and gate, not increasing either the distance between the source and gate or the distance between the drain and gate, stacking a salicide block layer between the source and gate to further increase the source resistance, stacking a salicide block layer between the drain and gate to further increase the drain resistance, stacking salicide block layers between the source and gate and between the drain and gate to further increase the source and drain resistance, or not stacking a salicide block layer between the source and gate or between the drain and gate.
[0052] The falling edge suppression unit can be implemented using one or more of the above methods.
[0053] The RC filter unit is implemented by connecting a resistor R and a capacitor C in series. The capacitor C can be one or more of PMOS, NMOS and MOM capacitors: (1) Only PMOS, NMOS or MOM capacitors are used; (2) PMOS and NMOS capacitors are connected in parallel, and the ratio of the two capacitors is determined by the magnitude of the change of the capacitance value of the two capacitors with the voltage, so as to ensure that the sum of the two capacitors fluctuates with the voltage change to the minimum; (3) PMOS or NMOS capacitors are connected in parallel with MOM capacitors; (4) PMOS, NMOS and MOM capacitors are used at the same time and connected in parallel.
[0054] MOM capacitors can overlap spatially with PMOS capacitors, NMOS capacitors, resistors R, and other devices to reduce the layout area, or they can be left unoverlapped.
[0055] One way to implement MOM capacitors is as a single-layer metal interdigitated capacitor, such as... Figure 11 As shown; another implementation method is to directly overlap multilayer metal interdigitated capacitors to achieve parallel connection, such as... Figure 12 As shown; the third implementation method is to achieve parallel connection of multilayer metal interdigitated capacitors by overlapping, such as... Figure 13 As shown, each forked finger is positioned above, below, to the left, and to the right as another electrode, increasing capacitance density and thus reducing the layout area.
[0056] The interdigitation width and spacing of the aforementioned MOM capacitors can be achieved using the minimum metal line width and minimum metal spacing, thus saving layout area.
[0057] S43. Adjust the size and layout of the single-event upset (SED) circuitry of the register unit;
[0058] Adjusting the size and layout of the register cell's anti-single-event upset (SOME) circuitry is to improve its SOME capability; the rising edge suppression unit can be adjusted using any one or more of the following methods:
[0059] Increase the number of rising edge suppression units;
[0060] In the rising edge suppression unit, reduce the width-to-length ratio of PMOS transistor M11 or increase the width-to-length ratio of NMOS transistor M21;
[0061] Add a resistor connected in series with the source of PMOS transistor M11 in the rising edge suppression unit;
[0062] In the rising edge suppression unit, increase the distance between the source and gate of PMOS transistor M11, or increase the distance between the drain and gate, or simultaneously increase both the distance between the source and gate and the distance between the drain and gate.
[0063] A salicide block layer is added between the source and gate of the PMOS transistor M11 in the rising edge suppression unit, or between the drain and gate, or both between the source and gate and between the drain and gate.
[0064] The falling edge suppression unit can be adjusted using any one or more of the following adjustment methods:
[0065] Increase the number of falling edge suppression units;
[0066] In the falling edge suppression unit, reduce the width-to-length ratio of NMOS transistor M24 or increase the width-to-length ratio of PMOS transistor M14;
[0067] Add a resistor connected in series with the source of NMOS transistor M24 in the falling edge suppression unit;
[0068] In the falling edge suppression unit, increase the distance between the source and gate of the NMOS transistor M24, or increase the distance between the drain and gate, or simultaneously increase both the distance between the source and gate and the distance between the drain and gate.
[0069] A salicide block layer is added between the source and gate of the NMOS transistor M24 in the falling edge suppression unit, or between the drain and gate, or both between the source and gate and between the drain and gate.
[0070] The size of the RC filter unit can be adjusted using any one or more of the following methods:
[0071] 1. Increase the resistance R in the RC filter unit;
[0072] 2. Increase the capacitance C in the RC filter unit.
[0073] Adjusting the layout of the register unit's anti-single-event upset circuit includes: adding rising edge suppression units, falling edge suppression units, and substrate contacts for the power / ground of PMOS and NMOS transistors in the RC filter unit to avoid single-event latch-up; reducing the overall area of the RC filter unit while keeping the RC product unchanged.
[0074] S44. Simulation verification: Does the register unit obtained in step S43 meet the preset requirements? If it does, then the register unit after register hardening is obtained; otherwise, return to step S43 to adjust the size and layout of the anti-single-event upset circuit.
[0075] The simulation verification step S43 determines whether the register unit obtained meets the preset requirements, including: the normal indicators such as speed and power consumption of the register unit obtained in step S43, as well as the radiation index against single-particle pulses, and whether the calculated indicators meet the preset requirements.
[0076] S5. Using the hardened register unit and the simplified unhardened register circuit, circuit design and fabrication are performed to obtain a register hardened circuit resistant to single-event upsets.
[0077] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A register hardening circuit design method to resist single-event upsets, characterized in that, include: A register hardening circuit resistant to single-event upsets is designed using a combination of system-level simplification and unit-level hardening. The system-level simplification method is used to reduce the number of registers, while the unit-level hardening method is used to improve the registers' resistance to single-event upsets.
2. The register hardening circuit design method against single-event upsets according to claim 1, characterized in that, The design of register hardening circuits resistant to single-event upsets employs a combination of system-level simplification and unit-level hardening, including: S1. Circuit design and fabrication using unhardened registers yield unhardened register circuits; unhardened register circuits include: non-hardened registers and hardened registers; S2. Debug the unhardened register circuit and obtain the debugging results of each hardenable register in the unhardened register circuit; S3. The debugging results of the register are used to simplify the unhardened register circuit, resulting in a simplified unhardened register circuit. S4. Perform unit-level hardening on each non-hardened register in the unhardened register circuit to obtain the hardened register unit of each non-hardened register. S5. Using the hardened register unit and the simplified unhardened register circuit, circuit design and fabrication are performed to obtain a register hardened circuit resistant to single-event upsets.
3. The register hardening circuit design method against single-event upsets according to claim 2, characterized in that, The simplified register unhardened circuit based on the debugging results of the hardened registers includes: deleting all hardened registers in the register unhardened circuit, and connecting the nodes corresponding to the output terminals of each hardened register to high or low level according to the debugging results, thus obtaining the simplified register unhardened circuit.
4. The register hardening circuit design method against single-event upsets according to claim 2, characterized in that, Unit-level hardening of non-hardened registers in unhardened circuits includes: S41. Disconnect the latch loop of the non-fixable register to obtain two disconnected ports A and A'; S42. Construct a single-event upset (SOME) circuit by connecting the input and output terminals of the SOME circuit to two disconnected ports A and A', respectively, to obtain a register unit; wherein, the SOME circuit includes, in sequence, a suppression unit and an RC filter unit; S43. Adjust the size and layout of the single-event upset (SED) circuitry of the register unit; S44. Verify whether the register unit obtained in step S43 meets the requirements. If it does, obtain the register unit after register hardening that is not fixed. Otherwise, return to step S43 to adjust the size and layout of the anti-single event upset circuit.
5. The register hardening circuit design method against single-event upsets according to claim 4, characterized in that, The suppression unit uses multiple rising edge suppression units connected in series, or multiple falling edge suppression units connected in series, or multiple rising edge suppression units and falling edge suppression units connected in series.
6. The register hardening circuit design method against single-event upsets according to claim 5, characterized in that, The sum of the number of rising edge suppression units and falling edge suppression units is even.
7. The register hardening circuit design method against single-event upsets according to claim 5, characterized in that, The rising edge suppression unit and falling edge suppression unit of the suppression unit can be interchanged.
8. The register hardening circuit design method against single-event upsets according to claim 5, characterized in that, The rising edge suppression unit includes a PMOS transistor M11 and an NMOS transistor M21; the source of the PMOS transistor M11 is connected to the power supply, and the drain of the PMOS transistor M21 is connected to the drain of the NMOS transistor M21, while the source of the NMOS transistor M21 is grounded; the gates of the PMOS transistor M11 and the NMOS transistor M21 are connected to the input terminal of the rising edge suppression unit, and the drains of the PMOS transistor M11 and the NMOS transistor M21 are connected to the output terminal of the rising edge suppression unit; the width-to-length ratio of the PMOS transistor M11 is smaller than that of the NMOS transistor M21.
9. A register hardening circuit design method against single-event upsets according to claim 8, characterized in that, The rising edge suppression unit also includes resistor R1, which is the source series resistor R1 of PMOS transistor M11.
10. A register hardening circuit design method against single-event upsets according to claim 8, characterized in that, The rising edge suppression unit increases the distance between the source and gate of the PMOS transistor M11, or increases the distance between the drain and gate, or simultaneously increases both the distance between the source and gate and the distance between the drain and gate.
11. The register hardening circuit design method against single-event upsets according to claim 8, characterized in that, The rising edge suppression unit has a salicide block layer superimposed between the source hole and the gate of the PMOS transistor M11, or between the drain hole and the gate, or simultaneously superimposed between the source hole and the gate and between the drain hole and the gate; wherein, the salicide block layer is a silicide barrier layer.
12. The register hardening circuit design method against single-event upsets according to claim 8, characterized in that, The falling edge suppression unit includes a PMOS transistor M14 and an NMOS transistor M24; the source of the PMOS transistor M14 is connected to the power supply, and the drain of the PMOS transistor M24 is connected to the drain of the NMOS transistor M24, while the source of the NMOS transistor M24 is grounded; the gates of the PMOS transistor M14 and the NMOS transistor M24 are connected to the input terminal of the falling edge suppression unit, and the drains of the PMOS transistor M14 and the NMOS transistor M24 are connected to the output terminal of the falling edge suppression unit; the width-to-length ratio of the PMOS transistor M14 is greater than that of the NMOS transistor M24.
13. The register hardening circuit design method against single-event upsets according to claim 12, characterized in that, The falling edge suppression unit also includes resistor R2, which is the source series resistor R2 of the NMOS transistor M24.
14. A register hardening circuit design method against single-event upsets according to claim 12, characterized in that, The falling edge suppression unit increases the distance between the source and gate of the NMOS device M24, or increases the distance between the drain and gate, or simultaneously increases both the distance between the source and gate and the distance between the drain and gate.
15. A register hardening circuit design method against single-event upsets according to claim 12, characterized in that, The falling edge suppression unit stacks a salicide block layer between the source and gate of the NMOS device M24, or stacks a salicide block layer between the drain and gate, or stacks a salicide block layer between both the source and gate and the drain and gate; wherein, the salicide block layer is a silicide barrier layer.
16. The register hardening circuit design method against single-event upsets according to claim 12, characterized in that, The RC filter unit is implemented by connecting a resistor R and a capacitor C in series.
17. A register hardening circuit design method against single-event upsets according to claim 16, characterized in that, Capacitor C is obtained by connecting one or more of PMOS capacitors, NMOS capacitors, and MOM capacitors in parallel.
18. A register hardening circuit design method against single-event upsets according to claim 17, characterized in that, When capacitor C is obtained by connecting a PMOS capacitor and an NMOS capacitor in parallel, the ratio of the PMOS capacitor to the NMOS capacitor is the ratio corresponding to the minimum fluctuation of the sum of the capacitance values of the PMOS capacitor and the NMOS capacitor with voltage change.
19. A register hardening circuit design method for resisting single-event upsets according to claim 17, characterized in that, The MOM capacitor overlaps spatially with the PMOS capacitor, NMOS capacitor, and resistor R.
20. A register hardening circuit design method against single-event upsets according to claim 17, characterized in that, MOM capacitors can be single-layer metal interdigitated capacitors, or multiple layers of metal interdigitated capacitors directly overlapped and connected in parallel, or multiple layers of metal interdigitated capacitors interleaved and overlapped and connected in parallel.
21. A register hardening circuit design method against single-event upsets according to claim 20, characterized in that, Adjusting the dimensions of the register cell's anti-single-event upset circuitry includes: Adjust the size of the rising edge suppression unit using one or more of the following adjustment methods: Increase the number of rising edge suppression units; In the rising edge suppression unit, reduce the width-to-length ratio of PMOS transistor M11 or increase the width-to-length ratio of NMOS transistor M21; Add a resistor connected in series with the source of PMOS transistor M11 in the rising edge suppression unit; In the rising edge suppression unit, increase the distance between the source and gate of PMOS transistor M11, or increase the distance between the drain and gate, or simultaneously increase both the distance between the source and gate and the distance between the drain and gate. A salicide block layer is added between the source and gate of the PMOS transistor M11 in the rising edge suppression unit, or between the drain and gate, or both between the source and gate and between the drain and gate; wherein, the salicide block layer is a silicide barrier layer. Adjust the size of the falling edge suppression unit using one or more of the following adjustment methods: Increase the number of falling edge suppression units; In the falling edge suppression unit, reduce the width-to-length ratio of NMOS transistor M24 or increase the width-to-length ratio of PMOS transistor M14; Add a resistor connected in series with the source of NMOS transistor M24 in the falling edge suppression unit; In the falling edge suppression unit, increase the distance between the source and gate of the NMOS transistor M24, or increase the distance between the drain and gate, or simultaneously increase both the distance between the source and gate and the distance between the drain and gate. A salicide block layer is added between the source and gate of the NMOS transistor M24 in the falling edge suppression unit, or between the drain and gate, or both between the source and gate and between the drain and gate. The size of the RC filter unit can be adjusted using one or more of the following methods: Increase the resistance R in the RC filter unit; Increase the capacitance C in the RC filter unit.