A method for verifying a parasitic parameter extraction model and a computer readable storage medium

Abstract

The present application relates to a kind of verification methods of parasitic parameter extraction model, comprising: generating multilayer stack test layout data, including the metal layer to be measured and the reference metal layer adjacent to the metal layer to be measured, the metal layer to be measured contains wire array, and the reference metal layer contains continuous metal flat plate;Based on the multilayer stack test layout data, obtain parasitic parameter extraction result data;From parasitic parameter extraction result data, the total parasitic parameter of target line net is extracted, and based on total parasitic parameter and the geometric size of target line net, the unit parasitic parameter of the metal layer to be measured is calculated.Utilize the continuous metal flat plate to form the highly uniform electric field distribution environment for the coverage of wire array.Based on this physical structure characteristics, the total parasitic parameter of line net level in parasitic parameter extraction result data can be accurately equivalent decomposition into unit parasitic parameter reflecting specific process conditions, thereby breaking through the limitation that standard output file can only provide coarse-grained data, meet the data needs of model refinement iteration.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, and in particular to a method for verifying a parasitic parameter extraction model and a computer-readable storage medium. Background Technology

[0002] In the back-end design flow of integrated circuits, parasitic parameter extraction is a key step to ensure that the timing, power consumption and other functions of the chip meet expectations. For digital circuits, the main purpose of parasitic parameter extraction is to accurately calculate the parasitic resistance (R) and capacitance (C) generated by metal interconnects in the input physical layout, and to output an SPEF file with capacitance and resistance information for subsequent post-simulation verification to ensure that the timing, power consumption and other functions of the chip meet expectations.

[0003] However, the existing technology has the following drawbacks: 1. Lack of automation in the overall verification process: The accuracy verification process of parasitic parameter extraction models usually includes test case generation, test case execution and result comparison. Each step requires a lot of manual operation, the repetitive work is heavy, and it is easy to introduce human error.

[0004] 2. Test cases need to be generated manually, resulting in low coverage: Manually generating test cases is time-consuming and limited in number, covering only a limited number of scenarios, resulting in low coverage and insufficient verification of the accuracy of the parasitic parameter extraction model.

[0005] 3. The parasitic parameter data in the SPEF file is only down to the net level, and the data granularity is insufficient: The SPEF file usually only marks the parasitic capacitance and parasitic resistance at the net level. However, in order to further iterate the parasitic parameter extraction model to be verified, the developers usually need more granular data, such as the unit capacitance and sheet resistance values ​​under specific line width and spacing conditions. It is difficult to obtain such information from the SPEF file.

[0006] 4. Lack of systematic reporting of comparison results: Existing methods lack a unified mechanism for generating comparison reports, making it difficult to present the differences in parasitic parameters between mainstream models and models to be validated in an intuitive and comprehensive manner, which is not conducive to model accuracy evaluation and subsequent problem identification. Summary of the Invention

[0007] To address the problems of insufficient data granularity and low verification efficiency in existing parasitic parameter extraction models, this invention provides a verification method for parasitic parameter extraction models, enabling automated extraction and high-precision verification of fine-grained parasitic parameters.

[0008] To address the aforementioned technical problems, this invention provides a verification method for a parasitic parameter extraction model, comprising: generating multi-layer stacked test layout data, wherein the multi-layer stacked test layout data includes a metal layer under test and a reference metal layer adjacent to the metal layer under test, the metal layer under test comprising a wire array, and the reference metal layer comprising a continuous metal plate; obtaining parasitic parameter extraction result data based on the multi-layer stacked test layout data; extracting the total parasitic parameters of a target mesh from the parasitic parameter extraction result data, and calculating the unit parasitic parameter of the metal layer under test based on the total parasitic parameters and the geometric dimensions of the target mesh.

[0009] The above scheme creates a uniform electric field environment by constructing a multi-layer stacked test layout that includes wire arrays and continuous metal plates. This allows the total parasitic parameters at the wire mesh level obtained from the standard extraction results to be equivalently converted into unit parasitic parameters that reflect the essential characteristics of the process. Thus, fine-grained data acquisition is achieved without changing the underlying logic of the extraction tool.

[0010] In one embodiment of the present invention, generating multilayer stacked test layout data includes: traversing a preset process parameter space to generate multiple sets of the multilayer stacked test layout data; wherein, the preset process parameter space includes: metal layer identifier, line width and spacing, the conductors in the conductor array have the line width and the spacing, and the continuous metal plate covers the conductor array in a direction perpendicular to the metal layer under test.

[0011] By traversing the process parameter space to automatically generate test data, the verification scenario fully covers key process dimensions, improving the automation and representativeness of test case generation.

[0012] In one embodiment of the present invention, generating multi-layer stacked test layout data further includes: using the minimum linewidth and minimum spacing corresponding to the preset process parameter space as a reference, traversing the linewidth and spacing according to a preset integer multiple; for each set of parameters obtained by traversal, generating the multi-layer stacked test layout data having a three-layer stacked structure or a two-layer stacked structure; wherein, the three-layer stacked structure includes: a first reference metal layer located above the metal layer under test and a second reference metal layer located below the metal layer under test, the two-layer stacked structure includes a second reference metal layer located below the metal layer under test, and the first reference metal layer and the second reference metal layer are both the continuous metal plate.

[0013] By employing specific multiplier traversal strategies and differentiated stacking structure designs, the testing granularity has been further refined, enabling it to adapt to the verification requirements of different interconnection structures and enhancing the flexibility of the verification scheme.

[0014] In one embodiment of the present invention, extracting the total parasitic parameters of the target mesh from the parasitic parameter extraction result data, and calculating the unit parasitic parameter of the metal layer under test based on the total parasitic parameters and the geometric dimensions of the target mesh, includes: selecting a central conductor in a uniform electric field environment in the conductor array as the target mesh; extracting the total capacitance and total resistance values ​​of the target mesh from the parasitic parameter extraction result data; calculating the unit capacitance value based on the total capacitance value and the geometric length of the target mesh; and calculating the sheet resistance value based on the total resistance value, the linewidth of the target mesh, and the effective length of the target mesh.

[0015] By selecting the central conductor in a uniform electric field environment as the target object, the calculation deviation caused by edge effects is eliminated, ensuring the physical accuracy of the conversion from total parameters to unit parameters.

[0016] In one embodiment of the present invention, calculating the unit capacitance value based on the total capacitance value and the geometric length of the target mesh includes: dividing the total capacitance value by the geometric length to obtain the unit capacitance value; calculating the sheet resistance value based on the total resistance value, the linewidth of the target mesh, and the effective length of the target mesh includes: dividing the product of the total resistance value and the linewidth by the effective length to obtain the sheet resistance value; wherein the effective length is the distance between the two ends of the target mesh.

[0017] This scheme clarifies the effective length correction mechanism that takes into account the port connection characteristics, avoids resistance calculation errors caused by the inconsistency between physical length and electrical length, and improves the accuracy of sheet resistance extraction.

[0018] In one embodiment of the present invention, obtaining parasitic parameter extraction result data based on the multi-layer stacked test layout data includes: converting the multi-layer stacked test layout data into a layout description file and a netlist connection file; inputting the layout description file and the netlist connection file into a parasitic parameter extraction model, driving the parasitic parameter extraction model to perform extraction operations, and outputting the parasitic parameter extraction result data.

[0019] This approach utilizes standardized file formats as an intermediate carrier, decoupling the verification method from specific extraction tools and improving the versatility and compatibility of the verification framework.

[0020] In one embodiment of the present invention, the layout description file and the netlist connection file are input into the parasitic parameter extraction model to drive the parasitic parameter extraction model to perform extraction operations, including: in the presence of multiple sets of the multi-layer stacked test layout data, a parallel scheduling mechanism is adopted to concurrently input multiple sets of the layout description file and the netlist connection file into the parasitic parameter extraction model to drive the parasitic parameter extraction model to concurrently perform the extraction operations.

[0021] This scheme makes full use of computing resources through a parallel scheduling mechanism, significantly shortens the verification cycle of large-scale test case sets, and improves the efficiency of model iteration.

[0022] In one embodiment of the present invention, the method further includes: obtaining a first unit parasitic parameter output by a benchmark parasitic parameter extraction model and a second unit parasitic parameter output by a parasitic parameter extraction model to be verified; calculating a parasitic parameter error index based on the first unit parasitic parameter and the second unit parasitic parameter; and generating a comparative data report containing overall error information and individual error information based on the parasitic parameter error index.

[0023] This solution establishes a systematic error assessment framework, which presents the differences in model accuracy in a visual way through multi-dimensional comparative reports, helping R&D personnel to quickly locate problems.

[0024] In one embodiment of the present invention, the parasitic parameter error index is calculated based on the first unit parasitic parameter and the second unit parasitic parameter, including: for each group of multilayer stacked test layout data, calculating the difference between the second unit parasitic parameter and the first unit parasitic parameter, and dividing the difference by the first unit parasitic parameter to obtain a single error value; calculating the mean error and the standard deviation of the error based on multiple single error values; the comparison data report includes a first report and a second report, the first report recording the first unit parasitic parameter, the second unit parasitic parameter and the single error value corresponding to each group of multilayer stacked test layout data, and the second report recording the mean error and the standard deviation of the error.

[0025] This approach provides a complete error analysis perspective, from micro-level individuals to macro-level statistics, supporting both the identification of specific outliers and the quantitative assessment of the overall stability of the model.

[0026] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the verification method for the parasitic parameter extraction model as described above.

[0027] The verification method for the parasitic parameter extraction model of the present invention has the following advantages compared with the prior art: 1. Automatic test case generation: A three-level nested loop is used to ensure that wiring patterns covering different metal layers, different line widths, and different spacing combinations are automatically generated.

[0028] 2. By constructing special graphic structures, SPEF files can output more granular data: By constructing flat plate structures on the upper and lower layers or only the lower layer of the metal layer under test, and repeatedly constructing straight wires with the same linewidth and spacing on the metal layer under test, the capacitance and resistance values ​​at the net level in the SPEF file are equivalent to the unit capacitance and sheet resistance values ​​under specific linewidth and spacing conditions, thereby achieving more granular capacitance and resistance comparison.

[0029] 3. Achieve full automation of the parasitic parameter extraction model accuracy verification process: Achieve full automation of the process including test case generation, test case execution, and result comparison. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the structure of the test layout data of the present invention, embodiment one; Figure 2 This is a schematic diagram of the structure of the test layout data of the present invention, embodiment two; Figure 3 This is a front view of the test layout data embodiment one of the present invention; Figure 4 This is a front view of the test layout data embodiment two of the present invention; Figure 5 This is a top view of the metal layer under test in this invention; Figure 6 This is a schematic diagram of the target wire network resistor and the top and bottom layer capacitors of the present invention; Figure 7 This is a schematic diagram of the target wire network resistor and sidewall capacitor of the present invention. Detailed Implementation

[0032] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0033] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] It should be noted that the following description covers various aspects of embodiments within the scope of the appended claims. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0035] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0036] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0037] like Figure 1 and Figure 2 As shown, this application provides a verification method for a parasitic parameter extraction model, which achieves equivalent extraction and verification of fine-grained parameters by constructing a specific physical test structure.

[0038] The validation method for this parasitic parameter extraction model mainly includes the following steps: Step S100: Generate multi-layer stacked test layout data. The multi-layer stacked test layout data includes a metal layer 100 under test and a reference metal layer 200 adjacent to the metal layer 100 under test. The metal layer 100 under test contains a wire array, and the reference metal layer 200 contains a continuous metal plate.

[0039] Specifically, the core of this step lies in constructing a physical environment capable of generating a uniform electric field distribution. For example... Figure 1 As shown, the conductor array in the metal layer 100 under test consists of multiple parallel long straight conductors with a preset linewidth L1 and spacing L2. A continuous metal plate in the reference metal layer 200 completely covers the conductor array in a direction perpendicular to the metal layer 100 under test. This coverage is not a simple geometric overlap, but rather designed to create ideal boundary conditions for a parallel plate capacitance model in terms of electrical characteristics. When the area of ​​the continuous metal plate is much larger than the overall area of ​​the conductor array, the electric field divergence effect at the edges of the conductor array can be eliminated, resulting in the conductors located in the central region of the array being in a highly uniform electric field environment. It should be understood that although... Figure 1 and Figure 2 A specific stacking configuration is shown, but in other embodiments, the reference metal layer 200 may be located only below the metal layer 100 under test (e.g., Figure 2 (as shown), or simultaneously located above and below the metal layer 100 under test (as shown). Figure 1 As shown in the figure, it is sufficient to satisfy the condition that the continuous metal plate forms an effective electric field shield or coupling with the wire array.

[0040] Step S200: Based on the multi-layer stacked test layout data, obtain the parasitic parameter extraction result data.

[0041] Specifically, the generated multi-layer stacked test layout data is used as input to drive the parasitic parameter extraction model to be verified to perform extraction operations. Because the test layout data has a regular geometric structure and well-defined electrical connections, the parasitic parameter extraction results output by the extraction model can accurately reflect the electrical response under this specific structure. This step achieves data mapping from the physical layout domain to the electrical parameter domain, and the obtained results contain complete parasitic information of the target net under the current test structure. This application does not limit the specific file format of the acquired data; it can be an industry-standard exchange format or an internal data structure of the tool. The key is that the data can characterize the total parasitic characteristics at the net level.

[0042] Step S300: Extract the total parasitic parameters of the target mesh from the parasitic parameter extraction result data, and calculate the unit parasitic parameters of the metal layer 100 under test based on the total parasitic parameters and the geometric dimensions of the target mesh.

[0043] Specifically, after obtaining the total parasitic parameters at the wire mesh level, the characteristics of the uniform electric field environment constructed in step S100 are used to decompose the total parasitic parameters into parasitic parameters per unit length. For example, for capacitance parameters, since the central conductor is in a uniform electric field, its total capacitance value has a strictly linear relationship with the conductor length. Therefore, the unit capacitance value can be obtained by dividing the total capacitance value by the geometric length. For resistance parameters, the sheet resistance value can also be derived based on the total resistance value and the geometric dimensions of the conductor. The effectiveness of this calculation logic depends entirely on the physical premise provided by the aforementioned specific layout structure. If a uniform field environment formed by continuous metal plates is lacking, edge effects will cause a nonlinear relationship between the total parameters and the length. In this case, simple division will not yield accurate unit parameters. Therefore, this application, through the deep integration of structural design and calculation logic, successfully overcomes the limitation of traditional verification methods that can only obtain coarse-grained data at the wire mesh level, and achieves the technical effect of directly using standard output results to verify fine-grained process parameters without modifying the underlying algorithm of the extraction model.

[0044] Furthermore, generating multi-layer stacked test layout data includes: traversing the preset process parameter space to generate multiple sets of multi-layer stacked test layout data; wherein, the preset process parameter space includes metal layer identifiers, line width L1 and spacing L2, the conductors in the conductor array have line width L1 and spacing L2, and a continuous metal plate covers the conductor array in a direction perpendicular to the metal layer under test.

[0045] Specifically, to comprehensively evaluate the accuracy of the parasitic parameter extraction model under different process conditions, this application employs an automated traversal mechanism to construct the test dataset. The preset process parameter space covers the key geometric dimensions affecting parasitic parameters, namely, metal layer identifiers, linewidths, and spacing. Metal layer identifiers are used to distinguish wiring layers of different heights in chip manufacturing, as the thickness, dielectric constant, and upper and lower layer environments of different metal layers vary; linewidths L1 and spacing L2 directly determine the self-capacitance, mutual capacitance, and resistance values ​​of the conductors. By traversing the combination of these three dimensions, a test case set covering the entire parameter space can be generated, avoiding scenario omissions when manually constructing test cases. More importantly, this step strictly limits the spatial positional relationship between the continuous metal plate and the conductor array, that is, the continuous metal plate must completely cover the conductor array in the direction perpendicular to the metal layer under test. Here, "coverage" does not only refer to the overlap of geometric shapes in the top view, but also means that in three-dimensional space, the projection area of ​​the continuous metal plate should completely contain the projection area of ​​the conductor array, and it is usually required that the edge of the plate extends beyond the edge of the conductor array by a certain distance. This structural design physically creates ideal boundary conditions for a parallel-plate capacitor, effectively shielding the external environment from interference with the electric field inside the wire array and ensuring that the wires in the central region of the array are in a highly uniform electric field environment. Only when this physical premise is met can the subsequent equivalent conversion from the total parameters at the wire mesh level to unit parameters have a theoretical basis. If the coverage is incomplete, edge effects will cause distortion of the electric field distribution, making it impossible for the extracted parameters to accurately characterize the unit characteristics under specific process conditions.

[0046] Furthermore, the preset process parameter space is traversed to generate multiple sets of multi-layer stacked test layout data, including: using the minimum linewidth and minimum spacing corresponding to the preset process parameter space as a benchmark, the linewidth L1 and spacing L2 are traversed according to a preset integer multiple; for each set of parameters obtained by traversal, multi-layer stacked test layout data with a three-layer stacked structure or a two-layer stacked structure is generated; wherein, the three-layer stacked structure includes a first reference metal layer located above the metal layer under test and a second reference metal layer located below the metal layer under test, and the two-layer stacked structure includes a second reference metal layer located below the metal layer under test, and the first reference metal layer and the second reference metal layer are both continuous metal plates.

[0047] Specifically, in terms of traversal strategy, this application preferably uses the minimum linewidth and minimum spacing specified by the process design kit as the reference unit, and performs step-by-step traversal according to preset integer multiples (e.g., 1x, 2x, 3x up to 10x). This approach can efficiently cover typical process windows from the smallest size to the most lenient size. However, it should be understood that the preset integer multiple is only a preferred exemplary implementation. In practical applications, the traversal step size can also adopt non-integer multiples (e.g., 1.5x, 2.5x), geometric sequences (e.g., sequences with a common ratio of 1.2), or even random sampling within the parameter space. The advantage of using non-uniform or random sampling is that it can detect the interpolation accuracy of the model at irregular grid points, preventing the verification results from overfitting to specific integer multiple points. Therefore, any method of sampling the process parameter space based on preset rules or strategies should be considered an equivalent alternative within the scope of protection of this application.

[0048] Regarding the stacking structure type, this application provides two differentiated physical structures for each set of parameter combinations to adapt to different verification requirements. For example... Figure 1 As shown, the three-layer stacked structure presents a sandwich-like layout of "upper plate - middle layer wire array - lower plate". In this structure, the first reference metal layer above the metal layer under test 100 and the second reference metal layer below it are both continuous metal plates. This structure simulates the most typical dense interconnect environment inside a chip, where the wires under test are simultaneously affected by the strong coupling between the upper and lower metal layers, making it suitable for verifying the accuracy of the model in handling complex inter-layer coupling capacitance and total capacitance. Figure 2 As shown, the two-layer stacked structure retains only the second reference metal layer below the metal layer under test 100 as a continuous metal plate, with a dielectric layer or other discontinuous structure above it. This structure is mainly used to simulate the interconnect characteristics under specific shielding scenarios, focusing on verifying the extraction accuracy of the conductor-to-ground capacitance and sidewall capacitance. Regardless of the stacking structure used, the first and second reference metal layers must remain continuous metal plates to ensure a stable potential reference surface and a uniform electric field background for the conductor array under test. By flexibly combining these two stacking structures with the aforementioned parameter traversal strategy, this application constructs a multi-dimensional, high-coverage test layout data generation mechanism, laying a solid data foundation for the refined verification of the parasitic parameter extraction model.

[0049] Furthermore, the total parasitic parameters of the target mesh are extracted from the parasitic parameter extraction results data, and the unit parasitic parameters of the metal layer under test are calculated based on the total parasitic parameters and the geometric dimensions of the target mesh. This includes: selecting the central conductor in a uniform electric field environment in the conductor array as the target mesh; extracting the total capacitance and total resistance values ​​of the target mesh from the parasitic parameter extraction results data; calculating the unit capacitance value based on the total capacitance value and the geometric length of the target mesh; and calculating the sheet resistance value based on the total resistance value, the linewidth of the target mesh, and the effective length of the target mesh.

[0050] Specifically, this step is the core link in achieving precise conversion from macroscopic wire mesh parameters to microscopic process parameters, and its accuracy is highly dependent on the ideality of the physical environment in which the target wire mesh is located. For example... Figure 5 As shown, the wire array consists of multiple parallel wires, with the wires on both sides of the array being edge wires and the wires in the middle region being center wires. In terms of electromagnetic field distribution, the edge wires exhibit significant asymmetry and divergence in their electric field distribution due to their proximity to other wires on one side and their orientation towards open space or a shielding wall on the other. This edge effect causes the parasitic capacitance and resistance characteristics of these wires to deviate from the ideal model of an infinite array. In contrast, the center wire has identical adjacent wire structures on both sides and is uniformly covered by a continuous metal plate in the vertical direction. This highly symmetrical geometric arrangement places it in an extremely uniform electrostatic field environment. Only under this uniform electric field environment do the parasitic parameters of the wires strictly follow the principle of translational symmetry, i.e., the total parasitic parameters exhibit a perfect linear proportional relationship with the wire length. Therefore, selecting the center wire as the target wire mesh is not an arbitrary engineering choice, but rather a necessary physical prerequisite for unit parameter calculation, eliminating the interference of boundary effects on verification accuracy, and ensuring that the extracted unit parameters truly reflect the intrinsic material properties under specific process conditions.

[0051] Furthermore, based on the total capacitance value and the geometric length of the target wire mesh, the unit capacitance value is calculated, including dividing the total capacitance value by the geometric length to obtain the unit capacitance value.

[0052] Specifically, such as Figure 6 As shown, in a three-layer stacked structure, the total capacitance of the central conductor mainly consists of three parts: the top layer capacitance C2 between the central conductor and the upper first reference metal layer, the bottom layer capacitance C1 between the central conductor and the lower second reference metal layer, and the sidewall capacitance C3 between the central conductor and the adjacent conductor in the same layer (e.g., ...). Figure 7 (As shown). Because the central conductor is in a uniform electric field environment, the capacitance components mentioned above are all uniformly distributed along the length of the conductor. Therefore, the total capacitance of the target wire mesh is... Its geometric length They satisfy a strict linear relationship, that is... Based on this physical law, it can be solved by simple division. Directly obtain the capacitance value per unit length .

[0053] Furthermore, based on the total resistance value, the linewidth of the target net, and the effective length of the target net, the sheet resistance value is calculated, including: dividing the product of the total resistance value and the linewidth by the effective length to obtain the sheet resistance value; wherein, the effective length is the distance between the two ends of the target net.

[0054] Specifically, the equivalent calculation of resistance parameters is more complex than that of capacitance, requiring the introduction of the crucial correction factor of "effective length." For example... Figure 5 and Figure 7 As shown, the two ends of the target wire (i.e., the center conductor) are connected to an external test circuit or reference potential via ports. In the physical layout, the geometric length of the conductor usually refers to the end-to-end distance of the metal pattern itself. However, in terms of electrical characteristics, the actual path length of the current is determined by the distance between the center points of the two ports; this distance is defined as the effective length. Due to the presence of contact holes or through-hole structures at the ports, current undergoes three-dimensional diffusion or contraction effects during injection and outflow from the conductors, resulting in uneven current density distribution near the ports. If the geometric length of the conductors is used directly in calculating the sheet resistance instead of the effective length between the ports, the additional resistance contribution or geometric deviation of the port contact area will be ignored, introducing a non-negligible systematic error. Especially at advanced process nodes, as conductor dimensions shrink, the proportion of port contact resistance in the total resistance increases significantly, further amplifying the impact of this deviation in length definition on verification accuracy. Therefore, this application explicitly defines the formula for calculating the sheet resistance as follows: ,in The extracted total resistance value, Let be the linewidth of the target mesh. This formula introduces the effective length. The resistance calculations were precisely corrected to ensure that the sheet resistance value derived from the total resistance at the wire mesh level accurately characterizes the intrinsic conductivity of the metal thin film, eliminating interference from the geometric effects at the test structure ports. This feature reflects the profound understanding of the physical essence in the parametric equivalence calculations of this application and is an indispensable technical means for achieving high-precision model verification.

[0055] Furthermore, based on the multi-layer stacked test layout data, parasitic parameter extraction result data is obtained, including: converting the multi-layer stacked test layout data into a layout description file and a netlist connection file; inputting the layout description file and the netlist connection file into the parasitic parameter extraction model, driving the parasitic parameter extraction model to perform extraction operations, and outputting parasitic parameter extraction result data.

[0056] Specifically, this step transforms the abstract test layout data structure into a standard input format recognizable by the parasitic parameter extraction model. The layout description file carries physical information such as the geometry, dimensions, and hierarchical relationships of the metal layer under test, the reference metal layer, and the conductor array, while the netlist connection file defines the electrical topology connections between conductors, ports, and reference planes. In this application, the layout description file and netlist connection file are functional overarching generalizations and are not limited to specific industry standard formats. For example, the layout description file can use DEF (Design Exchange Format), or GDSII, OASIS, or any other geometric data format that can accurately describe the integrated circuit layout; the netlist connection file can use Verilog netlist format, or SPICE netlist, CDL, or other text or binary formats that can characterize circuit connections. Similarly, the output parasitic parameter extraction results can be SPEF (Standard Parasitic Exchange Format) files, or DSPF, SBPF, or tool-specific parameter storage formats. This higher-level processing of file formats enables the verification method of this application to seamlessly interface with most mainstream and emerging parasitic parameter extraction tools on the market, without the need for customized development for the private interfaces of specific tools, thus significantly improving the universality and scalability of the verification framework. By separating physical layout information and electrical connection information into two independent standardized files for transmission, the integrity and accuracy of data interaction are also ensured, avoiding the risk of verification failure due to parsing errors in a single file format.

[0057] Furthermore, the layout description file and netlist link file are input into the parasitic parameter extraction model to drive the parasitic parameter extraction model to perform extraction operations. This includes: in the case of multiple sets of multi-layer stacked test layout data, a parallel scheduling mechanism is adopted to concurrently input multiple sets of layout description files and netlist link files into the parasitic parameter extraction model to drive the parasitic parameter extraction model to concurrently perform extraction operations.

[0058] Specifically, to cover the entire process parameter space, including metal layers, linewidths, and spacing, hundreds or even thousands of multi-layer stacked test layout data sets are typically generated. If a traditional serial execution mode is used—that is, extracting one set of data before starting the next—the verification cycle will increase linearly with the number of test cases, which is unacceptable given the computational demands of advanced process nodes, often exceeding several days. This application introduces a parallel scheduling mechanism designed to address the technical problem of low efficiency in large-scale test set verification. This mechanism is not a simple loop call to a software interface, but rather based on deep management of computing resources and task-level concurrency control. For example, a task pool can be constructed using multi-process or multi-threading technology, dynamically allocating multiple sets of layout description files and netlist join files to multiple parallel extraction model instances for simultaneous execution, based on the number of CPU cores or cluster node resources of the current computing device. In a specific implementation scenario, the scheduler can monitor the running status of each extraction task, immediately loading new test cases from the waiting queue upon completion of a task, ensuring that computing resources are always in a saturated working state. Furthermore, parallel scheduling can be combined with a distributed computing architecture to distribute test tasks with different parameter combinations to multiple workstations within a local area network for collaborative execution. Through this substantial concurrent acceleration method, the full-parameter space verification task, which originally required tens of hours, can be compressed to be completed in a few hours. This significantly shortens the iterative feedback cycle of the parasitic parameter extraction model, enabling researchers to verify more diverse process scenarios within a limited time, thereby improving the overall efficiency of model development. It should be understood that the specific granularity of parallel scheduling can be at the file level, task level, or even the operator level within the model. As long as concurrent processing of multiple sets of test data can be achieved, it falls within the scope of protection of this application.

[0059] Furthermore, after obtaining the unit parasitic parameter of the metal layer to be tested, the method further includes: obtaining the first unit parasitic parameter output by the benchmark parasitic parameter extraction model and the second unit parasitic parameter output by the parasitic parameter extraction model to be verified; calculating the parasitic parameter error index based on the first unit parasitic parameter and the second unit parasitic parameter; and generating a comparative data report containing overall error information and individual error information based on the parasitic parameter error index (as shown in Table 1).

[0060]

[0061] Table 1 Where R sq 1 represents the sheet resistance value extracted by the mainstream parasitic parameter extraction model, R sq 2 represents the sheet resistance value extracted from the model to be verified, C unit 1 and C unit 2. Similarly.

[0062] Specifically, this step establishes a closed-loop feedback mechanism for the verification results, transforming abstract differences in model accuracy into quantifiable engineering metrics. The benchmark parasitic parameter extraction model typically refers to an industry-recognized gold standard tool validated through numerous tape-outs, or a stable model that has passed acceptance testing in a previous version; its first unit parasitic parameter output is considered the truth reference. The parasitic parameter extraction model to be verified is the object in the current R&D iteration; its second unit parasitic parameter output reflects the current modeling level. By comparing the unit capacitance and sheet resistance of both models under the same multilayer stack test layout data, the degree of fit of the model to be verified to physical effects can be directly evaluated. The generated comparative data report adopts a two-tiered architecture of "overall + individual," providing both a macro-level overview of model quality and retaining the ability to trace anomalies at the micro-level, providing systematic data support for R&D personnel to quickly locate model defects.

[0063] Furthermore, based on the first unit parasitic parameter and the second unit parasitic parameter, the parasitic parameter error index is calculated, including: for each group of multilayer stacked test layout data, the difference between the second unit parasitic parameter and the first unit parasitic parameter is calculated, and the difference is divided by the first unit parasitic parameter to obtain the individual error value; based on multiple individual error values, the error mean and error standard deviation are calculated (as shown in Table 2).

[0064]

[0065] Table 2 Where R sq mean and R sq `dev` represents the mean error and standard deviation of the sheet resistance, respectively. Let `n` represent the number of test cases, then its calculation formula is as follows: ; ; ; C unit mean and C unit The calculation of dev is similar.

[0066] Specifically, the reason for using relative error instead of absolute error is that the numerical range of parasitic parameters is extremely large, potentially differing by several orders of magnitude from the minute capacitance of the bottom metal to the large capacitance of the top metal. Relative error can normalize the contribution of deviations from parameters of different orders of magnitude, making the evaluation results more statistically significant. Based on this, the mean error... This reflects the direction and magnitude of the systematic deviation of the model to be validated relative to the benchmark model. If the mean deviates significantly from zero, it indicates that the model has a global overestimation or underestimation trend, which usually requires adjustment of the basic material parameters or core formula coefficients; error standard deviation. This statistic characterizes the dispersion of the error distribution and reflects the stability of the model under different process angles or geometric combinations. If the standard deviation is too large, even if the mean is close to zero, it means that the model has a risk of local failure in certain specific scenarios. These two statistics together constitute the core dimensions for evaluating the accuracy of the model, and neither can be omitted.

[0067] Furthermore, the comparative data reports include a first report and a second report. The first report records the first unit parasitic parameter, the second unit parasitic parameter, and the individual error value corresponding to each group of multi-layer stacked test layout data. The second report records the mean error and the standard deviation of the error.

[0068] Specifically, the first report serves as an individual detailed table, with each row corresponding to a specific set of multi-layer stacked test layout data. Columns and fields cover process conditions such as metal layer identification, linewidth, and spacing, as well as corresponding baseline values, validation values, and percentage errors. The primary function of this report is to support "point-to-point" problem investigation. When R&D personnel discover anomalies in errors of a specific structure (such as sidewall capacitors under minimum spacing), they can quickly identify all relevant use cases by filtering the first report, and then analyze the differences between the electric field distribution characteristics under that specific physical scenario and the model assumptions. The second report serves as a statistical summary table, summarizing and displaying the mean and standard deviation of errors by process corner or metal layer category. Sometimes, it also includes auxiliary indicators such as maximum error and 95th percentile error. This report is mainly used for "face-to-face" overall evaluation, helping managers determine whether the current model version meets release standards, or to track accuracy convergence trends during multiple iterations. It should be understood that although this application describes the report content in tabular form, in other embodiments, the comparative data report may also include visual charts, such as error distribution histograms, parameter correlation scatter plots, or trend curves of error versus linewidth. These visualization techniques can more intuitively reveal the distribution patterns and potential dynamics of errors, effectively supplementing and replacing numerical reports. Through this multi-dimensional and multi-granular result presentation system, this application achieves efficient transformation from data calculation to engineering decision-making, significantly improving the professionalism and effectiveness of parasitic parameter extraction model verification.

[0069] In addition, this application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements a verification method for the parasitic parameter extraction model as described in any of the above method embodiments.

[0070] Specifically, the computer-readable storage medium is the physical entity carrying the technical solution of this application, enabling the aforementioned verification method to be stored, distributed, and executed in the form of a software product. The specific type of medium is not limited; it can be tangible non-volatile memory, such as read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory, disk storage devices (such as hard disk drives), optical disk storage devices (such as CD-ROMs, DVDs), or solid-state drives (SSDs); it can also be volatile memory, such as random access memory (RAM), which temporarily stores instructions and data during program execution. Regardless of the specific storage technology or processor architecture used, as long as it can implement the technical solution described in this application by executing the stored program, it falls within the protection scope of this application.

[0071] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A method for validating a parasitic parameter extraction model, characterized in that, include: Generate multi-layer stacked test layout data, which includes a metal layer under test and a reference metal layer adjacent to the metal layer under test. The metal layer under test includes a wire array, and the reference metal layer includes a continuous metal plate. Based on the multi-layer stacked test layout data, obtain the parasitic parameter extraction result data; The total parasitic parameters of the target mesh are extracted from the parasitic parameter extraction result data, and the unit parasitic parameters of the metal layer under test are calculated based on the total parasitic parameters and the geometric dimensions of the target mesh.

2. The verification method for the parasitic parameter extraction model according to claim 1, characterized in that, Generate multi-layer stacked test layout data, including: Traverse the preset process parameter space to generate multiple sets of the multi-layer stacked test layout data; The preset process parameter space includes: metal layer identification, line width and spacing, the conductors in the conductor array have the line width and the spacing, and the continuous metal plate covers the conductor array in a direction perpendicular to the metal layer to be tested.

3. The verification method for the parasitic parameter extraction model according to claim 2, characterized in that, Generating multi-layer stacked test layout data also includes: Based on the minimum line width and minimum spacing corresponding to the preset process parameter space, the line width and the spacing are traversed according to a preset integer multiple. For each set of parameters obtained through traversal, generate the multi-layer stacked test layout data with a three-layer stacked structure or a two-layer stacked structure; The three-layer stacked structure includes a first reference metal layer above the metal layer under test and a second reference metal layer below the metal layer under test. The two-layer stacked structure includes a second reference metal layer below the metal layer under test. Both the first reference metal layer and the second reference metal layer are continuous metal plates.

4. The verification method for the parasitic parameter extraction model according to claim 1, characterized in that, Extract the total parasitic parameters of the target mesh from the parasitic parameter extraction result data, and calculate the unit parasitic parameter of the metal layer under test based on the total parasitic parameters and the geometric dimensions of the target mesh, including: The central conductor in the conductor array, which is in a uniform electric field environment, is selected as the target wire mesh. Extract the total capacitance and total resistance of the target wire mesh from the parasitic parameter extraction result data; Calculate the unit capacitance value based on the total capacitance value and the geometric length of the target wire mesh; The sheet resistance value is calculated based on the total resistance value, the linewidth of the target mesh, and the effective length of the target mesh.

5. The verification method for the parasitic parameter extraction model according to claim 4, characterized in that, Based on the total capacitance value and the geometric length of the target wire mesh, the unit capacitance value is calculated, including: Divide the total capacitance value by the geometric length to obtain the unit capacitance value; Based on the total resistance value, the linewidth of the target mesh, and the effective length of the target mesh, the sheet resistance value is calculated, including: The product of the total resistance value and the line width is divided by the effective length to obtain the block resistance value; The effective length is the distance between the two ports of the target wire mesh.

6. The verification method for the parasitic parameter extraction model according to claim 1, characterized in that, Based on the multi-layer stacked test layout data, parasitic parameter extraction result data is obtained, including: The multi-layer stacked test layout data is converted into a layout description file and a netlist connection file; The map description file and the netlist connection file are input into the parasitic parameter extraction model, which drives the parasitic parameter extraction model to perform extraction operations and outputs the parasitic parameter extraction result data.

7. The verification method for the parasitic parameter extraction model according to claim 6, characterized in that, The layout description file and the netlist connection file are input into the parasitic parameter extraction model, driving the parasitic parameter extraction model to perform extraction operations, including: In the presence of multiple sets of the multi-layer stacked test layout data, a parallel scheduling mechanism is adopted to concurrently input multiple sets of the layout description files and the netlist connection files into the parasitic parameter extraction model, so as to drive the parasitic parameter extraction model to concurrently execute the extraction operation.

8. The verification method for the parasitic parameter extraction model according to claim 1, characterized in that, Also includes: Obtain the first unit parasitic parameter output by the baseline parasitic parameter extraction model, and the second unit parasitic parameter output by the parasitic parameter extraction model to be verified; Based on the first unit parasitic parameter and the second unit parasitic parameter, calculate the parasitic parameter error index; Based on the parasitic parameter error index, a comparative data report containing overall error information and individual error information is generated.

9. The verification method for the parasitic parameter extraction model according to claim 8, characterized in that, Based on the first unit parasitic parameter and the second unit parasitic parameter, the parasitic parameter error index is calculated, including: For each set of multi-layer stacked test layout data, the difference between the second unit parasitic parameter and the first unit parasitic parameter is calculated, and the difference is divided by the first unit parasitic parameter to obtain the single error value; Based on multiple individual error values, calculate the mean error and the standard deviation of the error; The comparison data report includes a first report and a second report. The first report records the first unit parasitic parameter, the second unit parasitic parameter, and the individual error value corresponding to each group of multi-layer stacked test layout data. The second report records the mean error and the standard deviation of the error.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the verification method for the parasitic parameter extraction model as described in any one of claims 1-9.

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