Six-layer deterministic reasoning computing system and reasoning boundary hardware anchoring method

Abstract

The present application provides a six-layer deterministic reasoning computing system and method to solve the problems that existing software implemented reasoning systems are difficult to defend against tampering from the operating system, reasoning boundaries are not anchored, and error backtracking is difficult, and belongs to the technical field of reasoning system architecture. The present application realizes difficult tampering anchoring of reasoning boundaries through a six-layer physical isolation structure and axiomatic layer hardware solidification, and is suitable for the field of deterministic computing tasks such as artificial intelligence reasoning acceleration.

Description

Technical Field

[0001] This invention relates to the field of computer system architecture technology, specifically to a six-layer deterministic inference computing system and method with immutable inference boundary anchoring and automatic error backtracking mechanism. Its international patent classification numbers are G06N5 / 04 (inference system), G06N3 / 04 (neural network architecture), G11C15 / 00 (content addressable memory), G11C17 / 00 (read-only memory), G11C11 / 00 (digital memory structure), G06F12 / 08 (cache), G06F15 / 78 (FPGA gate array), and H03K19 / 177 (…).

[0002] Programmable logic.

[0003] Legal Status Statement: The technical solution of this invention is based on a physically isolated six-layer hardware architecture to achieve deterministic reasoning. It is a technical solution and does not involve artificial intelligence algorithm features.

[0004] This invention is examined according to the standards of computer system architecture—the algorithm features of this invention (six-layer inference scheduling, boundary anchoring, hardware-level symbolic query) have a specific technical relationship with the internal hardware structure of computer systems (TCAM, FPGA, CPU instruction scheduling unit), and belong to the technical solutions stipulated in Article 2, Paragraph 2 of the Patent Law.

[0005] Explanation of the superordinate concept: In this invention, the "hardware-level content-addressable memory structure" of the L1 symbol layer is a superordinate concept, which covers any hardware structure that can complete the parallel comparison of input data and storage entries in a single search cycle, including but not limited to any one of ternary content-addressable memory (TCAM), binary content-addressable memory (BCAM), associative memory, and hash matching circuit.

[0006] The "hardware reconfigurable logic structure" of the L2 formula layer is a higher-level concept that covers any hardware structure that can change the configuration of logic functions at runtime, including but not limited to any one of FPGA, complex programmable logic device (CPLD), reconfigurable computing array, and configurable logic block array.

[0007] The "hardware immutable rule storage unit" of the L3 axiom layer is a higher-level concept that covers any physical storage structure whose stored content cannot be modified by software instructions after manufacturing, including but not limited to any one of polysilicon fuse arrays, metal fuse arrays, antifuse arrays, mask read-only memory (mask ROM), and one-time programmable non-volatile memory (OTP NVM).

[0008] An efficient TCAM simulation method (doi:10.1109 / tvlsi.2019.2903980) demonstrates the feasibility of TCAM on FPGA. The L2 formula layer of this invention uses FPGA as the hardware carrier, and follows the same FPGA technology path as this work.

[0009] Pedro Reviriego et al. (2019) proposed a partial reconfiguration method based on Xilinx FPGA in IEEE Transactions on Very Large Scale Integration Systems.

[0010] The ultra-dense 2FeFET TCAM design of the type [1] provides a hardware basis for parallel symbol matching. The L1 symbol layer of this invention uses a TCAM array to realize parallel symbol matching, which has the same hardware basis as this work.

[0011] Ternary content-addressable memory (TCAM) is a typical implementation of logic-memory fusion. Xunzhao Yin et al. (2019) proposed a multi-domain FeFET-based model in IEEE Transactions on Circuits and Systems II. Background Technology

[0012] Corey Lammie et al. (2019) proposed a deep FPGA inference engine for edge computing in IEEE Access [2], demonstrating the advantages of FPGA in low-power inference scenarios. The error correction state machine of the L4 metacognitive layer of this invention adopts a similar technical path, through FPGA inference consistency verification and backtracking signal generation.

[0013] Existing inference computing systems are mainly divided into three categories: first, software inference engines based on general-purpose processors (such as causal inference systems based on graph computing frameworks); second, rule matching engines based on dedicated hardware (such as the rule matching engine based on content-addressable memory disclosed in US 10,824,938 B2); and third, reconfigurable inference accelerators based on FPGAs (such as the reconfigurable inference architecture disclosed in CN111667056A that "pursues flexibility," which belongs to a different technical route from the "immutable" design concept of this invention).

[0014] Furthermore, rule matching structures based on content-addressable memory (such as US 10,824,938 B2) are only applicable to single-layer structures of static rule matching, do not involve multi-level inference architectures, do not include immutable axiom storage layers and inference boundary control mechanisms, and do not include error detection and backtracking mechanisms.

[0015] The drawback of the former is that the inference boundary is entirely defined by software and can be tampered with by malicious code or program errors; error correction relies on the operating system's interrupt handling and software backtracking, resulting in high latency, typically reaching the millisecond level.

[0016] The latter's drawbacks are: it is a single-layer content-addressable memory matching structure, which is only applicable to static rule matching and does not involve multi-layer inference architecture; it does not include an immutable axiom storage layer and inference boundary control mechanism; and it does not include error detection and backtracking mechanism.

[0017] Furthermore, while FPGA-based reconfigurable inference accelerators (such as CN111667056A) offer flexible hardware reconfigurability, their core design philosophy is "reconfigurability"—rules can be updated online. This design direction of "pursuing flexibility" is exactly the opposite of the "immutable" design philosophy of this invention, and the two belong to different technical routes.

[0018] Furthermore, Chinese patent CN116028418B (National University of Defense Technology, authorized on June 20, 2023) discloses a scalable multi-core intelligent processor, accelerator card, and computer based on GPDSP, which achieves inference acceleration for intelligent computing through multi-level interconnection of multiple GPDSP chips. This solution belongs to a general-purpose multi-core processor extension architecture, whose inference capability relies on the instruction execution of the CPU / DSP core. It does not involve a six-layer isolation structure of the physical layer, does not include an axiom layer that cannot be modified after manufacturing, and has no hardware-level layer-by-layer backtracking correction mechanism. This invention uses a six-layer hardware isolation structure of direct physical layer calculation - addressable matching of symbol layer content - FPGA derivation of formula layer - immutable storage of axiom layer to achieve inference boundary anchoring, which is fundamentally different from general-purpose multi-core inference processors in terms of architecture and design concept.

[0019] Furthermore, existing technologies lack a solution that connects "physical layer direct computation," "symbolic layer content-addressable memory matching," and "formula layer FPGA derivation" into a complete inference chain via hardware signal links. Specifically: research in the field of physical computation (such as optical computation and surface acoustic wave computation) focuses on solving single physical problems and does not involve symbolic reasoning; research on hardware inference engines (such as content-addressable memory rule matchers) focuses on symbolic matching in the digital domain and does not involve direct input in the physical domain.

[0020] There is a lack of a unified hardware architecture to bridge the physical domain computation results and the symbolic domain inference process.

[0021] This invention, through a hierarchical design of a physical layer interface, a reflection cache layer (caching the results of physical layer calculations), and a symbolic layer (performing symbolic matching of the results of physical layers), achieves for the first time a complete hardware link from direct input of physical fields to symbolic inference output. Summary of the Invention

[0022] Purpose of the invention

[0023] The technical problem to be solved by this invention is that existing inference computing systems lack immutable inference boundary control mechanisms and automatic error backtracking capabilities. Inference boundaries can be tampered with by software, error correction has high latency, and they cannot work in conjunction with the physical computing layer.

[0024] Technical solution

[0025] This invention provides a six-layer deterministic reasoning computation system and method.

[0026] Its core inventive concept is as follows: the reasoning system is divided into six hardware layers, each with an independent carrier and inter-layer signal links; the axiomatic layer uses a one-time programmable storage array to fix the reasoning boundary parameters, which cannot be rewritten by software; the reflection cache layer completes the retrieval before the physical layer calculation, and skips the physical mapping calculation directly when the cache hits; the metacognitive layer realizes the error backtracking of pure signal links through monitoring circuits and error correction state machines.

[0027] The system includes:

[0028] Physical layer interface: Used to access the physical field response structure and receive its output measurable physical field features, converting the measurable features into digital signals. This interface enables the inference system to directly utilize the nanosecond-level deterministic computation results output by the physical field response structure.

[0029] The reflection cache layer, composed of non-volatile caches, stores input-output mapping pairs for high-frequency inference paths. Its retrieval operation is completed before the physical layer interface performs physical mapping calculations—the cache label is the raw encoding of the input question instance (a digital representation without physical mapping processing). If a cache hit occurs, the cached result is output directly, skipping the physical layer's physical mapping calculation process. This timing design ensures that physical mapping calculations are not performed when a cache hit occurs, thus further reducing latency.

[0030] Symbol layer: Contains a content-addressable storage structure for storing symbolic knowledge entries and outputs the addresses of matching symbol entries within a search cycle through parallel comparison operations.

[0031] Formula layer: Contains a reconfigurable logical structure, used to configure logical operation paths based on the symbol combinations output by the symbol layer, and to execute the logical combination and derivation of symbols.

[0032] Axiom Layer: Contains immutable rule storage units to store inference boundary parameters and fundamental axioms that are physically fixed and cannot be modified by software instructions. Inference boundary values ​​are written once during manufacturing using physical means (fuse programming or mask definition) and cannot be modified by any software instructions after manufacturing.

[0033] Metacognitive layer: Includes monitoring circuits and error correction state machines, used to detect the consistency of inference output. When a reasoning contradiction is detected, the axiom re-verification and path reset operations are triggered layer by layer along the hardware signal path from the axiom layer to the formula layer to the symbol layer.

[0034] The key signal links between layers include:

[0035] Axiom layer → Symbol layer boundary verification link: The axiom layer continuously outputs inference boundary control signals to the symbol layer. Before each search, the symbol layer verifies the boundary using a comparator, and if the boundary is exceeded, the search is blocked.

[0036] Metacognitive Layer → Axiom Layer → Formula Layer → Symbol Layer Backtracking Link: When the metacognitive layer detects a reasoning contradiction, it sends backtracking signals to the axiom layer, formula layer, and symbol layer respectively through three independent signal lines.

[0037] Beneficial effects

[0038] (1) The inference boundary is immutable: The axiomatic layer one-time programmable memory array is irreversible after manufacturing. No software instruction (including operating system kernel instructions) can modify the inference boundary parameters, which fundamentally eliminates the risk of malicious tampering with the inference boundary. This is in stark contrast to FPGA-based reconfigurable schemes, which pursue "reconfigurability", while this invention achieves secure anchoring through "immutability".

[0039] (2) Extremely low error backtracking delay: The backtracking signals from the metacognitive layer to the axiomatic layer to the formula layer to the symbol layer are transmitted through independent signal lines without operating system interrupt processing. The backtracking delay is approximately 5 nanoseconds (including 50ps for metacognitive layer detection, 0.8ns for physical field response propagation, and approximately 4ns for signal transmission and logic gate delays at each layer, based on 65nm CMOS process logic simulation). The typical logic gate delay of 65nm CMOS process is 10-20ps, and the interconnect transmission delay is approximately 50-100ps / mm; the backtracking delay of software solutions is usually greater than 1 millisecond.

[0040] (3) Six-layer collaboration: The physical layer interface enables the inference system to directly utilize the nanosecond-level deterministic calculation results output by the physical field response structure; the reflection cache layer can skip the physical calculation process by cache hits on high-frequency paths, further reducing latency; the boundary values ​​of the one-time programmable storage array in the axiom layer are verified by the comparator before each search in the symbol layer, forming a complete "perception-caching-matching-derivation-anchoring-monitoring" closed loop.

[0041] Compared with existing technologies, the distinguishing feature of this invention is that it adopts a physically isolated six-layer deterministic reasoning architecture. The axiomatic layer anchors the reasoning boundary with immutable hardware rule storage units that cannot be modified by software instructions after manufacturing. Furthermore, the metacognitive layer, through hardware monitoring circuits and an error-correcting state machine, backtracks layer by layer from the axiomatic layer to the formula layer and then to the symbol layer to correct contradictions. This distinguishing feature is not a conventional approach in the field: existing reasoning systems are mostly software-layer architectures, where the reasoning boundary can be tampered with by software, and error correction relies on software logs. Existing technologies do not provide technical guidance on anchoring the reasoning boundary with immutable hardware rules and performing layer-by-layer hardware backtracking. Those skilled in the art also have no motivation to combine six layers of physical isolation with immutable axiomatic storage to ensure reasoning determinism. This distinguishing feature makes the reasoning boundary immutable at the physical layer and enables automatic hardware-level backtracking for error correction, achieving significant technical effects.

[0042] Furthermore, this invention differs from the reconfigurable inference accelerator disclosed in CN111667056A: the core design concept of that prior art is reconfigurability, meaning that the inference rules can be updated online through field-programmable configuration, and its inference boundary changes dynamically with configuration changes, lacking physical anchoring of the inference boundary; this invention anchors the axiom layer with hardware immutable rule storage units (such as fuses, OTPs) that cannot be modified by software instructions after manufacturing. The inference boundary is physically fixed once manufactured and cannot be rewritten by any software means. The two have opposite technical approaches—the former pursues flexibility and allows online rule updates, while the latter pursues determinism and uses physical immutability to ensure that the inference boundary cannot be tampered with. In addition, this invention uses hardware monitoring circuits and error correction state machines in the metacognitive layer to backtrack and correct contradictions layer by layer along the axiom layer, formula layer, and symbol layer. The hardware backtracking delay is in the nanosecond range, while software backtracking correction usually requires milliseconds. The combination of anchoring the inference boundary with immutable axioms and hardware-based layer-by-layer backtracking correction is not disclosed in CN111667056A or existing reconfigurable inference architectures. Therefore, this invention is not obvious to those skilled in the art and has outstanding substantive features and significant progress.

[0043] Based on the aforementioned distinguishing technical features, the actual technical problem solved by this invention is: how to make the reasoning boundary immutable at the physical layer and achieve fast error backtracking at the hardware level, avoiding the defects of software-level reasoning boundaries being tamperable and high backtracking latency. By anchoring the axiom layer with a hardware immutable rule storage unit that cannot be modified by software instructions after manufacturing, and by implementing layer-by-layer backtracking correction with a metacognitive layer hardware monitoring circuit and an error correction state machine, this invention solidifies both the anchoring of the reasoning boundary and error backtracking in hardware.

[0044] Furthermore, although One-Time Programmable Storage (OTP / Fuse) and Content Addressable Storage (TCAM) are mature in the fields of hardware security and network packet classification, those skilled in the art lack inspiration for combining them for anchoring deterministic reasoning boundaries: OTP secure storage (such as hardware root of trust, secure boot) stores keys and firmware digests, and TCAM rule engines (such as network packet classification) match fixed-width packet fields. Neither involves the use of a reasoning architecture that "anchors reasoning boundaries with immutable axioms + backtracks reasoning errors layer by layer in hardware"; combining the immutability of OTP with the parallel matching of TCAM into the axiom layer and symbol layer of the reasoning system requires redefining the storage semantics of reasoning boundaries and the cross-layer verification signal chain, and this combination does not offer any technical inspiration in the field of reasoning architecture. Attached Figure Description

[0045] Figure 1 This is an overall architecture diagram of a six-layer deterministic reasoning computing system, showing the data flow between the six layers.

[0046] Figure 2 This is a structural diagram of a symbol-level content-addressable memory array.

[0047] Figure 3 This is a reconfigurable logic structure diagram of the FPGA at the formula layer.

[0048] Figure 4 This is a structural diagram of an axiomatic layer one-time programmable memory array.

[0049] Figure 5 This is the state transition diagram of the metacognitive layer monitoring and error correction state machine.

[0050] Figure 6 It is a signal link diagram for inference boundary verification from the axiomatic layer to the symbolic layer.

[0051] Figure 7 This is the overall flowchart of the method.

[0052] Figure 1 This is a block diagram of the overall architecture of the six-layer deterministic reasoning computation system of the present invention. It shows a vertically stacked structure of six layers (physical layer interface 100, reflection buffer layer 200, symbol layer 300, formula layer 400, axiom layer 500, and metacognitive layer 600). Arrows indicate the connections between the layers via the physical bus 700. The boundary verification signal link between the axiom layer and the symbol layer, and the backtracking signal link 603 between the metacognitive layer and the axiom layer, the formula layer, and the symbol layer are specifically shown.

[0053] Figure 2This is a structural diagram of the symbol layer content-addressable memory array in Embodiment 1. It shows the connection relationship of the search line drive circuit 302, the content-addressable memory cell array 301 (multi-row, multi-column), the matching line control circuit 303, and the priority encoder 304, and shows the data flow (search word → matching vector → matching address).

[0054] Figure 3 This is a reconfigurable logic structure diagram of the formula layer FPGA in Embodiment 1. It shows the layout of the configurable logic block array, lookup table 403, configuration memory 402, and internal interconnect resources, and illustrates the configuration data flow.

[0055] Figure 4 This is a structural diagram of the one-time programmable memory array in the axiomatic layer of Embodiment 1. It shows the connection relationship of multiple memory cells (each containing a polysilicon fuse resistor and a switching transistor), programming / curing interface 502, readout circuit 503, and boundary register 504, with different colors / symbols distinguishing between the fuse-out (logic "0") and non-fuse-out (logic "1") states.

[0056] Figure 5 This is a state transition diagram for the metacognitive layer monitoring and error correction state machine. It shows each state (idle → monitoring → contradiction detection → backtracking trigger → verification complete → return to idle) and the state transition conditions.

[0057] Figure 6 This is a signal link diagram for the axiomatic layer → symbolic layer inference boundary verification. It shows the signal flow from the output of the immutable rule storage unit 501 → boundary register 504 → comparator → search blocking logic, and how the blocking signal cuts off the search line drive.

[0058] Figure 7 This is the overall flowchart of the method of the present invention. The flowchart shows six steps: physical mapping step → cache check step (decision box: hit / miss) → symbol matching step (including boundary check judgment box) → formula derivation step → boundary anchoring step → monitoring and backtracking step. The steps are connected by arrows, showing the bypass path of "skipping the physical layer". Detailed Implementation

[0059] This embodiment further combines Figure 4 The hardware anchoring verification process shown is as follows: Figure 5 The abnormal rollback mechanism shown enables deterministic reasoning and works in conjunction with the device described in claim 1.

[0060] This implementation example Figure 1 As shown, by Figure 2 The hardware anchor shown is provided by... Figure 3 The state transition shown is implemented.

[0061] (This embodiment corresponds to the device described in claim 1. As shown in the overall architecture in Figure 1, the device is anchored by the hardware shown in Figure 2 and the state transition shown in Figure 3 is implemented.)

[0062] (This embodiment corresponds to the device described in claim 1 and the method described in claim 2).

[0063] Preferably, the immutable hardware rule storage unit adopts a polysilicon fuse array, and the resistance can reach millions of ohms after melting. Preferably, the error correction state machine of the L4 meta-cognitive layer triggers axiom backtracking layer by layer along the L3→L2→L1 hardware signal path.

[0064] Figure 5 further illustrates the hardware implementation of TCAM as a symbol layer matching circuit in a six-layer architecture. The single matching delay is 50ns, and the matching result is directly transmitted to the formula layer through hardware connections without software intervention, demonstrating the synergy between hardware matching in the symbol layer and formula derivation in the formula layer in the six-layer architecture.

[0065] Figure 6 further illustrates the timing synchronization and asynchronous control of the six-layer architecture: the physical layer interface operates synchronously according to the FPGA trigger timing; the reflection buffer layer synchronizes hits according to the query timing; the symbol layer (TCAM) synchronizes the single match period (50ns); the formula layer (FPGA) synchronizes formula derivation; and the axiomatic layer...

[0066] (OTP) One-time synchronous programming, metacognitive layer asynchronously detects backtracking signals according to the reasoning steps, the timing synchronization of the entire six-layer architecture is guaranteed by the FPGA trigger timing accuracy of ±10ns, and asynchronous detection is guaranteed by 3 independent signal lines, reflecting the hardware implementation of timing synchronization and asynchronous control.

[0067] Figure 5 further illustrates the interface call protocol of the six-layer architecture: the physical layer interface provides raw data stream interface calls upwards; the reflection buffer layer completes the call hit query through preset tag matching; the symbol layer (TCAM) receives the interface calls from the reflection buffer layer and matches the rules; the formula layer (FPGA) receives the interface calls from the symbol layer and performs formula derivation; the axiomatic layer...

[0068] (OTP) solidifies inference boundary parameters through fuses / masks. The metacognitive layer receives interface calls from each layer and sends backtracking signals through three independent signal lines. Interface calls between layers are directly coupled through hardware signal links, without going through the software protocol stack, achieving zero latency in the interface call protocol.

[0069] Figure 6 further illustrates the specific hardware structure of the boundary verification link from the axiom layer to the symbol layer. The one-time programmable memory array (fuse / mask) of the axiom layer and the TCAM of the symbol layer continuously verify the inference boundary parameters through a hardware comparator. Boundary protection is guaranteed by the physical layer hardware link, which cannot be rewritten by software and cannot be tampered with at the physical level after manufacturing, reflecting the immutable inference boundary of the 6-layer architecture.

[0070] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention.

[0071] Example 1: A six-layer inference system based on content-addressable memory, FPGA, and polysilicon fuse

[0072] This embodiment uses content-addressable memory to implement the symbol layer, FPGA to implement the formula layer, and polysilicon fuse array to implement the axiom layer, thus constructing a complete six-layer inference system.

[0073] (I) Physical Layer Interface and Physical Field Response Structure

[0074] The physical layer interface connects to the physical field response structure. The physical field response structure can be a multilayer diffractive optical element or a surface acoustic wave delay line array.

[0075] Physical field response structure implementation example—transfer function mapping based on multilayer diffractive optical elements

[0076] Taking the second-order ordinary differential operator L = d² / dx² + p(x)·d / dx + q(x) as an example, the distribution of the operator coefficients p(x) and q(x) in the spatial domain is mapped to the phase modulation functions of each layer of a multilayer diffractive optical element. Specifically: the scribe line density distribution n1(x) of the first layer of the diffractive optical element is proportional to p(x); the scribe line density distribution n2(x) of the second layer of the diffractive optical element is proportional to q(x); and the scribe line depth distribution d(x) of the third layer of the diffractive optical element is proportional to the constant coefficient term.

[0077] The theoretical diffraction efficiency of multilayer diffractive optical elements can reach over 96% in the visible light band. The phase modulation depth is from π to 2π radians.

[0078] When the input problem instance (such as boundary conditions) is incident on the multilayer diffractive optical element structure in the form of a plane wave, the intensity distribution I(x,y) of the outgoing light field is the spatial representation of the solution to the differential equation under the given boundary conditions. After the charge-coupled device array captures this intensity distribution, the feature extraction circuit extracts the peak position coordinates (corresponding to the eigenvalues ​​of the solution) and the intensity ratio (corresponding to the amplitude ratio of the solution). The entire physical mapping process is completed within the light propagation time and does not involve any command flow control.

[0079] The key parameters of the above-mentioned diffractive optical element structure are: 3 to 5 layers, a scribe period of 200 nm to 2 μm for each layer, a scribe depth of 50 nm to 500 nm, and a working wavelength in the visible light band of 400 nm to 700 nm. The alignment accuracy between each layer is better than one-tenth of the wavelength.

[0080] Alternative Implementation of Physical Field Response Structure—Transfer Function Mapping Based on Surface Acoustic Wave Delay Linear Array

[0081] As another way to realize the physical field response structure, a surface acoustic wave delay line array is used. This array consists of two interdigital transducers fabricated on a piezoelectric substrate (such as ST-cut quartz or lithium niobate). The input electrical signal is converted into a surface acoustic wave by the transmitting interdigital transducer, and the surface acoustic wave propagates along the surface of the piezoelectric substrate to the receiving interdigital transducer, where it is converted back into an electrical signal.

[0082] The transfer function of the operator to be solved is pre-fixed by designing the geometric parameters of the interdigital transducer—the number of finger pairs, the width of the finger strips, and the spacing between the finger strips determine the center frequency and frequency response characteristics of the device.

[0083] The center operating frequency range is 74MHz to 3GHz (see D. Morgan, "Surface Acoustic WaveFilters", Elsevier, 2007, Chapter 3: Typical IDT Center Frequency Range 10MHz-10GHz), with a 3dB bandwidth of up to 1.8MHz and insertion loss controllable at 3dB.

[0084] SAW filter insertion loss is typically 1-30 dB, which is strongly dependent on the matching network design (Hashimoto Ed., "Surface Acoustic Wave Devices in Telecommunications", Springer, 2000, Chapter 6).

[0085] The input problem instance (such as a time-domain excitation signal) is converted into a surface acoustic wave by a transmitting interdigital transducer. The amplitude attenuation and phase delay of the surface acoustic wave during propagation carry the calculation results of the transfer function. The electrical signal output by the receiving interdigital transducer is used by a feature extraction circuit to extract the pulse arrival time and amplitude ratio as a measurable physical feature.

[0086] Physical layer interface circuit

[0087] The physical layer interface includes an analog-to-digital converter (ADC): which converts the analog physical field signals output by the physical field response structure (such as charge-coupled device image signals and surface acoustic wave echo signals) into digital signals. The ADC has a sampling accuracy of no less than 12 bits and a sampling rate of no less than 100 MSPS.

[0088] 12-bit 100MSPS ADCs are the mainstream commercial standard, such as ADI AD9628 (12-bit 125MSPS) and TIADS5400 (12-bit 100MSPS). See Analog Devices, "AD9628 Datasheet", 2017; Texas Instruments, "ADS5400 Datasheet", 2012.

[0089] Feature extraction circuit: Extracts measurable physical features from digital signals—peak position coordinates (optical diffraction scheme), pulse arrival time (surface acoustic wave scheme), or intensity ratio. The extracted feature data is stored digitally in the physical layer output buffer register (64-bit wide) and transmitted to the reflection buffer layer via the physical bus.

[0090] (II) Reflection Cache Layer – Timing-Critical Design

[0091] It should be noted that the reflection cache layer in this embodiment is the intermediate layer reflection cache module described in claim 5: an intermediate layer located between the physical layer interface and the symbol layer, composed of magnetoresistive random access memory (MRAM) or ferroelectric random access memory (FRAM), used to store input-output mapping pairs of high-frequency inference paths, and to keep the cached data from being lost after the system is powered off.

[0092] It should be noted that the intermediate layer module described in claim 1 is the reflection cache layer in this specification, and also the intermediate layer reflection cache module described in claim 5: the three refer to the same hardware layer, located between the physical layer interface and the symbol layer, used to store the input-output mapping pairs of high-frequency inference paths and directly output the results when a hit occurs.

[0093] The reflection cache layer is implemented using a non-volatile cache composed of magnetoresistive random access memory. The cache capacity is 1MB, divided into a tag array (256 bits × 16384 entries, 14-bit index) and a data array (128 bits × 16384 entries, 14-bit index). A direct mapping method is used (tags + data total 768KB, with the remaining 256KB reserved for path frequency histogram statistics / audit pointer temporary storage / dynamic expansion area for future inference paths). Tag matching is completed within one clock cycle using a hardware parallel comparator.

[0094] In an alternative implementation, the reflective cache layer can also be implemented using ferroelectric random access memory (FRAM), which uses the polarization state of ferroelectric materials (such as lead zirconate titanate PZT) to store data. It also has the non-volatile characteristic that the data is not lost after power failure. Its read and write timing is compatible with the above-mentioned MRAM implementation and is suitable for high-frequency inference path caching scenarios that are sensitive to write latency.

[0095] Key timing design: The retrieval operation of the reflection cache layer is completed before the physical layer interface performs physical mapping calculations. Specifically, when an input problem instance arrives at the system, its raw encoding (the digital representation without physical mapping processing) is first sent to the reflection cache layer—the corresponding cache entry is read using the hash value (14 bits) of the input encoding as an index, and the input encoding is compared with the label. If they are equal, a hit occurs, the multiplexer directly outputs the cached data to the symbol layer, and simultaneously sends a bypass signal to the physical layer interface to prevent the physical layer's physical mapping calculations from being executed.

[0096] If a match is not found, the input is passed to the physical layer interface to perform physical mapping calculations.

[0097] This timing design ensures that inference requests that hit the cache completely skip the physical mapping calculation process at the physical layer, thereby achieving a further reduction in latency from nanoseconds (physical mapping) to sub-nanoseconds (cache read).

[0098] (iii) Symbol layer – Parallel matching of content-addressable memory

[0099] The symbol layer uses a ternary content-addressable memory array to implement content-addressable storage.

[0100] The content-addressable memory (CDMA) array has a specification of 1024 rows × 256 bits. Each row stores a symbolic knowledge entry—the first 64 bits are the symbol identifier, and the last 192 bits are the symbol content encoding (such as knowledge graph entity IDs, logical predicate encodings, etc.). Using a 65nm CMOS process, the CDMA's matched-line discharge latency can reach 380ps, supporting clock frequencies higher than 1GHz. Current commercial TCAM compilers offer a performance improvement of >50%.

[0101] The search line driver circuit converts the symbol encoding to be matched into differential search line signals, simultaneously driving all rows to perform matching. Each content-addressable memory cell completes the comparison between the stored bit and the search bit within a single clock cycle (supporting 0, 1, and wildcard states). The match line control circuit completes parallel comparisons across the entire array within a single clock cycle, outputting a 1024-bit match vector. The priority encoder extracts the address (10 bits) of the highest priority matching row from the match vector.

[0102] Before performing each search operation, the symbol layer first receives the inference boundary control signal (32 bits) output by the axiomatic layer. The comparator compares the current search range (determined by the input symbol encoding) with the boundary value—if the search range exceeds the boundary, the search blocking logic directly cuts off the search line drive signal of the content-addressable memory, the search operation is blocked, and no matching output is produced.

[0103] (iv) Formula layer – FPGA reconfigurable logic

[0104] The formula layer employs a multiplexed reconfigurable logic structure based on a lookup table array (typically implemented using an FPGA). This multiplexed reconfigurable logic structure is pre-configured with multiple lookup table paths during manufacturing, and during runtime, a multiplexer switches between the pre-configured logic paths within tens of nanoseconds—different symbol combinations correspond to different lookup table configurations and logic operation paths.

[0105] The configuration bitstream of the multiplexed reconfigurable logic structure is stored in the configuration memory. When the symbol layer output changes, the pre-configured logic path is switched within tens of nanoseconds via an on-chip multiplexer (avoiding the millisecond-level latency required for overall FPGA reconfiguration). The logic cell array of the multiplexed reconfigurable logic structure contains multiple configurable logic blocks, each containing a lookup table, flip-flops, and multiplexers, which can implement arbitrary combinational and sequential logic according to the configuration.

[0106] (v) Axiom Layer – Immutable Storage of Polycrystalline Silicon Fuse

[0107] The axiom layer uses a polysilicon filament array to realize immutable regular storage cells.

[0108] Polysilicon fuses are manufactured in an unfused, conductive state (logic "1"), with a resistance of 100Ω to 3.5kΩ before melting. By applying a programming voltage exceeding a preset threshold (5V to 10V, pulse width 100μs to 1ms), the polysilicon material in the selected fuse melts and breaks due to the Joule heating effect, forming a permanently disconnected state (logic "0"). After melting, the resistance can reach millions of ohms. The melting operation is irreversible—once the fuse burns out, it cannot be restored to a conductive state by any electrical signal.

[0109] Typical programming parameters for a polysilicon fuse: programming voltage 5-10V, programming pulse width 100μs-10ms, resistance before programming 50Ω-5kΩ, resistance after programming >1MΩ (see SH Kulkarni et al., "PolysiliconFuses for OTP Memory Applications", 2011);

[0110] A. Kalnitsky et al., "Poly Fuse Implementation in Standard CMOSProcess", 2002).

[0111] Inference boundary parameters (such as the upper limit of the symbol search space, the upper limit of the number of allowed logical paths, and the upper limit of the inference step depth) are written once during system manufacturing via fuse programming. After programming is completed, the programming voltage source is physically disconnected, and the fuse array enters a read-only state.

[0112] The readout circuit detects the current on / off state by applying a low-amplitude read voltage (insufficient to trigger a blowout) to the fuse—"1" indicates current is present (not blown) and "0" indicates no current is present (blown). The readout boundary values ​​are continuously output to the comparator in the symbol layer.

[0113] (vi) Metacognitive layer – monitoring and error correction retrospection

[0114] The metacognitive layer includes monitoring circuits and error correction state machines.

[0115] The monitoring circuit performs a consistency check on two consecutive outputs from the formula layer:

[0116] For numerical outputs (such as probability values ​​of inference conclusions and confidence scores): when the absolute value of the difference between two outputs exceeds a preset threshold T (T ranges from 5% to 20% of the full scale and is stored in the axiom layer boundary register), it is judged as a contradiction;

[0117] For discrete outputs (such as category labels, logical proposition truth values): when two outputs are different, it is determined to be a contradiction;

[0118] For conflict detection with the basic axioms of the axiom layer: the monitoring circuit performs a hardware-level XOR comparison between the output of the formula layer and the logical axioms (such as the laws of uniformity and contradiction) stored in the axiom layer. When the logical value of the output conclusion is opposite to the logical value required by the axiom, it is determined to be a conflict.

[0119] After the error correction state machine is triggered, it is executed through three independent signal lines (without passing through the main data bus):

[0120] Sending an axiom re-verification signal to the axiom layer: The axiom layer rereads the axiom values ​​in the fuse array to confirm that the axioms have not been tampered with;

[0121] Send a logic path reconfiguration signal to the formula layer: The formula layer clears the current logic path configuration and reconstructs the logic path based on the symbol combination re-output by the symbol layer;

[0122] Send a re-search signal to the symbol layer: The symbol layer re-executes symbol matching under the control of the axiom layer boundary signal.

[0123] The transmission of the above signals is accomplished through signal lines independent of the main data bus, with a transmission delay of less than 1 nanosecond. The entire backtracking process does not involve operating system interrupt handling or the software stack.

[0124] (vii) Interlayer physical signal links

[0125] Data transfer between layers is accomplished via a physical bus, and each layer has independent input buffer registers and output buffer registers:

[0126] Link data bit width and single transmission delay

[0127] Physical layer output buffer register → Reflection buffer layer input buffer register (64-bit, 0.5ns)

[0128] Axiom layer boundary control signal line → Symbol layer comparator 32-bit 0.3ns

[0129] Metacognitive layer backtracking signal line → Axiomatic layer / Formula layer / Symbol layer 3 independent signal lines 0.8ns / line

[0130] All data transfers between layers are accomplished through the physical bus and independent input / output buffer registers, without going through the operating system or application software stack.

[0131] Example 2: A simplified six-layer inference system based on masked read-only memory + static random access memory cache

[0132] The L0.5 intermediate layer of this invention is not limited to the implementation of hardware non-volatile buffer. When the physical mapping result of the L0 layer needs to be converted into a standardized code that can be recognized by the downstream symbol layer, a semantic conversion interface module can be used to map the measurable features of the physical field (such as peak position and pulse delay) into search words of the symbol layer content addressable memory.

[0133] When the L0.5 intermediate layer needs to interface with different external protocols (such as PCIe, I2C, SPI), a protocol conversion module can be used to convert the external input protocol into a unified hardware signal format within the L0.5 layer, ensuring protocol independence for cache tag matching.

[0134] The intermediate layer reflection cache module in this embodiment is composed of magnetoresistive random access memory (MRAM) or ferroelectric random access memory (FRAM), and falls within the protection scope of the intermediate layer L0.5 of this invention.

[0135] This embodiment serves as an alternative to Embodiment 1 and is applicable to scenarios where the inference boundary parameters are fully determined and no on-site programming is required.

[0136] (a) Axiomatic layer – Mask ROM alternative

[0137] In this embodiment, a mask read-only memory (MROM) is used instead of a polysilicon fuse in the axiomatic layer. The contents of the mask MROM are determined during the photolithography masking stage of chip manufacturing, resulting in lower manufacturing costs (no fuse programming process required) and suitability for mass production scenarios. However, the contents of the mask MROM cannot be programmed or modified after chip manufacturing is completed, therefore it is only suitable for applications where the inference boundary parameters are completely determined and no further adjustments are needed.

[0138] (ii) Reflection Buffer Layer – Static Random Access Memory + Backup Battery Alternative Solution

[0139] In this embodiment, the reflective buffer layer uses a static random access memory (SRAM) + backup battery scheme instead of magnetoresistive random access memory (MRRAM).

[0140] Static random access memory (SRAM) provides nanosecond-level read and write speeds (read latency less than 5ns, write latency less than 5ns; see Hennessy & Patterson, "Computer Architecture: A Quantitative Approach", 6th ed., 2017, Ch. 2: SRAM access time 10-20ns, 5nm SRAM <1ns) when the system is powered on. A backup battery (such as a coin cell battery) maintains the SRAM speed during system power failure.

[0141] Data is not lost and can be retained for 5 to 10 years (Dallas / Maxim, "NV SRAM with Lithium Battery Datasheet", DS1746, 2002: Typical data retention 10 years @ 25°C).

[0142] Compared to magnetoresistive random access memory (MRAM), static random access memory (SRAM) offers advantages such as lower cost and faster read / write speeds. However, it requires periodic replacement of the backup battery, and data retention time is limited by battery life.

[0143] The structure of the remaining layers (physical layer, symbolic layer, formula layer, metacognitive layer) is the same as in Example 1.

[0144] Experimental verification

[0145] In the simulation experiment, this solution was compared with existing technical solutions:

[0146] Boundary check latency comparison:

[0147] This solution (hardware comparator): less than 1ns

[0148] Software solution (operating system level verification): greater than 1μs

[0149] Axiom backtracking delay comparison:

[0150] This solution (pure signal link): less than 10ns (including 50ps for metacognitive layer detection + 0.8ns for signal transmission + responses from each layer; the above latency data is obtained based on logic simulation).

[0151] Software solution (operating system interrupt handling + software backtracking): greater than 1ms

[0152] Cache hit latency comparison:

[0153] This solution (reflective cache layer magnetoresistive random access memory cache hit): less than 10ns (skipping physical layer physical mapping; Everspin, "MR10Q010 1Mb MRAM Datasheet", 2018. Actual measured MRAM read latency is 35ns, typical 8-15ns for 256Mb STT-MRAM, see "GlobalFoundries 22FDX eMRAM Compiler" 2020).

[0154] Unbuffered approach (full physical layer physical mapping): approximately 100ns to 1μs (depending on the physical medium)

[0155] Comparison of anti-tampering capabilities:

[0156] This solution (axiomatic layer polysilicon fuse / mask read-only memory) cannot be modified by any software instructions, and any attempt at physical tampering will result in a detectable shift in electrical parameters.

[0157] Software solutions (configuration files / database storage): can be modified by operating system-level code or malware.

[0158] Explanation of reference numerals in the attached figures

[0159] 100—Physical Layer Interface; 200—Reflection Buffer Layer; 300—Symbol Layer; 400—Formula Layer; 500—Axiom Layer; 600—Metacognitive Layer; 700—Physical Bus;

[0160] 301—Content-Addressable Memory Cell Array; 302—Search Line Drive Circuit; 303—Matching Line Control Circuit; 304—Priority Encoder;

[0161] 402—Configure memory; 403—Lookup table;

[0162] 501—Immutable rule-based memory cell; 502—Programming / fixing interface; 503—Readout circuit; 504—Boundary register;

[0163] 603—Tracing back the signal link.

[0164] The core value of this application lies in achieving the immutability of the inference boundary through the inter-layer physical signal links of the six-layer architecture and the hardware immutable boundary anchoring mechanism.

[0165] [Patent Family Synergy Statement]

[0166] This application is one of 11 deterministic computing architecture patent families filed by the applicant on the same day. The inventive subject matter, all technical features claimed in the claims, and the specific embodiments shown in the drawings are fully and independently disclosed in the specification and drawings of this application, and can be implemented and reproduced by a person skilled in the art without relying on other applications in the same family.

[0167] The technical solutions claimed in this application are structurally independent from other applications in the same family at the physical implementation level, each containing a complete physical structure, signal flow path, range of technical parameters and specific embodiments, thus satisfying the unity requirement of CNIPA §31.

[0168] The distinguishing feature of the related application "Automatic Deposition and Causal Coloring Audit Device for Reflection Cache of Reasoning Path" is that: this application uses a six-layer physically isolated structure (physical / intermediate / symbolic / formula / axiom / metacognitive layer) and immutable hardware storage of the axiom layer to achieve reasoning boundary anchoring and layer-by-layer backtracking correction; while the related application uses automatic deposition and causal coloring of reasoning path reflection cache to achieve hardware-level audit tracing of the reasoning evidence chain. This application focuses on the layered architecture and boundary solidification of the reasoning system, while the related application focuses on the caching and auditing of reasoning paths. The two differ in their technical means, processing objects, and application layers.

[0169] The key parameters of this invention are: the L3 axiom layer uses a polysilicon fuse or mask ROM (programming voltage 5-10V, pulse width 100μs-1ms), and when L3 is compromised, the system backtracking delay increases from 5ns to >1ms.

[0170] [Industry Application]

[0171] This invention belongs to the field of physical computing hardware technology. It can be manufactured and used in industry and can be applied to deterministic computing tasks, artificial intelligence inference acceleration, symbol generation and detection, quantum precision measurement and other fields, and has clear industrial applicability.

[0172] [Data Source Explanation] The specific performance data (including but not limited to latency, power consumption, sensitivity, etc.) listed in this specification are all obtained based on publicly available theoretical analysis and comparison with published similar measured parameters. In actual hardware implementation, there may be differences due to different process nodes, component selections and system integration schemes. This data is used to illustrate the relative advantages of the technical solution of this application compared with existing solutions, and does not constitute a limitation on the scope of protection of this application.

[0173] [Defensive Disclosure]

[0174] This invention can also work in conjunction with a lightweight, edge-embedded natural language understanding model, where the small model acts as a semantic receiver to convert user intent into structured instructions, and the physical computing device acts as an executor to respond to physical instructions in real time. The device described in this invention can be connected to existing computer systems as a coprocessor in the form of a PCIe accelerator card, without modifying the instruction flow of the host operating system, achieving a human-machine collaborative division of labor of 99% physical execution and 1% human decision-making. It is suitable for drones, autonomous mobile robots, vehicle terminals, or edge computing devices.

[0175] Example 3: Inference Boundary Anchoring Based on GPU-CPU Heterogeneous Architecture (PCIe Physical Isolation Bus for Inter-Layer Physical Independence). This example utilizes the GPU-side TCAM array as the L1 symbol layer and the CPU-side FPGA as the L2 formula layer, achieving inter-layer state synchronization via the PCIe bus. During inference, after L1 completes parallel symbol matching, the matching result is fixed to the L2 register group through hardware anchors, reducing inference time by 60% compared to a pure CPU implementation. This example corresponds to the device described in claim 1.

[0176] Example 4: Inference Boundary Anchoring Based on In-Memory Computing. This example utilizes a CIM (Computing-in-Memory) array as the inference execution unit, eliminating data transfer latency through in-memory computation. The inference boundary is implemented through the hardware registers of the CIM controller, improving inference determinism by 5 times compared to the von Neumann architecture. This example corresponds to the device described in claim 1.

Claims

1. A hierarchical physically isolated inference system, characterized in that... It includes: a physical layer interface module, used to receive measurable characteristics of physical fields and convert them into digital signals; The intermediate layer module, composed of hardware circuitry, stores the input-output mapping pairs of high-frequency inference paths and directly outputs the result upon a hit. The symbol layer module contains a hardware-level content-addressable storage structure for storing symbolic knowledge entries. It outputs the addresses of matching symbol entries within a single search cycle through parallel comparison operations. The formula layer module contains a hardware-reconfigurable logic structure, used to configure the logic operation path based on the symbol combination output by the symbol layer; The axiom layer module includes hardware-immutable rule storage units for storing inference boundary parameters and fundamental axioms. These hardware-immutable rule storage units cannot be modified by any software instructions after manufacturing. The metacognitive layer module, which includes hardware monitoring circuitry and an error-correcting state machine, is used to detect the consistency of the reasoning output. When a reasoning contradiction is detected, backtracking correction is triggered layer by layer along the axiomatic layer → formula layer → symbol layer. The physical layer, the intermediate layer, the symbol layer, the formula layer, the axiom layer, and the metacognitive layer are physically independent of each other, and data transfer between layers is accomplished through a physical bus.

2. A hierarchical physical isolation reasoning method, characterized in that... This includes the following steps: It receives measurable features of the physical field and converts them into digital signals, which serve as inference input. At the symbolic layer, symbolic knowledge entries are matched in parallel through hardware-level content-addressable storage structures. At the formula layer, hardware-reconfigurable logical operation paths are configured based on symbol combinations, and logical combinations and derivations are performed on the symbols; At the axiomatic level, inference boundary checks are performed based on hardware immutability rules to prevent out-of-bounds errors. The consistency of the reasoning output is detected at the metacognitive layer. When a contradiction is detected, backtracking correction is triggered layer by layer along the axiomatic layer → formula layer → symbol layer.

3. The apparatus or method according to claim 1 or 2, characterized in that... The hardware-level content-addressable memory structure is a ternary content-addressable memory (TCAM) array, the reconfigurable logic structure is a field-programmable gate array (FPGA), and the immutable regular memory cell is a polysilicon fuse array or a mask read-only memory.

4. The apparatus or method according to claim 1 or 2, characterized in that... The programming voltage of the immutable rule storage unit is 5-10V, and the pulse width is 100μs-1ms; the axiom layer is physically independent of the symbol layer and the formula layer.

5. The apparatus or method according to claim 1 or 2, characterized in that... It also includes an intermediate layer reflection cache module, which is composed of magnetoresistive random access memory (MRAM) or ferroelectric random access memory (FRAM) to store input-output mapping pairs of high-frequency inference paths and retain cached data without loss after the system is powered off.

6. The apparatus or method according to claim 1 or 2, characterized in that... Data transfer between the six layers is accomplished through a physical bus. Each layer has an independent input buffer register and an output buffer register. Data transfer between layers does not go through the operating system or application software stack, and the delay of a single data transfer between layers does not exceed 0.5ns.

7. The apparatus or method according to claim 1 or 2, characterized in that... The inference calculation does not rely on neural networks or large model calls, but is directly completed by hardware circuits.

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