A neural network data parallel scheduling method and system for in-memory computing chips

Abstract

The application discloses a neural network data parallel scheduling method and system for a memory-computing chip, and belongs to the technical field of artificial intelligence chips. The method collects a computing layer tensor dimension, characteristic values, a memory-computing macro array reference coordinate and magnetic storage particle polarity data; a logical-physical address two-dimensional geometric calibration mapping matrix is constructed relying on an array row width, a reference address and an operator step length, sliding window spatial overlap data is extracted, and a state flip bit, a polarity flip bit number and an expected update energy consumption are obtained through bitwise comparison; when there is overlap in the window, a multicast multiplexing scheduling instruction is issued; when the polarity flip bit number is less than a unit flip bit, a write bypass signal is output, and full-amount writing without state change is intercepted. The application reduces address conversion overhead, reduces repeated reading of overlapping data, and reduces energy consumption and device loss caused by invalid writing.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence chip technology, and in particular to a method and system for parallel scheduling of neural network data for in-memory computing chips. Background Technology

[0002] As the parameter size and computational complexity of deep learning models increase, the memory access bandwidth bottleneck in the traditional von Neumann architecture becomes increasingly prominent. In-memory computing chips combine computing units and storage units at the physical layer, helping to reduce the round-trip data transfer between the processor and memory. However, existing data scheduling schemes for in-memory computing chips still have the following technical problems.

[0003] Existing hardware and software scheduling mechanisms typically rely on the Memory Management Unit (MMU) to perform page table lookups from virtual addresses to physical addresses. One-dimensional linear indirect mapping does not fully utilize the geometric structure of neural network tensors and the two-dimensional spatial structure of in-memory physical arrays, which can easily increase address translation and scheduling overhead.

[0004] When performing computations with sliding window characteristics, such as convolution or local attention operations, adjacent computation windows often contain overlapping data. Existing addressing schemes struggle to directly identify overlapping regions at the physical address layer, leading to repeated readings of data at the same physical address and consuming on-chip network bandwidth.

[0005] In-memory computing chips using non-volatile magnetic media generate dynamic power consumption and device wear during data writing. If a full write is performed without comparing the current polarity state of the memory cell with the target polarity state, a write without state change will still occur even when the target state matches the current state, increasing unnecessary power consumption and the number of write operations. Summary of the Invention

[0006] To address the problems of high address translation overhead, redundant sliding window reading, and increased energy consumption and device losses due to stateless writing in existing technologies, this invention provides a neural network data parallel scheduling method and system for in-memory computing chips.

[0007] This invention provides a method for parallel scheduling of neural network data for in-memory computing chips, the method comprising: S10. Obtain the tensor geometric dimension data of the current computing layer and the target feature numerical data to be written, and obtain the two-dimensional reference coordinate data of the storage macro array port and the current polarity data of the underlying magnetic storage particles from the hardware interface. S20. Using hardware coordinate transformation logic, the tensor geometric dimension data is projected onto the physical space corresponding to the two-dimensional reference coordinate data according to the physical array row width, reference address and operator sliding step size, to construct a two-dimensional geometric coordinate hard calibration mapping matrix that represents the correspondence between logical coordinates and physical addresses. S30. Extract the data of the overlapping area of ​​the calculation window space of adjacent sliding windows according to the topological relationship between the logical coordinates and physical addresses in the two-dimensional geometric coordinate hard calibration mapping matrix, and compare the target physical polarity level data obtained by converting the target feature numerical data with the current polarity data of the underlying magnetic storage particles bit by bit to generate polarity reversal difference data including state reversal bit data, polarity reversal bit data and expected update energy consumption data. S40. When the data of the spatial overlapping area of ​​the calculation window indicates that there is spatial overlap, configure the on-chip network router node according to the source physical address and receiving port routing data corresponding to the overlapping area, and generate a physical layer multicast multiplexing scheduling instruction. S50. Set a unit flip bit as the polarity flip threshold data; when the polarity flip bit data does not reach the polarity flip threshold data, output a write bypass enable level signal through hardware control logic to intercept the full write operation that does not produce a state change, and complete the underlying data parallel scheduling of neural network data.

[0008] Furthermore, step S10 specifically includes: S11. Send a physical configuration query signal to the storage block control interface, parse the array base address, number of rows and number of columns fed back by the configuration register, and generate the two-dimensional reference coordinate data; S12. Send a non-destructive probe pulse to the underlying storage array, use a sensing amplifier to collect the readback magnetization level signal, and use an analog-to-digital converter to convert the magnetization level signal into the current polarity data of the underlying magnetic storage particles. S13. Analyze the computation graph of the currently executed neural network operator, extract the spatial height parameter and spatial width parameter of the input tensor or output tensor, and generate the tensor geometric dimension data; S14. Read the numerical sequence to be written from the operator output buffer corresponding to the neural network operator computation graph to generate the target feature numerical data.

[0009] Furthermore, step S20 specifically includes: S21. Parse the tensor geometric dimension data, extract the tensor space height parameter and tensor space width parameter, and extract the reference address M, physical array row width Wp and physical array row number Hp from the two-dimensional reference coordinate data; S22. Generate window row index p, window column index q, window inner row index u, and window inner column index v according to the tensor slicing algorithm, and obtain the vertical sliding step size Sh and the horizontal sliding step size Sw. S23. Calculate the physical row coordinate r, physical column coordinate c and physical addressing address C of the window element according to r=p×Sh+u, c=q×Sw+v and C=M+r×Wp+c, write each logical coordinate and the corresponding physical addressing address into the calibration register array, and generate the two-dimensional geometric coordinate hard calibration mapping matrix; where 0≤r<Hp and 0≤c<Wp; M is the base address of the physical array, Wp is the row width of the physical array, Hp is the number of rows of the physical array, p and q are sliding window indices, u and v are element indices within the window, and Sh and Sw are the longitudinal sliding step size and the transverse sliding step size respectively.

[0010] Further, extracting the data of the spatial overlapping region of the calculation window in step S30 includes: S31. According to the sliding step mechanism of the neural network, continuously extract the physical addressing address sets respectively corresponding to the front and rear adjacent sliding windows from the two-dimensional geometric coordinate hard calibration mapping matrix, so as to generate the subset array data of the sliding windows; S32. Input the physical addressing address sets corresponding to the front and rear adjacent sliding windows into the hardware address comparator circuit inside the chip, and perform parallel equality comparison on the address tags to obtain the intersection of the two address sets; S33. When the intersection is non-empty, the hardware address comparator circuit outputs a high level state, and outputs the starting physical address of the overlapping region as well as the overlapping height parameter and the overlapping width parameter; S34. Perform fixed-length field encapsulation on the starting physical address, the overlapping height parameter and the overlapping width parameter to generate the data of the spatial overlapping region of the calculation window.

[0011] Further, extracting the polarity flip difference data in step S30 includes: S35. Convert the target feature value data into target physical polarity level data according to the data coding rule adopted by the compute-in-memory chip, and synchronously collect the real-time working temperature data of the compute-in-memory chip; S36. Perform bitwise XOR comparison on the target physical polarity level data and the current polarity data of the underlying magnetic storage particles to generate state flip bit data Bi, count the bits with a value of 1 in Bi, and generate polarity flip bit number data Nf; S37. According to the energy cost function calculate the estimated update energy consumption data E, where the summation range is i=1 to N, is the i-th state flip bit data, α is the basic energy consumption constant per unit flip, T is the real-time working temperature data, is the normal temperature reference data, β is a positive physical thermal damping coefficient, and N is the total number of storage bits involved in the comparison; S38. Encapsulate the state flip bit data Bi, the polarity flip bit data Nf, and the expected update energy consumption data E into fields to generate the polarity flip difference data.

[0012] Furthermore, step S40 specifically includes: S41. Parse the source end reference physical address parameters of the overlapping region from the overlapping region data of the computing window space, and obtain multiple sets of receiving port routing data that require the overlapping region data according to the computing task allocation table. S42. Based on the multiple sets of receiving port routing data, write multicast transmission mask reference data into the multicast configuration register of the system on-chip network router node; S43. Send an asynchronous read request to the source reference physical address parameter and write the effective data payload into a temporary on-chip physical buffer block; S44. Construct a multicast addressing sequence based on the effective data load, the multicast transmission mask reference data, and the routing hop count, and output the physical layer multicast multiplexing scheduling instruction.

[0013] Furthermore, step S50 specifically includes: S51. Parse the polarity reversal bit data Nf from the polarity reversal difference data, and convert Nf into an analog comparison voltage signal through a digital-to-analog converter; S52. Set a unit flip bit as the polarity flip threshold data, and perform a differential comparison between the analog comparison voltage signal and the reference voltage corresponding to the polarity flip threshold data; S53. When the analog comparison voltage signal is lower than the reference voltage, Nf is determined to be zero, and the write bypass enable level signal is output. S54. The underlying write control drive circuit responds to the write bypass enable level signal by pulling down the global write enable pin voltage and blocking the bias write current to intercept full write operations that do not produce state changes.

[0014] Furthermore, the method also includes the step of determining transient feature lifecycle termination state data: S61. Read the data lifetime attribute data generated by the neural network compiler based on the tensor production nodes and consumer nodes of the operator computation graph, and write the remaining number of consumer nodes of the target feature tensor into the descending count register as the initial remaining lifetime decay value. S62. Enable the descending order counting logic circuit, listen to the calculation completion pulse signal of the network layer corresponding to each consumer node, and decrement the count value of the descending order counting register by one when a calculation completion pulse signal is received. S63. Scan the output of the descending count register through the hardware zero-crossing detection circuit; when the count value decreases to zero, set the hardware state latch trigger. S64. Read the high-level active signal of the output pin of the hardware state latch trigger and generate transient characteristic life cycle termination state data.

[0015] Furthermore, the method also includes the step of generating a space reclamation instruction based on the transient characteristic lifecycle termination state data: S71. Query the internal hardware trace page table based on the tensor identifier in the transient feature lifecycle termination state data, and read the underlying physical block base address parameter of the storage block occupied by the abandoned feature; S72. Send an overwrite request control frame to the address management microcontroller. The overwrite request control frame includes at least a page table entry index, the underlying physical block base address parameter, and a reclamation opcode. S73. The address management microcontroller sets the reclamation status bit of the target page table entry according to the overwrite request control frame, and clears the target valid bit mask parameter of the target page table entry to zero. S74. Add the address record corresponding to the underlying physical block base address parameter to the global cyclic free address pool and generate an in-situ zero-copy space reclamation instruction.

[0016] Another objective of this invention is to provide a neural network data parallel scheduling system for in-memory computing chips, comprising a main control processor, an in-memory computing chip, an on-chip network router, a write control drive circuit, and an acquisition module, a calibration construction module, a feature extraction module, a multicast scheduling module, and a hardware interception module disposed in the main control processor. The acquisition module is used to acquire the tensor geometric dimension data of the current computing layer and the target feature numerical data to be written, and to acquire the two-dimensional reference coordinate data of the storage macro array port and the current polarity data of the underlying magnetic storage particles from the hardware interface. The calibration construction module is used to project the tensor geometric dimension data onto the physical space corresponding to the two-dimensional reference coordinate data according to the physical array row width, reference address and operator sliding step size, and construct a two-dimensional geometric coordinate hard calibration mapping matrix that represents the correspondence between logical coordinates and physical addresses. The feature extraction module is used to extract the data of the overlapping area of ​​the computation window space of adjacent sliding windows, and generate polarity flip difference data including state flip bit data, polarity flip bit data and expected update energy consumption data by bit comparison; The multicast scheduling module is used to configure the on-chip network router according to the source physical address and receiving port routing data when there is spatial overlap, and generate physical layer multicast multiplexing scheduling instructions. The hardware interception module is used to set a unit flip bit as the polarity flip threshold data, and when the number of polarity flip bits does not reach the polarity flip threshold data, it controls the write control drive circuit to output a write bypass enable level signal to intercept the full write operation that does not produce a state change.

[0017] By adopting the above technical solution, the present invention has the following beneficial effects: 1. This invention constructs a two-dimensional geometric coordinate hard calibration mapping matrix by clearly defining the conversion relationship between row and column coordinates and physical addresses, so that tensor logical coordinates can be directly converted from hardware to physical addresses of the memory array, thereby reducing the overhead of software page table lookups and address translation. 2. This invention extracts the spatial overlap region of the sliding window at the physical address layer and generates a physical layer multicast multiplexing scheduling instruction, so that the data in the overlap region is distributed to multiple computing units after being read once, thereby reducing repeated reading and on-chip network bandwidth occupation. 3. This invention compares the current polarity state with the target polarity state bit by bit, and outputs a write bypass enable signal when the polarity flip bit is zero, thereby avoiding write operations that do not produce state changes, thus reducing the corresponding write power consumption and device losses. Attached Figure Description

[0018] Figure 1 A general flowchart of a neural network data parallel scheduling method for in-memory computing chips provided in an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the principle of constructing a two-dimensional geometric coordinate hard calibration mapping matrix provided in an embodiment of the present invention; Figure 3 A schematic diagram of the logical structure of multicast multiplexing and write bypass interception in the hardware read-write parallel scheduling mechanism provided in the embodiments of the present invention; Figure 4 This is a block diagram of the module structure of a neural network data parallel scheduling system for in-memory computing chips provided in an embodiment of the present invention. Detailed Implementation

[0019] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments. These embodiments are used to illustrate the implementation of the present invention and do not constitute a limitation on the scope of protection of the claims.

[0020] like Figure 1 As shown, this invention provides a method for parallel scheduling of neural network data for in-memory computing chips, the method comprising: Step S10: Obtain the tensor geometric dimension data of the current computing layer and the target feature numerical data to be written, and obtain the two-dimensional reference coordinate data of the storage macro array port and the current polarity data of the underlying magnetic storage particles from the hardware interface.

[0021] Step S10 is configured to establish a correspondence between software-side data and hardware-side states required for scheduling. The tensor geometric dimension data at least includes the spatial height and spatial width of the current tensor; the target feature value data is the sequence of values to be written into the compute-in-memory macro array in the operator output buffer; the two-dimensional reference coordinate data at least includes the physical array reference address, the number of physical array rows, and the physical array row width; the current polarity data of the underlying magnetic storage particles is the current binary polarity state of each storage bit in the target writing area.

[0022] In this embodiment, the current computing layer outputs a 4×4 feature map, and the compute-in-memory macro array is a 128×128 array. The system reads the physical array reference address M, the number of physical array rows Hp of 128 and the physical array row width Wp of 128 from the configuration register, and reads the current polarity state sequence of the target writing area through a non-destructive detection pulse. The target feature value data is quantized and encoded into target physical polarity level data according to the chip data coding rule.

[0023] Step S20: using a hardware coordinate conversion logic, project the tensor geometric dimension data to the physical space corresponding to the two-dimensional reference coordinate data according to the physical array row width, the reference address and the operator sliding step size, and construct a two-dimensional geometric coordinate hard calibration mapping matrix that characterizes the correspondence between logical coordinates and physical addresses.

[0024] Step S20 establishes the correspondence between logical coordinates and physical addresses through deterministic address conversion. Let the sliding window indices be p and q, the element indices in the window be u and v, the longitudinal sliding step size be Sh, and the transverse sliding step size be Sw, then the physical row coordinate r=p×Sh+u, the physical column coordinate c=q×Sw+v, and the physical addressing address C=M+r×Wp+c. The hardware coordinate conversion logic calculates C under the boundary condition of 0≤r<Hp and 0≤c<Wp, and writes the calculation result into the calibration register array.

[0025] In this embodiment, M is 0, Wp is 128, and both Sh and Sw are 1. For an element with a physical row coordinate of 1 and a physical column coordinate of 2, the physical addressing address C is 130. The physical addressing address corresponding to each element in the 4×4 feature map is calculated in the same manner to form a two-dimensional geometric coordinate hard calibration mapping matrix.

[0026] Step S30: extract the data of the spatial overlapping region of the calculation windows of adjacent sliding windows according to the topological relationship between the logical coordinates and the physical addresses in the two-dimensional geometric coordinate hard calibration mapping matrix, perform bitwise comparison on the target physical polarity level data converted from the target feature value data and the current polarity data of the underlying magnetic storage particles, and extract polarity flipping difference data.

[0027] Step S30 includes read link overlap detection and write link state difference detection. The read link calculates the intersection of the physical address sets corresponding to adjacent sliding windows, and encapsulates the starting physical address, overlap height, and overlap width of the intersection into data representing the overlap area of ​​the calculation window space. The write link performs a bitwise XOR operation between the target physical polarity level data and the current polarity data to obtain state flip bit data Bi; it counts the bits in Bi that are 1 to obtain polarity flip bit data Nf; and it calculates the expected update energy consumption data E based on the real-time operating temperature, and encapsulates Bi, Nf, and E into polarity flip difference data.

[0028] In this embodiment, the 3×3 convolutional window moves one position to the right with a horizontal sliding stride of 1, and the physical address sets of the preceding and following windows form a 3×2 intersection. The system encapsulates this intersection into data for the overlapping region of the computational window space. If the target physical polarity level data differs from the current polarity data by 3 bits, then 3 bits of the state flip bit data are set to 1, and the polarity flip bit data Nf is 3.

[0029] Step S40: Execute the read-write parallel scheduling mechanism based on the extraction results: When the data in the overlapping area of ​​the computation window space indicates that there is spatial overlap, configure the on-chip network router node according to the source physical address and receiving port routing data corresponding to the overlapping area, and generate physical layer multicast multiplexing scheduling instructions.

[0030] Step S40 is used to reduce repeated readings of overlapping data. The system parses the source-end reference physical address from the overlapping region data in the computation window space and obtains the receiving port routing data according to the computation task allocation table; then, it writes the multicast transmission mask into the multicast configuration register of the on-chip network router node, initiates a read of the overlapping region, and distributes the read data payload to the corresponding computation unit.

[0031] In this embodiment, the overlapping region data is shared by arithmetic logic unit A, which performs the calculation for the previous window, and arithmetic logic unit B, which performs the calculation for the next window. The system initiates a read of the overlapping region and sends the data to arithmetic logic unit A and arithmetic logic unit B respectively according to the multicast transmission mask.

[0032] Step S50: When the polarity-flipped bit data does not reach the preset polarity-flipped threshold data, the hardware control logic outputs a write bypass enable level signal to intercept the full write operation flowing to the underlying magnetic storage particles, thereby completing the underlying data parallel scheduling of the neural network data.

[0033] Step S50 employs a lossless write bypass determination. The polarity inversion threshold is set to one unit of inversion, i.e., Nf threshold is 1. Since Nf is a non-negative integer, when Nf is less than 1, it can be determined that the target physical polarity level data is completely consistent with the current polarity data. At this time, the output write bypass enable level signal will not change the correctness of the target data; when Nf is greater than or equal to 1, the write bypass enable level signal remains invalid, and the write control drive circuit continues to execute the predetermined write operation.

[0034] In this embodiment, if the initial comparison yields Nf of 3, the write bypass enable signal remains invalid, and the write control drive circuit performs the write operation. After the write operation is completed, when writing the same target data to the same area again, if the bit comparison yields Nf of 0, the system outputs the write bypass enable signal and blocks the write current that does not produce a state change.

[0035] Furthermore, the sub-steps of step S10 specifically include: Step S11: Send a physical configuration query signal to the storage block control interface, parse the array base address, number of rows and number of columns fed back by the configuration register, and generate two-dimensional reference coordinate data.

[0036] The system reads the array base address, row number, and column number from the configuration register through the storage block control interface, and generates two-dimensional reference coordinate data accordingly. This method keeps the source of coordinate data, data fields, and read path fixed.

[0037] In this embodiment, the configuration register returns the physical array row number 128, the physical array row width 128, and the reference address M of the target array block, based on which the system generates two-dimensional reference coordinate data.

[0038] Step S12: Send a non-destructive probe pulse to the underlying storage array, use a sensing amplifier to collect the readback magnetization level signal, and use an analog-to-digital converter to convert the magnetization level signal into the current polarity data of the underlying magnetic storage particles.

[0039] The system uses a non-destructive probe pulse below the write threshold to read the magnetoresistive state of the memory cell. The pulse is then converted to an analog level by a sensing amplifier and quantized into a binary polarity state by an analog-to-digital converter. The amplitude and duration of the probe pulse are set according to the non-destructive read specifications of the target memory chip.

[0040] In one embodiment, when a probe pulse passes through a particle at a specific pin and the particle returns to a high-resistance state, the analog-to-digital converter recognizes this as a logic 1 and updates the underlying magnetic storage to the particle's current polarity data.

[0041] Step S13: Analyze the computation graph of the currently executed neural network operator, extract the spatial height and spatial width parameters of the input tensor or output tensor, and generate tensor geometric dimension data.

[0042] The neural network operator computation graph includes operator types, input and output tensor descriptors, and data dependencies between nodes. The system reads the spatial height field and spatial width field in the tensor descriptor corresponding to the current operator to generate tensor geometric dimension data.

[0043] In one embodiment, a compiler parses the computation graph of the convolutional layer, extracts that the length of the input feature map is 4 and the width is 4, and generates corresponding tensor geometric dimension data.

[0044] Step S14: Read the to-be-written value sequence from the operator output buffer corresponding to the neural network operator computation graph, and generate target feature value data.

[0045] The system reads the value sequence that has completed computation and is waiting to be written from the output buffer of the current operator, and generates the target feature value data according to the data bit width and quantization format supported by the processing-in-memory chip.

[0046] In one embodiment, the value sequence output by the computation of the convolutional layer is directly truncated to serve as the target feature value data for subsequent scheduling preparation.

[0047] Further, the sub-steps of step S20 specifically include: Step S21: Parse the tensor geometric dimension data, extract the tensor spatial height parameter and the tensor spatial width parameter, and extract the base address M, the physical array row width Wp and the physical array row number Hp from the two-dimensional reference coordinate data.

[0048] Step S21 reads the tensor spatial height parameter and the tensor spatial width parameter, and reads the base address M, the physical array row width Wp and the physical array row number Hp from the physical array configuration register. The physical array row width Wp represents the number of addressable storage units in each physical row.

[0049] In this embodiment, both the tensor spatial height and spatial width are 4, both the physical array row width Wp and the physical array row number Hp are 128, and the physical array base address M is 0.

[0050] Step S22: Generate the window row index p, the window column index q, the in-window row index u and the in-window column index v according to a tensor slicing algorithm, and acquire the longitudinal sliding step Sh and the transverse sliding step Sw.

[0051] The window row index p and the window column index q are used to determine the position of the current sliding window, and the in-window row index u and the in-window column index v are used to determine the position of an element in the window. For a computation window with a height Kh and a width Kw, 0≤u<Kh and 0≤v<Kw.

[0052] In this embodiment, for a 3×3 convolution window, the value ranges of u and v are both 0 to 2; both the vertical sliding step Sh and the horizontal sliding step Sw are 1.

[0053] Step S23: Calculate the physical row coordinate r, the physical column coordinate c and the physical addressing address C according to r=p×Sh+u, c=q×Sw+v and C=M+r×Wp+c, and write the logical coordinates and the physical addressing addresses into the calibration register array to generate a two-dimensional geometric coordinate hard calibration mapping matrix.

[0054] Wherein, M is the base address of the physical array, Wp is the row width of the physical array, and Hp is the number of rows of the physical array; p and q are sliding window indexes, u and v are element indexes within the window; Sh and Sw are the vertical sliding step and the horizontal sliding step respectively; the physical coordinates satisfy 0≤r<Hp and 0≤c<Wp.

[0055] The above conversion relationship takes the row width of the physical array as the row span, and converts the two-dimensional physical coordinates into a unique linear physical addressing address. The hardware coordinate conversion logic can be implemented by a multiply-add circuit, a boundary comparator and a calibration register array, and the calculated address does not depend on the operating system page table lookup.

[0056] In this embodiment, M is 0, Wp is 128, and both Sh and Sw are 1. For an element with a physical row coordinate r of 1 and a physical column coordinate c of 2, the calculated physical addressing address C is 130. The system performs the same calculation on the remaining elements covered by the target tensor to form a two-dimensional geometric coordinate hard calibration mapping matrix.

[0057] Further, extracting the data of the spatial overlapping region of the calculation window in step S30 includes: Step S31: According to the neural network sliding step mechanism, continuously extract the physical addressing address sets respectively corresponding to the adjacent front and rear sliding windows from the two-dimensional geometric coordinate hard calibration mapping matrix, so as to generate sliding window subset array data.

[0058] The system reads the corresponding physical addressing addresses from the two-dimensional geometric coordinate hard calibration mapping matrix according to the index ranges of the adjacent front and rear sliding windows, so as to form a first address set and a second address set respectively.

[0059] In this embodiment, the first address set corresponds to a 3×3 convolution window, and the second address set corresponds to a 3×3 region covered after the convolution window moves right by one horizontal sliding step.

[0060] Step S32: Input the first address set and the second address set into the hardware address comparator circuit inside the chip, and perform parallel equality comparison on the address tags to obtain the intersection of the two address sets.

[0061] A hardware address comparator circuit can be composed of parallel comparison units and merge logic. Each comparison unit performs an equality comparison on two sets of address tags, and the merge logic forms an overlapping address set based on the comparison results.

[0062] In this embodiment, the comparison results show that the right two columns of addresses in the first address set are the same as the left two columns of addresses in the second address set, and the overlapping address set corresponds to a 3×2 region.

[0063] Step S33: When the overlapping address set is not empty, the hardware address comparator circuit outputs a high level state and outputs the starting physical address of the overlapping region, the overlapping height parameter, and the overlapping width parameter.

[0064] When the overlapping address set is not empty, the hardware address comparator circuit outputs a high level and outputs the starting physical address, overlapping height parameter, and overlapping width parameter of the overlapping address set.

[0065] In this embodiment, the hardware address comparator circuit outputs a high-level state, the overlap height parameter is 3, the overlap width parameter is 2, and the minimum address in the overlap address set is used as the starting physical address.

[0066] Step S34: Encapsulate the starting physical address, overlap height parameter, and overlap width parameter into fixed-length fields to generate the calculation window space overlap area data.

[0067] The data for the overlapping region of the computation window space is encapsulated using fixed-length fields, which include at least an overlap validity flag, the starting physical address, the overlap height parameter, and the overlap width parameter. The bit width of each field is determined based on the physical array address width and the maximum computation window size.

[0068] In this embodiment, the overlap validity flag, starting physical address, overlap height parameter 3, and overlap width parameter 2 are written into the corresponding fields in sequence to generate the overlap area data of the calculation window space.

[0069] Further, in step S30, the polarity reversal difference data is extracted, including: Step S35: Convert the target feature numerical data into target physical polarity level data according to the data encoding rules adopted by the memory chip, and simultaneously collect the real-time operating temperature data of the memory chip.

[0070] The target feature numerical data is converted into target physical polarity level data according to the quantization bit width and polarity encoding rules adopted by the in-memory chip. The temperature sensor synchronously collects the real-time operating temperature data of the target array blocks to estimate the update energy consumption corresponding to the state transition.

[0071] In this embodiment, the target feature numerical data adopts binary polarity encoding, and the real-time operating temperature data T measured by the temperature sensor is 65℃.

[0072] Step S36: Perform a bitwise XOR comparison between the target physical polarity level data and the current polarity data of the underlying magnetic storage particles to generate state flip bit data Bi, and count the bits with a value of 1 in Bi to generate polarity flip bit data Nf.

[0073] The target physical polarity level data is XORed with the current polarity data. An XOR result Bi of 1 indicates that the i-th storage bit needs to be toggled, and Bi of 0 indicates that the i-th storage bit does not need to be toggled. The bits with a value of 1 in Bi are counted to obtain the polarity toggled bit number data Nf.

[0074] In this embodiment, 3 bits in the bitwise XOR result are 1, so Nf is 3. The state flip bit data Bi also retains the positions of each difference bit for subsequent energy consumption estimation and write control.

[0075] Step S37: According to the energy cost function Calculate the expected updated energy consumption data E, where the summation ranges from i=1 to N. Let be the i-th state flip-over bit data, α be the basic energy consumption constant per unit flip-over, and T be the real-time operating temperature data. The reference data is at room temperature, β is a positive physical thermal damping coefficient, and N is the total number of storage bits involved in the comparison.

[0076] Step S38: Flip the state bit data The polarity inversion bit data Nf and the expected updated energy consumption data E are encapsulated into fields to generate polarity inversion difference data.

[0077] The energy cost function accumulates the unit switching energy consumption corresponding to the state switching bit. The negative sign in the exponent term is used to characterize the relationship between the unit switching energy consumption and the increase in real-time operating temperature under the heat-assisted switching model adopted in this embodiment. α, β, and T0 are determined by the device calibration data of the target in-memory chip and written into the energy consumption parameter register. The polarity switching difference data includes at least the state switching bit data Bi, the number of polarity switching bits Nf, and the expected update energy consumption data E.

[0078] In this embodiment, Nf = 3, real-time operating temperature data T, and device calibration parameters α, β, and T0 are substituted into the energy cost function to obtain the expected updated energy consumption data E, and Bi, Nf, and E are encapsulated as polarity reversal difference data.

[0079] Furthermore, the sub-steps of step S40 specifically include: Step S41: Parse the source-end reference physical address parameters of the overlapping region from the overlapping region data of the calculation window space, and obtain multiple sets of receiving port routing data that require the overlapping region data according to the calculation task allocation table.

[0080] The system determines the receiving and computing unit and its receiving port for the overlapping area data according to the computing task allocation table, and writes the corresponding routing port number into multiple sets of receiving port routing data.

[0081] In this embodiment, the source reference physical address corresponds to the starting physical address of the overlapping area, and the receiving port routing data points to arithmetic logic unit A and arithmetic logic unit B, respectively.

[0082] Step S42: Based on the routing data of multiple receiving ports, write the multicast transmission mask reference data into the multicast configuration register of the system on-chip network router node.

[0083] Each valid bit of the multicast transmission mask corresponds to an output port of the on-chip network router. After receiving a data packet containing the multicast identifier, the router copies the data packet to the corresponding output port according to the valid bits.

[0084] In this embodiment, the valid bits of the output ports corresponding to arithmetic logic unit A and arithmetic logic unit B are set, while the valid bits of the other output ports are cleared to zero.

[0085] Step S43: Send an asynchronous read request to the source reference physical address parameter and write the valid data payload into a temporary on-chip physical buffer block.

[0086] The hardware controller initiates an asynchronous read from the source reference physical address and writes the returned data payload into an on-chip physical buffer block; the depth of this buffer block is not less than the data length of the overlapping region.

[0087] In this embodiment, the system initiates a read of the 3×2 overlapping region and writes the data payload of 6 elements into the on-chip physical buffer block.

[0088] Step S44: Construct a multicast addressing sequence based on the effective data load, multicast transmission mask reference data, and routing hop count, and output the physical layer multicast multiplexing scheduling instruction.

[0089] The physical layer multicast multiplexing scheduling instruction includes at least the source base physical address, data length, multicast transmission mask, and routing hop count. The on-chip network router performs data replication and port forwarding based on the multicast transmission mask.

[0090] In this embodiment, the overlapping region data in the on-chip physical buffer block is read once and then sent to arithmetic logic unit A and arithmetic logic unit B respectively.

[0091] Furthermore, the sub-steps of step S50 specifically include: Step S51: Parse the polarity reversal bit data Nf from the polarity reversal difference data, and convert Nf into an analog comparison voltage signal through a digital-to-analog converter.

[0092] The digital-to-analog converter converts the polarity-flipped bit data Nf into an analog comparison voltage signal according to a preset linear ratio. This ratio ensures that one unit of flipped bit corresponds to a specific unit comparison voltage.

[0093] In this embodiment, one unit flip bit corresponds to 0.5V. When Nf is 0, the analog comparison voltage signal is 0V, and when Nf is 3, the analog comparison voltage signal is 1.5V.

[0094] Step S52: Set a unit flip bit as the polarity flip threshold data, and perform a differential comparison between the analog comparison voltage signal and the reference voltage corresponding to the polarity flip threshold data.

[0095] The reference voltage is set to the voltage corresponding to one unit of flip-flop, i.e., 0.5V. A differential hardware voltage threshold comparator circuit is used to determine whether the analog comparison voltage signal is lower than this reference voltage.

[0096] In this embodiment, when Nf is 0, the analog comparison voltage signal 0V is lower than the reference voltage of 0.5V; when Nf is 3, the analog comparison voltage signal 1.5V is higher than the reference voltage of 0.5V.

[0097] Step S53: When the analog comparison voltage signal is lower than the reference voltage, determine that Nf is zero and output the write bypass enable level signal.

[0098] When the analog comparison voltage signal is lower than the reference voltage, since Nf is a non-negative integer and the reference voltage corresponds to a unit flip bit, Nf can be determined to be 0, and the differential hardware voltage threshold comparator circuit outputs a write bypass enable signal.

[0099] In this embodiment, when the analog comparison voltage signal is 0V, the comparator outputs a low-level active write bypass enable signal; when the analog comparison voltage signal is 1.5V, the write bypass enable signal remains inactive.

[0100] Step S54: In response to the write bypass enable level signal, the underlying write control drive circuit pulls down the global write enable pin voltage and blocks the bias write current to intercept full write operations that do not produce state changes.

[0101] The write bypass enable level signal is directly input to the write control drive circuit. When this signal is valid, the write control drive circuit pulls down the global write enable pin voltage and blocks the bias write current; when this signal is invalid, the write control drive circuit performs the write according to the original write timing.

[0102] In this embodiment, when Nf is 0, the write control drive circuit blocks the write current that does not produce a state change; when Nf is 3, the write control drive circuit continues to perform the write operation, so that the target region reaches the target physical polarity state.

[0103] Furthermore, the method of the present invention also includes the step of determining transient characteristic lifecycle termination state data: Step S61: Read the data lifetime attribute data generated by the neural network compiler based on the tensor production nodes and consumer nodes of the operator computation graph, and write the remaining number of consumer nodes of the target feature tensor into the descending count register as the initial remaining lifetime decay value.

[0104] The data lifecycle attribute data is obtained by the neural network compiler through activity analysis of the operator computation graph. For each feature tensor, the compiler records its producer nodes, all consumer nodes, and the number of remaining consumer nodes, and writes the number of remaining consumer nodes as the initial remaining lifetime decay value into the descending count register.

[0105] In this embodiment, the target feature tensor is consumed by the subsequent two network layers, and the initial remaining lifetime decay value is set to 2.

[0106] Step S62: Enable the descending order counting logic circuit, listen to the calculation completion pulse signal of the network layer corresponding to each consumer node, and decrement the count value of the descending order counting register by one when a calculation completion pulse signal is received.

[0107] When each consumer node completes a calculation, it outputs a calculation completion pulse signal. After receiving the calculation completion pulse signal, the descending counting logic circuit decrements the count value of the descending counting register by one.

[0108] In this embodiment, after the two consumer nodes complete their calculations in sequence, the count value of the descending count register decreases from 2 to 1, and then from 1 to 0.

[0109] Step S63: Scan the output of the descending count register through the hardware zero-crossing detection circuit; when the count value decreases to zero, set the hardware state latch trigger.

[0110] The hardware zero-crossing detection circuit compares the output of the descending count register with zero. When the comparison result is equal, the hardware zero-crossing detection circuit sets the hardware state latch flip-flop and holds it in that state until space reclamation is complete.

[0111] In this embodiment, after the count value of the descending count register is reduced to 0, the hardware state latch trigger outputs a high-level active signal.

[0112] Step S64: Read the high-level active signal of the output pin of the hardware state latch trigger and generate transient characteristic life cycle termination state data.

[0113] The transient characteristic lifecycle termination state data includes at least a tensor identifier and a lifecycle termination valid flag. The system writes the high-level active signal of the hardware state latch flip-flop into the lifecycle termination valid flag field.

[0114] In this embodiment, the system encapsulates the tensor identifier of the target feature tensor with the valid lifetime termination flag to generate transient feature lifetime termination state data.

[0115] Furthermore, the method of the present invention also includes the step of generating a space reclamation instruction based on transient characteristic lifecycle termination state data: Step S71: Query the internal hardware trace page table based on the tensor identifier in the transient feature lifecycle termination state data, and read the underlying physical block base address parameter of the storage block occupied by the abandoned feature.

[0116] The page table entries in the hardware tracing page table include at least a tensor identifier, the underlying physical block base address parameter, the target valid bitmask parameter, and the reclamation status bit. The system queries the corresponding page table entry based on the tensor identifier and reads the underlying physical block base address parameter.

[0117] In this embodiment, the system queries the target page table entry based on the tensor identifier and reads the underlying physical block base address parameter 0x00A0.

[0118] Step S72: Send an overwrite request control frame to the address management microcontroller. The overwrite request control frame includes at least the page table entry index, the underlying physical block base address parameter, and the reclamation opcode.

[0119] The overwrite request control frame includes at least the page table entry index, the underlying physical block base address parameter, and the reclamation opcode. The address management microcontroller verifies that the page table entry index matches the underlying physical block base address parameter before performing a reclamation status update.

[0120] In this embodiment, the system sends an overwrite request control frame to the address management microcontroller, which includes the target page table entry index, the underlying physical block base address parameter 0x00A0, and the reclamation opcode.

[0121] Step S73: The address management microcontroller sets the reclaim status bit of the target page table entry according to the overwrite request control frame and clears the target valid bit mask parameter of the target page table entry to zero.

[0122] The address management microcontroller sets the reclaim status bit of the target page table entry and clears the target valid bitmask parameter, logically severing the valid association between the physical block and the original feature tensor. This process does not move the data in the original physical block.

[0123] In this embodiment, the target valid bitmask parameter is cleared from 1 to 0, the data in the original physical block remains unchanged, and it waits for subsequent write overwriting.

[0124] Step S74: Add the address record corresponding to the underlying physical block base address parameter to the global circular free address pool and generate an in-situ zero-copy space reclamation instruction.

[0125] The address management microcontroller writes the base address parameters of the underlying physical block, after clearing the valid bits, into the global circular free address pool, so that the physical block can be reused by subsequent storage allocation requests.

[0126] In this embodiment, the underlying physical block base address parameter 0x00A0 is added to the global circular free address pool, forming the execution result of the in-situ zero-copy space reclamation instruction.

[0127] The above embodiments are further described below with reference to the accompanying drawings: like Figure 1 As shown, this embodiment provides a method for parallel scheduling of neural network data for in-memory computing chips. This method is executed by a hardware controller or processor located inside the in-memory computing system, and specifically includes the following steps: In step S10, the acquisition module 101 reads the tensor descriptor, operator output buffer, physical array configuration register, and the current polarity state of the target write region, and obtains tensor geometric dimension data, target feature numerical data, two-dimensional reference coordinate data, and the current polarity data of the underlying magnetic storage particles, respectively.

[0128] like Figure 2 As shown, in step S20, the calibration construction module 102 calculates the physical coordinates and physical addressing addresses according to r=p×Sh+u, c=q×Sw+v and C=M+r×Wp+c, and writes the correspondence between the logical coordinates and the physical addressing addresses into the calibration register array to form a two-dimensional geometric coordinate hard calibration mapping matrix.

[0129] In step S30, the feature extraction module 103 performs an intersection comparison on the physical address sets corresponding to adjacent sliding windows to generate data on the overlapping area of ​​the calculation window space; at the same time, it performs a bitwise XOR operation on the target physical polarity level data and the current polarity data to generate state flip bit data Bi, polarity flip bit data Nf, and expected update energy consumption data E.

[0130] like Figure 3 As shown, in steps S40 and S50, the multicast scheduling module 104 configures the on-chip network router according to the source physical address and receiving port routing data of the overlapping area to realize one-time reading and multi-port distribution of overlapping data; the hardware interception module 105 outputs a write bypass enable level signal when Nf is 0 to block the write current that does not produce a state change.

[0131] like Figure 4 As shown, this embodiment also provides a neural network data parallel scheduling system for in-memory computing chips. The system includes a main control processor 100, an in-memory computing chip 200, an on-chip network router, and a write control drive circuit. The main control processor 100 includes an acquisition module 101, a calibration construction module 102, a feature extraction module 103, a multicast scheduling module 104, and a hardware interception module 105. Each module can be implemented by dedicated logic circuits or by the processor executing instructions from memory.

[0132] The acquisition module 101 is used to acquire the tensor geometric dimension data of the current computing layer and the target feature numerical data to be written, and to acquire the two-dimensional reference coordinate data of the in-memory macro array port inside the in-memory chip 200 and the current polarity data of the underlying magnetic storage particles from the hardware interface.

[0133] The calibration construction module 102 is used to read the physical array reference address M, the physical array row width Wp and the physical array row number Hp, generate a two-dimensional geometric coordinate hard calibration mapping matrix according to the deterministic address conversion relationship, and write the mapping matrix into the calibration register array of the main control processor 100.

[0134] The feature extraction module 103 is used to extract the data of the overlapping area of ​​the computation window space of adjacent sliding windows, and to generate polarity reversal difference data including Bi, Nf and E by bitwise XOR, flip bit count and energy cost calculation.

[0135] The multicast scheduling module 104 is used to configure the on-chip network router according to the source physical address and the receiving port routing data when there is spatial overlap, and output physical layer multicast multiplexing scheduling instructions to the in-memory computing chip 200.

[0136] The hardware interception module 105 is used to set a unit flip bit as the polarity flip threshold data, and output a write bypass enable level signal to the write control drive circuit of the memory chip 200 when Nf is 0, so as to intercept the full write operation that does not produce a state change.

[0137] The following uses a convolutional neural network for two-dimensional image feature maps as an example to illustrate... Figures 1 to 4 The execution process of the technical solution shown is explained.

[0138] The main control processor 100 executes a convolutional layer in a convolutional neural network with a convolutional window size of 3×3 and a vertical sliding stride Sh and a horizontal sliding stride Sw of 1.

[0139] First, the acquisition module 101 reads the tensor geometric dimension data of the 4×4 feature map from the tensor descriptor and reads the target feature numerical data from the operator output buffer; it reads the reference address M, the number of rows Hp and the width Wp of the 128×128 physical array from the configuration register of the storage chip 200; and it reads the current polarity state of the target write region through a non-destructive probe pulse.

[0140] Subsequently, the calibration construction module 102 calculates the physical address of each window element according to r=p×Sh+u, c=q×Sw+v, and C=M+r×Wp+c. For example... Figure 2 As shown, each logical coordinate and its corresponding physical address are written into the calibration register array to form a two-dimensional geometric coordinate hard calibration mapping matrix.

[0141] During the calculation, after the 3×3 convolution window moves to the right by one horizontal sliding step, the two right columns of addresses in the first window are the same as the two left columns of addresses in the second window, forming a 3×2 overlapping region. The feature extraction module 103 encapsulates the starting physical address, overlap height 3, and overlap width 2 into the overlapping region data of the calculation window space. At the same time, three bits of the XOR result between the target physical polarity level data and the current polarity data are 1, so Nf is 3, and the expected updated energy consumption data E is obtained according to the energy cost function.

[0142] Finally, the multicast scheduling module 104 generates a physical layer multicast multiplexing scheduling instruction based on the source physical address of the overlapping area and the receiving port routing data corresponding to arithmetic logic unit A and arithmetic logic unit B, so that the data in the 3×2 overlapping area is distributed to the two arithmetic logic units after being read once. For write operations, when Nf is 3, the write bypass enable level signal remains invalid, and the write control drive circuit performs the write operation; when the same target data is subsequently written to the same area and Nf becomes 0, the hardware interception module 105 outputs the write bypass enable level signal to block the write current that does not produce a state change.

[0143] The above embodiments are used to illustrate the technical solution of the present invention. Those skilled in the art can make adjustments to the specific parameters and implementation circuits without departing from the technical concept defined in the claims; the scope of protection of the present invention is determined by the claims.

Claims

1. A method for parallel scheduling of neural network data for in-memory computing chips, characterized in that, The method includes: S10. Obtain the tensor geometric dimension data of the current computing layer and the target feature numerical data to be written, and obtain the two-dimensional reference coordinate data of the storage macro array port and the current polarity data of the underlying magnetic storage particles from the hardware interface. S20. Using hardware coordinate transformation logic, the tensor geometric dimension data is projected onto the physical space corresponding to the two-dimensional reference coordinate data according to the physical array row width, reference address and operator sliding step size, to construct a two-dimensional geometric coordinate hard calibration mapping matrix that represents the correspondence between logical coordinates and physical addresses. S30. Extract the data of the overlapping area of ​​the calculation window space of adjacent sliding windows according to the topological relationship between the logical coordinates and physical addresses in the two-dimensional geometric coordinate hard calibration mapping matrix, and compare the target physical polarity level data obtained by converting the target feature numerical data with the current polarity data of the underlying magnetic storage particles bit by bit to generate polarity reversal difference data including state reversal bit data, polarity reversal bit data and expected update energy consumption data. S40. When the data of the spatial overlapping area of ​​the calculation window indicates that there is spatial overlap, configure the on-chip network router node according to the source physical address and receiving port routing data corresponding to the overlapping area, and generate a physical layer multicast multiplexing scheduling instruction. S50. Set a unit flip bit as the polarity flip threshold data; when the polarity flip bit data does not reach the polarity flip threshold data, output a write bypass enable level signal through hardware control logic to intercept the full write operation that does not produce a state change, and complete the underlying data parallel scheduling of neural network data.

2. The neural network data parallel scheduling method for in-memory computing chips according to claim 1, characterized in that, Step S10 specifically includes: S11. Send a physical configuration query signal to the storage block control interface, parse the array base address, number of rows and number of columns fed back by the configuration register, and generate the two-dimensional reference coordinate data; S12. Send a non-destructive probe pulse to the underlying storage array, use a sensing amplifier to collect the readback magnetization level signal, and use an analog-to-digital converter to convert the magnetization level signal into the current polarity data of the underlying magnetic storage particles. S13. Analyze the computation graph of the currently executed neural network operator, extract the spatial height parameter and spatial width parameter of the input tensor or output tensor, and generate the tensor geometric dimension data; S14. Read the numerical sequence to be written from the operator output buffer corresponding to the neural network operator computation graph to generate the target feature numerical data.

3. The neural network data parallel scheduling method for in-memory computing chips according to claim 1, characterized in that, Step S20 specifically includes: S21. Parse the tensor geometric dimension data, extract the tensor space height parameter and tensor space width parameter, and extract the reference address M, physical array row width Wp and physical array row number Hp from the two-dimensional reference coordinate data; S22. Generate window row index p, window column index q, window inner row index u, and window inner column index v according to the tensor slicing algorithm, and obtain the vertical sliding step size Sh and the horizontal sliding step size Sw. S23. Calculate the physical row coordinate r, physical column coordinate c and physical addressing address C of the window element according to r=p×Sh+u, c=q×Sw+v and C=M+r×Wp+c, write each logical coordinate and the corresponding physical addressing address into the calibration register array, and generate the two-dimensional geometric coordinate hard calibration mapping matrix; where 0≤r<Hp and 0≤c<Wp; M is the base address of the physical array, Wp is the row width of the physical array, Hp is the number of rows of the physical array, p and q are sliding window indices, u and v are element indices within the window, and Sh and Sw are the longitudinal sliding step size and the transverse sliding step size respectively.

4. The neural network data parallel scheduling method for in-memory computing chips according to claim 1, characterized in that, Extracting the spatial overlapping region data of the calculation window in step S30 includes: S31. According to the sliding step mechanism of the neural network, continuously extract the physical addressing address sets respectively corresponding to the front and rear adjacent sliding windows from the two-dimensional geometric coordinate hard calibration mapping matrix, and generate the sliding window subset array data; S32. Input the physical addressing address sets corresponding to the front and rear adjacent sliding windows into the hardware address comparator circuit inside the chip, and perform parallel equality comparison on the address tags to obtain the intersection of the two address sets; S33. When the intersection is non-empty, the hardware address comparator circuit outputs a high level state, and outputs the starting physical address of the overlapping region as well as the overlapping height parameter and the overlapping width parameter; S34. Perform fixed-length field encapsulation on the starting physical address, the overlapping height parameter and the overlapping width parameter to generate the spatial overlapping region data of the calculation window.

5. The neural network data parallel scheduling method for in-memory computing chips according to claim 1, characterized in that, Extracting the polarity flipping difference data in step S30 includes: S35. Convert the target feature value data into target physical polarity level data according to the data coding rule adopted by the compute-in-memory chip, and synchronously collect the real-time working temperature data of the compute-in-memory chip; S36. Perform bitwise XOR comparison on the target physical polarity level data and the current polarity data of the underlying magnetic storage particles to generate state flipping bit data Bi, count the bits with a value of 1 in Bi to generate polarity flipping bit count data Nf; S37, According to the energy cost function Calculate the expected updated energy consumption data E, where the summation ranges from i=1 to N. Let be the i-th state flip-over bit data, α be the basic energy consumption constant per unit flip-over, and T be the real-time operating temperature data. For room temperature reference data, β is a positive physical thermal damping coefficient, and N is the total number of storage bits involved in the comparison; S38. Perform field encapsulation on the state flipping bit data Bi, the polarity flipping bit count data Nf and the estimated update energy consumption data E to generate the polarity flipping difference data.

6. The neural network data parallel scheduling method for in-memory computing chips according to claim 1, characterized in that, Step S40 specifically includes: S41. Parse out the source-end base physical address parameter of the overlapping region from the spatial overlapping region data of the calculation window, and obtain multiple sets of receiving port routing data that require the overlapping region data according to the calculation task allocation table; S42. Write the multicast transmission mask base data into the multicast configuration register of the router node of the system network-on-chip according to the multiple sets of receiving port routing data; S43. Send an asynchronous read request to the source-end base physical address parameter, and write the valid data payload into the temporary on-chip physical buffer block; S44. Construct a multicast addressing sequence according to the valid data payload, the multicast transmission mask base data and the number of routing hops, and output the physical layer multicast multiplexing scheduling instruction.

7. The neural network data parallel scheduling method for in-memory computing chips according to claim 1, characterized in that, Step S50 specifically includes: S51. Parse the polarity reversal bit data Nf from the polarity reversal difference data, and convert Nf into an analog comparison voltage signal through a digital-to-analog converter; S52. Set a unit flip bit as the polarity flip threshold data, and perform a differential comparison between the analog comparison voltage signal and the reference voltage corresponding to the polarity flip threshold data; S53. When the analog comparison voltage signal is lower than the reference voltage, Nf is determined to be zero, and the write bypass enable level signal is output. S54. The underlying write control drive circuit responds to the write bypass enable level signal by pulling down the global write enable pin voltage and blocking the bias write current to intercept full write operations that do not produce state changes.

8. The neural network data parallel scheduling method for in-memory computing chips according to claim 1, characterized in that, The method also includes the step of determining transient feature lifecycle termination state data: S61. Read the data lifetime attribute data generated by the neural network compiler based on the tensor production nodes and consumer nodes of the operator computation graph, and write the remaining number of consumer nodes of the target feature tensor into the descending count register as the initial remaining lifetime decay value. S62. Enable the descending order counting logic circuit, listen to the calculation completion pulse signal of the network layer corresponding to each consumer node, and decrement the count value of the descending order counting register by one when a calculation completion pulse signal is received. S63. Scan the output of the descending count register using a hardware zero-crossing detection circuit; When the count value decreases to zero, the hardware state latch trigger is set; S64. Read the high-level active signal of the output pin of the hardware state latch trigger and generate transient characteristic life cycle termination state data.

9. The neural network data parallel scheduling method for in-memory computing chips according to claim 8, characterized in that, The method further includes the step of generating a space reclamation instruction based on the transient characteristic lifecycle termination state data: S71. Query the internal hardware trace page table based on the tensor identifier in the transient feature lifecycle termination state data, and read the underlying physical block base address parameter of the storage block occupied by the abandoned feature; S72. Send an overwrite request control frame to the address management microcontroller. The overwrite request control frame includes at least a page table entry index, the underlying physical block base address parameter, and a reclamation opcode. S73. The address management microcontroller sets the reclamation status bit of the target page table entry according to the overwrite request control frame, and clears the target valid bit mask parameter of the target page table entry to zero. S74. Add the address record corresponding to the underlying physical block base address parameter to the global cyclic free address pool and generate an in-situ zero-copy space reclamation instruction.

10. A neural network data parallel scheduling system for in-memory computing chips, used to implement the neural network data parallel scheduling method for in-memory computing chips as described in any one of claims 1 to 9, characterized in that, The system includes a main control processor, a memory computing chip, an on-chip network router, a write control driver circuit, and an acquisition module, a calibration construction module, a feature extraction module, a multicast scheduling module, and a hardware interception module disposed in the main control processor. The acquisition module is used to acquire the tensor geometric dimension data of the current computing layer and the target feature numerical data to be written, and to acquire the two-dimensional reference coordinate data of the storage macro array port and the current polarity data of the underlying magnetic storage particles from the hardware interface. The calibration construction module is used to project the tensor geometric dimension data onto the physical space corresponding to the two-dimensional reference coordinate data according to the physical array row width, reference address and operator sliding step size, and construct a two-dimensional geometric coordinate hard calibration mapping matrix that represents the correspondence between logical coordinates and physical addresses. The feature extraction module is used to extract the data of the overlapping area of ​​the computation window space of adjacent sliding windows, and generate polarity flip difference data including state flip bit data, polarity flip bit data and expected update energy consumption data by bit comparison; The multicast scheduling module is used to configure the on-chip network router according to the source physical address and receiving port routing data when there is spatial overlap, and generate physical layer multicast multiplexing scheduling instructions. The hardware interception module is used to set a unit flip bit as the polarity flip threshold data, and when the number of polarity flip bits does not reach the polarity flip threshold data, it controls the write control drive circuit to output a write bypass enable level signal to intercept the full write operation that does not produce a state change.

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