A dual time constant adaptive neuron circuit with input path control

Abstract

The application discloses a kind of input passage control's double time constant adaptive neuron circuit, including leakage integration circuit and double exponential adaptive input passage control circuit, wherein: the leakage integration circuit is used to accumulate input signal, and fires a voltage pulse when reaching firing threshold;The double exponential adaptive input passage control circuit is used to generate control signal according to the voltage pulse to control the continuous firing frequency of the leakage integration circuit, and according to the voltage pulse, the speed of the control signal change is changed.The remarkable effect is: the adaptability of neuron and the performance of LSNN network are significantly improved, the short-term and long-term adaptation needs can be considered simultaneously, the adjustability and robustness of hardware are enhanced, it is beneficial to integrated into large-scale edge computing system, and efficient calculation is realized in these resource-limited application scenarios, and it has great development prospect.

Description

Technical Field

[0001] This invention relates to the fields of artificial intelligence and integrated circuit technology, and more particularly to memristor-based artificial neuron circuits, specifically to a dual-time-constant adaptive neuron circuit with input path control. Background Technology

[0002] With the development of artificial intelligence technology, the traditional computing paradigm based on the von Neumann architecture is increasingly revealing its fundamental bottlenecks. This architecture relies on the physical separation of storage and computation, and frequent data transfer leads to significant "memory walls" and "power walls," greatly limiting the improvement of computing efficiency. Especially when dealing with brain-like tasks such as pattern recognition, associative memory, and autonomous learning, its efficiency is several orders of magnitude lower than that of the biological brain. The biological brain, with its high parallelism, event-driven nature, in-memory computing, ultra-low power consumption (complex cognition can be completed with about 20 watts), and amazing fault tolerance and learning plasticity, is expected to reshape the computing landscape in the future, empowering many cutting-edge fields such as edge computing, autonomous systems, intelligent sensing, and brain-computer interfaces.

[0003] Current neuromorphic computing systems widely use LIF (Leaky Integrate and Fire) neurons, which have a very simple structure and can accurately describe the electrical behavior of biological neurons. However, the function of these neurons is too singular to simulate the adaptive behavior of biological nervous systems. Real biological neurons have more complex dynamic behaviors; more than 30% of the neurons in the frontal lobe of the human brain possess adaptive functions, and these neurons have been proven to be crucial for improving the computational power of neuromorphic computing systems.

[0004] In adaptive neurons, adaptive control with dual time constants is crucial, requiring an automatic control circuit to regulate the firing frequency of the neuron. Adaptive suppression of the input current is the simplest method for achieving this. However, currently, there is no simple implementation of an adaptive neuron circuit with a dual-time-constant input path control. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a dual-time-constant adaptive neuron circuit for input path control. This circuit can efficiently realize neuron functions by utilizing the dynamic characteristics of volatile memristors, and efficiently realize frequency adaptation by introducing an adaptive circuit structure in the charging path. The control signal has dual-time-constant attenuation characteristics, providing a core functional component for intelligent bionic systems.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A dual-time-constant adaptive neuron circuit with input path control, the key features of which include a leakage integrator circuit and a dual-exponential adaptive input path control circuit, wherein: The leakage integration circuit is used to accumulate the input signal and release a voltage pulse when the emission threshold is reached. The dual-exponential adaptive input path control circuit is used to generate a control signal based on the voltage pulse to control the continuous firing frequency of the leakage integrator circuit, and to change the rate of change of the control signal based on the voltage pulse.

[0007] Furthermore, the circuit also includes an actuator through which the leakage integration circuit receives the input signal, and the actuator also responds to the control signal to control the continuous firing frequency of the leakage integration circuit.

[0008] Furthermore, the actuator is an NMOS transistor. M 2. NMOS transistor M The drain of 2 receives the input signal, and the NMOS transistor... M The source of transistor 2 is connected to the input terminal of the leakage integrator circuit, and the NMOS transistor... M The gate of 2 is connected to the control signal output terminal of the dual exponential adaptive input path control circuit.

[0009] Furthermore, the leakage integration circuit includes a volatile threshold resistive memristor and a capacitor. C 1. Resistance R 1. A capacitor is connected in series at one end of the volatile threshold resistive memristor. C 1. Grounded, volatile threshold resistor, memristor, and capacitor. C The common node of 1 receives the input signal, and the other end of the volatile threshold resistive memristor is connected in series with a resistor. R 1. Grounding, the other end of the volatile threshold resistive memristor and the resistor R The common node of 1 outputs a voltage pulse.

[0010] Furthermore, the dual-exponential adaptive input path control circuit includes an NMOS transistor. M 3 and PMOS transistors M 1. NMOS transistor M The gate of transistor 3 is connected to the output of the leakage integration circuit, and the NMOS transistor... M The drain of 3 is connected to a capacitor C 2 is connected to the voltage source, NMOS transistor M 3's source is grounded; PMOS transistor M The gate of transistor 1 is connected to the output terminal of the leakage integration circuit, and the PMOS transistor is... M The source of 1 is connected to a resistor R 2. Connected to the voltage source, PMOS transistorM The drain of 1 is connected to a capacitor C 3. Connected to the voltage source, PMOS transistor M The source of 1 is also related to the NMOS transistor. M 3's drain and capacitor C The common nodes of 2 are connected to form the output terminal of the control signal.

[0011] Furthermore, the input signal is a voltage signal.

[0012] Furthermore, the volatile threshold resistive switching memristor is a Mott memristor based on Mott phase transition, a diffuse memristor based on metal conductive filaments, or an OTS memristor based on chalcogenides.

[0013] Furthermore, the Mott memristor is based on VO2 or NbO. x Devices.

[0014] Furthermore, the diffuse memristor is an Ag or Cu-based device.

[0015] Furthermore, the OTS memristor is a chalcogenide device based on Se or Te.

[0016] The significant effects of this invention are: This invention provides an adaptive neuron circuit with dual time constants for input path control based on a volatile threshold resistive memristor. It utilizes the dynamic behavior of the volatile threshold resistive memristor to simulate the basic leakage, accumulation, and firing functions of biological neurons, and transmits the fired pulses to the adaptive input path control circuit. On one hand, the magnitude of the neuron's input current can be suppressed by pulling down the control signal, thereby suppressing its continuous firing frequency and achieving the adaptive purpose. On the other hand, the size of the capacitor can also be controlled by the pulses, thereby changing the time constant of the adaptive input path control circuit and altering the rate of change of the control signal.

[0017] Compared with existing single-time-constant adaptive neuron circuits, this invention can significantly improve the accuracy, convergence speed, and long-term memory capacity of LSNN networks. Furthermore, it also boasts the flexibility, efficiency, low power consumption, and high robustness of hardware implementation. These advantages make it a promising candidate to break through the "memory wall / power wall" in in-memory computing systems, becoming a core operator for edge intelligence applications such as real-time speech and vision, associative memory, and online learning. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the circuit structure of the present invention; in, R , C and M These represent resistor, capacitor, and transistor, respectively.V in Input voltage, V dd The power supply voltage, V mem For membrane potential, V spike To output pulse voltage, V ctrl For control signals.

[0019] Figure 2 The voltage waveforms of each node in the circuit described in this invention and the removal of... Figure 1 middle M 1 and C Voltage waveforms at each node after step 3; Figure 3 The circuit described in this invention is used at different input voltages. V in Voltage waveforms at each node below; Figure 4 The circuit described in this invention has different width-to-length ratios. M Voltage waveforms at each node in Figure 2; Figure 5 The circuit described in this invention has different capacitance values. C Voltage waveforms at each node in Figure 1; Figure 6 The circuit described in this invention has different resistances R Voltage waveforms at each node in Figure 2. Detailed Implementation

[0020] The specific embodiments and working principles of the present invention will be further described in detail below with reference to the accompanying drawings.

[0021] This invention proposes a dual-time-constant adaptive neuron circuit for neuromorphic computing based on a volatile threshold resistive memristor. This circuit simulates the impulse firing function of neurons and, upon detecting its own impulse firing, limits the current magnitude of subsequent input neurons, thereby achieving adaptive neuron firing frequency. Simultaneously, this adaptive input path control circuit can adjust the time constant of the RC circuit based on impulse firing, achieving dual-time-constant and dual-exponential variation functionality. Combining these functions, this invention not only addresses the shortcomings of single-time-constant adaptive neuron circuits, such as limited working memory span, slow training convergence, and high parameter sensitivity, but also overcomes the problems of high circuit resource overhead and insufficient reconfigurability previously reported. Unlike other reported single-time-constant adaptive neuron circuits, the dual-time-constant adaptive neuron circuit based on a volatile threshold resistive memristor input path control of this invention introduces a gated PMOS in the adaptive input path control circuit. When a pulse arrives, a series PMOS transistor temporarily disconnects part of the capacitor from the circuit, causing the time constant of the RC circuit to first be small and then large. This allows for the formation of a "fast-slow" two-stage time constant threshold change and adaptive suppression with a very small number of devices, and achieves a unified encoding function for long short-term memory.

[0022] Specific embodiments of the present invention are as follows:

[0023] Example:

[0024] like Figure 1 As shown, this embodiment of the invention proposes a dual-time-constant adaptive neuron circuit for input path control, specifically including a leakage integrator circuit, an actuator, and a dual-exponential adaptive input path control circuit, wherein: The leakage integration circuit is used to receive input signals through the actuator, accumulate the stimulation of the input signals, and release a voltage pulse when the release threshold is reached; The dual-exponential adaptive input path control circuit is used to generate a control signal based on the voltage pulse and output it to the actuator to control the continuous firing frequency of the leakage integral circuit; and to change the rate of change of the control signal based on the voltage pulse. The actuator responds to the control signal to control the continuous firing frequency of the leakage integrator circuit.

[0025] In this example, the leakage integrator circuit includes a volatile threshold resistive memristor and a capacitor. C 1. Resistance R 1. A capacitor is connected in series at one end of the volatile threshold resistive memristor. C 1. Grounded, volatile threshold resistor, memristor, and capacitor. CThe common node of 1 receives the input signal, and the other end of the volatile threshold resistive memristor is connected in series with a resistor. R 1. Grounding, the other end of the volatile threshold resistive memristor and the resistor R The common node outputs a voltage pulse to the dual exponential adaptive input path control circuit.

[0026] In this example, the actuator is an NMOS transistor. M 2. NMOS transistor M The drain of 2 receives the input signal, and the NMOS transistor... M The source of 2 and the input of the leakage integrator circuit (i.e., the volatile threshold resistor memristor and capacitor) C Connected to the common node of 1, NMOS transistor M The gate of 2 is connected to the control signal output terminal of the dual exponential adaptive input path control circuit.

[0027] In this example, the dual-exponential adaptive input path control circuit includes an NMOS transistor. M 3 and PMOS transistors M 1. NMOS transistor M The gate of transistor 3 is connected to the output of the leakage integration circuit, and the NMOS transistor... M The drain of 3 is connected to a capacitor C 2 is connected to the voltage source, NMOS transistor M 3's source is grounded; PMOS transistor M The gate of 1 and the output of the leakage integrator circuit (i.e., the other end of the volatile threshold resistive memristor and the resistor) R 1 (common node) connection, PMOS transistor M The source of 1 is connected to a resistor R 2. Connected to the voltage source, PMOS transistor M The drain of 1 is connected to a capacitor C 3. Connected to the voltage source, PMOS transistor M The source of 1 is also related to the NMOS transistor. M 3's drain and capacitor C The common node of 2 is connected to form the output terminal of the control signal and connected to the NMOS transistor. M 2's gate.

[0028] Based on the above circuit structure description, the principle of this embodiment is as follows: The circuit diagram of the input path control dual-time-constant adaptive neuron circuit described in this embodiment is as follows: Figure 1 As shown, it consists of two parts. The first part is a leakage integrator circuit based on a volatile threshold resistive memristor, specifically: The leakage integration circuit consists of a volatile threshold switching memristor and a pulse readout resistor.R 1. Connected in series, and then to the membrane capacitance of a simulated neuron. C 1. Parallel connection, the whole system is controlled by NMOS transistors. M 2. Receive input signal; volatile threshold resistive memristor and capacitor C The common node connected by 1 is the membrane potential. V mem Node, which is simultaneously connected to NMOS transistors M The source of 2 is connected, and the memristor is connected to the resistor. R 1. Form a resistor voltage divider circuit, with the common connection node serving as the voltage divider node and also as the output pulse. V spike Node; the voltage input signal is a voltage signal. V in NMOS transistor M The drain of 2 is the input terminal. V in NMOS transistor M The gate of 2 is the feedback control terminal. V ctrl able to control M The degree of conduction of 2; The second part is the dual-exponential adaptive input path control circuit. Specifically, the dual-exponential adaptive input path control circuit consists of a capacitor. C 2. Resistance R 2 and capacitor C 3-series PMOS transistors M The parallel section consisting of these three branches is then connected in series with a pull-down NMOS transistor. M It consists of 3 parts.

[0029] Among them, capacitor C 2. C 3 and resistance R The upper end of 2 is connected to the power supply voltage source. V dd ,capacitance C 2's lower end, resistor R 2's lower end, PMOS transistor M 1 source, NMOS transistor M 3 drain and M The node connected to the gate of 2 is the control voltage. V ctrl Used to control NMOS transistors M 2. Gate electrode; simultaneously, PMOS transistor M 1 and NMOS transistors M The gate of 3 is also connected to the output pulse. V spike Nodes are used to control capacitors. C3. Whether it is connected to the circuit; Adaptive input path control circuit for detecting leakage integration circuit V spike The node pulse output pulls down the NMOS transistor when the leakage integrator circuit delivers a pulse. M 3. Turn on to reduce control voltage V ctrl Reduce NMOS transistor M The conduction level of PMOS transistor 2 limits the magnitude of the input current to the neuron and reduces the frequency of continuous pulse firing, thereby achieving adaptive behavior; simultaneously, during pulse firing, the PMOS transistor... M 1. Turn off, so that the capacitor C 3. By removing the time constant from the circuit and reducing it, the time constant of the RC circuit is restored after the pulse ends, thus achieving dual time constant and dual threshold change behavior. The specific process is as follows: Initially, control signal V ctrl High level, NMOS transistor M 2. Conduction. When an input signal is applied to this neuron circuit, charge is released in the capacitor. C Accumulated on 1, V mem Increase. Simultaneously, capacitance... C The charge on 1 passes through the memristor and R 1. Leakage to the ground; when V mem The increase causes the voltage drop of the memristor to reach the threshold voltage. V th The memristor changes to a low resistance state, and the capacitor... C 1. Rapid discharge, in V spike A voltage pulse is generated at the node. V mem The reduction causes the voltage drop of the memristor to decrease to the holding voltage. V hold The memristor switches to a high-resistance state, ending the pulse delivery. This pulse is then transmitted to the NMOS transistor. M 3. And make it conductive, so that V ctrl It becomes smaller. At this time, the NMOS transistor... M 2. The reduced conductivity leads to a smaller input current and slower charging speed in the leakage integrator circuit, which in turn limits the frequency of subsequent neuron pulse firing. After the pulse is delivered, the NMOS transistor... M 3. Turn off again. V ctrl The voltage is increased through an RC circuit. Initially, Vctrl The decrease is greater than the increase, causing the firing frequency of neurons to continuously decrease; when the frequency of neuronal firing pulses decreases to a certain value, V ctrl The decrease will equal the increase, thus stabilizing the frequency of neuron firing pulses, at which point the circuit enters a stable mode. For PMOS transistors... M 1 and capacitor C In the series branch of circuit 3, when the pulse is emitted, the PMOS transistor... M 1 will be turned off, causing the capacitor to... C 3 No longer with capacitors C 2. Resistance R 2 in parallel, and then V ctrl The time constant of the adaptive input path control circuit will decrease when the pulse is reduced; after the pulse ends, the PMOS transistor... M 1 will be re-energized, causing the capacitor to... C 3 and capacitor C 2. Resistance R 2 in parallel, and then V ctrl The time constant of the adaptive input path control circuit will increase again when the input is increased.

[0030] Therefore, this circuit can limit the magnitude of the input current when the neuron fires pulses continuously, thereby gradually suppressing its firing frequency; at the same time, the time constant of the adaptive input path control circuit can also switch between a larger value and a smaller value.

[0031] Figure 2 The control voltage waveform and removal diagram of the input path controlled dual-time constant adaptive neuron circuit described in this invention. Figure 1 PMOS transistor M 1 and capacitor C The control voltage waveform of the single-time-constant adaptive neuron circuit after step 3. First, regarding the control voltage waveform of the dual-time-constant adaptive neuron circuit on the left, for the leakage integrator circuit, at the initial time, V mem When the impedance is 0, the memristor is in a high-resistance state, and at the same time... V ctrl The NMOS transistor is at a high level. M 2 Gate-source voltage V gs = V ctrl - V mem NMOS transistors with voltages greater than their turn-on voltage M 2 is in the ON state, and the leakage integrator circuit is ready to accumulate the input. The input signal...V in Under stimulation, neurons begin to leak integral capacitance. C 1. Charging, while the capacitor C 1. Passing through a memristor and a resistor R The leakage path formed by 1 discharges slowly, overall V mem Increase. When V mem Increase until the voltage drop across the memristor is greater than its threshold voltage. V th The memristor undergoes a resistance change and enters a low-resistance state, the leakage path resistance decreases, and the capacitance... C 1. Discharge rapidly, and in V spike A voltage pulse is generated at the node, and at the same time V mem Rapidly decreased. When V mem Reduce until the voltage drop across the memristor is less than its holding voltage. V hold The memristor returns to the high-resistance state, thus completing one pulse delivery. For the adaptive input path control circuit, the first stage is the pulse delivery phase. During the voltage pulse delivery process of the leakage integrator circuit, when... V spike The node voltage increases until it exceeds that of the NMOS transistor. M At a turn-on voltage of 3, the NMOS transistor M 3. The circuit is turned on and forms a pull-down path, allowing the control signal to... V ctrl The temperature dropped rapidly. At this time, the NMOS transistor... M 2 Gate-source voltage V gs Reduce, NMOS transistor M The reduced conductivity of transistor 2 and the smaller input current to the neuron slow down the subsequent charging speed of the neuron, resulting in a lower frequency of continuous firing and exhibiting adaptive firing behavior. Simultaneously, during pulse firing, the PMOS transistor... M 1. Turn off, so that the capacitor C 3. Removing it from the circuit reduces the time constant of the RC circuit, meaning that at this point... V ctrl It exhibits a rapid exponential decrease. After the pulse output ends, V spike The node is low, NMOS transistor M 3. Turn off, then V ctrl The charge rises slowly through the RC circuit, at which point the leakage integration phase begins. Simultaneously, the PMOS transistor... M 1. Re-energizes the capacitor, causing it to...C 3. When it is reintroduced into the circuit, the time constant of the RC circuit increases, that is, at this time... V ctrl The exponential increase is relatively slow. If subsequent input... V in If it persists, the two stages described above will repeat continuously. However, it should be noted that in the initial stage, due to... V ctrl Larger neurons have larger charging currents and higher firing frequencies, which makes them more efficient. V ctrl The decrease will be greater than the increase, and the charging current of the neuron will continue to decrease, while the firing frequency will continue to decline; when the frequency of the neuron's firing pulses decreases to a certain value, V ctrl The decrease in amplitude will equal the increase in amplitude, thus stabilizing the frequency of neuron firing pulses, at which point the circuit enters steady-state mode. Next, we focus on the control voltage waveform of the single-time-constant adaptive neuron circuit on the right. Its overall workflow is consistent with that of the dual-time-constant adaptive neuron circuit, except that... V ctrl There are some differences in the changes. Specifically, compared to the dual-time-constant adaptive neuron circuit... V ctrl The circuit exhibits a rapid exponential decrease followed by a slower exponential increase. Because the capacitance and resistance of the adaptive input path control circuit in the single-time-constant adaptive neuron circuit are fixed, the time constant of the RC circuit remains constant. V ctrl This will exhibit a single-speed exponential change. Therefore, we can see that, compared to traditional single-time-constant adaptive neuron circuits, dual-time-constant adaptive neuron circuits, by introducing a dual exponential decay mechanism, significantly improve the adaptability of neurons and the performance of LSNN networks. Its fast exponential decay component allows neurons to respond quickly to frequent inputs, while the slow exponential decay component helps maintain memory for longer periods, thus simultaneously addressing both short-term and long-term adaptive needs. Furthermore, the dual-time-constant design makes it more flexible in handling tasks at different time scales and does not require strict time constant matching, enhancing the hardware's tunability and robustness.

[0032] In specific implementations, the volatile threshold resistive switching memristor described in this invention can be a Mott memristor based on Mott phase transition, a diffuse memristor based on a metal conductive filament, or an OTS memristor based on chalcogenides. Further, the Mott memristor can be based on VO2 or NbO. x Devices using E-Motte insulator materials, diffused memristors can be devices based on active metals such as Ag and Cu, while OTS memristors can be chalcogenide devices based on chalcogen elements such as Se and Te.

[0033] Specifically, taking the VO2 MOT memristor as an example, Figures 3 to 6 The present invention provides an input path control dual-time-constant adaptive neuron circuit based on a VO2 volatile threshold resistive Mott memristor under different input voltages. V in Different width-to-length ratios M 2. Different capacitors C 1 and different resistors R Waveform diagram of operation under condition 2. Figure 3 The top image shows the waveform with the original parameters, and the bottom left image shows the waveform with smaller parameters. V in The waveform at that time, the lower right is larger. V in The waveform at that time. It can be observed that when the input voltage increases, the charging current of the neuron at the initial moment increases, and the firing frequency is higher, but correspondingly, V ctrl The rate of decline is also faster; and after stabilization, V ctrl It will become lower than before to limit the larger input current caused by a larger input voltage, and at the same time, the stabilized pulse firing frequency will also be higher. Figure 4 In the middle, the top shows the waveform with the original parameters, and the bottom left shows the waveform with the original parameters. M The waveform when the width-to-length ratio is small is shown in the lower right corner. M 2. Waveform when the width-to-length ratio is large. It can be observed that due to the large width-to-length ratio... M When 2 increases, M 2. Under the same conditions, the conductivity will increase, therefore, at the initial moment, the charging current of the neuron increases, and the firing frequency is higher, but correspondingly, V ctrl The rate of decline is also faster; and after stabilization, V ctrl It will become lower than before to limit the larger input current caused by the larger aspect ratio, and at the same time, the stabilized pulse firing frequency will also be higher. Figure 5 In the middle, the top shows the waveform with the original parameters, and the bottom left shows the waveform with smaller parameters. C The waveform at time 1, with the lower right being the larger one. C The waveform at time 1. It can be observed that... C When 1 increases, it directly increases the time constant of the leakage integrator circuit, thus slowing down the rate at which the neuron reaches the threshold voltage. This significantly reduces the pulse firing frequency of the neuron at various stages. Figure 6 In the middle, the top shows the waveform with the original parameters, and the bottom left shows the waveform with smaller parameters. R The waveform at time 2, with the larger value in the lower right corner. R The waveform at time 2. It can be observed that, due to...R The change of 2 will increase the time constant of the adaptive input path control section, which in turn leads to V ctrl The overall rate of change has slowed down; while V ctrl This is another control signal that limits the input current to the neuron. A slower rate of change in this signal causes the neuron's input current to recover more slowly after the pulse ends, thus reducing the pulse firing frequency. It is particularly important to note that, in order to... V ctrl This allows the phenomenon to be maintained and accumulated across multiple pulses, resulting in an effective and stable adaptive phenomenon. This requires... V ctrl Become relative V mem The "slow variable" refers to ensuring that the time constant of the adaptive input path control circuit is much larger than the time constant of the leakage integral discharging circuit. Therefore, it can be proven that the invention can achieve its purpose under various parameter conditions, demonstrating its adjustability, adaptability, and robustness.

[0034] In summary, this invention proposes a novel adaptive neuron circuit with dual time constants for input path control, applicable to neuromorphic computing. It utilizes a volatile threshold resistive memristor as the core device of a leakage integrator circuit to simulate neuron firing behavior. A transistor is introduced at its input to control the conduction state of the input path. When a neuron fires a pulse, the pulse is transmitted to the simple and low-hardware-overhead adaptive input path control circuit, which controls the transistor to reduce its conduction level, thereby limiting the neuron's input current and reducing its continuous firing frequency, thus achieving adaptive behavior. Simultaneously, using only an additional transistor and capacitor, the capacitor is reduced during pulse input and increased after pulse termination, thereby altering the RC circuit's time constant, achieving dual time constants and dual threshold changes. Compared to traditional single-time-constant adaptive neuron circuits, this invention significantly improves neuron adaptability and LSNN network performance, simultaneously addressing both short-term and long-term adaptive needs, enhancing hardware adjustability and robustness. It is well-suited for integration into large-scale edge computing systems, such as intelligent human-computer interaction systems, enabling efficient computation in resource-constrained application scenarios, and shows great promise for future development.

[0035] The technical solution provided by this invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make several improvements and modifications to this invention without departing from the principles of this invention, and these improvements and modifications also fall within the protection scope of the claims of this invention.

Claims

1. A dual-time-constant adaptive neuron circuit with input path control, characterized in that: This includes a leakage integrator circuit and a dual-exponential adaptive input path control circuit, wherein: The leakage integration circuit is used to accumulate the input signal and release a voltage pulse when the emission threshold is reached. The dual-exponential adaptive input path control circuit is used to generate a control signal based on the voltage pulse to control the continuous firing frequency of the leakage integral circuit, and to change the rate of change of the control signal based on the voltage pulse. The leakage integration circuit includes a volatile threshold resistive memristor and a capacitor. C 1. Resistance R 1. A capacitor is connected in series at one end of the volatile threshold resistive memristor. C 1. Grounded, volatile threshold resistor, memristor, and capacitor. C The common node of 1 receives the input signal, and the other end of the volatile threshold resistive memristor is connected in series with a resistor. R 1. Grounding, the other end of the volatile threshold resistive memristor and the resistor R The common node of 1 outputs a voltage pulse; The dual-exponential adaptive input path control circuit includes an NMOS transistor. M 3 and PMOS transistors M 1. NMOS transistor M The gate of transistor 3 is connected to the output of the leakage integration circuit, and the NMOS transistor... M 3's drain via capacitor C 2 is connected to the voltage source, NMOS transistor M 3's source is grounded; PMOS transistor M The gate of transistor 1 is connected to the output terminal of the leakage integration circuit, and the PMOS transistor is... M The source of 1 is connected to a resistor R 2. Connected to the voltage source, PMOS transistor M The drain of 1 is connected to a capacitor C 3. Connected to the voltage source, PMOS transistor M The source of 1 is also related to the NMOS transistor. M 3's drain and capacitor C The common nodes of 2 are connected to form the output terminal of the control signal.

2. The dual-time-constant adaptive neuron circuit with input path control according to claim 1, characterized in that: The circuit also includes an actuator through which the leakage integrator circuit receives the input signal, and the actuator also responds to the control signal to control the continuous firing frequency of the leakage integrator circuit.

3. The dual-time-constant adaptive neuron circuit with input path control according to claim 2, characterized in that: The actuator uses an NMOS transistor. M 2. NMOS transistor M The drain of 2 receives the input signal, and the NMOS transistor... M The source of transistor 2 is connected to the input terminal of the leakage integrator circuit, and the NMOS transistor... M The gate of 2 is connected to the control signal output terminal of the dual exponential adaptive input path control circuit.

4. The dual-time-constant adaptive neuron circuit with input path control according to any one of claims 1-3, characterized in that: The input signal is a voltage signal.

5. The dual-time-constant adaptive neuron circuit with input path control according to any one of claims 1-3, characterized in that: The volatile threshold resistive switching memristor is a Mott memristor based on Mott phase transition, a diffuse memristor based on a metal conductive filament, or an OTS memristor based on a chalcogenide.

6. The dual-time-constant adaptive neuron circuit with input path control according to claim 5, characterized in that: The Mott memristor is based on VO2 or NbO. x Components.

7. The dual-time-constant adaptive neuron circuit with input path control according to claim 5, characterized in that: The diffuse memristor is an Ag or Cu-based device.

8. The dual-time-constant adaptive neuron circuit with input path control according to claim 5, characterized in that: The OTS memristor is a chalcogenide device based on Se or Te.

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