Computer vision-based motherboard circuit defect detection method and system, and storage medium

Abstract

The application discloses a mainboard circuit defect detection method and system based on computer vision, and a storage medium. The target detection network is used to obtain an element preliminary detection result. The detection result is divided into a high-reliability subset and a to-be-verified subset according to a geometric matching degree in combination with a packaging size and a pin connection relationship analyzed by a circuit design netlist. A circuit topology graph is constructed with the element as a node and the pin connection as an edge. For the to-be-verified element, the position of the high-reliability adjacent element is reversely deduced with a packaging descriptor to generate a corrected detection frame and update the node attribute, and finally a full-amount detection result correction set is formed. On this basis, the pin position connectivity verification based on region growth is performed on each network path, open-circuit defects and adjacent network short-circuit defects are determined, and the detection result carrying the defect position coordinates is generated. The application realizes automatic correction of the mainboard circuit element positioning deviation and accurate detection of the pin-level connectivity defects.

Description

Technical Field

[0001] This invention relates to the field of computer vision, and in particular to a method, system, and storage medium for detecting defects in motherboard circuits based on computer vision. Background Technology

[0002] Currently, motherboard circuit defect detection typically employs a target detection network to process the motherboard circuit image under inspection, directly outputting the category, detection frame position, and detection confidence level of each component. Based on the detection frame position, connectivity analysis is performed on the circuit regions between components to determine open circuits or short circuits. However, target detection networks are prone to component positioning misalignment or misclassification in areas with densely packed components or high component appearance similarity. Furthermore, when relying solely on a single detection frame position for circuit connectivity determination, component positioning deviations are directly transmitted to the circuit defect analysis stage, leading to false alarms or missed detections in the circuit connectivity verification results, significantly limiting the accuracy of defect detection. Summary of the Invention

[0003] This invention provides a method, system, and storage medium for detecting defects in motherboard circuits based on computer vision.

[0004] In a first aspect, embodiments of the present invention provide a computer vision-based method for detecting defects in motherboard circuits, comprising: acquiring a preliminary detection result set, spatial resolution parameters corresponding to the motherboard circuit image to be detected, and a circuit design netlist file; dividing the preliminary detection result set into a high-reliability detection result subset and a test detection result subset based on the geometric matching degree between the detection frame position coordinate sequence of each component in the preliminary detection result set and the standard package size descriptor of the corresponding component category in the component package size descriptor set, and constructing a circuit topology diagram with component identifiers as nodes and pin network connection relationships as edges based on the component pin network connection relationship set; for the target test component in the test detection result subset, identifying high-reliability adjacent components with pin network connection relationships to the target test component in the circuit topology diagram, performing spatial position back-calculation processing using the detection frame position coordinate sequence of the high-reliability adjacent components and the standard package size descriptor of the target test component, generating a corrected detection frame position coordinate sequence of the target test component, and updating the corrected detection frame position coordinate sequence to... In the circuit topology diagram, the detection box position coordinate sequence attribute of the corresponding node is used. After obtaining the full detection result correction set formed by the subset of high reliability detection results and the updated subset of detection results to be verified, the network paths corresponding to the pin network connection relationship in the circuit topology diagram are traversed. The pin position connectivity verification process is performed on the detection box position coordinate sequence of the components at both ends of each network path to generate network path connectivity verification results. Based on the network path connectivity verification results, network paths with open circuit defects of component pins and network path pairs with short circuit defects of adjacent networks are determined. Based on the network paths with open circuit defects of component pins and network path pairs with short circuit defects of adjacent networks, combined with the detection box position coordinate sequence of each component in the full detection result correction set, open circuit defect description information containing the open circuit defect network path identifier and the corresponding component pin position coordinate sequence and short circuit defect description information containing the short circuit defect network path pair identifier and the corresponding short circuit area position coordinate sequence are generated. The open circuit defect description information and the short circuit defect description information are merged and output as the motherboard circuit defect detection result.

[0005] Secondly, embodiments of the present invention provide a computer system, including: a memory for storing computer-executable instructions or computer programs; and a processor for executing the computer-executable instructions or computer programs stored in the memory to implement the above-mentioned computer vision-based motherboard circuit defect detection method.

[0006] Thirdly, embodiments of the present invention provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in the above method.

[0007] The embodiments of the present invention have the following beneficial effects: This invention acquires preliminary detection results and circuit design netlist files, and uses the geometric matching degree between the component detection box position and the standard package size to divide high-reliability detection results and detection results to be verified. It then constructs a circuit topology diagram with components as nodes and pin network connections as edges, introducing circuit logic constraints into the detection result verification process. For the component to be verified, spatial position is reversed based on the known positions of high-reliability adjacent components in the topology diagram and the standard package size descriptor, generating corrected detection box position coordinates to suppress positioning deviations of low-confidence or mismatched package size components. After obtaining the corrected set of all detection results, the network path is traversed to verify pin position connectivity. Based on the connectivity verification results, open-circuit defect network paths and adjacent short-circuit defect network path pairs are identified, allowing defect determination to filter false alarms caused by visual noise using connectivity constraints. Finally, the corrected detection box positions are combined to generate open-circuit defect description information and short-circuit defect description information containing positioning coordinates, and then merged and output. This ensures that the motherboard circuit defect detection results have both visual evidence support and circuit logic consistency under a single image source, effectively improving the accuracy and robustness of defect detection. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the architecture of an application scenario provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the computer system provided in an embodiment of the present invention; Figure 3 This is a logical schematic diagram of the method provided in the embodiments of the present invention.

[0009] Figure 4 This is a flowchart illustrating the motherboard circuit defect detection method based on computer vision provided in an embodiment of the present invention. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing embodiments of the invention only and is not intended to limit the invention.

[0012] See Figure 1 , Figure 1This is a schematic diagram of an architecture for a possible application scenario provided by an embodiment of the present invention. An industrial camera 400 is connected to a computer system 200 via a network 300. The network 300 can be a wide area network (WAN), a local area network (LAN), or a combination of both, using wireless or wired links for data transmission. The industrial camera 400 is used to acquire images of the circuit board to be inspected and send them to the computer system 200; the computer system 200 is used to execute the method provided by the embodiment of the present invention.

[0013] In some embodiments, the computer system 200 can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms. It can also be a distributed computer system on an industrial production line, an edge device, etc., but is not limited to these.

[0014] The computer system implementing the computer vision-based motherboard circuit defect detection method provided in this embodiment of the invention will now be described. (See also...) Figure 2 , Figure 2 This is a schematic diagram of the structure of the computer system provided in an embodiment of the present invention. Figure 2 The computer system shown includes at least one processor 210, memory 250, at least one network interface 220, and an external interface 230. The various components in the computer system 200 are coupled together via a bus system 240. It is understood that the bus system 240 is used to implement communication between these components. In addition to a data bus, the bus system 240 also includes a power bus, a control bus, and a status signal bus. However, for clarity, ... Figure 2 The general labeled all buses as Bus System 240.

[0015] Processor 210 can be an integrated circuit chip with signal processing capabilities, such as a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor can be a microprocessor or any conventional processor, etc.

[0016] External interface 230 may include, for example, one or more speakers and / or one or more visual displays. External interface 230 may also include one or more input devices 232, such as a keyboard, mouse, microphone, touch screen display, camera, etc.

[0017] The memory 250 may be removable, non-removable, or a combination thereof. Exemplary hardware devices include solid-state storage, hard disk drives, optical disk drives, etc. The memory 250 may optionally include one or more storage devices physically located away from the processor 210.

[0018] The memory 250 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), and the volatile memory may be random access memory (RAM). The memory 250 described in this embodiment is intended to include any suitable type of memory.

[0019] In some embodiments, memory 250 is capable of storing data to support various operations, examples of which include programs, modules, and data structures or subsets or supersets thereof, as illustrated below.

[0020] Operating system 251 includes system programs for handling various basic system services and performing hardware-related tasks, such as the framework layer, core library layer, driver layer, etc., for implementing various basic business functions and handling hardware-based tasks; The network communication module 252 is used to reach the industrial camera via one or more (wired or wireless) network interfaces 220, exemplary network interfaces 220 including: Bluetooth, WiFi, and Universal Serial Bus (USB), etc. Presentation module 253 is configured to enable the display of information (e.g., external interface for operating peripheral devices and displaying content and information) via one or more output devices 231 (e.g., display screen, speaker, etc.) associated with external interface 230; The input processing module 254 is used to detect and translate one or more user inputs or interactions from one or more input devices 232.

[0021] The following describes the motherboard circuit defect detection method based on computer vision provided by embodiments of the present invention. In practical implementation, the motherboard circuit defect detection method based on computer vision provided by embodiments of the present invention can be implemented by a computer system. See also Figure 3 and Figure 4 The motherboard circuit defect detection method based on computer vision provided in this embodiment of the invention may include the following steps: Step S100: Obtain the preliminary detection result set, the spatial resolution parameters corresponding to the motherboard circuit image to be detected, and the circuit design netlist file. The preliminary detection result set is output by the target detection network after processing the motherboard circuit image to be detected. It includes the component category descriptor, detection box position coordinate sequence, and detection confidence of each component. The circuit design netlist file is parsed to obtain the component package size descriptor set and the component pin network connection relationship set.

[0022] The preliminary detection result set is output by the target detection network after forward inference of the motherboard circuit image to be detected. The target detection network adopts a single-stage detection architecture based on anchor points, which is composed of three cascaded parts: a backbone feature extraction network, a neck feature fusion network, and a detection head.

[0023] For example, the backbone feature extraction network can adopt a cross-stage local network structure. By dividing the feature map of the base layer into two parts, one part undergoes dense convolution processing, and the other part is directly passed and concatenated in the channel dimension for output, thereby reducing computational bottlenecks and enhancing gradient flow. The backbone network may contain, for example, five downsampling stages, each consisting of multiple stacked residual convolutional units. Each residual convolutional unit contains a pointwise convolutional layer and a depthwise convolutional layer, followed by a batch normalization layer and a linear unit activation function with leakage correction, ultimately outputting feature maps of five different spatial resolutions. The neck feature fusion network adopts a bidirectional fusion structure of a path aggregation network and a feature pyramid network, containing two information propagation paths: top-down and bottom-up. In the top-down path, deep low-resolution feature maps are upsampled using bilinear interpolation and concatenated with adjacent shallow high-resolution feature maps in the channel dimension. Then, a pointwise convolutional layer compresses the number of channels to a preset value. In the bottom-up path, shallow feature maps are downsampled using convolutions with a stride of 2 and concatenated with adjacent deep feature maps, also undergoing pointwise convolution to compress the number of channels. The neck network outputs three feature maps at different scales, responsible for detecting large, medium, and small components, respectively. The detection head employs a decoupled structure, predicting the offsets of three prior anchor boxes for each feature map grid cell. The decoupled detection head separates the classification and regression tasks into two independent branches. The classification branch contains two stacked pointwise convolutional layers, with the number of output channels equal to the total number of component categories. The regression branch also contains two stacked pointwise convolutional layers, with the number of output channels equal to four times the number of anchor boxes, corresponding to the bounding box center coordinate offset, width scaling factor, and height scaling factor, respectively. Additionally, a confidence branch is included, with the number of output channels equal to the number of anchor boxes, representing the probability of a target object existing within each predicted box.

[0024] For example, during the training phase, supervised training is performed using a dataset containing a massive number of motherboard circuit images and their corresponding annotations. The training data covers circuit board samples with various layout densities and component package types. The annotation information includes the bounding box coordinates and component category identifier for each component. The loss function used during training can be composed of a weighted sum of three parts: the bounding box regression loss uses the full intersection-union loss function, directly optimizing the center point distance and aspect ratio consistency between the predicted and ground truth boxes; the classification loss uses the binary cross-entropy loss function; and the confidence loss uses the binary cross-entropy loss function. The optimizer uses the stochastic gradient descent algorithm with momentum, and the momentum coefficient and weight decay coefficient can be set according to actual needs. During training, a cosine annealing learning rate decay strategy can be used, gradually decaying to one-thousandth of the initial learning rate in the last few training epochs. After each training epoch, the average precision metric is calculated using the validation set. If this metric does not improve within several consecutive epochs, an early stopping mechanism is triggered. Data augmentation strategies include random horizontal flipping, random scaling, mosaic data augmentation, and hue, saturation, and brightness transformations to improve the model's robustness to changes in illumination and scale.

[0025] During the inference application phase, before inputting the motherboard circuit image to be detected into the trained target detection network, the image resolution is uniformly scaled to a preset size. The input image data needs to undergo pixel value normalization, that is, the original pixel values ​​in the range of 0 to 255 are divided by 255 and scaled to the range of 0 to 1. After the target detection network outputs dense prediction results on three feature maps, it needs to undergo decoding to convert the offset output by the network into bounding box coordinates relative to the original image coordinate system. The decoding process involves multiplying the center coordinate offset of the network output by a preset step size and adding it to the coordinate of the upper left corner of the grid cell, and multiplying the width and height scaling factor by the preset width and height of the corresponding anchor box. All predicted boxes after decoding undergo non-maximum suppression to filter out duplicate detections and low-confidence detections. The final retained detection results constitute the preliminary detection result set. Each detection record in this set corresponds to a component and contains three information fields: the component category descriptor is an identifier string that represents the type of the component package, such as a string identifying a 0805 packaged capacitor or a string identifying a QFP packaged integrated circuit; the detection box position coordinate sequence is a quadruple consisting of four integer pixel coordinate values, which correspond in order to the x-coordinate of the top left corner, y-coordinate of the top left corner, x-coordinate of the bottom right corner, and y-coordinate of the bottom right corner of the bounding box; and the detection confidence is a floating-point value between 0 and 1, reflecting the model's confidence in the presence of a component of the corresponding category within the detection box.

[0026] The spatial resolution parameter corresponding to the image of the motherboard circuit under test defines the actual physical distance represented by a single pixel in the image. It is a calibration coefficient that connects the image pixel space with the real physical space. This parameter can be obtained by consulting the factory calibration certificate of the industrial camera and lens, or by calculating it by photographing a standard calibration board of known physical dimensions under the same imaging conditions. Specifically, two feature points with a known distance are selected on the calibration board, their pixel distance in the image is measured, and the physical distance is divided by the pixel distance to obtain the resolution value per pixel in micrometers.

[0027] A circuit design netlist file is a standardized text file output by circuit design automation software. Internally, it describes the package information and pin network connections of all components on a circuit board using a structured syntax. The parsing process of this netlist file first identifies the file format version and determines the parsing rule to use based on the format identifier header. If it is a general netlist format, the file content is organized alternately with component declaration sections and network connection declaration sections. In the component declaration section, each component declaration statement is enclosed in a pair of parentheses. The parser uses a finite state machine to identify the field separators within the parentheses and extract the fields. The state machine initially operates in an idle state. When it reads a left parenthesis, it enters the component parsing state, where tokens are read sequentially. The first token is the component identifier, followed by the component package name or package code. The parser uses the package code as an index key to search and match in a pre-built component package specification library. This specification library is organized in the form of a data table, with each record storing a package code and its corresponding standard package width and height dimension ranges. The standard package width dimension range is defined by minimum and maximum width values, representing the allowable physical size range of the package along the reference horizontal axis in the circuit board plane. The standard package height dimension range is defined by minimum and maximum height values, representing the allowable physical size range along the reference vertical axis. When a matching record is found, the parser stores the range value along with the package designation into the component package size descriptor set, using the component identifier as the index key. In the network connection declaration section, each network declaration statement is also enclosed in parentheses, with the network name and pin reference list separated by a field separator. The pin reference list consists of several pairs of component identifiers and pin identifiers. The parser uses a recursive descent method to peel off each pair of references sequentially, generating a series of paired pin connection relationship records. Each record contains a first component identifier, a first pin identifier, a second component identifier, a second pin identifier, and a common network identifier. All records are combined to form the component pin network connection relationship set, which essentially defines the electrical network connectivity topology between the pins of various components on the circuit board.

[0028] Step S200: Based on the geometric matching degree between the detection frame position coordinate sequence of each component in the preliminary detection result set and the standard package size descriptor of the corresponding component category in the component package size descriptor set, the preliminary detection result set is divided into a high-reliability detection result subset and a test result subset to be verified. Based on the component pin network connection relationship set, a circuit topology diagram is constructed with component identifiers as nodes and pin network connection relationships as edges. Each node in the circuit topology diagram carries the detection frame position coordinate sequence of the corresponding component and the component category descriptor as node attributes.

[0029] In one implementation, step S200 may specifically include the following steps S210 to S260: Step S210: For each component in the preliminary test result set, extract the standard package size descriptor with the same component category identifier as the component category descriptor from the component package size descriptor set. The standard package size descriptor includes the standard package width dimension range and the standard package height dimension range.

[0030] The system iterates through each detected component record in the preliminary detection result set, using the component category descriptor of the current component record as the query keyword to perform an exact match search in the component package size descriptor set. The component category descriptor in the preliminary detection results is stored as a category name string corresponding to the category index number output by the target detection network. This string uses the same naming convention as the package code stored in the component package size descriptor set to ensure direct string equality comparison. When a match is found, a standard package size descriptor structure corresponding to that category is extracted. This structure contains two physical size range members: a standard package width dimension range and a standard package height dimension range. The standard package width dimension range is described by a left boundary value and a right boundary value. The left boundary value is the minimum physical size allowed for the component of this category packaged in the circuit board plane along a preset width reference direction, and the right boundary value is the maximum physical size allowed. The standard package height dimension range is also described by a left boundary value and a right boundary value, corresponding to the minimum and maximum physical sizes along a preset height reference direction, respectively. These two ranges are derived from the package specifications or industry standard package specifications provided by the component manufacturer, reflecting the space required for the standard pad layout of this package type.

[0031] Step S220: Based on the spatial resolution parameters, convert the standard package width direction dimension range and the standard package height direction dimension range into pixel standard width range and pixel standard height range in pixels.

[0032] To establish comparability between the physical size constraints of components and the detection box size in the image domain, the spatial resolution parameter obtained in step S100 is used for dimensional conversion. The spatial resolution parameter records the physical side length corresponding to a unit pixel, and its value records the spatial span represented by each pixel on the circuit board plane. The conversion process involves dividing the physical size value of the standard package width dimension range by the spatial resolution parameter, and the quotient is the left boundary value of the standard pixel width dimension range; the right boundary value of the standard package width dimension range is divided by the spatial resolution parameter, and the quotient is the right boundary value of the standard pixel width dimension range. These two boundary values ​​together define the standard pixel width dimension range, representing the ideal range within which the detection box width of this type of component should fall when counted in pixels in the image. Similarly, the same division operation is performed on the left and right boundary values ​​of the standard package height dimension range to obtain the left and right boundary values ​​of the standard pixel height dimension range, defining the reasonable numerical range of the detection box height at the pixel level. This dimensional conversion ensures that the physical design rules can be directly applied in the image processing flow.

[0033] Step S230: Calculate the width span and height span of the area enclosed by the detection frame position coordinate sequence of the element, and determine whether the width span falls within the standard pixel width range and whether the height span falls within the standard pixel height range. When both results fall within the range, generate a package size matching status indicator indicating that the package size matches. When either result does not fall within the range, generate a package size mismatch status indicator indicating that the package size does not match.

[0034] For the currently processed element, its detection box position coordinate sequence consists of four values: the top-left x-coordinate, the top-left y-coordinate, the bottom-right x-coordinate, and the bottom-right y-coordinate. The width span is calculated by subtracting the top-left x-coordinate from the bottom-right x-coordinate; the difference represents the number of pixels the detection box spans horizontally in the image. The height span is calculated by subtracting the top-left y-coordinate from the bottom-right y-coordinate; the difference represents the number of pixels the detection box spans vertically in the image. After obtaining these two dimensions, a dual-interval inclusion check is performed. The first check compares the width span with the standard pixel width interval, checking if the width span is greater than or equal to the left boundary value and less than or equal to the right boundary value of the standard pixel width interval. The second check compares the height span with the standard pixel height interval, checking if the height span is greater than or equal to the left boundary value and less than or equal to the right boundary value of the standard pixel height interval. A package size matching status indicator is generated if and only if both the width and height span dimensions fall within their respective pixel standard ranges. If either of these ranges is not within the specified range, a package size mismatch status indicator is generated. The logical value of the package size matching status indicator is used to drive subsequent traffic classification decisions.

[0035] Step S240: When the generated package size matching status indicator indicates that the package size is matched, the detection confidence of the component is compared with the preset high confidence benchmark range. When the detection confidence is within the high confidence benchmark range, the component category descriptor, detection frame position coordinate sequence and detection confidence of the component are included in the high reliability detection result subset. When the detection confidence is outside the high confidence benchmark range, the component is included in the test result subset to be verified.

[0036] The high-confidence benchmark range is a pre-calibrated and defined confidence threshold interval. The lower limit of the interval is determined by statistically analyzing the confidence distribution of correctly detected samples on the validation set by the target detection network, ensuring that the confidence of the vast majority of correctly detected samples falls above this lower limit. The upper limit of the interval is 1.0. When the component's package size matching status indicator signifies a package size match, its detection confidence value is further reviewed. The detection confidence value is compared with the lower limit of the high-confidence benchmark range. If the detection confidence is greater than or equal to the lower limit, it is determined that the detection confidence is within the high-confidence benchmark range. This indicates that the target detection network has high reliability in both category identification and position regression for the component, and its detection frame size is consistent with the physical package specifications. Both verifications pass. Therefore, the complete detection record of the component, including the component category descriptor, detection frame position coordinate sequence, and detection confidence, is included in the high-reliability detection result subset. If the detection confidence level is less than the lower limit of the high confidence benchmark range, even if the package size matches the specifications, it will still be included in the subset of test results to be verified, so that further verification can be carried out using the circuit topology relationship.

[0037] Step S250: When the generated package size matching status indicator indicates that the package size does not match, the component category descriptor, detection box position coordinate sequence and detection confidence of the component are directly included in the subset of the detection results to be verified.

[0038] Package size mismatch means that the spatial range covered by the bounding box predicted by the target detection network deviates from the standard package size range that the component category should have. This deviation may be caused by various factors, such as component mounting misalignment, visual feature weakening due to pad surface oxidation, mutual occlusion between adjacent components, or regression error of the network itself. Regardless of the cause of the deviation, detection results with package sizes that do not meet design specifications cannot be directly accepted as high-reliability results. Therefore, no secondary judgment is made on its detection confidence. The component category descriptor, detection box position coordinate sequence, and detection confidence of this component are all directly included in the subset of detection results to be verified, and left for subsequent steps to perform position back-inference and correction based on topological adjacency relationships.

[0039] Step S260: After classifying all components, generate a circuit topology diagram based on the component pin network connection relationship set, with each component identifier as a node and the pin network connection relationship between any two component identifiers as edges. For each component classified into the high reliability test result subset, locate the corresponding node in the circuit topology diagram and write the detection box position coordinate sequence of the component into the detection box position coordinate sequence attribute of the node. For each component classified into the test result subset to be verified, locate the corresponding node in the circuit topology diagram and set the test status mark to be verified. Use the high reliability test result subset, the test result subset to be verified, and the circuit topology diagram carrying the test status mark to be verified as input for subsequent processing.

[0040] For example, the generation of a circuit topology diagram can employ a graph data model based on an adjacency list. First, an empty graph structure object is initialized. This object internally maintains a node dictionary and an edge list. The node dictionary stores node objects with component identifiers as keys, and the edge list stores each edge object representing a pin network connection. Each connection record in the component pin network connection set is traversed, extracting the first and second component identifiers. For each component identifier that has not appeared before, a new node object is created in the node dictionary with that identifier as the key. The node object's attribute set includes three attribute fields: the detection box position coordinate sequence, the component category descriptor, and the status flag to be verified. Initially, all attributes are empty or default values. Then, an undirected edge is added to the edge list. The two endpoints of this undirected edge are bound to the node objects corresponding to the first and second component identifiers, respectively. The edge object's attributes record the first pin identifier, the second pin identifier, and the network identifier corresponding to this connection. Once all connection records have been traversed, the circuit topology diagram is constructed.

[0041] Next, attribute backfilling is performed to fuse and align the visual information from the preliminary detection results with the topology information from the netlist file at the node level. Each component record in the high-reliability detection result subset is traversed, and the corresponding node object is located in the node dictionary using the component identifier in the component record as the key. The four coordinate values ​​of the detection box position coordinate sequence of that component record are written into the detection box position coordinate sequence attribute field of the node object, and the component category descriptor is written into the component category descriptor attribute field. The pending verification status flag remains set to indicate a state where verification is not required. Subsequently, each component record in the pending verification detection result subset is traversed, and after locating the corresponding node object in the node dictionary, the component category descriptor is written into the attribute field. The pending verification status flag is set to indicate a state where verification is required, and the detection box position coordinate sequence is temporarily written as the original coordinate sequence from the preliminary detection results. At this point, each node in the circuit topology diagram contains both its electrical connection context in the circuit and carries visual detection status and position information from the target detection network.

[0042] As one implementation, in step S260, before using the subset of high-reliability detection results, the subset of detection results to be verified, and the circuit topology diagram carrying the status flag to be verified as input for subsequent processing, the following steps S261 to S266 may also be included: Step S261: Arrange all elements in the subset of test results to be verified in descending order of detection confidence to generate an ordered sequence of elements to be verified. Elements that appear earlier in the ordered sequence of elements to be verified have higher detection confidence.

[0043] The sorting process employs a descending sorting algorithm based on detection confidence scores. The detection confidence field of each element record in the subset of detection results to be verified is extracted as the sorting key. If two records have the same detection confidence, the lexicographical order of the element identifiers is used as the secondary sorting key to ensure result determinism. The sorting algorithm can be implemented using introspection sort or merge sort. After sorting, a linearly ordered data structure is formed, i.e., an ordered sequence of elements to be verified. The earlier an element appears in the sequence, the higher its detection confidence score, indicating a stronger grasp of its prediction results by the target detection network. Therefore, it should receive priority in the subsequent topology-based correction process.

[0044] Step S262: Select the current component to be verified sequentially from the ordered sequence of components to be verified. Traverse the adjacent nodes that have a direct edge connection with the node where the current component to be verified is located in the circuit topology diagram. Obtain the verification status marking of each adjacent node. When there is at least one adjacent node that does not have a verification status marking and belongs to the high reliability detection result subset, mark the current component to be verified as a component to be reversed and corrected, and establish a direct correction reference binding relationship between the component to be reversed and the adjacent nodes that meet the conditions.

[0045] The components to be verified are selected sequentially from front to back according to their ordered sequence. For each selected component, its corresponding node is located in the circuit topology diagram. Then, by traversing all edges connected to that node, a set of all its adjacent nodes is obtained. For each adjacent node in the set, its verification status flag field is checked. If the verification status flag of an adjacent node indicates that verification is not required, and the component record corresponding to that adjacent node exists in the high reliability detection result subset, then that adjacent node is determined as a reference node that meets the conditions. Once at least one such reference node is found, the processing status flag of the current component to be verified is immediately updated to the component to be reverse-engineered for correction, and a direct correction reference binding relationship record is constructed. This direct correction reference binding relationship record contains the identifier field of the component to be reverse-engineered for correction and the identifier field of the reference node, clarifying the spatial position calculation dependency between the two. The direct correction reference binding relationship means that the precise position of the component to be reverse-engineered for correction can be calculated backwards using the known high reliability position information of the reference node, based on the pin-level topology constraints between the two.

[0046] Step S263: When there are no adjacent nodes that meet the conditions, continue to check whether each adjacent node has been marked as a component to be back-pushed and corrected. When at least one adjacent node has been marked as a component to be back-pushed and corrected, establish a cascaded correction reference binding relationship between the current component to be verified and the marked component to be back-pushed and corrected.

[0047] If, after traversing all adjacent nodes of the element to be verified, no node is found that simultaneously satisfies the condition of being verified being marked as "no" and belongs to a subset of the high reliability detection results, then the process checks the adjacent node set for nodes whose processing state has been marked as elements to be corrected. Although such nodes have not yet completed their own position correction, they have established a correction dependency chain with high reliability nodes in the current or previous round. If at least one such node exists, one is selected as a cascade reference node, and a cascade correction reference binding relationship record is established. The cascade correction reference binding relationship record also includes the current element to be verified identifier field and the reference element identifier field, and additionally includes a cascade flag to indicate that the binding relationship belongs to an indirect correction chain. This mechanism allows position correction information to propagate gradually along the topology edges, enabling elements to be verified that are not directly adjacent to high reliability nodes to obtain correction references through the cascade transmission of intermediate nodes.

[0048] Step S264: When there are no adjacent nodes that do not have a status mark to be verified and belong to the subset of high reliability detection results, and there are no adjacent nodes that have been marked as elements to be reversed and corrected, the current element to be verified is kept in the ordered sequence of elements to be verified and re-selected in order after all elements in this round are selected.

[0049] When neither of the two types of neighboring nodes with reference capabilities exists, it indicates that all neighboring nodes surrounding the element to be verified in the topology graph are currently in a state of pending verification and no corrective binding relationships have been established. Due to the lack of a reliable position reference source, it is impossible to effectively calculate the position of the element to be verified at this time. Therefore, the element is temporarily left unprocessed and preserved in its original position within the ordered sequence of elements to be verified. After the sequential selection of all elements in the sequence is completed in this round, there may still be some elements that have not been processed. At this point, the process returns to the beginning of the sequence and a new round of sequential selection begins. This multi-round iterative strategy allows the reference conditions of the surrounding neighboring nodes to be gradually satisfied in subsequent rounds as some elements are successfully bound.

[0050] Step S265: If no new direct correction reference binding relationship or cascade correction reference binding relationship is successfully established after all components are selected in this round, all currently retained components in the ordered sequence of components to be verified are marked as uncorrectable components, and the uncorrectable components are removed from the sequence, terminating the re-selection process; otherwise, continue to the next round of sequential selection process.

[0051] At the end of each round of complete sequence selection, the total number of newly established direct correction reference bindings and cascade correction reference bindings is counted. If this total is zero, it means that after one round of traversal, no new correction dependency relationship has been established between any component to be verified and its adjacent nodes, the topology propagation link has reached saturation, and the remaining components to be verified are located in an area of ​​isolated nodes in the circuit topology diagram, unable to be connected to high-reliability nodes by any path. In this case, all components still remaining in the ordered sequence of components to be verified are marked as uncorrectable components, removed from the sequence, and a global termination flag is set to indicate the end of the re-selection loop. Conversely, if at least one new binding relationship has been established in this round, it means the correction chain is still expanding, the loop has not terminated, and the next round of sequential selection processing begins.

[0052] Step S266: Based on the established direct correction reference binding relationship and cascade correction reference binding relationship, set the processing priority of the component to be corrected that has a direct correction reference binding relationship to be higher than that of the component to be corrected that has a cascade correction reference binding relationship, and rearrange the ordered sequence of components to be verified in descending order of processing priority.

[0053] The priority allocation logic is based on the reliability hierarchy of the correction reference. Components to be corrected that have direct correction reference binding relationships have reference nodes directly derived from a subset of high-reliability test results, and their location information has the highest reliability, thus receiving a higher processing priority. Components to be corrected that have cascaded correction reference binding relationships have reference sources passed through one or more layers of components to be verified, posing a risk of error accumulation, and therefore receiving a lower processing priority. The rearrangement operation first traverses all established direct correction reference binding relationships, collecting the identifiers of the components to be corrected involved into a first priority list; then it traverses all cascaded correction reference binding relationships, collecting the identifiers of the components to be corrected involved into a second priority list. The first and second priority lists are merged sequentially to obtain a rearranged ordered sequence of components to be verified. In this sequence, all components with direct correction references are listed first, followed by components with cascaded correction references, while components without either direct or cascaded relationships have been removed in step S265.

[0054] As one implementation, after rearranging the ordered sequence of elements to be verified according to processing priority from high to low in step S266, the following steps S267 to S2613 may also be included: Step S267: According to the order of the rearranged ordered sequence of the elements to be verified, select the elements to be corrected that have direct correction reference binding relationship in turn, and obtain the detection box position coordinate sequence of the adjacent node pointed to by its direct correction reference binding relationship as the direct reference position coordinate sequence.

[0055] The elements to be back-reamed that belong to the first priority group and have direct correction reference binding relationships in the rearranged ordered sequence of elements to be verified are locked and processed one by one in order. For the currently selected element to be back-reamed, the adjacent node is located in the circuit topology diagram based on the reference node element identifier stored in its direct correction reference binding relationship record, and the coordinate quadruple stored in its detection box position coordinate sequence attribute field is read. This coordinate quadruple contains the precise position boundary of the high-reliability adjacent element in the image and is directly extracted as the direct reference position coordinate sequence.

[0056] Step S268: Obtain the standard package size descriptor corresponding to the component category descriptor of the component to be reversed from the component package size descriptor set; read the offset direction vector and offset distance of each pin of the component to be reversed relative to the package geometric center in the standard package size descriptor; select the corresponding offset direction vector and offset distance according to the specific pin network connection relationship between the component to be reversed and the adjacent node.

[0057] The component category descriptor of the component to be reverse-engineered is used to query the corresponding standard package size descriptor in the component package size descriptor set. This standard package size descriptor not only includes the overall width and height dimensions of the package but also embeds a pin geometry information list. For each pin number in the package, this list records the theoretical offset direction vector and theoretical offset distance of the pin pad center relative to the package's geometric center. The offset direction vector is a two-dimensional unit direction vector indicating the direction from the package's geometric center to the pin pad center within the circuit board plane; the offset distance is the straight-line physical distance from the package's geometric center to the pin pad center. To determine which pair of offset direction vectors and offset distances to use, the pin identifier pairs recorded on the connecting edges between the component to be reverse-engineered and the adjacent nodes used as references are read from the circuit topology diagram to confirm the pin numbers involved in the connection on the component side. Then, this pin number is matched and searched in the pin geometry information list to extract the corresponding offset direction vector and offset distance parameters.

[0058] Step S269: Based on the spatial resolution parameters, convert the selected offset distance into a pixel offset distance in pixels.

[0059] Divide the offset distance value obtained in step S268 (in physical dimensions) by the spatial resolution parameter; the quotient is the pixel offset distance (in pixels). This pixel offset distance represents the theoretical pixel span between the center of the pin pad and the geometric center of the package in the image coordinate system.

[0060] Step S2610: Using the geometric center coordinate point of the direct reference position coordinate sequence as the origin of the operation, reverse the selected offset direction vector and multiply it by the pixel offset distance to obtain the displacement vector. Superimpose the displacement vector with the origin of the operation to obtain the predicted geometric center coordinate point of the element to be reversed.

[0061] First, the geometric center coordinates of the direct reference position coordinate sequence are calculated. The x-coordinate of the geometric center is obtained by summing the x-coordinates of the top-left and bottom-right corners of the direct reference position coordinate sequence and dividing by 2; the y-coordinate is obtained by summing the y-coordinates of the top-left and bottom-right corners and dividing by 2. This step yields the pixel center position of the high-reliability adjacent element detection frame, which serves as the reference origin for subsequent calculations. Then, geometric inversion is performed based on the physical connection relationship: two pin pads connected by wires are physically close or aligned in the circuit board design. Since the pin position of the reference element is known, the pin position of the element to be corrected should be spatially adjacent to the corresponding pin position of the reference element. Therefore, the theoretical direction pointing from the geometric center of the reference element to the corresponding pin of the element to be corrected should be the opposite direction from the geometric center of the element to be corrected to the direction of that pin. Accordingly, the two components of the offset direction vector obtained in step S268 are negativeed to obtain an inverted direction vector. This inverted direction vector is then multiplied by the pixel offset distance obtained in step S269 using a scalar multiplication, that is, each component of the direction vector is multiplied by the pixel offset distance to obtain a displacement vector. The starting point of this displacement vector is the geometric center of the reference element, and the ending point points to the predicted position of the geometric center of the element to be corrected. This displacement vector is then vector-superimposed with the coordinates of the origin of the calculation, that is, the horizontal coordinates are added together and the vertical coordinates are added together. The result is the coordinate point of the predicted geometric center of the element to be corrected.

[0062] Step S2611: Based on the spatial resolution parameters, convert the standard package width direction dimension range and the standard package height direction dimension range in the standard package size descriptor into the standard pixel width range and the standard pixel height range. Using the predicted geometric center coordinate point as the center, combine the standard pixel width range and the standard pixel height range to generate the predicted detection box position coordinate sequence surrounding the predicted geometric center coordinate point.

[0063] The predicted geometric center coordinates need to be expanded from a point to a bounding box. First, using the same method as in step S220, the standard package width dimension range is converted to a pixel standard width range, and the standard package height dimension range is converted to a pixel standard height range, utilizing spatial resolution parameters. Since the physical package size range provides a reasonable width and height range for the component from the pad boundary to the other side pad boundary, the median value of the pixel standard width range is taken as the width of the predicted detection box, and the median value of the pixel standard height range is taken as the height of the predicted detection box. Then, using the predicted geometric center coordinates as the center of the rectangle, the rectangle is expanded to the left by half the predicted detection box width to obtain the upper left x-coordinate, expanded upwards by half the predicted detection box height to obtain the upper left y-coordinate, expanded to the right by half the predicted detection box width to obtain the lower right x-coordinate, and expanded downwards by half the predicted detection box height to obtain the lower right y-coordinate. These four coordinate values ​​are sequentially arranged to form the predicted detection box position coordinate sequence.

[0064] Step S2612: Calculate the spatial intersection-union ratio between the predicted detection box position coordinate sequence and the original detection box position coordinate sequence of the element to be reversed. When the spatial intersection-union ratio is lower than the preset overlap reference, the predicted detection box position coordinate sequence is used as the corrected detection box position coordinate sequence. When the spatial intersection-union ratio is not lower than the preset overlap reference, the original detection box position coordinate sequence is retained as the corrected detection box position coordinate sequence.

[0065] The spatial intersection-union ratio (IUGR) is used to measure the geometric consistency between the predicted detection box and the original detection box. The calculation process first determines the intersection region of the two rectangles: the x-coordinate of the top-left corner of the intersection is the larger of the x-coordinates of the top-left corners of both boxes; the y-coordinate is the larger of the y-coordinates of the top-left corners of both boxes; and the x-coordinate and y-coordinate are the smaller of the x-coordinates and y-coordinates of the bottom-right corners of both boxes. If both the x-coordinate and y-coordinate of the bottom-right corner are greater than or equal to the x-coordinate and y-coordinate of the bottom-right corner, the intersection area can be calculated by multiplying the intersection width by the intersection height; otherwise, the intersection area is 0. The union area equals the sum of the predicted detection box area and the original detection box area minus the intersection area. The spatial IUGR is the intersection area divided by the union area. A preset overlap threshold is a predetermined IUGR threshold used to define whether the predicted box and the original box spatially overlap. When the spatial intersection-union ratio (IUGR) is below this threshold, it indicates a significant difference between the predicted and original detection locations, suggesting that the original detection boxes may be inaccurately located. Therefore, the predicted detection box coordinate sequence derived from the topological relationship is adopted as the corrected detection box coordinate sequence. When the IUGR is not lower than this threshold, it indicates a good match between the prediction and the original results, suggesting that the original detection boxes themselves have reliable positional accuracy. Therefore, the original detection box coordinate sequence is retained as the corrected detection box coordinate sequence.

[0066] Step S2613: Write the corrected detection box position coordinate sequence into the detection box position coordinate sequence attribute of the node corresponding to the element to be reversed in the circuit topology diagram, and clear the node's verification status mark.

[0067] Regardless of whether the corrected detection box position coordinate sequence comes from the back-propagation prediction or retains the original coordinates, this coordinate sequence is overwritten into the detection box position coordinate sequence attribute field of the node corresponding to the element to be corrected in the circuit topology diagram. Simultaneously, the node's pending verification state is updated to indicate a state where verification is not required, signifying that the element has transitioned from a pending verification state to a confirmed state, and its position information can subsequently be used as a reference source for other elements to be verified. This clearing operation allows the correction chain to continue propagating to deeper adjacent nodes in subsequent iterations.

[0068] Step S300: For the target component to be verified in the subset of test results, identify the high-reliability adjacent components that have pin network connections with the target component to be verified in the circuit topology diagram. Use the detection box position coordinate sequence of the high-reliability adjacent components and the standard package size descriptor of the target component to perform spatial position back-calculation to generate the corrected detection box position coordinate sequence of the target component to be verified. Update the corrected detection box position coordinate sequence to the detection box position coordinate sequence attribute of the corresponding node in the circuit topology diagram.

[0069] In one implementation, step S300 may specifically include the following steps S310 to S370: Step S310: In the circuit topology diagram, search for all adjacent nodes that have a direct edge connection with the node where the target component to be verified is located and do not have a verification status marker, and determine them as high-reliability adjacent components.

[0070] In the circuit topology diagram, locate the node corresponding to the target component to be verified, traverse all edges associated with that node, and collect the node identifier of each edge's peer node. For each adjacent node, check its verification status flag field. If the flag indicates that the node does not need verification, add this adjacent node to the high-reliability adjacent component candidate list. After all edges have been traversed, the high-reliability adjacent component candidate list contains component nodes that are directly connected to the target component to be verified in the topology and whose own position information has been confirmed as reliable. These nodes constitute a reference set for spatial location inference.

[0071] Step S320: Extract the detection frame position coordinate sequence of each high-reliability adjacent component and calculate its geometric center coordinate point. At the same time, based on the component category descriptor of the target component to be verified, obtain the corresponding standard package size descriptor from the component package size descriptor set, and read the offset direction vector and offset distance set of each pin relative to the package geometric center from the standard package size descriptor.

[0072] For each component in the high-reliability adjacent component candidate list, its detection frame position coordinate sequence is read, and the horizontal and vertical coordinates of the geometric center are calculated using the coordinates of the upper left and lower right corners, in the same way as the aforementioned geometric center extraction method. Simultaneously, based on the component category descriptor of the target component to be verified, the corresponding standard package size descriptor is retrieved from the component package size descriptor set, and a complete list of pin geometry information is extracted from it. This list establishes a mapping from each pin number to its offset direction vector and offset distance; multiple pins constitute a set of offset direction vectors and offset distances.

[0073] Step S330: Based on the spatial resolution parameter, convert each offset distance in the offset distance set into a pixel offset distance in pixels to obtain the pixel offset distance set.

[0074] Using the same method as the previous steps, each offset distance recorded in physical units in the offset distance set is divided by the spatial resolution parameter to generate a corresponding pixel offset distance. All pixel offset distances are then summarized into a pixel offset distance set. Each element in this set corresponds one-to-one with a pin number and is selected for use according to the pin in subsequent calculations.

[0075] Step S340: For each high-reliability adjacent element, based on the pin network connection relationship between the high-reliability adjacent element and the target element to be verified, select the offset direction vector and pixel offset distance of the corresponding pin from the set of offset direction vectors and pixel offset distances. Using the geometric center coordinate point of the high-reliability adjacent element as the base point, multiply the selected offset direction vector by the selected pixel offset distance to obtain the displacement vector. Then, superimpose the displacement vector with the base point to obtain a candidate coordinate point for predicting the geometric center.

[0076] For each high-reliability adjacent element, the pin number involved in the connection on the target element to be verified is first determined by querying the edge record connecting the high-reliability adjacent element and the target element to be verified in the circuit topology diagram. Then, using this pin number, an index is performed in the offset direction vector set and pixel offset distance set of the target element to be verified, retrieving the corresponding offset direction vector and pixel offset distance. Using the geometric center coordinate point of the high-reliability adjacent element as the base point, the two components of the offset direction vector are inverted to obtain a unit vector pointing towards the geometric center of the target element to be verified. Each component of this unit vector is multiplied by the pixel offset distance to obtain a displacement vector. The components of the displacement vector are added to the components of the base point coordinates to obtain the candidate coordinate points for the predicted geometric center. If there are multiple high-reliability adjacent elements, this operation is performed once for each element, generating one candidate coordinate point, potentially resulting in multiple candidate coordinate points for the predicted geometric center.

[0077] Step S350: When there are multiple high-reliability adjacent elements, spatial clustering is performed on the multiple candidate coordinate points of the predicted geometric center. The spatial clustering process groups the candidate coordinate points whose spatial distance is within the preset clustering distance range into the same cluster, and selects the geometric mean coordinate point of the cluster with the most candidate coordinate points as the final predicted geometric center coordinate point.

[0078] Spatial clustering employs density-based or distance-based clustering paradigms, calculating the Euclidean distance between each candidate point for predicting the geometric center and constructing a distance matrix. A preset clustering distance range defines the maximum allowable distance between candidate points that can be considered to belong to the same cluster. The clustering process first initializes each candidate point as an independent cluster, then iteratively merges two clusters with a distance smaller than the preset clustering distance range until all clusters have a pairwise distance greater than this range. After clustering, the number of candidate points within each cluster is counted, and the cluster with the most candidate points is selected. Within this cluster, the arithmetic mean of the x-coordinates of all candidate points is used as the x-coordinate of the final predicted geometric center, and the arithmetic mean of the y-coordinates of all candidate points is used as the y-coordinate. If the number of high-reliability adjacent elements is only 1, this single candidate point directly serves as the final predicted geometric center.

[0079] Step S360: Based on the spatial resolution parameters, convert the standard package width direction dimension range and the standard package height direction dimension range in the standard package size descriptor into the standard pixel width range and the standard pixel height range. Using the final predicted geometric center coordinate point as the center, combine the standard pixel width range and the standard pixel height range to generate a rectangular correction detection box position coordinate sequence.

[0080] The same rectangle generation logic based on the standard size range of the encapsulation is used as in step S2611. The median value of the standard pixel width range is taken as the width of the corrected detection box, and the median value of the standard pixel height range is taken as the height of the corrected detection box. With the final predicted geometric center coordinate point as the center of the rectangle, the width and height are expanded by half in each of the four directions (up, down, left, and right) to obtain the coordinates of the upper left and lower right corners of the corrected detection box. This quadruple is the position coordinate sequence of the corrected detection box.

[0081] Step S370: Update the corrected detection box position coordinate sequence to the detection box position coordinate sequence attribute of the node corresponding to the target component to be verified in the circuit topology diagram.

[0082] The corrected detection box position coordinate sequence generated in the above steps is written over and written into the detection box position coordinate sequence attribute field of the node corresponding to the target component to be verified in the circuit topology diagram, replacing the original preliminary detection box position coordinate sequence.

[0083] As one implementation, before step S370, the following steps S3701 to S3705 may also be included: Step S3701: Obtain the original detection box position coordinate sequence of the target component to be verified in the preliminary detection result set, and calculate the spatial intersection-union ratio between the original detection box position coordinate sequence and the corrected detection box position coordinate sequence.

[0084] The original detection frame position coordinate sequence of the target component to be verified is extracted from the preliminary detection result set. This sequence consists of four values: the x-coordinate of the upper left corner, the y-coordinate of the upper left corner, the x-coordinate of the lower right corner, and the y-coordinate of the lower right corner. The original detection frame position coordinate sequence and the corrected detection frame position coordinate sequence generated in step S360 are input into the spatial intersection-union calculation process. During the calculation, the intersection area of ​​the two rectangles is first determined: the x-coordinate of the upper left corner of the intersection is taken as the larger value between the x-coordinate of the upper left corner of the original detection frame and the x-coordinate of the upper left corner of the corrected detection frame; the y-coordinate of the upper left corner of the intersection is taken as the larger value between the y-coordinate of the upper left corner of the original detection frame and the y-coordinate of the upper left corner of the corrected detection frame; the x-coordinate of the lower right corner of the intersection is taken as the smaller value between the x-coordinate of the lower right corner of the original detection frame and the y-coordinate of the lower right corner of the corrected detection frame; and the y-coordinate of the lower right corner of the intersection is taken as the smaller value between the y-coordinate of the lower right corner of the original detection frame and the y-coordinate of the lower right corner of the corrected detection frame. If the x-coordinate of the bottom right corner of the intersection is greater than the x-coordinate of the top left corner and the y-coordinate of the bottom right corner is greater than the y-coordinate of the top left corner, then the intersection area is the product of the intersection width and the intersection height; otherwise, the intersection area is zero. Next, the area of ​​the original detection boxes is calculated, which is the product of the original detection box width and height, where the width is the original bottom right x-coordinate minus the original top left x-coordinate, and the height is the original bottom right y-coordinate minus the original top left y-coordinate. Similarly, the area of ​​the corrected detection boxes is calculated. The union area is the sum of the areas of the original detection boxes and the corrected detection boxes minus the intersection area. Finally, the spatial intersection-union ratio (IUU) is the intersection area divided by the union area, and this value falls within a closed interval between 0 and 1.

[0085] Step S3702: When the calculated spatial intersection-union ratio is lower than the preset overlap benchmark, the corrected detection box position coordinate sequence is used as the final detection box position coordinate sequence. When the spatial intersection-union ratio is not lower than the preset overlap benchmark, the original detection box position coordinate sequence is retained as the final detection box position coordinate sequence.

[0086] The preset overlap benchmark is a pre-defined cross-union ratio (CUI) threshold. This threshold is determined by statistically analyzing the CUI distribution between correctly labeled boxes and boxes with different degrees of offset in a large number of circuit board image samples. It is used to define whether the original detection box and the corrected detection box are spatially highly overlapping. The spatial CUI value calculated in step S3701 is compared with the preset overlap benchmark. When the spatial CUI is lower than the benchmark, it indicates that there is a significant difference in spatial position between the corrected detection box and the original detection box. The original detection box may be mispositioned due to regression bias of the target detection network or local image interference. The corrected detection box is derived by back-calculation based on the pin-level topology relationship of highly reliable adjacent elements and is supported by circuit design rules. Therefore, the position coordinate sequence of the corrected detection box is adopted as the final detection box position coordinate sequence. When the spatial CUI is not lower than the benchmark, it indicates that the corrected detection box and the original detection box are highly consistent. The original detection box itself already has reliable position accuracy and does not need to be replaced by the back-calculation result. Therefore, the original detection box position coordinate sequence is retained as the final detection box position coordinate sequence. This comparison mechanism effectively prevents overcorrection, ensuring that position updates are only performed when the original detection is indeed biased.

[0087] Step S3703: Write the final detection box position coordinate sequence into the detection box position coordinate sequence attribute of the node corresponding to the target component to be verified in the circuit topology diagram, and clear the verification status mark of the node.

[0088] After determining the final detection box position coordinate sequence, the corresponding node object is located in the circuit topology diagram using the component identifier of the target component to be verified as the key. The detection box position coordinate sequence attribute field of this node object is updated to the four coordinate values ​​of the final detection box position coordinate sequence, overwriting the original preliminary detection box coordinates. Simultaneously, the verification status flag of this node object is changed from a value indicating verification to a value indicating no verification is required, completing the node state transition. Through this operation, the position information of the target component to be verified is officially confirmed, and its node is removed from the verification set, becoming a high-reliability node. This allows it to serve as a new reference source in subsequent iterative propagation, providing position correction basis for other adjacent components still in the verification state.

[0089] Step S3704: In the circuit topology diagram, retrieve the associated nodes that have a direct edge connection with the nodes of the currently updated detection box position coordinate sequence attributes and still have a pending verification status mark. For each associated node, determine whether it meets the conditions for using the updated node for spatial position back-inference processing. If it meets the conditions, mark the associated node as a component to be back-inferred and establish a direct correction reference binding relationship with the updated node.

[0090] Whenever the detection box position coordinate sequence attribute of a node is updated and the pending verification state mark is cleared, that node becomes a new reliable anchor point. Centered on this updated node, all its adjacent edges are traversed in the circuit topology diagram, obtaining the node identifier of the node at the end of each edge, forming a set of associated nodes. For each associated node in the associated node set, its pending verification state mark is checked to see if it is still pending verification. If the associated node still has a pending verification state mark, it is further determined whether it meets the conditions for spatial location back-reasoning. The judgment logic for this condition is: there is at least one direct edge connection between the associated node and the updated node, and the associated node has not yet established any direct correction reference binding relationship, or the reference node of its existing binding relationship is at a lower level in the topology than the currently updated node. When the condition is met, the processing state mark of the associated node is updated to the pending correction element, and a new direct correction reference binding relationship record is constructed. This record contains the pending correction element identifier field and the updated node element identifier field, and also attaches the corresponding pin network connection relationship for subsequent back-reasoning. This operation enables the instantaneous diffusion of correction capabilities; whenever the location of a node is confirmed, its unconfirmed neighboring nodes immediately have the opportunity to be corrected.

[0091] Step S3705: For the newly established direct correction reference binding relationship, using the detection box position coordinate sequence of the updated node as the reference position coordinate sequence, generate the correction detection box position coordinate sequence of the associated node according to the spatial position back-calculation method and update it to the circuit topology diagram.

[0092] For each newly established direct correction reference binding relationship in step S3704, a spatial position back-calculation process is immediately triggered. The detection box position coordinate sequence of the updated node is extracted as a reference position coordinate sequence. The standard package size descriptor of the associated node is obtained from the component package size descriptor set. The pin offset direction vector and offset distance corresponding to the specific pin network connection relationship between the associated node and the updated node are read. After being converted into pixel offset distance by the spatial resolution parameter, the displacement vector is obtained by multiplying the inverse direction vector and the pixel offset distance with the geometric center of the updated node as the base point. After superposition, the predicted geometric center coordinate point of the associated node is obtained. Then, the predicted detection box position coordinate sequence is generated by combining the standard package size range, and the final detection box position coordinate sequence of the associated node is determined by spatial intersection-union-comparison verification. The final detection box position coordinate sequence is written into the attribute field of the corresponding node of the associated node in the circuit topology diagram, and the unverified state mark of the node is cleared. Through this series of operations, the correction information is propagated from the updated node along the topology edge to the associated node, realizing position correction within a single-step neighborhood.

[0093] In one implementation, after step S3705, the following steps S3706 to S3710 may also be included: Step S3706: Traverse all remaining nodes in the circuit topology diagram that still have a state mark to be verified, and check for each remaining node whether there is an updated node that has a direct edge connection with the remaining node and has the final detection box position coordinate sequence.

[0094] After completing the previous round of node updates and new binding relationship processing, there may still be some remaining nodes in the circuit topology diagram with uncleared pending verification status markers. A full graph scan is initiated to collect all nodes in the node dictionary whose pending verification status markers are still in the pending verification state, forming a list of remaining nodes. For each remaining node in this list, all its adjacent edges are traversed to obtain the peer node. It is then checked whether the peer node's pending verification status marker has been cleared and whether its checkbox position coordinate sequence attribute field contains a valid final checkbox position coordinate sequence. If at least one such peer node exists, it is marked as an updated node that meets the conditions, and further adjacency traversal of the remaining node is paused, as at least one usable reference source has been found.

[0095] Step S3707: When there is an updated node that meets the conditions, upgrade the remaining node to a component to be corrected by back-pushing and establish a direct correction reference binding relationship with the updated node. Use the final detection box position coordinate sequence of the updated node as the reference position coordinate sequence, generate the correction detection box position coordinate sequence of the remaining node according to the spatial position back-pushing process, and update the node attributes.

[0096] For the remaining nodes that have been updated and meet the conditions found in step S3706, their processing status is immediately updated to be corrected components. The first updated node that meets the conditions is selected as the reference node, and a direct correction reference binding relationship record is constructed, which includes the component identifier of the remaining node and the component identifier of the updated node. Then, the spatial position back-inference processing flow is triggered: the final detection box position coordinate sequence of the updated node is used as the reference position coordinate sequence. The standard package size descriptor of the remaining node is obtained from the component package size descriptor set. The offset direction vector and offset distance corresponding to the pin network connection relationship between the remaining node and the updated node are read and converted into pixel offset distance through spatial resolution parameters. The displacement vector is obtained by multiplying the reverse direction vector and the pixel offset distance with the geometric center of the updated node as the base point. After superposition, the predicted geometric center coordinate point is obtained. Then, the predicted detection box position coordinate sequence is generated by combining the standard package size range. The corrected detection box position coordinate sequence is determined by spatial intersection-union verification. Finally, the corrected detection box position coordinate sequence is written into the detection box position coordinate sequence attribute field of the corresponding node of the remaining node, and the status mark to be verified of the node is cleared.

[0097] Step S3708: After completing one round of traversal and upgrade processing of all remaining nodes, re-check whether there are any remaining nodes in the circuit topology diagram that have a status mark to be verified and have nodes that have been updated in accordance with the conditions.

[0098] After each round of traversal and upgrade processing of all remaining nodes, the node dictionary of the circuit topology graph is scanned again to count the number of nodes still marked with unverified states. For these nodes, each node is checked to see if any of its adjacent nodes have been updated. If at least one node with an unverified state satisfies this condition, then the current round of processing has produced a valid topology propagation effect, and the next round of traversal and upgrade processing needs to be executed.

[0099] Step S3709: When there are still remaining nodes that meet the conditions, continue to execute the next round of traversal and upgrade processing until there are no nodes with unverified status markers or no remaining nodes that can establish direct correction reference binding relationships after a certain round of traversal.

[0100] A loop control structure is set up, and the loop continues only if at least one remaining node was successfully upgraded and its pending verification status flag was cleared in the previous round of processing. The content of each loop body is consistent with the descriptions in steps S3706 and S3707. After a loop body completes, if the pending verification status flags of all nodes in the circuit topology diagram have been cleared, the loop terminates normally. If, although some nodes still retain their pending verification status flags, none of these nodes have an updated node among their adjacent nodes, it indicates that the remaining pending verification nodes cannot be connected to the confirmed high-reliability nodes through any topology path, and the correction propagation reaches saturation, causing the loop to terminate. The nodes retaining their pending verification status flags at this point are the components that ultimately cannot be corrected.

[0101] Step S3710: Merge all nodes that have completed the update of the detection box position coordinate sequence with the nodes that originally belonged to the high reliability detection result subset to form a full detection result correction set. Each component identifier in the full detection result correction set corresponds to a final detection box position coordinate sequence.

[0102] The node dictionary of the circuit topology diagram is traversed, collecting all node records where the attribute fields of the detection box position coordinate sequence have been written with valid coordinate values ​​and the state to be verified is marked as not requiring verification. The component identifiers and detection box position coordinate sequences from these node records are extracted and merged with the component records that originally belonged to the high-reliability detection result subset. During merging, if the same component identifier exists in two sources simultaneously, the version in the node dictionary is preferred, as it may have been iteratively corrected and is more accurate. The merged result set is the full detection result correction set. This set uses the component identifier as a unique index, with each component identifier uniquely corresponding to a confirmed or corrected final detection box position coordinate sequence, providing a unified component position benchmark for subsequent connectivity verification and defect determination.

[0103] Step S400: After obtaining the full set of corrected test results formed by combining the subset of high-reliability test results and the updated subset of test results to be verified, traverse the network paths corresponding to the network connection relationships of each pin in the circuit topology diagram, perform pin position connectivity verification on the detection box position coordinate sequence of the components at both ends of each network path, generate network path connectivity verification results, and determine the network paths with open-circuit defects of component pins and the network path pairs with short-circuit defects of adjacent networks based on the network path connectivity verification results.

[0104] In one implementation, step S400 may specifically include the following steps S410 to S470: Step S410: Extract the pin network connection relationship represented by each edge in the circuit topology diagram, and obtain the first component identifier and second component identifier, as well as the first pin identifier and second pin identifier corresponding to the nodes at both ends of the edge.

[0105] The edge list of the circuit topology is traversed one by one. Each edge object stores references to the two end nodes of the electrical connection and the specific pin pairing information. The component identifier associated with the first end node is read from the edge object as the first component identifier, and the component identifier associated with the second end node is read as the second component identifier. At the same time, the pin numbers used by the connection on the first end node side are extracted from the edge attributes as the first pin identifier, and the pin numbers used on the second end node side are extracted as the second pin identifier. These four identifiers completely define the two electrical endpoints of a network path.

[0106] Step S420: Obtain the first detection frame position coordinate sequence corresponding to the first component identifier and the second detection frame position coordinate sequence corresponding to the second component identifier from the full detection result correction set, and extract the first pin local position coordinates corresponding to the first pin identifier and the second pin local position coordinates corresponding to the second pin identifier from the corresponding standard package size descriptor.

[0107] In the full-scale inspection result correction set, the final inspection box position coordinate sequence of the component is retrieved using the first component identifier as the query key, and denoted as the first inspection box position coordinate sequence; similarly, the second inspection box position coordinate sequence is retrieved using the second component identifier. Then, based on the component category descriptor corresponding to the first component identifier, the standard package size descriptor of the component is located in the component package size descriptor set. From its pin geometry information list, the center position of the pad of the pin in the component local coordinate system is extracted according to the first pin identifier, and denoted as the first pin local position coordinate. The origin of this local position coordinate coordinate system is usually located at the package geometry center, and the horizontal and vertical coordinates are given as the offset relative to the origin in physical dimensions. The second pin local position coordinate is obtained in the same way.

[0108] Step S430: Based on the spatial resolution parameters, convert the local position coordinates of the first pin and the local position coordinates of the second pin into local pixel position coordinates of the first pin and the local pixel position coordinates of the second pin in pixels.

[0109] The conversion process divides the x-coordinate and y-coordinate of the local position coordinates of the first pin by the spatial resolution parameter to obtain the x-component and y-component of the local pixel position coordinates of the first pin; the local pixel position coordinates of the second pin are calculated in the same way. Both pairs of local pixel position coordinates are in pixels and represent the relative offset of the pin pad center in the local pixel coordinate system of their respective components.

[0110] Step S440: Calculate the geometric center coordinates of the first detection box position coordinate sequence, add the local pixel position coordinates of the first pin to the geometric center coordinates to obtain the first global pin position coordinates; calculate the geometric center coordinates of the second detection box position coordinate sequence, add the local pixel position coordinates of the second pin to the geometric center coordinates to obtain the second global pin position coordinates.

[0111] The x-coordinate of the geometric center coordinates of the first detection box position coordinate sequence is determined by the average of the x-coordinates of the upper left and lower right corners of the first detection box, and the y-coordinate is determined by the average of the y-coordinates of the upper left and lower right corners of the first detection box. Adding the x-component of the local pixel position coordinates of the first pin to the x-coordinate of the geometric center, and adding the y-component to the y-coordinate of the geometric center, yields the first global pin position coordinates. These coordinates represent the exact pixel position of the pin in the global coordinate system of the motherboard circuit image under test. The second global pin position coordinates are calculated using the same process. These two global pin position coordinates define the two endpoints of a network path in the image.

[0112] Step S450: Using the line connecting the first global pin position coordinates and the second global pin position coordinates as the center line, expand outwards to both sides with a preset pixel width as half width to construct a rectangular analysis area covering the first global pin position coordinates and the second global pin position coordinates.

[0113] First, calculate the vector and length of the line connecting the first global pin location coordinates to the second global pin location coordinates. The direction of this line is the major axis of the rectangular analysis area. The preset pixel width is a fixed value that should be greater than the average wiring width of the motherboard circuitry to ensure that the rectangular area can fully accommodate the possible circuit traces and the base areas on both sides. Using the line connecting the first and second global pin location coordinates as the center line, translate the line in the direction of the preset pixel width to both sides of the center line to obtain two parallel boundary lines. Draw a cut-off line perpendicular to the line at the two endpoints of the line. The area enclosed by the four lines is the rectangular analysis area, which fully covers the reasonable wiring path between the two pins under test.

[0114] Step S460: Within the rectangular analysis area, using the first global pin position coordinates as the growth starting seed point, perform region growth processing based on pixel grayscale similarity. During the growth process, only pixels whose grayscale values ​​are within the preset motherboard line foreground grayscale range are included in the growth area, thus obtaining the connected pixel area that can be reached from the growth starting seed point.

[0115] Region growing is an iterative pixel aggregation algorithm. It first initializes an empty foreground pixel set and a queue of pixels to be processed. The growth starting seed point, i.e., the coordinates of the first global pin, is added to the queue and marked as visited. A preset grayscale range for the motherboard circuitry is defined as a range of grayscale values, pre-calibrated based on the typical grayscale characteristics of the motherboard copper foil circuitry in the image. The copper foil circuitry area exhibits lower grayscale under appropriate lighting. The algorithm repeatedly retrieves the first pixel from the queue and checks if its grayscale value falls within the preset foreground grayscale range. If it does, the pixel is added to the foreground pixel set, and the unvisited pixels in its 8-neighborhood are added to the end of the queue and marked as visited. If the retrieved pixel's grayscale value is not within the range, it is neither added to the foreground set nor has its neighborhood expanded. When the queue is empty, region growing stops. At this point, all pixels in the foreground pixel set constitute a continuously reachable connected pixel region along the circuit direction from the growth starting seed point.

[0116] Step S470: Determine whether the position coordinates of the second global pin are located inside the connected pixel region. If they are inside, generate a connectivity verification result indicating that the network path connectivity is normal. If they are not inside, generate a connectivity verification result indicating that the network path connectivity is abnormal. Record the network path identifier, first element identifier, second element identifier, first pin identifier, and second pin identifier of the network path with abnormal connectivity to the network path connectivity abnormal record table.

[0117] Check whether the pixel corresponding to the second global pin position coordinate has been included in the foreground pixel set of the connected pixel region. If the pixel belongs to the set, it indicates that the foreground pixel of the line starting from the first pin can extend continuously to the second pin, and there is a visible conductive line connection between the two. At this time, a conclusive mark indicating normal network path connectivity is generated. If the second global pin position coordinate is not within the connected pixel region, it indicates that the line is interrupted at some point during the growth process due to a break, occlusion, or missing element, and the two pins cannot be connected by continuous copper foil foreground pixels. At this time, a conclusive mark indicating abnormal network path connectivity is generated, and the complete identification information of the network path, including the network path identifier, the first component identifier, the second component identifier, the first pin identifier, and the second pin identifier, is appended as a record to the network path connectivity abnormal record table.

[0118] In one implementation, after step S470, the following steps S480 to S4130 may also be included: Step S480: Extract the set of pixels at the growth front boundary of the region growth process. The set of pixels at the growth front boundary consists of pixels that are on the boundary of the growth region when the region growth stops.

[0119] After region growth stops, the foreground pixel set is determined. The method for extracting the growth front boundary pixel set is to traverse each pixel in the foreground pixel set and check if there is at least one pixel in its 8-neighborhood that does not belong to the foreground pixel set. If so, the foreground pixel is considered a boundary pixel. All boundary pixels that meet the condition are collected to form the growth front boundary pixel set. This set represents the front position where growth stopped due to grayscale not conforming to the foreground range.

[0120] Step S490: Calculate the Euclidean distance between each pixel in the set of pixels at the growth front boundary and the coordinates of the second global pin position, and mark the pixel with the smallest calculated Euclidean distance as the breakpoint coordinates.

[0121] The distance metric uses Euclidean distance, calculated by taking the square root of the sum of the squares of the differences in the x and y coordinates of two pixels. The set of boundary pixels at the growth front is traversed, and for each boundary pixel, its Euclidean distance to the coordinates of the second global pin is calculated, continuously tracking the current minimum distance value and its corresponding pixel coordinates. After traversal, the boundary pixel with the smallest distance is marked as the breakpoint coordinates. These coordinates approximately indicate the location where the circuit break occurs—the closest point on the growth path to the target pin that was not reached.

[0122] Step S4100: Construct a rectangular line break candidate region using the line connecting the breakpoint position coordinates and the second global pin position coordinates as the diagonal. Perform local adaptive binarization processing on the set of pixels within the rectangular line break candidate region to generate a binary map of the line break candidate region.

[0123] Using the coordinates of the breakpoint and the second global pin as the two vertices of the diagonal, a rectangular region with sides parallel to the coordinate axes is constructed; this region is the candidate region for the rectangular line break. Local adaptive binarization processing employs a Gaussian weighted method based on the region mean: For each pixel within the rectangular region, a local neighborhood window of a preset size is taken as the center; the Gaussian weighted average of the pixel grayscale values ​​within this window is calculated; and this average, minus a preset offset, is used as the binarization threshold for the center pixel. If the grayscale value of the center pixel is greater than this threshold, it is set as the background value in the binary image; otherwise, it is set as the foreground value. This processing effectively addresses threshold deviations caused by uneven local illumination.

[0124] Step S4110: Perform morphological closing operation processing on the binary map of the candidate region of line breakage. The size of the structural element used in the morphological closing operation processing is determined according to the Euclidean distance between the breakpoint position coordinates and the second global pin position coordinates according to a preset ratio.

[0125] Morphological closing is a combined process of first dilating the binary image and then eroding it. The structuring element is either circular or square, and its radius or half-side length is determined by multiplying the Euclidean distance between the breakpoint coordinates and the second global pin coordinates by a preset scaling factor and rounding up. Closing can fill narrow breaks and small holes in the foreground region while maintaining a relatively unchanged edge morphology, helping to bridge minor breaks caused by imaging noise or etching processes.

[0126] Step S4120: Perform connected component analysis on the binary graph of the candidate region of line break after morphological closing operation to detect whether there is a connected component that simultaneously contains the foreground pixel where the break point position coordinates are located and the foreground pixel where the second global pin position coordinates are located.

[0127] Connectivity analysis employs either a two-pass scan method or a seed-fill method to label all foreground pixels in the binary image with connected components. After labeling, it checks whether the connected component label of the pixel corresponding to the breakpoint coordinates matches the connected component label of the pixel corresponding to the second global pin coordinates. If the labels match, it indicates that after the closing operation fills the small gaps, the two positions belong to the same connected component, meaning there exists a connected component that simultaneously contains both points.

[0128] Step S4130: When a connected component is detected, it is determined that the network path has a repairable line break and a connectivity verification result containing a repairable marker is generated. When no connected component is detected, the rectangular analysis area is expanded to obtain an expanded analysis area. The consistency of the line direction distribution within the expanded analysis area is calculated. When the consistency is lower than the preset direction consistency benchmark, it is determined that the network path has an unrepairable line break and a connectivity verification result containing an unrepairable marker is generated.

[0129] If connected component analysis detects that two points are connected, the break can be bridged through simple morphological processing, making it repairable. A connectivity anomaly record with a repairable marker is generated. If no connected component is detected, the break gap is large or other structural damage exists. In this case, the rectangular analysis area is expanded outward by a preset extended pixel size to obtain an extended analysis area. Within this area, the gradient direction distribution of the foreground pixels is extracted. Specifically, the gradient magnitude and gradient direction angle of each foreground pixel within the area are calculated. The gradient direction angle is quantized into several direction intervals, and the number of pixels in each interval is counted to construct a direction distribution histogram. The consistency level is measured by the concentration of this histogram. If the percentage of the maximum value interval is lower than the preset direction consistency benchmark, it indicates that the line direction is chaotic, and the break area may be accompanied by severe physical damage. This is determined to be an irreparable line break, and a connectivity verification result with an irreparable marker is generated.

[0130] In one implementation, step S400, determining the network path with an open-circuit defect in a component pin based on the network path connectivity verification result, may specifically include the following steps S4140 to S4190: Step S4140: Traverse the network path identifiers recorded in the network path connectivity anomaly record table. For each recorded network path identifier, query the set of cascaded network paths that share pins with that network path from the circuit topology diagram.

[0131] For each record in the network path connectivity anomaly log, its network path identifier is extracted. In the circuit topology diagram, starting from the edge corresponding to the network path identifier, all edges connected to either end node of that edge and represented by different network path identifiers are found. Specifically, the first and second component identifiers at both ends of the network path are located, and all other network paths with the first component identifier as one end and all other network paths with the second component identifier as one end are found respectively. After merging and deduplicating, a cascaded network path set is formed. A cascaded network path refers to other electrical connection paths that share at least one pin endpoint with the anomaly network path.

[0132] Step S4150: Obtain the connectivity verification results for each cascaded network path in the cascaded network path set, and determine whether there is at least one cascaded network path whose connectivity verification result is normal.

[0133] Query the connectivity check result generated in step S470 for each cascaded network path in the cascaded network path set. If any of the check results is marked as having normal connectivity, it indicates that the pin is not physically completely isolated and that there is a good line connection in at least one direction.

[0134] Step S4160: When the connectivity verification result of at least one cascaded network path is normal, extract the first global pin position coordinates and the second global pin position coordinates of the pins at both ends of the current network path, calculate the pixel distance between the two points, obtain the package outline size of the component to which the pin belongs from the corresponding standard package size descriptor, convert the package outline size into the pixel package outline size according to the spatial resolution parameter, compare and analyze the pixel distance and the pixel package outline size, and generate a physical connectivity evaluation mark.

[0135] After the cascade connectivity check passes, the physical distance between the two unconnected pins is further evaluated to determine if they should be connected. First, the coordinates of the first and second global pin positions are obtained in the same manner as in step S440, and the Euclidean pixel distance between the two points is calculated. Next, the standard package size descriptors of the two components at both ends of the current network path are obtained, and their package outline dimensions are extracted. The package outline dimensions are the overall length and width occupied by the corresponding component package on the circuit board plane. The package outline dimensions are converted to pixel package outline dimensions using spatial resolution parameters, and the larger value between the width and height is selected as the pixel scale reference for the component. The pixel distance between the two points is compared with the pixel scale references of the two components. If the pixel distance is less than the maximum value of the pixel scale references of the two components, the two pins are physically close enough, and a mark indicating that physical connectivity is satisfied is generated; otherwise, a mark indicating that physical connectivity is not satisfied is generated.

[0136] Step S4170: When the physical connectivity evaluation mark indicates that the physical connectivity meets the preset conditions, it is determined that there is an open circuit defect in the current network path. The current network path identifier, the first global pin position coordinate, and the second global pin position coordinate are recorded as open circuit defect network path information.

[0137] When the physical connectivity evaluation flag generated in step S4160 indicates that the physical connectivity requirements are met, it means that at the physical layout level, the distance between the two pins is within a reasonable range allowed by the component package size, and there should be a direct wire connection. However, the connectivity check in step S470 is judged as abnormal, which suggests that the network path has an open circuit defect caused by a broken circuit. The associated information of this defect, including the network path identifier, the first global pin position coordinates, and the second global pin position coordinates, is integrated into an open circuit defect network path information record.

[0138] Step S4180: Combine the open circuit defect network path information with the corresponding repairable or unrepairable markers to form a component pin open circuit defect confirmation record.

[0139] Extract the repairable or non-repairable markers corresponding to the network path from the connectivity verification result generated in step S4130, and append them to the open-circuit defect network path information record generated in step S4170 to form a complete component pin open-circuit defect confirmation record. This confirmation record also includes the location coordinates of the defect, the component pins involved, and a preliminary judgment on the repairability of the defect, providing a direct basis for subsequent maintenance decisions.

[0140] Step S4190: When the connectivity verification results of all cascaded network paths in the cascaded network path set are all connectivity anomalies, mark the current network path as a potential open-circuit defect network path, and perform line break candidate region analysis on the network path to further confirm the open-circuit defect.

[0141] If the judgment result of step S4150 is that the connectivity check result of any cascaded network path in the cascaded network path set is normal, it means that no intact line connection was detected in all electrical connection directions for this pin, and the entire local network area may be in a large-scale abnormal state. At this time, it is not appropriate to directly conclude that the current network path definitely has an open circuit defect, because it may also be caused by the failure of a common node further upstream. The current network path is marked as a potential open circuit defect network path, and a line break candidate region analysis process similar to steps S4100 to S4130 is triggered to perform more detailed break detection and repairability assessment on the area between the pins at both ends of the network path. Based on the assessment results, it is finally determined whether it is confirmed as an open circuit defect.

[0142] Step S500: Based on the network path with open circuit defects in component pins and the network path pair with short circuit defects in adjacent networks, and combined with the full detection results, correct the detection frame position coordinate sequence of each component in the set, generate open circuit defect description information containing the open circuit defect network path identifier and the corresponding component pin position coordinate sequence, and short circuit defect description information containing the short circuit defect network path pair identifier and the corresponding short circuit area position coordinate sequence, and merge the open circuit defect description information and the short circuit defect description information to output the motherboard circuit defect detection result.

[0143] In one implementation, step S500 generates open-circuit defect description information containing open-circuit defect network path identifiers and corresponding component pin location coordinate sequences, which may specifically include the following steps S510 to S570: Step S510: Obtain the network path identifier of the network path with the open circuit defect of the component pin, and extract the first component identifier, second component identifier, first pin identifier and second pin identifier corresponding to the network path identifier from the circuit topology diagram.

[0144] For each confirmed network path with an open-circuit defect in a component pin, its network path identifier is extracted as a query key, and the corresponding edge object is retrieved from the edge list of the circuit topology diagram. From the topology connection attributes of this edge object, the first component identifier corresponding to the first end node and the second component identifier corresponding to the second end node are extracted. At the same time, the pin pairing information stored in the edge object is extracted to obtain the first pin identifier and the second pin identifier, providing a dual positioning basis for components and pins for subsequent coordinate calculations.

[0145] Step S520: Obtain the first final detection box position coordinate sequence corresponding to the first element identifier and the second final detection box position coordinate sequence corresponding to the second element identifier from the full detection result correction set.

[0146] Using the first element identifier as the key, a search is performed in the full detection result correction set to retrieve the final detection box position coordinate sequence corresponding to that element, denoted as the first final detection box position coordinate sequence. The second element identifier is searched in the same way to obtain the second final detection box position coordinate sequence. These two coordinate sequences respectively provide the precise location boxes of the two related elements in the image.

[0147] Step S530: Obtain the first standard package size descriptor from the component package size descriptor set according to the component category descriptor of the first component identifier, and extract the local position coordinates of the first pin corresponding to the first pin identifier from it. Obtain the second standard package size descriptor according to the component category descriptor of the second component identifier, and extract the local position coordinates of the second pin corresponding to the second pin identifier from it.

[0148] The first standard package size descriptor is located in the component package size descriptor set by using the component category descriptor associated with the first component identifier. The pin geometry information list of this descriptor is then indexed by the first pin identifier to retrieve the local position coordinates of the first pin. Similarly, the second standard package size descriptor is obtained using the second component identifier, and the local position coordinates of the second pin are extracted by the second pin identifier. These two local position coordinates describe the offset of each pin relative to the package geometry center in its respective component local coordinate system.

[0149] Step S540: Based on the spatial resolution parameters, convert the local position coordinates of the first pin into the local pixel position coordinates of the first pin, and convert the local position coordinates of the second pin into the local pixel position coordinates of the second pin.

[0150] Using the same method as in step S430, divide the horizontal and vertical coordinates of the local position coordinates of the first pin by the spatial resolution parameter to obtain the local pixel position coordinates of the first pin; perform the same operation on the local position coordinates of the second pin to obtain the local pixel position coordinates of the second pin.

[0151] Step S550: Calculate the geometric center coordinates of the first final detection box position coordinate sequence, add the local pixel position coordinates of the first pin to the geometric center coordinates to obtain the first global open-circuit pin position coordinates; calculate the geometric center coordinates of the second final detection box position coordinate sequence, add the local pixel position coordinates of the second pin to the geometric center coordinates to obtain the second global open-circuit pin position coordinates.

[0152] The average of the top-left and bottom-right x-coordinates of the first final detection box position coordinate sequence is taken as the geometric center x-coordinate, and the average of the top-left and bottom-right y-coordinates is taken as the geometric center y-coordinate. The x-component of the first pin local pixel position coordinate is added to the geometric center x-coordinate, and the y-component is added to the geometric center y-coordinate to obtain the first global open-circuit pin position coordinate. The same steps are applied to the second final detection box position coordinate sequence and the second pin local pixel position coordinate to obtain the second global open-circuit pin position coordinate. These two coordinates accurately pinpoint the global pixel positions of the two pin pads involved in the open-circuit defect in the image to be inspected.

[0153] Step S560: Combine the network path identifier, the coordinates of the first global open pin location, and the coordinates of the second global open pin location into an open circuit defect description information entry, and add the open circuit defect description information entry to the open circuit defect description information list.

[0154] Construct an open-circuit defect description entry, which contains at least four data fields: network path identifier, first global open-circuit pin location coordinates, second global open-circuit pin location coordinates, and a repairable or non-repairable flag inherited from the component pin open-circuit defect confirmation record. Append this entry to the end of the open-circuit defect description information list.

[0155] Step S570: Perform the above operation on all network paths with open circuit defects in component pins to obtain a complete list of open circuit defect description information.

[0156] The process iterates through all confirmed open-circuit defect records for component pins, repeating steps S510 to S560 for each record until all open-circuit defects are converted into structured descriptive information entries. The final list of open-circuit defect descriptions contains a complete description of all detected open-circuit defects on the motherboard circuit currently under inspection.

[0157] In one implementation, step S500 involves generating short-circuit defect description information that includes short-circuit defect network path pair identifiers and corresponding short-circuit region location coordinate sequences. Specifically, this may include the following steps S580 to S5130: Step S580: Extract the first global pin position coordinates and the second global pin position coordinates corresponding to the pins at both ends of all network paths in the circuit topology diagram. Construct the minimum bounding rectangle that surrounds the first global pin position coordinates and the second global pin position coordinates for each network path, and construct a spatial index structure using the minimum bounding rectangle as the index unit.

[0158] Traverse each edge in the circuit topology diagram, and calculate the first and second global pin position coordinates for each edge according to step S440. Take the smaller x-coordinate as the left boundary of the minimum bounding rectangle, the larger x-coordinate as the right boundary, the smaller y-coordinate as the top boundary, and the larger y-coordinate as the bottom boundary, thus forming the spatial bounding rectangle of the network path. Using an R-tree spatial index structure, insert the minimum bounding rectangles of all network paths as spatial objects into the R-tree one by one. The internal nodes of the R-tree store the minimum bounding rectangles of all spatial objects contained in their child nodes, while the leaf nodes directly store the minimum bounding rectangles and pointers to the corresponding network path identifiers.

[0159] Step S590: For each network path, use the spatial index structure to retrieve all candidate neighboring network paths whose minimum bounding rectangle edge distance to the network path is less than the preset neighbor distance benchmark, and form a set of candidate neighboring network paths.

[0160] For the network path to be analyzed, the minimum bounding rectangle constructed in step S580 is taken, and its width is expanded outward in four directions by a preset proximity distance benchmark to form a query rectangle. A spatial intersection query is performed in the R-tree index using this query rectangle as the search window to retrieve all other network paths whose minimum bounding rectangle overlaps with or contains the query rectangle. After excluding the current network path itself from the search results, the remaining network paths are the candidate neighboring network paths, all of which are stored in the candidate neighboring network path set. The preset proximity distance benchmark limits the maximum spatial distance at which two lines are considered likely to short-circuit.

[0161] Step S5100: For each candidate neighboring network path in the candidate neighboring network path set, calculate the first and second pixels that are closest to the line foreground pixel region of the current network path and the line foreground pixel region of the candidate neighboring network path. The first pixel belongs to the line foreground pixel region of the current network path and the second pixel belongs to the line foreground pixel region of the candidate neighboring network path.

[0162] To obtain the foreground pixel region of the current network path, within the minimum bounding rectangle of the current network path, using the first and second global pin position coordinates of the network path as seed points, perform a region growth process with the same parameters as in step S460. The union of the connected pixel regions grown from the two seed points is then taken as the foreground pixel region of the current network path. This process is repeated for candidate neighboring network paths to obtain their foreground pixel regions. A nearest-neighbor search algorithm is then used to traverse each pixel in the foreground pixel region of the current network path, calculating its Euclidean distance to each pixel in the foreground pixel region of the candidate neighboring network path. The minimum distance value and its corresponding pixel pair coordinates are continuously tracked and updated. After traversal, the two pixels corresponding to the minimum distance value are the first pixel and the second pixel. The first pixel belongs to the current network path, and the second pixel belongs to the candidate neighboring network path.

[0163] Step S5110: Using the midpoint of the line connecting the first pixel and the second pixel as the center, construct a local detection window covering the first pixel and the second pixel, and perform superpixel segmentation on the pixels within the local detection window to obtain multiple superpixel blocks.

[0164] The mean coordinates of the first and second pixels are calculated as the midpoint of the line connecting them. Centered on this midpoint, a rectangle with sides parallel to the coordinate axes is constructed as a local detection window. The width of this rectangle is the horizontal distance between the first and second pixels plus twice the preset extended margin, and the height is the vertical distance between the two points plus twice the preset extended margin. Within this local detection window, a simple linear iterative clustering superpixel segmentation algorithm is executed. The algorithm first evenly distributes initial cluster center seed points within the window at preset grid intervals. The spatial interval of each seed point depends on the window area and the desired number of superpixels. During iteration, the distance from each pixel to several surrounding cluster centers is calculated. This distance is a weighted combination of spatial distance and color distance. The spatial distance is calculated using the Euclidean distance between the pixel coordinates and the cluster center coordinates, while the color distance is calculated using the absolute difference between the pixel's grayscale value and the cluster center's grayscale value. The two distance components are balanced using preset weighting coefficients. Each pixel is assigned to the superpixel block represented by the cluster center with the smallest weighted distance. After each round of assignment, the cluster center position is updated based on the average coordinates and average grayscale values ​​of pixels within each superpixel block. After a preset number of iterations, fragmented superpixels with too small an area or spatial discontinuity are merged into adjacent superpixel blocks with the highest similarity, ultimately outputting several connected and regular superpixel blocks.

[0165] Step S5120: Determine whether there is a boundary sharing relationship between the superpixel block containing the first pixel and the superpixel block containing the second pixel. If there is a boundary sharing relationship, check the continuity of grayscale value transition of the pixels on both sides of the boundary sharing line segment. If the grayscale value transition is continuous, determine that there is a short circuit between the current network path and the candidate neighboring network path. If there is no boundary sharing relationship between the superpixel block containing the first pixel and the superpixel block containing the second pixel, perform edge detection processing on the local detection window to detect whether there is an edge line segment that forms a continuous connection between the first pixel and the second pixel. If a continuous edge line segment is detected, determine that there is a short circuit between the current network path and the candidate neighboring network path.

[0166] First, identify the superpixel block containing the first pixel and the superpixel block containing the second pixel. Extract all boundary pixels of these two superpixel blocks and check if their boundary pixel sets intersect, i.e., whether at least one pixel is adjacent to both superpixel blocks. If such a shared boundary exists, take a row of pixels at a preset offset distance on both sides of the shared boundary segment and calculate the average absolute difference of the grayscale values ​​of these two rows of pixels. If this difference is lower than a preset smoothing threshold, it indicates that the grayscale transition on both sides of the boundary is continuous and smooth, and the foreground areas of the two lines naturally merge at this point, which is considered a short connection. If there is no boundary sharing relationship between the two superpixel blocks, the Cannibal edge detection algorithm is used to process the local detection window. Canney edge detection first smooths the window image using a Gaussian kernel, with the standard deviation of the Gaussian kernel preset to a fixed value. Then, it calculates the gradient magnitude and direction for each pixel, performing non-maximum suppression on the gradient magnitude image, retaining only local maxima in the gradient direction. Next, it employs dual-threshold processing, with a high threshold and a low threshold set according to a preset ratio. Pixels with gradient magnitudes higher than the high threshold are marked as strong edges, while pixels between the high and low thresholds that are adjacent to strong edge pixels are marked as weak edges. Finally, it connects weak edges to strong edges through hysteresis edge tracing, forming continuous edge segments. Between the first and second pixels, it checks whether a continuous path consisting of eight-neighborhood connections of strong or weak edge pixels exists; if so, it is also considered a short connection.

[0167] Step S5130: Combine the current network path identifier and the candidate neighboring network path identifier that are determined to have a short circuit into a short circuit defect network path pair identifier, and use the coordinates of the midpoint of the line connecting the first pixel and the second pixel as the short circuit region location coordinates. Combine the short circuit defect network path pair identifier and the short circuit region location coordinates into a short circuit defect description information entry and add it to the short circuit defect description information list.

[0168] After step S5120 determines that a short circuit exists, the network path identifiers of the two involved network paths are sorted lexicographically. The two identifiers are then concatenated using a connector to form a unique short circuit defect network path pair identifier. The coordinates of the midpoint of the line connecting the first and second pixels calculated in step S5110 are extracted as approximate spatial coordinates of the short circuit defect, denoted as the short circuit region location coordinates. The short circuit defect network path pair identifier and the short circuit region location coordinates are packaged into a short circuit defect description information entry, and this entry is appended to the short circuit defect description information list. This process is repeated until all candidate neighboring network path pairs have been detected, ultimately obtaining a complete short circuit defect description information list.

[0169] As one implementation, after merging the open-circuit defect description information and the short-circuit defect description information to output the motherboard circuit defect detection result, the following steps S600 to S1000 may also be included: Step S600: For each open-circuit defect description entry in the motherboard circuit defect detection results, extract the network path identifier from the entry, trace the cascaded network path in both directions along the network path in the circuit topology diagram, and obtain the connectivity verification results of all traced cascaded network paths.

[0170] For each entry in the open-circuit defect description information list in the motherboard circuit defect detection results, read its network path identifier field. Locate the edge corresponding to the network path in the circuit topology diagram. Starting from the two endpoints of the edge, trace outwards along all adjacent edges, using the first component identifier and the second component identifier as starting points respectively. During the tracing process, collect all other network paths that share at least one pin endpoint with the current network path, forming a cascaded network path set. For each cascaded network path in the set, consult the connectivity verification result record generated in step S470, extract the corresponding connectivity status flag, and summarize to form a connectivity verification result set for all cascaded network paths.

[0171] Step S700: When the connectivity verification results of all traced cascaded network paths indicate normal connectivity, mark the defect impact range of the open-circuit defect description information entry as a local open-circuit defect. When at least one of the traced cascaded network paths indicates abnormal connectivity, mark the defect impact range of the open-circuit defect description information entry as a propagating open-circuit defect.

[0172] Check the connectivity verification result set obtained in step S600. If the connectivity status of each record in the set is normal, it indicates that the open-circuit defect only affects the current network path itself and has not affected other electrical connections sharing the same pin. The open circuit is an isolated fault, and a marker indicating the scope of influence of a local open-circuit defect is added to the original open-circuit defect description entry. If any record in the set has a connectivity abnormality, it indicates that the pin where the open-circuit defect is located also participates in other network paths that also have connectivity problems, and the scope of influence of the defect has spread outward along the circuit topology. A marker indicating the scope of influence of a propagating open-circuit defect is added to the original entry.

[0173] Step S800: For each short-circuit defect description information entry in the motherboard circuit defect detection results, extract the first network path identifier and the second network path identifier contained in the short-circuit defect network path pair identifier in the entry, and query the functional circuit area design mark that is associated with the first network path identifier and the second network path identifier in the circuit topology diagram.

[0174] For each entry in the short-circuit defect description information list in the motherboard circuit defect detection results, the short-circuit defect network path pair identifier is parsed to separate the first network path identifier and the second network path identifier. The edge objects corresponding to each of the two network paths are located in the circuit topology diagram, and the functional circuit region design mark is read from the additional attributes of the edge objects or from the component attributes of their two endpoints. This functional circuit region design mark is extracted and stored in the topology diagram edge attributes during the circuit design netlist file parsing stage, based on the prefix of the network name, the schematic module to which the component belongs, or the region annotation information in the netlist file, and is used to identify the functional circuit block to which the network path belongs.

[0175] Step S900: When the two functional circuit area design marks found indicate that the first network path identifier and the second network path identifier belong to the same functional circuit area, the defect impact range of the short circuit defect description information entry is marked as a short circuit defect within the functional area. When the two functional circuit area design marks indicate that they belong to different functional circuit areas, the defect impact range of the short circuit defect description information entry is marked as a short circuit defect across functional areas.

[0176] Compare whether the design markings of the two functional circuit regions obtained in step S800 are consistent. If the two markings are the same, it means that the two network paths that caused the short circuit were originally designed within the same functional circuit region, and the impact of the short circuit defect is limited to this functional region. Add a marking indicating the scope of the short circuit defect's impact within the functional region to the original short circuit defect description entry. If the two markings are different, it means that the short circuit occurred between network paths belonging to two different functional circuit regions. This short circuit across functional boundaries may cause unexpected conduction between two originally electrically isolated functional modules, making the fault more severe and complex. Add a marking indicating the scope of the short circuit defect's impact across functional regions to the original entry.

[0177] Step S1000: Integrate all open-circuit defect description information entries and all short-circuit defect description information entries carrying defect impact range markers to generate an enhanced motherboard circuit defect detection result containing defect impact range classification markers.

[0178] An enhanced motherboard circuit defect detection result data structure is created, containing two sub-lists: an enhanced open-circuit defect list and an enhanced short-circuit defect list. All open-circuit defect description entries processed in step S700 and marked as localized or propagating open-circuit defects are copied to the enhanced open-circuit defect list. All short-circuit defect description entries processed in step S900 and marked as short-circuit defects within functional areas or across functional areas are copied to the enhanced short-circuit defect list. Metadata information such as the detection timestamp, the motherboard circuit image file name, and the circuit design netlist file name are appended to the header of this data structure. Finally, the integrated enhanced motherboard circuit defect detection results are serialized and output in a standard format. This enhanced detection result clearly defines the spatial location, defect type, and hierarchical scope of the defect for each defect.

[0179] This invention provides a computer-readable storage medium storing computer-executable instructions or a computer program. When the computer-executable instructions or the computer program are executed by a processor, the processor will execute the computer vision-based motherboard circuit defect detection method provided in this invention. For example, ... Figure 3 The method for detecting defects in motherboard circuits based on computer vision is shown.

[0180] In some embodiments, the computer-readable storage medium may be a read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic surface memory, optical disk, or CD-ROM, etc.; or it may be a device that includes one or any combination of the above-mentioned memories.

[0181] The above description is merely an embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of the present invention are included within the scope of protection of the present invention.

Claims

1. A computer vision-based method for detecting defects in motherboard circuits, characterized in that, The method includes: Obtain a preliminary set of test results, spatial resolution parameters corresponding to the circuit image of the motherboard to be tested, and circuit design netlist file; Based on the geometric matching degree between the detection frame position coordinate sequence of each component in the preliminary detection result set and the standard package size descriptor of the corresponding component category in the component package size descriptor set, the preliminary detection result set is divided into a high-reliability detection result subset and a test result subset. Based on the component pin network connection relationship set, a circuit topology diagram with component identifiers as nodes and pin network connection relationships as edges is constructed. For the target component to be verified in the subset of the test results, a high-reliability adjacent component with a pin network connection relationship with the target component to be verified is determined in the circuit topology diagram. The spatial position is reversed using the detection box position coordinate sequence of the high-reliability adjacent component and the standard package size descriptor of the target component to be verified to generate a corrected detection box position coordinate sequence of the target component to be verified. The corrected detection box position coordinate sequence is then updated to the detection box position coordinate sequence attribute of the corresponding node in the circuit topology diagram. After obtaining the full set of corrected test results formed by combining the subset of high-reliability test results and the updated subset of test results to be verified, the network paths corresponding to the network connection relationships of each pin in the circuit topology diagram are traversed. The pin position connectivity verification process is performed on the detection box position coordinate sequence of the components at both ends of each network path to generate network path connectivity verification results. Based on the network path connectivity verification results, network paths with open-circuit defects of component pins and network path pairs with short-circuit defects of adjacent networks are determined. Based on the network paths with open-circuit defects in component pins and the network path pairs with short-circuit defects in adjacent networks, the detection frame position coordinate sequence of each component in the full detection result correction set is combined to generate open-circuit defect description information containing open-circuit defect network path identifiers and corresponding component pin position coordinate sequences, and short-circuit defect description information containing short-circuit defect network path pair identifiers and corresponding short-circuit region position coordinate sequences. The open-circuit defect description information and the short-circuit defect description information are then merged and output as the motherboard circuit defect detection result.

2. The method according to claim 1, characterized in that, The preliminary detection result set is divided into a high-reliability detection result subset and a test result subset based on the geometric matching degree between the detection frame position coordinate sequence of each component in the preliminary detection result set and the standard package size descriptor of the corresponding component category in the component package size descriptor set. A circuit topology diagram is then constructed based on the component pin network connection relationship set, with component identifiers as nodes and pin network connection relationships as edges. For each component in the preliminary test result set, a standard package size descriptor with the same component category identifier as the component category descriptor is extracted from the component package size descriptor set. The standard package size descriptor includes a standard package width dimension range and a standard package height dimension range. Based on the spatial resolution parameters, the standard package width direction dimension range and the standard package height direction dimension range are converted into pixel standard width range and pixel standard height range in pixels. Calculate the width and height span of the area enclosed by the detection frame position coordinate sequence of the element, determine whether the width span falls within the standard width range of the pixel and whether the height span falls within the standard height range of the pixel, generate a package size matching status indicator indicating package size matching when both results are within the range, and generate a package size mismatching status indicator indicating package size mismatch when either result is not within the range. When the generated package size matching status indicator indicates that the package size is matched, the detection confidence of the component is compared with the preset high confidence benchmark range. When the detection confidence is within the high confidence benchmark range, the component category descriptor, detection frame position coordinate sequence and detection confidence of the component are classified into the high reliability detection result subset. When the detection confidence is outside the high confidence benchmark range, the component is classified into the test result subset to be verified. When the generated package size matching status indicator flag indicates that the package size does not match, the component category descriptor, detection box position coordinate sequence and detection confidence of the component are directly included in the subset of the detection results to be verified. After classifying all components, a circuit topology diagram is generated based on the set of component pin network connections, with each component identifier as a node and the pin network connection relationship between any two component identifiers as edges. For each component that is included in the high reliability test result subset, the corresponding node is located in the circuit topology diagram and the test box position coordinate sequence of the component is written into the test box position coordinate sequence attribute of the node. For each component that is included in the test result subset to be verified, the corresponding node is located in the circuit topology diagram and a test status marker is set.

3. The method according to claim 2, characterized in that, Before using the high-reliability detection result subset, the detection result subset to be verified, and the circuit topology diagram carrying the status flag to be verified as input for subsequent processing, the method further includes: All elements belonging to the subset of test results to be verified are arranged in descending order of detection confidence to generate an ordered sequence of elements to be verified. The elements that appear earlier in the ordered sequence of elements to be verified have higher detection confidence. Select the current component to be verified sequentially from the ordered sequence of components to be verified. Traverse the adjacent nodes that have a direct edge connection with the node where the current component to be verified is located in the circuit topology diagram. Obtain the verification status marking of each adjacent node. When there is at least one adjacent node that does not have a verification status marking and belongs to the subset of the high reliability detection results, mark the current component to be verified as a component to be reversed and corrected, and establish a direct correction reference binding relationship between the component to be reversed and the adjacent nodes that meet the conditions. When there are no adjacent nodes that meet the conditions, continue to check whether each adjacent node has been marked as a component to be back-pushed and corrected. When at least one adjacent node has been marked as a component to be back-pushed and corrected, establish a cascaded correction reference binding relationship between the current component to be verified and the marked component to be back-pushed and corrected. When there are neither adjacent nodes that do not have a status mark to be verified and belong to a subset of high reliability detection results, nor adjacent nodes that have been marked as elements to be reversed and corrected, the current element to be verified is retained in the ordered sequence of elements to be verified and re-selected in order after all elements in this round have been selected. If no new direct correction reference binding relationship or cascade correction reference binding relationship is successfully established after all components are selected in this round, all currently retained components in the ordered sequence of components to be verified are marked as uncorrectable components, and the uncorrectable components are removed from the sequence, terminating the re-selection process; otherwise, the next round of sequential selection process continues. Based on the established direct correction reference binding relationship and cascade correction reference binding relationship, the processing priority of the component to be corrected that has a direct correction reference binding relationship is set to be higher than that of the component to be corrected that has a cascade correction reference binding relationship, and the ordered sequence of the components to be verified is rearranged in order of processing priority from high to low.

4. The method according to claim 3, characterized in that, After rearranging the ordered sequence of elements to be verified according to processing priority from high to low, the process further includes: Following the order of the rearranged ordered sequence of the elements to be verified, the elements to be corrected that have direct correction reference binding relationships are selected in turn, and the detection box position coordinate sequence of the adjacent nodes pointed to by their direct correction reference binding relationships is obtained as the direct reference position coordinate sequence. Obtain the standard package size descriptor corresponding to the component category descriptor of the component to be reversed from the set of component package size descriptors. Read the offset direction vector and offset distance of each pin corresponding to the pin of the component to be reversed from the package geometric center in the standard package size descriptor. Select the corresponding offset direction vector and offset distance according to the specific pin network connection relationship between the component to be reversed and the adjacent node. Based on the spatial resolution parameters, the selected offset distance is converted into a pixel offset distance in pixels. Using the geometric center coordinates of the direct reference position coordinate sequence as the origin of the operation, the selected offset direction vector is reversed and multiplied by the pixel offset distance to obtain the displacement vector. The displacement vector is then superimposed with the origin of the operation to obtain the predicted geometric center coordinates of the element to be reversed and corrected. Based on the spatial resolution parameters, the standard package width direction dimension range and the standard package height direction dimension range in the standard package size descriptor are converted into pixel standard width range and pixel standard height range. Taking the predicted geometric center coordinate point as the center, and combining the pixel standard width range and pixel standard height range, a predicted detection box position coordinate sequence surrounding the predicted geometric center coordinate point is generated. Calculate the spatial intersection-union ratio between the predicted detection box position coordinate sequence and the original detection box position coordinate sequence of the element to be back-inferred and corrected. When the spatial intersection-union ratio is lower than a preset overlap benchmark, the predicted detection box position coordinate sequence is used as the corrected detection box position coordinate sequence. When the spatial intersection-union ratio is not lower than the preset overlap benchmark, the original detection box position coordinate sequence is retained as the corrected detection box position coordinate sequence. Write the corrected detection box position coordinate sequence into the detection box position coordinate sequence attribute of the node corresponding to the element to be corrected in the circuit topology diagram, and clear the node's pending verification status mark.

5. The method according to any one of claims 1-4, characterized in that, For the target component to be verified in the subset of the test results, high-reliability adjacent components with pin network connections to the target component to be verified are identified in the circuit topology diagram. Spatial position back-calculation is performed using the detection frame position coordinate sequence of the high-reliability adjacent components and the standard package size descriptor of the target component to be verified, generating a corrected detection frame position coordinate sequence for the target component to be verified, including: In the circuit topology diagram, all adjacent nodes that have a direct edge connection with the node where the target element to be verified is located and do not have a verification status mark are identified as high-reliability adjacent elements. Extract the detection frame position coordinate sequence of each high-reliability adjacent element and calculate its geometric center coordinate point. At the same time, based on the component category descriptor of the target component to be verified, obtain the corresponding standard package size descriptor from the component package size descriptor set, and read the offset direction vector and offset distance set of each pin relative to the package geometric center from the standard package size descriptor. Based on the spatial resolution parameter, each offset distance in the offset distance set is converted into a pixel offset distance in units of pixels to obtain a pixel offset distance set; For each high-reliability adjacent element, based on the pin network connection relationship between the high-reliability adjacent element and the target element to be verified, the offset direction vector and pixel offset distance of the corresponding pin are selected from the set of offset direction vectors and pixel offset distances. Taking the geometric center coordinate point of the high-reliability adjacent element as the base point, the selected offset direction vector is reversed and multiplied by the selected pixel offset distance to obtain the displacement vector. The displacement vector is then superimposed with the base point to obtain a predicted geometric center candidate coordinate point. When there are multiple high-reliability adjacent elements, spatial clustering is performed on the multiple candidate coordinate points of the predicted geometric center. The spatial clustering process groups the candidate coordinate points whose spatial distance is within the preset clustering distance range into the same cluster, and selects the geometric mean coordinate point of the cluster with the most candidate coordinate points as the final predicted geometric center coordinate point. Based on the spatial resolution parameters, the standard package width direction dimension range and the standard package height direction dimension range in the standard package size descriptor are converted into pixel standard width range and pixel standard height range. Taking the final predicted geometric center coordinate point as the center, and combining the pixel standard width range and pixel standard height range, a rectangular correction detection box position coordinate sequence is generated. The corrected detection box position coordinate sequence is updated to the detection box position coordinate sequence attribute of the node corresponding to the target component to be verified in the circuit topology diagram.

6. The method according to claim 5, characterized in that, Before updating the corrected detection box position coordinate sequence to the detection box position coordinate sequence attribute of the node corresponding to the target component to be verified in the circuit topology diagram, the method further includes: Obtain the original detection box position coordinate sequence of the target component to be verified in the preliminary detection result set, and calculate the spatial intersection-union ratio (IUU) between the original detection box position coordinate sequence and the corrected detection box position coordinate sequence. When the calculated spatial intersection-union ratio is lower than the preset overlap benchmark, the corrected detection box position coordinate sequence is used as the final detection box position coordinate sequence; when the spatial intersection-union ratio is not lower than the preset overlap benchmark, the original detection box position coordinate sequence is retained as the final detection box position coordinate sequence. Write the final detection box position coordinate sequence into the detection box position coordinate sequence attribute of the node corresponding to the target component to be verified in the circuit topology diagram, and clear the verification status mark of the node. In the circuit topology diagram, retrieve the associated nodes that have a direct edge connection with the nodes of the currently updated detection box position coordinate sequence attributes and still have a pending verification status mark. For each associated node, determine whether it meets the condition of using the updated node for spatial position back-inference processing. When it meets the condition, mark the associated node as a back-inference correction element and establish a direct correction reference binding relationship with the updated node. For the newly established direct correction reference binding relationship, the detection box position coordinate sequence of the updated node is used as the reference position coordinate sequence. The correction detection box position coordinate sequence of the associated node is generated according to the spatial position back-calculation method and updated to the circuit topology diagram.

7. The method according to claim 6, characterized in that, The process of establishing a new direct correction reference binding relationship, using the updated node's detection box position coordinate sequence as a reference position coordinate sequence, generating the corrected detection box position coordinate sequence of the associated node according to the spatial position back-calculation method, and updating it to the circuit topology diagram, further includes: Traverse all remaining nodes in the circuit topology diagram that still have a state mark to be verified, and check for each remaining node whether there is an updated node that has a direct edge connection with the remaining node and has the final detection box position coordinate sequence. When there is an updated node that meets the conditions, the remaining node is upgraded to a component to be corrected by back-pushing and a direct correction reference binding relationship is established with the updated node. The final detection box position coordinate sequence of the updated node is used as the reference position coordinate sequence. The correction detection box position coordinate sequence of the remaining node is generated according to the spatial position back-pushing process and the node attributes are updated. After completing a round of traversal and upgrade processing of all remaining nodes, re-examine whether there are any remaining nodes in the circuit topology diagram that have a status mark to be verified and have nodes that have been updated in accordance with the conditions. If there are still remaining nodes that meet the conditions, continue to execute the next round of traversal and upgrade processing until there are no nodes with unverified status markers or no remaining nodes that can establish direct correction reference binding relationships after a certain round of traversal. All nodes that have completed the update of the detection box position coordinate sequence are merged with the nodes that originally belonged to the high reliability detection result subset to form a full detection result correction set. Each element identifier in the full detection result correction set corresponds to a final detection box position coordinate sequence.

8. The method according to claim 1, characterized in that, The process involves traversing the network paths corresponding to the pin network connections in the circuit topology diagram, performing pin position connectivity verification on the detection box position coordinate sequence of the components at both ends of each network path, and generating network path connectivity verification results, including: Extract the pin network connection relationship represented by each edge in the circuit topology diagram, and obtain the first component identifier and second component identifier, as well as the first pin identifier and second pin identifier corresponding to the nodes at both ends of the edge; The first detection frame position coordinate sequence corresponding to the first component identifier and the second detection frame position coordinate sequence corresponding to the second component identifier are obtained from the full detection result correction set, and the local position coordinates of the first pin corresponding to the first pin identifier and the local position coordinates of the second pin corresponding to the second pin identifier are extracted from the corresponding standard package size descriptor. Based on the spatial resolution parameters, the local position coordinates of the first pin and the local position coordinates of the second pin are respectively converted into local pixel position coordinates of the first pin and local pixel position coordinates of the second pin in pixels. Calculate the geometric center coordinates of the first detection box position coordinate sequence, and add the local pixel position coordinates of the first pin to the geometric center coordinates to obtain the first global pin position coordinates; calculate the geometric center coordinates of the second detection box position coordinate sequence, and add the local pixel position coordinates of the second pin to the geometric center coordinates to obtain the second global pin position coordinates; Using the line connecting the first global pin position coordinates and the second global pin position coordinates as the center line, and expanding outwards to both sides with a preset pixel width as half width, a rectangular analysis area covering the first global pin position coordinates and the second global pin position coordinates is constructed. Within the rectangular analysis area, the first global pin position coordinates are used as the growth starting seed point. Region growth processing based on pixel grayscale similarity is performed. During the growth process, only pixels whose grayscale values ​​are within the preset motherboard line foreground grayscale range are included in the growth area to obtain the connected pixel area that can be reached from the growth starting seed point. Determine whether the second global pin position coordinates are located inside the connected pixel region. If they are inside, generate a connectivity verification result indicating normal network path connectivity. If they are not inside, generate a connectivity verification result indicating abnormal network path connectivity. Record the network path identifier, first element identifier, second element identifier, first pin identifier, and second pin identifier of the abnormal network path in the network path connectivity abnormal record table.

9. A computer system, characterized in that, include: Memory is used to store executable instructions or computer programs. The processor, when executing computer-executable instructions or computer programs stored in the memory, implements the computer vision-based motherboard circuit defect detection method according to any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the steps of the method according to any one of claims 1 to 8.

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