Display panel and driving method thereof

Abstract

The application provides a display panel and a driving method thereof. The display panel comprises a plurality of pixel units arranged in an array; a plurality of gate lines, each pixel unit being provided with two gate lines, the two gate lines being a first gate line and a second gate line; a plurality of data lines, each column of pixel units being provided with three data lines; each pixel unit comprising a first switch transistor, a second switch transistor and a pixel electrode, the control end of the first switch transistor being connected to the first gate line of the corresponding row, the control end of the second switch transistor being connected to the second gate line of the corresponding row, and the output ends of the two switch transistors being connected to the pixel electrode; for each column of pixel units, the three data lines are connected to the input ends of the first switch transistors or the second switch transistors of the multiple rows of pixel units distributed in the column according to a predetermined row period, and the rows connected by the three data lines are different from each other and collectively cover all the rows in the predetermined row period.

Description

Technical Field

[0001] This invention relates to the technical field of display panels, and more specifically, to a display panel and its driving method. Background Technology

[0002] With the rapid development of electronic information technology and consumer display products, users' demands for visual experience continue to upgrade, and screen refresh rate has become one of the key indicators for measuring display performance. Display device refresh rates have undergone an initial increase from 60Hz to 90Hz, and have now fully entered the era of high refresh rates. Refresh rates of 144Hz and even 240Hz and above are gradually becoming the mainstream configuration for gaming monitors, high-end smartphones, and professional display devices. Higher refresh rates can significantly improve the smoothness and response speed of dynamic images, reduce ghosting and motion blur, thereby bringing users a more immersive and accurate visual presentation.

[0003] However, in high refresh rate driving mode, the pixel charging time of the display panel is significantly compressed. Taking a 240Hz refresh rate as an example, its single-frame scan cycle is only 4.166 milliseconds, compared to the traditional 60Hz cycle of approximately 16.66 milliseconds, reducing the charging time by 75%. This drastic reduction in charging time can easily cause the pixel electrodes to fail to reach the target voltage within the limited time, leading to insufficient pixel charging. This problem directly manifests as decreased display brightness and reduced screen brightness uniformity.

[0004] Therefore, how to effectively solve the problems of brightness decay and uneven display caused by insufficient charging time while ensuring a smooth high refresh rate experience has become a research topic that urgently needs to be addressed in the current display technology field. This is of great significance for improving the overall performance and market competitiveness of display products.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] To address the problems in the prior art, the present invention aims to provide a display panel and its driving method. The display panel is configured with three data lines and a dual-transistor structure in each column, realizing time-division multiplexing and alternating charging of the data lines, extending the charging time to twice that of the traditional architecture. Furthermore, by utilizing the pre-charging of the third data line and a multi-stage parallel writing mechanism, the accuracy of pixel voltage writing and screen uniformity at high refresh rates are significantly improved while avoiding signal conflicts.

[0007] Specifically, a first aspect of the present invention provides a display panel, comprising: Multiple pixel units, the multiple pixel units being arranged in an array in the display area of ​​the display panel; Multiple gate lines are provided, and each pixel unit is provided with two gate lines, namely a first gate line and a second gate line. Multiple data lines are provided, with three data lines corresponding to each column of pixel units, namely the first data line, the second data line, and the third data line; Each pixel unit includes a first switching transistor, a second switching transistor, and a pixel electrode. The control terminal of the first switching transistor is connected to the first gate line of the corresponding row, the control terminal of the second switching transistor is connected to the second gate line of the corresponding row, and the output terminals of both the first and second switching transistors are connected to the pixel electrode. For each column of pixel units, the first data line, the second data line, and the third data line are respectively connected to the input terminals of the first or second switching transistors of multiple rows of pixel units distributed in the column according to a predetermined row period, and the rows connected by the first data line, the second data line, and the third data line are different from each other in the predetermined row period and together cover all rows in the predetermined row period.

[0008] According to a first aspect of the invention, the predetermined row period is 6 rows.

[0009] According to a first aspect of the invention, the first data line is connected to the input terminal of a first switching transistor of a pixel unit located in rows 6i+1, 6i+2, 6i+4 and 6i+5 of the column; The second data line is connected to the second switching transistor of the pixel unit located in the 6i+1 and 6i+4 rows of the column, and to the input terminal of the first switching transistor of the pixel unit located in the 6i+3 and 6i+6 rows. The third data line is connected to the input terminal of the second switching transistor of the pixel unit located in the 6i+2, 6i+3, 6i+5 and 6i+6 rows of the column; Where i is a natural number.

[0010] According to a first aspect of the present invention, the first data line, the second data line, and the third data line are respectively connected to different data driving circuits.

[0011] According to a first aspect of the present invention, the display panel further includes a source drive module, the source drive module including a data drive chip and a plurality of multiplexing circuits; The data driver chip includes multiple output ports, each of which is connected to a multiplexing circuit. The multiplexing circuit is used to distribute the signal output from one of the output ports to the three data lines of a column of pixel units.

[0012] According to a first aspect of the present invention, the first data line, the second data line and the third data line extend along the column direction and are arranged periodically in the row direction according to a group of three data lines corresponding to a column of pixel units.

[0013] According to a first aspect of the invention, it further includes a gate driving circuit connected to a plurality of said gate lines for providing a turn-on signal to the first gate line and the second gate line in a time-division manner.

[0014] According to a first aspect of the invention, the gate driving circuit sequentially drives the first gate line and the second gate line of each row of pixel units within the same frame period.

[0015] A second aspect of the present invention provides a driving method for a display panel, applied to the display panel described in the first aspect, wherein the display panel further includes a gate driving circuit; The gate driving circuit is connected to multiple gate lines and is used to provide turn-on signals to the first gate line and the second gate line in a time-division manner. The driving method includes: In a series of consecutive timing stages, the gate driving circuit sequentially turns on the first gate line and the second gate line of each row of pixel units in a predetermined order. Charge the data cable or pixel unit.

[0016] According to a second aspect of the invention, the predetermined row period is 6 rows; The first data line is connected to the input terminal of the first switching transistor located in rows 6i+1, 6i+2, 6i+4 and 6i+5 of the column; The second data line is connected to the second switching transistor of the pixel unit located in the 6i+1 and 6i+4 rows of the column, and to the input terminal of the first switching transistor of the pixel unit located in the 6i+3 and 6i+6 rows. The third data line is connected to the input terminal of the second switching transistor of the pixel unit located in rows 6i+2, 6i+3, 6i+5, and 6i+6 of the column; where i is a natural number; The driving method includes: t1 stage: Both the first and second data lines are in the on state, and the first and second switching transistors of the pixel unit in row 6i+1 are pre-charged; In stage t2: the first gate line of row 6i+1 is in the on state, and the first data line writes data to the pixel unit of row 6i+1; the third data line is in the on state, and the third data line is pre-charged in preparation for writing data to the second switching transistor of the pixel unit of row 6i+2. In stage t3: the second gate line of row 6i+1 is turned on, and the second data line writes data to the pixel unit of row 6i+1; the second gate line of row 6i+2 is turned on, and the third data line writes data to the pixel unit of row 6i+2; the first data line is turned on, and the first data line is pre-charged in preparation for writing data to the first switching transistor of the pixel unit of row 6i+2. t4 stage: The first gate line of row 6i+2 is in the on state, and the first data line writes data to the pixel unit of row 6i+2; the second data line and the third data line are both in the on state, and the second data line and the third data line are precharged in preparation for writing data to the first switching transistor and the second switching transistor of the pixel unit of row 6i+3. t5 stage: The first gate line of row 6i+3 is in the on state, and the second data line writes data to the pixel unit of row 6i+3; the first data line is in the on state, pre-charges the first data line, and prepares to write data to the first switching transistor of the pixel unit of row 6i+4. In stage t6: the second gate line of row 6i+3 is turned on, and the third data line writes data to the pixel unit of row 6i+3; the first gate line of row 6i+4 is turned on, and the first data line writes data to the pixel unit of row 6i+4; the second data line is turned on, and the second data line is pre-charged in preparation for writing data to the second switching transistor of the pixel unit of row 6i+4. t7 stage: The second gate line of row 6i+4 is in the on state, and the second data line writes data to the pixel unit of row 6i+4; the first data line and the third data line are both in the on state, pre-charge the first data line and the third data line, and prepare to write data to the first switching transistor and the second switching transistor of the pixel unit of row 6i+5. t8 stage: The second gate line of row 6i+5 is in the on state, and the third data line writes data to the pixel unit of row 6i+5; the second data line is in the on state, and the second data line is pre-charged in preparation for writing data to the first switching transistor of the pixel unit of row 6i+6. In stage t9: the first gate line of row 6i+5 is turned on, and the first data line writes data to the pixel unit of row 6i+5; the first gate line of row 6i+6 is turned on, and the second data line writes data to the pixel unit of row 6i+6; the third data line is turned on, and the third data line is pre-charged in preparation for writing data to the second switching transistor of the pixel unit of row 6i+6. In stage t10: the second gate line of row 6i+6 is turned on, and the third data line writes data to the pixel unit of row 6i+6. Repeat phases t1 to t10, incrementing i by 1 each time a complete cycle from t1 to t10 is completed.

[0017] Compared with existing technologies, the display panel and its driving method provided by this invention, by configuring three data lines for each column of pixel units and combining them with a dual-transistor pixel structure with two gate lines, achieves time-division multiplexing and alternating charging of data lines within a predetermined row cycle. In one frame scan cycle, two data lines sequentially charge and discharge the pixels in the current row, extending the effective charging time of a single row to twice that of traditional architectures, significantly alleviating brightness decay caused by insufficient charging time at high refresh rates; simultaneously, the third data line pre-charges subsequent rows, further optimizing write efficiency. The three data lines connect different rows respectively within the predetermined row cycle and collectively cover all rows, effectively avoiding data line conflicts. Combined with the multi-stage parallel pre-charging and data writing driving method, while significantly extending the charging window, the accuracy and uniformity of pixel voltage writing are greatly improved, comprehensively enhancing the uniformity of the image under high resolution and high refresh rate displays. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without inventive effort. Furthermore, the drawings are merely illustrative diagrams of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0019] Figure 1 This is a schematic diagram of the array circuit structure of a display panel according to an embodiment of the present invention; Figure 2This is a schematic diagram of the driving timing of a display panel according to an embodiment of the present invention; Figures 3 to 12 These are state diagrams of the display panel in the first embodiment of the present invention, specifically the t1 to t10 stages. Detailed Implementation

[0020] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present invention can be modified or changed according to different viewpoints and application systems without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0021] The present invention will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can readily implement it. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0022] In the representation of this invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics represented in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, those skilled in the art can combine and integrate different embodiments or examples represented in this invention, as well as features of different embodiments or examples, without contradiction.

[0023] To clearly illustrate the present invention, components unrelated to the description are omitted, and the same or similar constituent elements throughout the specification are given the same reference numerals.

[0024] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.

[0025] When we say that a device is "above" another device, this can mean that it is directly above the other device, or it can mean that other devices are present in between. Conversely, when we say that a device is "directly" "above" another device, there are no other devices present in between.

[0026] Although the terms first, second, etc., are used in some instances herein to refer to various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, first interface and second interface, etc., are used. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0027] The technical terms used herein are for reference only to specific embodiments and are not intended to limit the invention. The singular form used herein includes the plural form unless the statement explicitly indicates otherwise. The word "comprising" as used in this specification means to specify a particular characteristic, region, integer, step, operation, element, and / or component, and does not exclude the presence or addition of other characteristics, regions, integers, steps, operations, elements, and / or components.

[0028] Unless otherwise defined in this application, all terms, including technical and scientific terms as used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with relevant technical literature and the content of this present instruction, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.

[0029] The display panel and its driving method of the present invention are further described below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments are not intended to limit the scope of protection of the present invention.

[0030] This invention provides a display panel to extend the charging time of pixel units. Figure 1 This is a schematic diagram of the array circuit structure of a display panel according to an embodiment of the present invention. Specifically, the display panel includes multiple pixel units, multiple gate lines, and multiple data lines.

[0031] Pixel units are arranged in an array on the display area of ​​the display panel. Multiple gate lines extend along the row direction, and each pixel unit Pmn is configured with two gate lines, where m is the column number of the pixel unit and n is the row number of the pixel unit. For ease of description, these two gate lines are defined as the first gate line Gn and the second gate line Gn', respectively. Multiple data lines extend along the column direction, and each column of pixel units is configured with three data lines. For ease of description, these three data lines are defined as the first data line Dm, the second data line Dm', and the third data line Dm'', respectively.

[0032] In the row direction, three data lines (i.e., the first data line Dm, the second data line Dm', and the third data line Dm'') are grouped together, corresponding to a column of pixel units, and are arranged periodically. That is, each column of pixel units has three corresponding data lines on the same side or both sides.

[0033] Each pixel unit includes a first switching transistor Tmn1, a second switching transistor Tmn2, and a pixel electrode (not shown). The control terminal (e.g., gate) of the first switching transistor Tmn1 is connected to the first gate line Gn of the corresponding row, its input terminal (e.g., source) is connected to the corresponding data line, and its output terminal (e.g., drain) is connected to the pixel electrode. The control terminal of the second switching transistor Tmn2 is connected to the second gate line Gn' of the corresponding row, its input terminal is connected to the corresponding data line, and its output terminal is connected to the pixel electrode. In this embodiment, the first switching transistor Tmn1 and the second switching transistor Tmn2 are used to write the voltage signal provided by the data line to the pixel electrode under the control of the conduction signal provided by the gate line, so as to control the display grayscale of the pixel unit.

[0034] For each column of pixel units, its corresponding three data lines are not connected to all pixel units in that column. Instead, they are distributed according to a predetermined row period and connected to the input terminals of the first switching transistor Tmn1 or the second switching transistor Tmn2 of a specific number of pixel units in that column. Furthermore, within the predetermined row period, the rows connected to the first data line Dm, the second data line Dm', and the third data line Dm'' are all different, and they collectively cover all rows within the predetermined row period.

[0035] Preferably, the predetermined row period is 6 rows. That is, every 6 rows of pixel units constitute a repeating unit, and the connection relationship between the three data lines of the column and the 6 rows of pixel units presents a periodic repetition. That is, the m-th row of pixel units can be labeled as the 6i+1, 6i+2, 6i+3, 6i+4, 6i+5 and 6i+6 rows, where i is a natural number (0, 1, 2, …).

[0036] In one specific embodiment, the first data line Dm of each column is connected to the input terminal of the first switching transistor of the pixel unit located in rows 6i+1, 6i+2, 6i+4, and 6i+5 of the m-th column. The second data line is connected to the input terminals of the second switching transistors of the pixel units located in rows 6i+1 and 6i+4 of the same column, and to the input terminals of the first switching transistors of the pixel units located in rows 6i+3 and 6i+6 of the same column; the third data line Dm'' is connected to the input terminals of the second switching transistors of the pixel units located in rows 6i+2, 6i+3, 6i+5, and 6i+6 of the m-th column. This connection relationship ensures that data line resources are rationally allocated within each 6-row cycle, providing a hardware foundation for subsequent alternating charging and pre-charging operations.

[0037] Taking the first 6 rows and the first column (i.e. i=0) of the display panel as an example, the first data line D1 of the first column is connected to the input terminals of the first switching transistor T111 of the pixel unit P11 in the first row, the first switching transistor T121 of the pixel unit P12 in the second row, the first switching transistor T141 of the pixel unit P14 in the fourth row, and the first switching transistor T151 of the pixel unit P15 in the fifth row.

[0038] The second data line D1' in the first column is connected to the input terminals of the second switching transistor T112 of the pixel unit P11 in the first row, the second switching transistor T142 of the pixel unit P14 in the fourth row, the first switching transistor T131 of the pixel unit P13 in the third row, and the first switching transistor T161 of the pixel unit P16 in the sixth row.

[0039] The third data line D1'' in the first column is connected to the input terminals of the second switching transistor T122 of pixel unit P12 in the second row, the second switching transistor T132 of pixel unit P13 in the third row, the second switching transistor T152 of pixel unit P15 in the fifth row, and the second switching transistor T162 of pixel unit P16 in the sixth row.

[0040] To improve display quality, in this embodiment, the display panel further includes a source driving module and a gate driving circuit. Specifically, the gate driving circuit is connected to multiple gate lines and is used to provide turn-on signals to the first gate line Gn and the second gate line Gn' in a time-division multiplexing manner. Within one frame display cycle, the gate driving circuit sequentially drives the gate lines of each row of pixel units Pmn, specifically by first turning on the first gate line Gn row by row, then turning on the second gate line Gn' row by row, or by using other preset timing sequences.

[0041] The source driver module includes a data driver chip and multiple multiplexing circuits. The data driver chip includes multiple output ports, each connected to a multiplexing circuit. The multiplexing circuit distributes the signal output from one output port to the first data line Dm, the second data line Dm', and the third data line Dm'' of a corresponding column of pixel units Pmn according to timing. By using multiplexing circuits, the number of pins on the data driver chip can be effectively reduced, lowering chip cost and the fan-out area of ​​the panel. Preferably, each output port of the data driver chip can output three data voltages in a time-division multiplexing manner, which are then provided to three data lines respectively through three switching transistors in the multiplexing circuit. Figure 1 As shown, each output port of the data driver chip can output three data voltages in a time-division manner, which are respectively provided to the first data line Dm through the first switch M1 in the multi-channel distribution circuit, to the second data line Dm' through the second switch M2, and to the third data line Dm'' through the third switch M3.

[0042] In this embodiment, the first data line Dm, the second data line Dm', and the third data line Dm'' can be connected to different data driver circuits to achieve independent voltage control. Alternatively, as described above, they can be connected to the output port of the same data driver chip through a multiplexing circuit to save resources. This invention does not impose specific limitations in this regard.

[0043] The display panel provided by this invention configures two gate lines for pixel units in the same row and three data lines for pixel units in the same column. Within one frame, during the row scanning phase, two of the three data lines sequentially charge and discharge the pixel units in the current row, while the third data line pre-charges the pixel units in the next row. This alternating charging and discharging of two data lines extends the charging time for pixel units in the same row, approximately twice the time of the existing architecture (one data line per column of pixels). This not only effectively solves the problem of insufficient pixel charging time in high-resolution, high-refresh-rate display panels but also avoids voltage attenuation due to leakage caused by prolonged continuous charging and discharging of a single data line, thereby improving display uniformity and image quality.

[0044] The driving method of the display panel of the present invention will be described in detail below with reference to specific timing.

[0045] Please see Figure 2 This invention also provides a driving method for a display panel, applied to the aforementioned display panel. The driving method includes: in a series of consecutive timing stages, sequentially turning on the first gate line Gn and the second gate line Gn' of each row of pixel units in a predetermined order via a gate driving circuit; simultaneously, pre-charging or writing data to the data lines or pixel units via a source driving module.

[0046] Based on the above connection relationship between the pixel unit and each data line (the predetermined row cycle is 6 rows), the driving method of the present invention includes the following 10 timing stages (t1 to t10) within a 6-row cycle, and repeats in this way. After each 6-row cycle is completed, i increases by 1.

[0047] For ease of understanding, the following description uses i=0 as an example, that is, the driving process for the pixel units in rows 1 to 6 (i.e., rows 6i+1 to 6i+6). In each stage, a low level indicates that the gate line is turned on or the data line is in a conducting state.

[0048] t1 stage (pre-charging stage 1): Both the first data line Dm and the second data line Dm' are in the on state, and the first data line Dm and the second data line Dm' are precharged in preparation for writing data to the first switching transistor Tmn1 and the second switching transistor Tmn2 of the pixel unit in the first row (6i+1 row) of all columns.

[0049] If both the first data line D1 and the second data line D1' in the first column are in the ON state, it is used to prepare the first switching transistor T111 and the second switching transistor T112 of the pixel unit P11 in the first row of the first column for data writing (pre-charging). Figure 3 As shown, the operating states of the pixel units in the remaining columns, the data lines connected to the pixel units, and the states of the gate lines are the same as in the first example, and the same applies to subsequent stages. At this time, the gate driving circuit has not yet turned on the gate lines of the first row. Pre-charging refers to pre-establishing the voltage on the first data line Dm and the second data line Dm' to a certain potential to prepare for subsequent data writing.

[0050] During this stage, the first data line Dm is pre-charged through its own load capacitance or related circuitry, and the second data line Dm' is pre-charged through its own load capacitance or related circuitry. For example, the first data line Dm is pre-charged through the first switching transistor Tm11 of the pixel unit Pm1 in the first row and m column, and the second data line Dm' is pre-charged through the second switching transistor Tm12 of the pixel unit Pm1 in the first row and n column.

[0051] t2 phase: The first gate line Gn of the first row (row 6i+1) is in the on state, and the first data line Dm of all columns writes data to the pixel unit of the first row in that column. At the same time, the third data line Dm'' is in the on state, and the third data line Dm'' is precharged in preparation for writing data to the second switching transistor Tmn2 of the pixel unit of the second row (row 6i+2) of all columns.

[0052] If the first gate line G1 in the first row and first column is in the ON state, the first data line D1 writes data to the pixel unit P11 in the first row and first column. Simultaneously, the third data line D1'' is in the ON state, pre-charging the third data line D1'' in preparation for writing data to the second switching transistor T122 of the pixel unit P12 in the second row and first column. Figure 4 As shown.

[0053] During this phase, the first data line Dm undertakes the data writing task for the current row (row 1), while the third data line Dm'' is pre-charged in advance to pre-charge the transistors required for the next row (row 2).

[0054] t3 phase: The second gate line Gn' of row 1 (row 6i+1) is enabled, and the second data line Dm' writes data to the pixel cells of row 1 (completing the full data writing of the pixel cells in row 1). The second gate line Gn' of row 2 (row 6i+2) is enabled, and the third data line Dm'' writes data to the pixel cells of row 2. Simultaneously, the first data line Dm is enabled, pre-charged, and prepared to write data to the first switching transistor Tmn1 of row 2 (row 6i+2).

[0055] If the second gate line G1' in the first row of the first column is on, the second data line D1' in the first row of the first column writes data to pixel unit P11 in the first column of the first row; if the second gate line G2' in the second row of the first column is on, the third data line D1'' in the first column writes data to pixel unit P12 in the second row; simultaneously, the first data line D1 is on, pre-charging the first data line D1 in preparation for writing data to the first switching transistor T121 in the second row. Figure 5 As shown.

[0056] This stage enables the second data writing to the first row of pixels, extending the charging time, while simultaneously initiating the formal writing and pre-charging of the second row of pixels.

[0057] t4 stage: The first gate line Gn of the second row (row 6i+2) is in the ON state, and the first data line Dm writes data to the pixel unit of the second row (completing the full data writing of the pixel unit of the second row). At the same time, the second data line Dm' and the third data line Dm'' are both in the ON state, pre-charging the second data line Dm'' and the third data line Dm'', preparing to write data to the first switching transistor Tmn1 and the second switching transistor Tmn2 of the pixel unit of the third row (row 6i+3).

[0058] If the first gate line G2 in the second row of the first column is turned on, the first data line D1 writes data to pixel unit P12 in the second row of the first column. Simultaneously, the second data line D1' and the third data line D1'' are both turned on, pre-charging them to prepare for writing data to the first switching transistor T131 and the second switching transistor T132 of pixel unit P13 in the third row of the first column. Figure 6 As shown.

[0059] t5 stage: The first gate line Gn of the third row (6i+3) is in the on state, and the second data line Dm' writes data to the pixel unit of the third row. At the same time, the first data line Dm is in the on state, and the first data line Dm is precharged in preparation for writing data to the first switching transistor Tmn1 of the pixel unit of the fourth row (6i+4).

[0060] If the first gate line G3 in the third row of the first column is in the ON state, the second data line D1' writes data to pixel unit P13 in the third row. Simultaneously, the first data line D1 is in the ON state, pre-charging it to prepare for writing data to the first switching transistor T141 of pixel unit P14 in the fourth row. Figure 7 As shown.

[0061] t6 stage: The second gate line Gn' of row 3 (row 6i+3) is turned on, and the third data line Dm'' writes data to the pixel unit of row 3 (completing the full data writing of the pixel unit of row 3). Simultaneously, the first gate line Gn of row 4 (row 6i+4) is turned on, and the first data line Dm writes data to the pixel unit of row 4. Furthermore, the second data line Dm' is turned on, pre-charged, and prepared to write data to the second switching transistor Tmn2 of the pixel unit of row 4 (row 6i+4).

[0062] If the second gate line G3' in the third row of column 1 is turned on, the third data line D1'' writes data to pixel unit P13 in the third row (completing the full data write of pixel unit P13 in the third row). Simultaneously, the first gate line G4 in the fourth row is turned on, and the first data line D1 writes data to pixel unit P14 in the fourth row. Furthermore, the second data line D1' is turned on, pre-charging it to prepare for writing data to the second switching transistor T142 of pixel unit P14 in the fourth row. Figure 8 As shown.

[0063] t7 stage: The second gate line Gn' of row 4 (row 6i+4) is in the ON state, and the second data line Dm' writes data to the pixel unit of row 4 (completing the full data writing of the pixel unit of row 4). At the same time, the first data line Dm and the third data line Dm'' are both in the ON state, pre-charging the first data line Dm and the third data line Dm'', preparing to write data to the first switching transistor Tmn1 and the second switching transistor Tmn2 of the pixel unit of row 5 (row 6i+5).

[0064] If the second gate line Gn' of the 4th row (6i+4th row) in column 1 is in the ON state, the second data line D1' writes data to the pixel unit in the 4th row. Simultaneously, the first data line D1 and the third data line D1'' are both in the ON state, pre-charging the first data line D1 and the third data line D1'' to prepare for writing data to the first switching transistor T151 and the second switching transistor T152 of the pixel unit in the 5th row (6i+5th row). Figure 9 As shown.

[0065] t8 stage: The second gate line Gn' of the 5th row (6i+5th row) is in the ON state, and the third data line Dm'' writes data to the pixel unit of the 5th row. At the same time, the second data line Dm' is in the ON state, pre-charged, and prepared to write data to the first switching transistor Tmn1 of the pixel unit of the 6th row (6i+6th row).

[0066] If the second gate line G5' in the 5th row of column 1 is in the ON state, the third data line D1'' writes data to pixel unit P15 in the 5th row. Simultaneously, the second data line D1' is in the ON state, pre-charging it to prepare for writing data to the first switching transistor T161 of pixel unit P16 in the 6th row. Figure 10 As shown.

[0067] t9 stage: The first gate line Gn of row 5 (row 6i+5) is turned on, and the first data line Dm writes data to the pixel unit of row 5 (completing the full data writing of the pixel unit of row 5). Simultaneously, the first gate line Gn of row 6 (row 6i+6) is turned on, and the second data line Dm' writes data to the pixel unit of row 6. Furthermore, the third data line Dm'' is turned on, pre-charging the third data line Dm'' in preparation for writing data to the second switching transistor Tmn2 of the pixel unit of row 6 (row 6i+6).

[0068] If the first gate line G5 in the 5th row of column 1 is turned on, the first data line D1 writes data to pixel unit P15 in the 5th row. Simultaneously, the first gate line G6 in the 6th row is turned on, and the second data line D1' writes data to pixel unit P16 in the 6th row. Furthermore, the third data line D1'' is turned on, pre-charging it to prepare for writing data to the second switching transistor T162 of pixel unit P16 in the 6th row. Figure 11 As shown.

[0069] t10 stage: The second gate line Gn' of row 6 (row 6i+6) is turned on, and the third data line Dm'' writes data to the pixel unit of row 6 (completes the full data writing of the pixel unit of row 6).

[0070] If the second gate line G6' in the 6th row of column 1 is in the ON state, the third data line D1'' writes data to pixel unit P16 in the 6th row (completing the full data write of pixel unit P16 in the 6th row). Figure 12 As shown.

[0071] As can be seen from the description of stages t1 to t10 above, for each row of pixel units, the data writing process may be distributed across multiple timing stages, completed by two different data lines in a time-sharing manner. For example, the first row of pixel units is written by the first data line Dm in stage t2, and then written again by the second data line Dm' in stage t3. This alternating charging and discharging method significantly increases the effective charging time of each row of pixels, ensuring that the pixel capacitor is fully charged to the target voltage, thereby improving the display effect.

[0072] Repeat the above stages t1 to t10. Each time a complete cycle from t1 to t10 is completed, i is incremented by 1, which enables drive control of all row pixel units on the display panel.

[0073] In some embodiments of the present invention, the gate driving circuit sequentially drives the first gate line Gn and the second gate line Gn' of each row of pixel units within the same frame period. For example, the turn-on signal can be provided sequentially in the order of the first gate line G1 of the first row, the second gate line G1' of the first row, the first gate line G2 of the second row, the second gate line G2' of the second row, and so on. Similarly, the data lines specifically connected to the first and second switching transistors can be adjusted, as long as the two switching transistors of each pixel unit are driven by different data lines. In other words, the connection relationship between each data line and each switching transistor can be adjusted according to the actual wiring requirements and the number of data lines without changing the row-by-row driving timing. In other embodiments, staggered activation or other preset sequences can also be used, as long as they can be coordinated with the above-mentioned data line pre-charging and write timing.

[0074] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

[0075] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that, include: Multiple pixel units, the multiple pixel units being arranged in an array in the display area of ​​the display panel; Multiple gate lines are provided, and each pixel unit is provided with two gate lines, namely a first gate line and a second gate line. Multiple data lines are provided, with three data lines corresponding to each column of pixel units, namely the first data line, the second data line, and the third data line; Each pixel unit includes a first switching transistor, a second switching transistor, and a pixel electrode. The control terminal of the first switching transistor is connected to the first gate line of the corresponding row, the control terminal of the second switching transistor is connected to the second gate line of the corresponding row, and the output terminals of both the first and second switching transistors are connected to the pixel electrode. For each column of pixel units, the first data line, the second data line, and the third data line are respectively connected to the input terminals of the first or second switching transistors of multiple rows of pixel units distributed in the column according to a predetermined row period, and the rows connected by the first data line, the second data line, and the third data line are different from each other in the predetermined row period and together cover all rows in the predetermined row period.

2. The display panel according to claim 1, characterized in that, The predetermined row cycle is 6 rows.

3. The display panel according to claim 2, characterized in that, The first data line is connected to the input terminal of the first switching transistor of the pixel unit located in the 6i+1, 6i+2, 6i+4 and 6i+5 rows of the column; The second data line is connected to the second switching transistor of the pixel unit located in the 6i+1 and 6i+4 rows of the column, and to the input terminal of the first switching transistor of the pixel unit located in the 6i+3 and 6i+6 rows. The third data line is connected to the input terminal of the second switching transistor of the pixel unit located in the 6i+2, 6i+3, 6i+5 and 6i+6 rows of the column; Where i is a natural number.

4. The display panel according to claim 1, characterized in that, The first data line, the second data line, and the third data line are respectively connected to different data driving circuits.

5. The display panel according to claim 1, characterized in that, It also includes a source driver module, which includes a data driver chip and multiple multiplexing circuits; The data driver chip includes multiple output ports, each of which is connected to a multiplexing circuit. The multiplexing circuit is used to distribute the signal output from one of the output ports to the three data lines of a column of pixel units.

6. The display panel according to claim 1, characterized in that, The first data line, the second data line, and the third data line extend along the column direction and are arranged periodically in the row direction according to the three data lines corresponding to a column of pixel units.

7. The display panel according to claim 1, characterized in that, It also includes a gate driving circuit, which is connected to multiple gate lines and is used to provide turn-on signals to the first gate line and the second gate line in a time-division manner.

8. The display panel according to claim 7, characterized in that, The gate driving circuit sequentially drives the first gate line and the second gate line of each row of pixel units within the same frame period.

9. A driving method for a display panel, characterized in that, The display panel described in claim 1 further includes a gate driving circuit. The gate driving circuit is connected to multiple gate lines and is used to provide turn-on signals to the first gate line and the second gate line in a time-division manner. The driving method includes: In a series of consecutive timing stages, the gate driving circuit sequentially turns on the first gate line and the second gate line of each row of pixel units in a predetermined order. Charge the data cable or pixel unit.

10. The driving method for a display panel according to claim 9, characterized in that, The predetermined row cycle is 6 rows; The first data line is connected to the input terminal of the first switching transistor located in rows 6i+1, 6i+2, 6i+4 and 6i+5 of the column; The second data line is connected to the second switching transistor of the pixel unit located in the 6i+1 and 6i+4 rows of the column, and to the input terminal of the first switching transistor of the pixel unit located in the 6i+3 and 6i+6 rows. The third data line is connected to the input terminal of the second switching transistor of the pixel unit located in rows 6i+2, 6i+3, 6i+5 and 6i+6 of the column; Where i is a natural number; The driving method includes: t1 stage: Both the first data line and the second data line are in the on state, and the first data line and the second data line are pre-charged in preparation for writing data to the first switching transistor and the second switching transistor of the pixel unit in row 6i+1. In stage t2: the first gate line of row 6i+1 is in the on state, and the first data line writes data to the pixel unit of row 6i+1; the third data line is in the on state, and the third data line is pre-charged in preparation for writing data to the second switching transistor of the pixel unit of row 6i+2. In stage t3: the second gate line of row 6i+1 is turned on, and the second data line writes data to the pixel unit of row 6i+1; the second gate line of row 6i+2 is turned on, and the third data line writes data to the pixel unit of row 6i+2; the first data line is turned on, and the first data line is pre-charged in preparation for writing data to the first switching transistor of the pixel unit of row 6i+2. t4 stage: The first gate line of row 6i+2 is in the on state, and the first data line writes data to the pixel unit of row 6i+2; the second data line and the third data line are both in the on state, and the second data line and the third data line are precharged in preparation for writing data to the first switching transistor and the second switching transistor of the pixel unit of row 6i+3. t5 stage: The first gate line of row 6i+3 is in the on state, and the second data line writes data to the pixel unit of row 6i+3; the first data line is in the on state, pre-charges the first data line, and prepares to write data to the first switching transistor of the pixel unit of row 6i+4. In stage t6: the second gate line of row 6i+3 is turned on, and the third data line writes data to the pixel unit of row 6i+3; the first gate line of row 6i+4 is turned on, and the first data line writes data to the pixel unit of row 6i+4; the second data line is turned on, and the second data line is pre-charged in preparation for writing data to the second switching transistor of the pixel unit of row 6i+4. t7 stage: The second gate line of row 6i+4 is in the on state, and the second data line writes data to the pixel unit of row 6i+4; the first data line and the third data line are both in the on state, pre-charge the first data line and the third data line, and prepare to write data to the first switching transistor and the second switching transistor of the pixel unit of row 6i+5. t8 stage: The second gate line of row 6i+5 is in the on state, and the third data line writes data to the pixel unit of row 6i+5; the second data line is in the on state, and the second data line is pre-charged in preparation for writing data to the first switching transistor of the pixel unit of row 6i+6. In stage t9: the first gate line of row 6i+5 is turned on, and the first data line writes data to the pixel unit of row 6i+5; the first gate line of row 6i+6 is turned on, and the second data line writes data to the pixel unit of row 6i+6; the third data line is turned on, and the third data line is pre-charged in preparation for writing data to the second switching transistor of the pixel unit of row 6i+6. In stage t10: the second gate line of row 6i+6 is turned on, and the third data line writes data to the pixel unit of row 6i+6. Repeat stages t1 through t10, incrementing i by 1 each time a complete cycle from t1 to t10 is completed.

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