Gate driving circuit and display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel. The gate driving circuit comprises N cascaded gate driving modules. Each gate driving module comprises an abnormality detection unit, is connected with a driving output end of a current stage and a detection line corresponding to the current stage respectively, and is configured to: in a scanning stage, transmit a signal state of a gate driving signal of the current stage to the detection line, so that a subsequent stage load determines whether the current stage gate driving module has an abnormality according to an output signal on the detection line. Therefore, by arranging the abnormality detection unit in each stage gate driving module and guiding the gate driving signal output by each stage gate driving module to the detection line, precise positioning of a fault position of a GOA unit is realized without damaging the panel.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, specifically relating to a gate driving circuit and a display panel. Background Technology

[0002] In the display panel, the Gate Driver on Array (GOA) circuit implements line-by-line scanning drive through multiple cascaded GOA units, with each GOA unit outputting a corresponding line scan signal (Gn). When a display malfunction occurs, it is necessary to locate the faulty GOA unit for fault analysis.

[0003] Currently, the common method is to break the glass of the color filter substrate to expose the GOA region, and then use an oscilloscope probe to probe the corresponding position. However, this method is cumbersome, and the GOA region is easily damaged during the breaking process. Inaccurate measurement signals may occur because the ITO traces in the GOA region are short-circuited with the ITO layer on the color filter substrate. Furthermore, the destructive nature of the experiment renders the sample unusable, resulting in wasted costs.

[0004] Therefore, how to accurately locate the fault position of the GOA unit without damaging the panel is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] This application provides a gate driving circuit and a display panel. By setting an anomaly detection unit in each stage of the gate driving module, the gate driving signals output by each stage of the gate driving module are guided to the detection line, thereby achieving accurate location of the fault position of the GOA unit without damaging the panel.

[0006] In a first aspect, this application provides a gate driving circuit, including N cascaded gate driving modules and multiple detection lines; the nth-stage gate driving module includes: a pre-charge unit, connected to the stage transmission output terminal of the nith-stage gate driving module and the drive control node of the current stage, configured to: pre-charge the drive control node of the current stage in response to the stage transmission signal output by the nith-stage gate driving module; an output unit, connected to the drive control node and the clock signal line corresponding to the current stage, configured to: output the stage transmission signal and the gate driving signal of the current stage in response to the clock signal output by the clock signal line and the voltage on the drive control node; and an anomaly detection unit, connected to the drive output terminal of the current stage and the detection line corresponding to the current stage, configured to: during the scanning phase, transmit the signal state of the gate driving signal of the current stage to the detection line, so that the subsequent load can determine whether there is an anomaly in the current stage gate driving module based on the output signal on the detection line.

[0007] Optionally, the anomaly detection unit includes: a storage subunit connected to a reference voltage terminal and a voltage storage node of the current stage, configured to: receive and store the reference voltage output from the reference voltage terminal during the blanking phase; and a detection subunit connected to the drive output terminal, the voltage storage node, and the detection line, configured to: in the scanning phase, in response to the voltage on the drive control node of the current stage, transfer the reference voltage on the voltage storage node to the detection line, so that the subsequent load determines whether there is an anomaly in the current stage gate drive module based on the comparison result between the reference voltage and the output voltage on the detection line.

[0008] Optionally, the gate drive circuit further includes a reset line, and the abnormality detection unit further includes a reset subunit, which is connected to the voltage storage node and the reset line respectively, and is configured to: in the blanking phase, in response to the reset voltage output by the reset line, reset the voltage storage node before the reference voltage is written to the voltage storage node.

[0009] Optionally, the storage sub-unit includes: a first transistor, wherein the control terminal and a first terminal of the first transistor are respectively connected to the reference voltage terminal; and a storage capacitor, wherein the first terminal of the storage capacitor is connected to the second terminal of the first transistor, and the second terminal of the storage capacitor is connected to the voltage storage node.

[0010] Optionally, the detection subunit includes: a second transistor, the control terminal of which is connected to the drive control node of the current stage or the stage output terminal of the current stage, and the first terminal of which is connected to the drive output terminal of the current stage; and a third transistor, the control terminal of which is connected to the second terminal of the second transistor, the first terminal of which is connected to the voltage storage node, and the second terminal of which is connected to the detection line of the current stage.

[0011] Optionally, the reset subunit includes: a fourth transistor, the control terminal of the fourth transistor being connected to the reset line, the first terminal of the fourth transistor being connected to the voltage storage node, and the second terminal of the fourth transistor being connected to a low-level terminal.

[0012] Optionally, the anomaly detection unit includes: a first detection subunit connected to the drive output terminal and the detection line, configured to: pull down the voltage on the detection line to a low level in response to the gate drive signal output by the drive output terminal of the current stage during the scanning phase under normal conditions and when the current stage is in a scanning state; and a second detection subunit connected to the drive output terminal and the detection line, configured to: pull down the voltage on the detection line to a low level in response to the gate drive signal output by the drive output terminal of the current stage during the scanning phase under normal conditions and when the current stage is in a non-scanning state.

[0013] Optionally, the first detection subunit includes: a fifth transistor, the control terminal of which is connected to the drive control node, the first terminal of which is connected to the drive output terminal, and the second terminal of which serves as a first node; and a sixth transistor, the control terminal of which is connected to the first node, the first terminal of which is connected to the detection line, and the second terminal of which is connected to a low-level terminal; wherein the first terminal of the sixth transistor serves as a second node.

[0014] Optionally, the second detection subunit includes: a seventh transistor, the control terminal of which is connected to a noise reduction control node, the first terminal of which is connected to the drive output terminal, and the second terminal of which is connected to the detection line; wherein the voltage of the noise reduction control node is opposite to that of the drive control node; and an eighth transistor, the control terminal of which is connected to the second node, the first terminal of which is connected to the first node, and the second terminal of which is connected to the low-level terminal.

[0015] Optionally, the precharge unit includes a ninth transistor, wherein the control terminal and the first terminal of the ninth transistor are connected to the drive output terminal of the ni-th gate drive module, and the second terminal of the ninth transistor is connected to the drive control node.

[0016] Optionally, the output unit includes a tenth transistor, an eleventh transistor, and a second capacitor; the control terminals of the tenth transistor and the eleventh transistor are respectively connected to the drive control node, the first terminals of the tenth transistor and the eleventh transistor are connected to the clock signal line, the second terminal of the tenth transistor serves as a stage transmission output terminal, and the second terminal of the eleventh transistor serves as a drive output terminal; wherein, the second capacitor is disposed between the drive control node and the drive output terminal.

[0017] Secondly, this application provides a display panel including a display area and a non-display area, wherein the display area includes multiple scan lines; the non-display area includes a gate driving circuit, and the drive output terminal of the circuit unit in the gate driving circuit is electrically connected to at least one scan line.

[0018] The technical solutions provided in this application have at least the following beneficial effects: This application sets up an anomaly detection unit in each stage of the gate drive module and connects the anomaly detection unit to the drive output terminal of the current stage and the corresponding detection line. This allows the gate drive signals output by each stage of the gate drive module to be guided to the detection line without affecting the normal display function. This enables the subsequent load to detect anomalies in the working state of each stage of the gate drive module, thereby achieving accurate location of GOA unit faults without damaging the panel, reducing detection costs, and improving the efficiency and accuracy of fault analysis. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0020] Figure 1 The diagram shown is a schematic diagram of a gate driving circuit provided in an embodiment of this application.

[0021] Figure 2 The diagram shown is a structural schematic of a gate driving module provided in an embodiment of this application.

[0022] Figure 3 The diagram shown is a circuit schematic of a gate driving module provided in an embodiment of this application.

[0023] Figure 4 The figure shown is a timing diagram provided in an embodiment of this application.

[0024] Figure 5 The diagram shown is a structural schematic of another gate driving module provided in an embodiment of this application.

[0025] Figure 6 The diagram shown is a circuit schematic of another gate driving module provided in an embodiment of this application.

[0026] Figure 7 The diagram shown is another timing diagram provided by an embodiment of this application.

[0027] Explanation of reference numerals in the attached figures: 10. Gate drive circuit; 100. Gate drive module; 110. Precharge unit; 120. Output unit; 130. Anomaly detection unit; 131. Storage subunit; 132. Detection subunit; 133. Reset subunit; 134. First detection subunit; 135. Second detection subunit; 200. Detection line; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; C1, storage capacitor; C2, output capacitor; Qn, drive control node; Gn, drive output terminal; Cn, voltage storage node; An, first node; Bn, second node; RE, reset line; SW, reference voltage terminal; Pn, noise reduction control node; VSS, low level terminal. Detailed Implementation

[0028] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0029] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0030] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0031] Figure 1The diagram shows a schematic of a gate driving circuit 10 according to an embodiment of this application. The gate driving circuit 10 of this embodiment includes N cascaded gate driving modules 100 and multiple detection lines 200. One gate driving module 100 is connected to one detection line 200. The number of detection lines 200 can be matched with the number of clock signal lines; that is, two adjacent gate driving modules 100 are connected to different detection lines 200, while multiple non-adjacent gate driving modules 100 can be connected to the same detection line 200. The detection lines 200 are used to transmit the status signals inside the gate driving module 100 to the subsequent load, so that the subsequent load can determine the operating status of the gate driving module 100. Figure 1 As shown, in this embodiment, each gate drive module 100 includes a precharge unit 110, an output unit 120, and an anomaly detection unit 130.

[0032] For the nth-stage gate drive module 100, the pre-charge unit 110 is connected to the stage transmission output terminal of the nith-stage gate drive module and the current-stage drive control node Qn, respectively. It is used to pre-charge the current-stage drive control node Qn in response to the stage transmission signal output by the nith-stage gate drive module; that is, when the stage transmission signal from the previous stage or multiple stages arrives, the current-stage drive control node Qn is pre-charged, allowing the voltage of this node to be established in advance, preparing for the subsequent output stage. It should be noted that in this embodiment, n is a variable, and N and i are constants. The value range of n is [1, 2, ..., N], and the value of i can be 2, 3, or 4. Figure 1 In this diagram, Qn-1 represents the drive control node of the (n-1)th stage gate drive module, Qn+1 represents the drive control node of the (n+1)th stage gate drive module, Gn-1 represents the drive output terminal of the (n-1)th stage gate drive module, Gn+1 represents the drive output terminal of the (n+1)th stage gate drive module, Fn-i represents the stage transmission output terminal of the nith stage gate drive module, Fn-1-i represents the stage transmission output terminal of the (n-1-i)th stage gate drive module, Fn+1-i represents the stage transmission output terminal of the (n+1-i)th stage gate drive module, CF1 represents the detection line corresponding to the (n-1)th stage gate drive module, CF2 represents the detection line corresponding to the nth stage gate drive module, and CF3 represents the detection line corresponding to the (n+1)th stage gate drive module.

[0033] In this embodiment, the output unit 120 is connected to the drive control node Qn and the clock signal line corresponding to the current stage, respectively. It is used to output the stage transmission signal and the gate drive signal of the current stage in response to the clock signal output from the clock signal line and the voltage on the drive control node Qn. That is, after the voltage of the drive control node Qn is established, in response to the clock signal provided by the clock signal line, the clock signal is output as the gate drive signal of the current stage to the pixel array of the display panel to drive the pixels of the corresponding row to turn on. At the same time, the clock signal is also output as the stage transmission signal to the gate drive module 100 of the next stage or multiple stages below, as the input trigger signal of its precharge unit 110.

[0034] In this embodiment, the anomaly detection unit 130 is connected to the current stage's drive output terminal Gn and the corresponding detection line 200, respectively. It is configured to: during the scanning phase, transmit the signal state of the current stage's gate drive signal to the detection line 200, so that the subsequent load can determine whether the current stage's gate drive module 100 is abnormal based on the output signal on the detection line 200.

[0035] It should be noted that in this embodiment, the downstream load (such as a source driver chip or timing controller) is connected to each detection line 200. Based on the signal output from each detection line 200, the amplitude, timing, or level state of the signal is analyzed to determine which stage of the gate driver module 100 has an abnormal output. In other words, the function of the anomaly detection unit 130 is to lead out the state of the gate drive signal to the detection line 200 for downstream load to judge without affecting the normal output function of the gate driver module 100.

[0036] In summary, this application sets up an anomaly detection unit 130 in each stage gate drive module 100 and connects the anomaly detection unit 130 to the current stage drive output terminal Gn and the corresponding detection line 200, so that the gate drive signals output by each stage gate drive module 100 are guided to the detection line 200 without affecting the normal display function. This enables the subsequent load to detect anomalies in the working state of each stage gate drive module 100, thereby achieving accurate location of the gate drive unit fault without damaging the panel, reducing detection costs, and improving the efficiency and accuracy of fault analysis.

[0037] Figure 2 The diagram shown is a structural schematic of a gate driving module 100 provided in an embodiment of this application; as follows: Figure 2 As shown, the anomaly detection unit 130 in this embodiment includes a storage subunit 131 and a detection subunit 132, specifically: (1) The storage sub-unit 131 is connected to the reference voltage terminal SW and the voltage storage node Cn of the current stage, respectively, and is used to receive and store the reference voltage output by the reference voltage terminal SW during the blanking phase of the previous frame. The blanking phase is the idle period between two adjacent scanning phases. During this period, the gate driving module 100 does not output the gate driving signal. Therefore, the storage sub-unit 131 can use this idle time to complete the sampling and storage of the reference voltage without interfering with the normal scanning driving process. The voltage storage node Cn is a node with charge retention capability, which can maintain the stored voltage value for a period of time.

[0038] (2) The detection subunit 132 is connected to the drive output terminal Gn, the voltage storage node Cn, and the detection line 200, respectively. During the scanning phase of the current frame, in response to the voltage on the current stage drive control node Qn, it transmits the reference voltage on the voltage storage node Cn to the detection line 200, so that the subsequent load can determine whether there is an abnormality in the current stage gate drive module 100 based on the comparison result between the reference voltage and the output voltage on the detection line 200. It should be noted that during the blanking phase, since the drive control node Qn is in an inactive state, the detection subunit 132 is not turned on, so the reference voltage stored in the storage subunit 131 will not be transmitted to the detection line 200. When the scanning phase arrives, the current stage drive control node Qn is charged to a high level by the pre-charge unit 110, and the detection subunit 132 is turned on in response to the voltage on the drive control node Qn, transmitting the reference voltage stored on the voltage storage node Cn to the detection line 200. In other words, the detection subunit 132 provides a signal path during the scanning phase, so that an electrical connection is formed between the voltage storage node Cn and the detection line 200, and the voltage collected by the subsequent load on the detection line 200 is the reference voltage pre-stored by the storage subunit 131.

[0039] It should be noted that the subsequent load compares the voltage received on detection line 200 with the original reference voltage output from the reference voltage terminal SW. If the two are basically consistent, it indicates that the detection sub-unit 132 is conducting normally during the scanning phase, and the reference voltage on the voltage storage node Cn is successfully transmitted to the detection line 200. This indirectly indicates that the current stage's drive control node Qn and drive output terminal Gn are both in normal working condition. If there is a significant deviation between the two, such as the voltage on detection line 200 being much lower than the reference voltage or having no signal at all, it indicates that the detection sub-unit 132 has failed to conduct normally. This could be due to the voltage of the drive control node Qn failing to establish, or it could be due to an abnormality in the drive output terminal Gn itself, causing the detection sub-unit 132 to malfunction. The subsequent load can then determine whether there is an abnormality in the current stage's gate drive module 100 based on the comparison result.

[0040] Therefore, this embodiment achieves time-division multiplexing of the reference voltage through the cooperation of the storage subunit 131 and the detection subunit 132. Specifically, the reference voltage is stored during the blanking phase and transmitted to the detection line 200 during the scanning phase for judgment by the subsequent load. Since the reference voltage is a known and stable benchmark value, the subsequent load only needs to compare the voltage on the detection line 200 with the original reference voltage to determine the anomaly, eliminating the need for complex signal analysis, reducing the processing requirements of the subsequent load, and improving the reliability of anomaly detection.

[0041] In another embodiment, such as Figure 2 As shown, the gate drive circuit 10 also includes a reset line RE, and the abnormal detection unit 130 also includes a reset subunit 133. The reset subunit 133 is connected to the voltage storage node Cn and the reset line RE respectively, and is used to reset the voltage storage node Cn during the blanking phase of each frame and before the reference voltage is written to the voltage storage node Cn.

[0042] Specifically, at the start of the blanking phase, the reset line RE first outputs a reset voltage, controlling the reset sub-unit 133 to conduct, releasing the residual charge on the voltage storage node Cn to a low level, thus pulling the potential of the voltage storage node Cn down to its initial state. Subsequently, the reference voltage terminal SW outputs a reference voltage, and the storage sub-unit 131 writes the reference voltage into the already cleared voltage storage node Cn. In other words, the reset operation and the write operation are performed sequentially and do not overlap.

[0043] This embodiment introduces a reset subunit 133 and controls the reset operation to be executed before the write operation in terms of timing. This ensures that the voltage storage node Cn is in a consistent initial state before storing the reference voltage each time, thereby guaranteeing the accuracy and consistency of the reference voltage stored in each frame and improving the accuracy and reliability of anomaly detection.

[0044] Figure 3 The diagram shown is a circuit schematic of a gate driving module 100 provided in an embodiment of this application; as follows: Figure 3 As shown, the storage sub-unit 131 in this embodiment includes a first transistor T1 and a storage capacitor C1; the control terminal and the first terminal of the first transistor T1 are respectively connected to the reference voltage terminal SW; the first terminal of the storage capacitor C1 is connected to the second terminal of the first transistor T1, and the second terminal of the storage capacitor C1 is connected to the voltage storage node Cn.

[0045] like Figure 3As shown, the detection subunit 132 in this embodiment includes a second transistor T2 and a third transistor T3; the control terminal of the second transistor T2 is connected to the drive control node Qn of the current stage or the stage transmission output terminal Gn of the current stage, and the first terminal of the second transistor T2 is connected to the drive output terminal Gn of the current stage; the control terminal of the third transistor T3 is connected to the second terminal of the second transistor T2, the first terminal of the third transistor T3 is connected to the voltage storage node Cn, and the second terminal of the third transistor T3 is connected to the detection line 200 of the current stage.

[0046] like Figure 3 As shown, the reset subunit 133 in this embodiment includes: a fourth transistor T4, the control terminal of the fourth transistor T4 is connected to the reset line RE, the first terminal of the fourth transistor T4 is connected to the voltage storage node Cn, and the second terminal of the fourth transistor T4 is connected to the low-level terminal VSS.

[0047] This combination Figure 4 The corresponding timing diagram illustrates the working principle of the gate drive module 100 in this embodiment as follows: (1) During the scanning phase of the current frame: the precharge unit 110 receives the stage transmission signal output by the nith stage and precharges the drive control node Qn, causing the potential of the drive control node Qn to rise. The output unit 120 responds to the voltage and clock signal on the drive control node Qn, outputs the gate drive signal to the pixel array, and simultaneously outputs the signal as a stage transmission signal to the next stage.

[0048] At this time, the drive control node Qn is at a high level, the gate drive signal is at a high level, and the second transistor T2 and the third transistor T3 are in the on state; the reference voltage terminal SW outputs a low level. Although the first transistor T1 is in the off state, the storage capacitor C1 has stored the reference voltage written in the previous frame's blanking stage and maintains this voltage. Therefore, the on-state third transistor T3 transfers the reference voltage on the voltage storage node Cn to the detection line 200. At the same time, the reset line RE outputs a low level, and the fourth transistor T4 is in the off state. It should be noted that the subsequent stage load collects the voltage of the detection line 200 during the corresponding time period when this stage is scanned. At this time, the voltage on the detection line 200 is consistent with the reference voltage stored in the storage capacitor C1, indicating that the current stage is working normally.

[0049] (2) During the blanking phase of the current frame: At the beginning of the blanking phase, the reset line RE outputs a high-level reset voltage, the fourth transistor T4 is turned on, connecting the voltage storage node Cn to the low-level terminal VSS, releasing any residual charge on the storage capacitor C1 to the low-level terminal VSS, and resetting the voltage of the storage capacitor C1 to a low level. Subsequently, the reset voltage becomes invalid, and the fourth transistor T4 is turned off. Then, the reference voltage terminal SW outputs a high-level reference voltage, the first transistor T1 is turned on, and the reference voltage charges the storage capacitor C1 through the first transistor T1. The voltage across the storage capacitor C1 gradually rises and stabilizes at the amplitude of the reference voltage. Subsequently, the reference voltage becomes invalid, and the first transistor T1 is turned off. Since the first transistor T1 uses a diode connection, it can prevent the reverse leakage of charge on the storage capacitor C1 after being turned off, and the storage capacitor C1 continues to maintain the reference voltage. During this phase, the second transistor T2 and the third transistor T3 are both turned off, and there is no signal output on the detection line 200.

[0050] It should be noted that the downstream load determines whether the currently scanned stage is working properly by comparing the voltage on detection line 200 with the reference voltage stored in storage capacitor C1: if they match, it indicates that the drive control node Qn and the gate drive signal of that stage are normal; if there is no signal on detection line 200 or the signal amplitude deviates significantly from the reference voltage, it indicates that the drive control node Qn of that stage has failed to establish a high level or the gate drive signal is abnormal. When the drive control node Qn fails to establish a high level, the second transistor T2 is not turned on, the third transistor T3 cannot be turned on, and the reference voltage in storage capacitor C1 cannot be transmitted to detection line 200. When the gate drive signal is abnormal and its voltage amplitude is insufficient, although the second transistor T2 is turned on, it cannot make the control terminal of the third transistor T3 reach a sufficient turn-on voltage, the third transistor T3 cannot be fully turned on, and the signal output on detection line 200 shows amplitude attenuation. The downstream load can deduce and accurately locate the faulty stage based on the timing of the detected abnormality.

[0051] Figure 5 The diagram shown is a structural schematic of another gate driving module 100 provided in an embodiment of this application; as follows: Figure 5 As shown, the anomaly detection unit 130 in this embodiment includes a first detection subunit 134 and a second detection subunit 135, specifically: (1) The first detection subunit 134 is connected to the drive output terminal Gn and the detection line 200. During the normal scanning phase and when the current stage is in scanning mode, it pulls the voltage on the detection line 200 down to a low level in response to the gate drive signal output by the drive output terminal Gn of the current stage. It should be noted that when the current stage is in scanning mode, the drive control node Qn is at a high level, and the drive output terminal Gn outputs a high-level gate drive signal. The first detection subunit 134 is turned on under the control of this gate drive signal, connecting the detection line 200 to the low-level terminal VSS, thereby pulling the voltage on the detection line 200 down to a low level. When the drive output terminal Gn fails to output a high-level gate drive signal normally, the first detection subunit 134 cannot be turned on, and the voltage on the detection line 200 will remain at a high level or in a floating state, instead of being pulled down to a low level.

[0052] (2) The second detection subunit 135 is connected to the drive output terminal Gn and the detection line 200. During the scanning phase under normal conditions, when the current stage is in a non-scanning state, it pulls the voltage on the detection line 200 down to a low level in response to the gate drive signal output from the drive output terminal Gn of the current stage. It should be noted that when the current stage is in a non-scanning state, the drive control node Qn is at a low level, but the gate drive signal on the drive output terminal Gn is also at a low level during the non-scanning period. The second detection subunit 135 is turned on in response to this low-level gate drive signal, connecting the detection line 200 to the low-level terminal VSS, thus maintaining the voltage on the detection line 200 at a low level. In other words, regardless of whether the current stage is in a scanning state or a non-scanning state, during normal operation, the first detection subunit 134 and the second detection subunit 135 continuously pull the detection line 200 down to a low level during their respective corresponding time periods. Therefore, the detection line 200 remains at a low level throughout the entire scanning phase.

[0053] It should be noted that the downstream load continuously monitors the voltage of the detection line 200 throughout the scanning phase. During normal operation, the detection line 200 is always at a low level. If the detection line 200 reaches a high level or floats during a certain period, it indicates that the first detection subunit 134 or the second detection subunit 135, which should have been conducting during that period, failed to perform the pull-down operation correctly. Based on the periods when the detection line 200 is not at a low level, and combined with the current scanning timing, the downstream load can determine that the gate drive module 100 corresponding to that period is malfunctioning. Therefore, in this embodiment, the first detection subunit 134 and the second detection subunit 135 alternately pull the detection line 200 to a low level during different periods, ensuring that the detection line 200 is always at a low level during normal operation. The downstream load only needs to detect whether the detection line 200 is always at a low level to determine whether any stage is malfunctioning. The determination logic is simple and efficient, requires no reference voltage, and has a more simplified structure. Meanwhile, since the detection line 200 is always at a low level during normal operation, the downstream load does not need to distinguish the difference in signal amplitude between normal and abnormal conditions, but only needs to determine whether there is a non-low level signal, which improves the anti-interference capability and reliability of the detection.

[0054] Figure 6 The diagram shown is a circuit schematic of another gate driving module 100 provided in an embodiment of this application; as follows: Figure 6 As shown, the first detection subunit 134 in this embodiment includes a fifth transistor T5 and a sixth transistor T6; the control terminal of the fifth transistor T5 is connected to the drive control node Qn, the first terminal of the fifth transistor T5 is connected to the drive output terminal Gn, and the second terminal of the fifth transistor T5 serves as the first node An; the control terminal of the sixth transistor T6 is connected to the first node An, the first terminal of the sixth transistor T6 is connected to the detection line 200, and the second terminal of the sixth transistor T6 is connected to the low-level terminal VSS; wherein, the first terminal of the sixth transistor T6 serves as the second node Bn.

[0055] like Figure 6 As shown, the second detection subunit 135 in this embodiment includes a seventh transistor T7 and an eighth transistor T8; the control terminal of the seventh transistor T7 is connected to the noise reduction control node Pn, the first terminal of the seventh transistor T7 is connected to the drive output terminal Gn, and the second terminal of the seventh transistor T7 is connected to the detection line 200; the control terminal of the eighth transistor T8 is connected to the second node Bn, the first terminal of the eighth transistor T8 is connected to the first node An, and the second terminal of the eighth transistor T8 is connected to the low-level terminal VSS.

[0056] This combination Figure 7 The corresponding timing diagram illustrates the working principle of the gate drive module 100 in this embodiment as follows: (1) During the scanning phase of the current frame and when the current level is in scanning state: the precharge unit 110 receives the stage transmission signal output by the ni-th level and precharges the drive control node Qn, causing the potential of the drive control node Qn to rise. The output unit 120 responds to the voltage and clock signal on the drive control node Qn, outputs the gate drive signal to the pixel array, and simultaneously outputs the signal as a stage transmission signal to the next level. At this time, the drive control node Qn is at a high level, the gate drive signal is at a high level, and the noise reduction control node Pn is at a low level. The fifth transistor T5 turns on in response to the high level of the drive control node Qn, and transmits the high level of the gate drive signal to the first node An, making the first node An high level. The sixth transistor T6 turns on in response to the high level of the first node An, connecting the detection line 200 (i.e., the second node Bn) to the low-level terminal VSS, and the voltage on the detection line 200 is pulled down to a low level. Meanwhile, the control terminal of the seventh transistor T7 is in a turned-off state because the noise reduction control node Pn is at a low level, and the control terminal of the eighth transistor T8 is also in a turned-off state because the detection line 200 is at a low level. Therefore, during normal operation, the detection line 200 remains at a low level during this period. The subsequent load collects the voltage of the detection line 200 during the corresponding period when this stage is scanned. At this time, it is at a low level, indicating that the current stage is working normally during this period. It should be noted that the noise reduction control node Pn in this embodiment is a key node in the noise reduction unit (not shown in the figure) in the gate drive module 100. The voltages of the noise reduction control node Pn and the drive control node Qn are opposite, specifically as follows: Figure 7 As shown.

[0057] (2) During the scanning phase of the current frame and when the current stage is in a non-scanning state: the drive control node Qn becomes low, the gate drive signal becomes low, and the noise reduction control node Pn becomes high. The fifth transistor T5 turns off in response to the low level of the drive control node Qn, and the first node An becomes floating. The seventh transistor T7 turns on in response to the high level of the noise reduction control node Pn, transmitting the low-level gate drive signal on the drive output terminal Gn to the detection line 200, which is pulled down to a low level. The control terminal of the eighth transistor T8 is connected to the detection line 200. The low level of the detection line 200 turns on the eighth transistor T8, connecting the first node An to the low-level terminal VSS, further ensuring that the first node An remains at a low level. The sixth transistor T6 turns off in response to the low level of the first node An. Therefore, during normal operation, the detection line 200 remains at a low level during this period. That is, regardless of whether the current stage is in a scanning state or a non-scanning state, the detection line 200 is always pulled down to a low level throughout the scanning phase.

[0058] It should be noted that the downstream load continuously monitors the voltage of detection line 200 throughout the scanning phase. If detection line 200 is high or floating at any moment, it indicates that the transistor that should have been turned on and pulled down to low level at that moment has failed to function properly. Since the downstream load can know the current stage being scanned, it can deduce the fault location based on the timing of non-low level occurrences of detection line 200. Specifically, if detection line 200 is high while a stage is in scanning mode, it indicates an abnormality in the drive control node Qn or gate drive signal of that stage, causing the fifth transistor T5 or the sixth transistor T6 to fail to conduct properly; if detection line 200 is high while a stage is not in scanning mode, it indicates an abnormality in the noise reduction control node Pn of that stage, causing the seventh transistor T7 to fail to conduct properly. Based on this, the downstream load can accurately locate the faulty stage and preliminarily determine the type of fault signal.

[0059] Finally, it should be noted that... Figure 2 and Figure 6 In the circuit structure shown, the precharge unit 110 includes a ninth transistor T9. The control terminal and the first terminal of the ninth transistor T9 are connected to the drive output terminal of the ni-th stage gate drive module, and the second terminal of the ninth transistor T9 is connected to the drive control node Qn. The output unit 120 includes a tenth transistor T10, an eleventh transistor T11, and a second capacitor C2. The control terminals of the tenth transistor T10 and the eleventh transistor T11 are respectively connected to the drive control node Qn. The first terminals of the tenth transistor T10 and the eleventh transistor T11 are connected to the clock signal line. The second terminal of the tenth transistor T10 serves as the stage transmission output terminal Fn, and the second terminal of the eleventh transistor T11 serves as the drive output terminal Gn. The second capacitor C2 is disposed between the drive control node Qn and the drive output terminal Gn. In this embodiment, the tenth transistor T10 is used to output the stage transmission signal, and the eleventh transistor T11 is used to output the gate drive signal. The working principle of the precharge unit 110 and the output unit 120 in this embodiment is the same as that of related technologies, and will not be described again here.

[0060] In one embodiment, this application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines; the non-display area includes a gate driving circuit of any of the above embodiments, and the drive output terminal of the gate driving module in the gate driving circuit is electrically connected to at least one scan line.

[0061] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0062] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0063] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, It includes N cascaded gate drive modules and multiple detection lines; the nth stage gate drive module includes: The pre-charge unit is connected to the stage transmission output terminal of the ni-th stage gate drive module and the drive control node of the current stage, respectively, and is configured to: pre-charge the drive control node of the current stage in response to the stage transmission signal output by the ni-th stage gate drive module. The output unit, which is connected to the drive control node and the clock signal line corresponding to the current stage, is configured to output the stage transmission signal and the gate drive signal of the current stage in response to the clock signal output by the clock signal line and the voltage on the drive control node. The storage sub-unit, which is connected to the reference voltage terminal and the voltage storage node of the current stage respectively, is configured to receive and store the reference voltage output by the reference voltage terminal during the blanking phase. The detection subunit, connected to the drive output terminal of the current stage, the voltage storage node, and the detection line corresponding to the current stage, is configured to: during the scanning phase, in response to the voltage on the drive control node of the current stage, transfer the reference voltage on the voltage storage node to the detection line, so that the subsequent load can determine whether there is an abnormality in the gate drive module of the current stage based on the comparison result between the reference voltage and the output voltage on the detection line.

2. The gate driving circuit according to claim 1, characterized in that, The gate driving circuit further includes a reset line, and the gate driving circuit further includes: A reset subunit, connected to the voltage storage node and the reset line respectively, is configured to: during the blanking phase, in response to the reset voltage output by the reset line, reset the voltage storage node before the reference voltage is written to the voltage storage node.

3. The gate driving circuit according to claim 1, characterized in that, The storage subunit includes: The first transistor has its control terminal and its first terminal connected to the reference voltage terminal, respectively. A storage capacitor, the first end of which is connected to the second end of the first transistor, and the second end of which is connected to the voltage storage node.

4. The gate driving circuit according to claim 1, characterized in that, The detection subunit includes: The second transistor has its control terminal connected to the drive control node of the current stage or the stage output terminal of the current stage, and its first terminal connected to the drive output terminal of the current stage. The third transistor has its control terminal connected to the second terminal of the second transistor, its first terminal connected to the voltage storage node, and its second terminal connected to the detection line of the current stage.

5. The gate driving circuit according to claim 2, characterized in that, The reset subunit includes: The fourth transistor has its control terminal connected to the reset line, its first terminal connected to the voltage storage node, and its second terminal connected to the low-level terminal.

6. A gate driving circuit, characterized in that, It includes N cascaded gate drive modules and multiple detection lines; the nth stage gate drive module includes: The pre-charge unit is connected to the stage transmission output terminal of the ni-th stage gate drive module and the drive control node of the current stage, respectively, and is configured to: pre-charge the drive control node of the current stage in response to the stage transmission signal output by the ni-th stage gate drive module. The output unit, which is connected to the drive control node and the clock signal line corresponding to the current stage, is configured to output the stage transmission signal and the gate drive signal of the current stage in response to the clock signal output by the clock signal line and the voltage on the drive control node. The first detection subunit, connected to the drive output terminal of the current stage and the detection line corresponding to the current stage, is configured to: pull down the voltage on the detection line to a low level in response to the gate drive signal output by the drive output terminal of the current stage during the normal scanning phase and when the current stage is in the scanning state. The second detection subunit, connected to the drive output terminal and the detection line, is configured to: during the scanning phase under normal conditions and when the current stage is in a non-scanning state, pull down the voltage on the detection line to a low level in response to the gate drive signal output by the drive output terminal of the current stage.

7. The gate driving circuit according to claim 6, characterized in that, The first detection subunit includes: The fifth transistor has its control terminal connected to the drive control node, its first terminal connected to the drive output terminal, and its second terminal serving as the first node. A sixth transistor, wherein the control terminal of the sixth transistor is connected to the first node, the first terminal of the sixth transistor is connected to the detection line, and the second terminal of the sixth transistor is connected to the low-level terminal; wherein the first terminal of the sixth transistor serves as the second node.

8. The gate driving circuit according to claim 7, characterized in that, The second detection subunit includes: A seventh transistor, the control terminal of which is connected to a noise reduction control node, the first terminal of which is connected to the drive output terminal, and the second terminal of which is connected to the detection line; wherein, the voltage of the noise reduction control node is opposite to that of the drive control node; The eighth transistor has its control terminal connected to the second node, its first terminal connected to the first node, and its second terminal connected to the low-level terminal.

9. The gate driving circuit according to any one of claims 1-8, characterized in that, The precharge unit includes: a ninth transistor, the control terminal and the first terminal of the ninth transistor are connected to the drive output terminal of the ni-th gate drive module, and the second terminal of the ninth transistor is connected to the drive control node; The output unit includes a tenth transistor, an eleventh transistor, and a second capacitor; the control terminals of the tenth transistor and the eleventh transistor are respectively connected to the drive control node, the first terminals of the tenth transistor and the eleventh transistor are connected to the clock signal line, the second terminal of the tenth transistor serves as the stage transmission output terminal, and the second terminal of the eleventh transistor serves as the drive output terminal; wherein, the second capacitor is disposed between the drive control node and the drive output terminal.

10. A display panel, comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines; characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-9, wherein the driving output terminal of the circuit unit in the gate driving circuit is electrically connected to at least one scan line.

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