Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a display area and a non-display area located on at least one side of the display area. The non-display area is provided with a gate drive circuit. The gate drive circuit comprises a first silicon semiconductor transistor and a first oxide transistor. The first silicon semiconductor transistor comprises a first bottom gate electrode and a first active part arranged along the thickness direction of the display panel. The first oxide transistor is located on the side of the first silicon semiconductor transistor away from the substrate. The first oxide transistor comprises a second bottom gate electrode and a second active part arranged along the thickness direction of the display panel. The interval between the second bottom gate electrode of the first oxide transistor and the substrate is greater than the interval between the first bottom gate electrode of the first silicon semiconductor transistor and the substrate. The second bottom gate electrode on the side relatively closer to the water vapor intrusion path is farther away from the substrate, thereby reducing the risk of corrosion of the second bottom gate electrode by water vapor and improving the reliability of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the continuous development of display technology, people have placed increasingly higher demands on the resolution, power consumption, and image quality of display products. To improve display performance, existing display devices typically employ Low Temperature Polycrystalline Oxide (LTPO) technology to fabricate the pixel driving circuits in the display panel's driving backplane. LTPO technology combines the high carrier mobility of Low Temperature Polycrystalline Silicon (LTPS) with the low leakage current characteristics of oxide semiconductors, offering advantages such as high resolution, high response speed, high brightness, high aperture ratio, and low power consumption.

[0003] In existing display panels using LTPO technology, the LTPO pixel driving circuit requires a gate-on-array (GOA) driving circuit located on the array substrate to provide the driving signal. However, to meet the requirements of narrow bezel design, the GOA circuit is usually integrated into the non-display area surrounding the display area. This significantly reduces the space of the encapsulation or barrier structure originally located in the bezel area, making it easier for moisture to seep into the non-display area from the substrate edge. At the same time, in the gate driving circuit located in the GOA area, the bottom gates of the thin-film transistor devices are usually located on the same conductive layer. The bottom gates of thin-film transistors in different areas of this conductive layer are connected to different potential signals. When moisture intrudes, the potential difference within the same conductive layer can easily trigger electrochemical corrosion, causing corrosion failure of circuit traces or electrodes. This, in turn, causes abnormal driving function of the display panel and reduces the long-term reliability of the product. Summary of the Invention

[0004] This application provides a display panel and display device to reduce the risk of corrosion failure of non-display area circuits in the display panel due to moisture intrusion.

[0005] This application provides a display panel, including a display area and a non-display area located on at least one side of the display area. The display panel includes a substrate and a gate driving circuit located on one side of the substrate. The gate driving circuit is located in the non-display area and includes: The first silicon semiconductor transistor includes a first bottom gate and a first active portion disposed along the thickness direction of the display panel; A first oxide transistor is located on the side of the first silicon semiconductor transistor away from the substrate. The first oxide transistor includes a second bottom gate and a second active portion disposed along the thickness direction of the display panel. The distance between the second bottom gate and the substrate is greater than the distance between the first bottom gate and the substrate.

[0006] Optionally, in one embodiment, the gate driving circuit further includes a second oxide transistor, the distance between the second oxide transistor and the display area is smaller than the distance between the first oxide transistor and the display area, and the second oxide transistor includes a third bottom gate and a third active portion disposed along the thickness direction of the display panel; The distance between the third bottom gate and the substrate is greater than or equal to the distance between the first bottom gate and the substrate.

[0007] Optionally, in one embodiment, the spacing between the third bottom gate and the substrate is equal to the spacing between the second bottom gate and the substrate.

[0008] Optionally, in one embodiment, the display panel includes multiple sets of gate driving circuits, the multiple sets of gate driving circuits including a first set of gate driving circuits and multiple second sets of gate driving circuits; The distance between the first group of gate driving circuits and the display area is greater than the distance between the plurality of second group of gate driving circuits and the display area. The first group of gate driving circuits includes the first oxide transistor, and the second group of gate driving circuits includes the second oxide transistor.

[0009] Optionally, in one embodiment, at least one of the second group of gate drive circuits further includes the first oxide transistor.

[0010] Optionally, in one embodiment, the display panel includes: A first electrode layer is disposed on the substrate and includes the first bottom gate of the first silicon semiconductor transistor; A first active layer is disposed on the side of the first electrode layer away from the substrate, and includes the first active portion of the first silicon semiconductor transistor; The second electrode layer is disposed on the side of the first active layer away from the substrate, and includes the first top gate of the first silicon semiconductor transistor and the second bottom gate of the first oxide transistor. The second active layer is disposed on the side of the second electrode layer away from the substrate, and includes the second active portion of the first oxide transistor; A third electrode layer is disposed on the side of the second active layer away from the substrate, and includes the second top gate of the first oxide transistor.

[0011] Optionally, in one embodiment, the display panel further includes a storage capacitor, the storage capacitor including a first electrode and a second electrode, the first electrode and the second electrode being disposed opposite to each other along the thickness direction of the display panel; The second electrode layer further includes the first electrode plate of the storage capacitor; the second electrode plate of the storage capacitor is disposed on the same layer as the second active part.

[0012] Optionally, in one embodiment, the display panel further includes a pixel driving circuit located in the display area, the pixel driving circuit comprising: The second silicon semiconductor transistor includes a fourth bottom gate and a fourth active portion disposed along the thickness direction of the display panel; The third oxide transistor includes a fifth bottom gate and a fifth active portion disposed along the thickness direction of the display panel; The spacing between the first bottom gate and the substrate, the spacing between the fourth bottom gate and the substrate, and the spacing between the fifth bottom gate and the substrate are all equal.

[0013] Optionally, in one embodiment, the first bottom gate of the first silicon semiconductor transistor and the fourth bottom gate of the second silicon semiconductor transistor both receive a ground voltage signal; The second bottom gate of the first oxide transistor and the fifth bottom gate of the third oxide transistor both receive a negative potential power supply signal.

[0014] This application also provides a display device, which includes any of the display panels described above.

[0015] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide a display panel and a display device. The display panel includes a display area and a non-display area located on at least one side of the display area. A gate driving circuit is disposed in the non-display area. The gate driving circuit includes a first silicon semiconductor transistor and a first oxide transistor. The first silicon semiconductor transistor includes a first bottom gate and a first active portion disposed along the thickness direction of the display panel. The first oxide transistor is located on the side of the first silicon semiconductor transistor away from the substrate. The first oxide transistor includes a second bottom gate and a second active portion disposed along the thickness direction of the display panel. By setting the distance between the second bottom gate of the first oxide transistor and the substrate to be greater than the distance between the first bottom gate of the first silicon semiconductor transistor and the substrate, the second bottom gate, which is relatively closer to the moisture intrusion path, is further away from the substrate, thereby reducing the risk of moisture corrosion of the second bottom gate and improving the reliability of the display panel. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the planar structure of the display panel provided in an embodiment of this application; Figure 2 This is a first partial cross-sectional schematic diagram of a display panel provided in an embodiment of this application; Figure 3 This is a second partial cross-sectional schematic diagram of the display panel provided in an embodiment of this application; Figure 4 A partial structural diagram of the display panel provided in an embodiment of this application; Figure 5 A circuit diagram of a sub-pixel provided in an embodiment of this application; Figure 6 This is a schematic diagram of the planar structure of the display device provided in the embodiments of this application.

[0018] Explanation of reference numerals in the attached figures: 1-Display panel; 100-Display area; 200-Non-display area; SP-Sub-pixel; C1-Storage capacitor; C11-First electrode plate; C12-Second electrode plate; 1000-Driving circuit layer; 1100-Pixel driving circuit; 1110-First silicon semiconductor transistor; 1111-Fourth bottom gate; 1112-Fourth active part; 1113-Fourth top gate; 1120-Third oxide transistor; 1121-Fifth bottom gate; 1122-Fifth active part; 1123-First... Five top gates; 210-Gate driving circuit; 2101-First group of gate driving circuits; 2102-Second group of gate driving circuits; 2110-First oxide transistor; 2111-Second bottom gate; 2112-Second active part; 2113-Second top gate; 2120-Second oxide transistor; 2121-Third bottom gate; 2122-Third active part; 2123-Third top gate; 2130-First silicon semiconductor transistor; 2131-First bottom gate; 2132- First active layer; 2133-First top gate; 11-Substrate; 12-Blocking layer; 121-First blocking layer; 122-Second blocking layer; 13-First electrode layer; 14-Buffer layer; 15-First active layer; 16-First gate insulating layer; 17-Second electrode layer; 18-First interlayer insulating layer; 19-Second active layer; 110-Second gate insulating layer; 111-Third electrode layer; 112-Second interlayer insulating layer; 113-Fourth electrode layer; 114-First planarization layer; 11 5-Fifth electrode layer; 1151-Transfer electrode; 116-Second planarization layer; 117-Sixth electrode layer; 1171-First electrode; 118-Pixel definition layer; 1181-Opening; 119-Barrier; H1-Spacing between the fifth bottom gate and the substrate; H2-Spacing between the second bottom gate and the substrate; H3-Spacing between the third bottom gate and the substrate; H4-Spacing between the fourth bottom gate and the substrate; H5-Spacing between the first bottom gate and the substrate; 2-Display device; 21-Middle frame. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower in the actual use or working mode of the device, specifically the drawing direction in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only, and features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0021] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections or detachable connections; mechanical connections or electrical connections or connections that allow communication; direct connections or indirect connections through an intermediate medium; and connections within two components or interactions between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0022] The following disclosure provides many different embodiments for implementing different structures of this application. To simplify the disclosure of this application, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0023] Please combine Figure 1 and Figure 2 This embodiment provides a display panel 1, which includes a display area 100 and a non-display area 200 disposed on one side of the display area 100. The display area 100 includes a plurality of sub-pixels SP, which can be arranged in an array to receive scanning signals and data signals from the non-display area 200, and drive the light-emitting devices in each sub-pixel SP to emit light of corresponding brightness according to the signals, thereby realizing image display.

[0024] Furthermore, the display panel 1 includes a substrate 11 and a driving circuit layer 1000 located on one side of the substrate 11. The driving circuit layer 1000 includes a pixel driving circuit 1100 located in the display area 100 and a gate driving circuit 210 located in the non-display area 200. The pixel driving circuit 1100 is used to provide driving current or driving voltage to the light-emitting devices in the display area 100 to control each sub-pixel SP to display an image. The gate driving circuit 210 is used to provide a step-by-step shifted scanning signal to each scanning signal line in the display area 100 to control the line-by-line conduction and cutoff of each sub-pixel SP in the display area 100.

[0025] Specifically, Figure 1The example described uses a non-display area 200 surrounding a display area 100, but this embodiment is not limited to this. The non-display area 200 can be located on one, two, or three sides of the display area 100. Furthermore, when the display panel 1 in this embodiment needs to house under-display sensors (such as an under-display camera), the display panel 1 can also have a punch-hole area within the display area 100, which may or may not be displayed. When the display panel 1 in this embodiment uses a full-screen display, the non-display area 200 can be bent or folded to the back of the display panel 1.

[0026] The pixel driving circuit 1100 includes a third oxide transistor 1120, which includes a fifth bottom gate 1121 and a fifth active portion 1122 disposed along the thickness direction of the display panel 1; the gate driving circuit 210 includes a first silicon semiconductor transistor 2130 and at least one first oxide transistor 2110, which includes a first bottom gate 2131 and a first active portion 2132 disposed along the thickness direction of the display panel 1; at least one first oxide transistor 2110 is located on the side of the first silicon semiconductor transistor 2130 away from the substrate 11, and the first oxide transistor 2110 includes a second bottom gate 2111 and a second active portion 2112 disposed along the thickness direction of the display panel 1; wherein, the distance H2 between the second bottom gate 2111 and the substrate 11 is greater than the distance H5 between the first bottom gate 2131 and the substrate 11.

[0027] It should be noted that during the fabrication of the display panel 1, a large-size motherboard is typically cut into multiple independent display panels 1 along a dicing channel. The dicing channel is located in the edge region of the display panel 1, corresponding to the outer periphery of the non-display area 200. The side of the gate driving circuit 210 furthest from the display area 100 is located near the dicing channel. Since the dicing channel is the cross-section formed by cutting the display panel 1, the film structure is exposed at this location. Moisture can easily seep into the interior of the display panel 1 from the dicing channel along the film interface or the edge of the substrate 11. The side of the gate driving circuit 210 furthest from the display area 100 is the closest to the dicing channel, so this area is most significantly affected by moisture intrusion. In a high-temperature and high-humidity working environment, moisture intrusion will be further aggravated, easily causing corrosion to the circuit traces and electrodes in the non-display area 200.

[0028] It is understood that in this embodiment, by setting the distance H2 between the second bottom gate 2111 of the first oxide transistor 2110 and the substrate 11 to be greater than the distance H5 between the first bottom gate 2131 of the first silicon semiconductor transistor 2130 and the substrate 11, the second bottom gate 2111, which is closer to the moisture intrusion path, is further away from the substrate 11 than the first bottom gate 2131. Since moisture intrudes from the edge of the substrate 11 and mainly diffuses laterally along the film interface closer to the substrate 11, as the distance from the substrate 11 increases, the path required for moisture to reach the second bottom gate 2111 is longer and the diffusion resistance is greater, resulting in a relatively weaker impact from moisture. Therefore, placing the second bottom gate 2111, which is close to the moisture intrusion path and susceptible to corrosion, at a position relatively far from the substrate 11 can reduce the probability of contact between the second bottom gate 2111 and moisture, thereby reducing the risk of corrosion failure and improving the long-term reliability of the display panel 1 in high temperature and high humidity environments.

[0029] Furthermore, the display panel 1 includes a first barrier layer 121, a first electrode layer 13, a second barrier layer 122, a buffer layer 14, a first active layer 15, a first gate insulating layer 16, a second electrode layer 17, a first interlayer insulating layer 18, a second active layer 19, a second gate insulating layer 110, a third electrode layer 111, and a second interlayer insulating layer 112, all stacked on a substrate 11 along the thickness direction of the display panel 1. The following will describe in detail the purpose of each layer and their logical relationships, taking into account their material properties and functional positioning.

[0030] The substrate 11 can be a rigid substrate or a flexible substrate. When the substrate 11 is a rigid substrate, the material can be metal or glass. When the substrate 11 is a flexible substrate, the material can include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane-based resin, cellulose resin, silicone resin, polyimide-based resin, and polyamide-based resin. This embodiment does not limit the material of the substrate 11.

[0031] The materials of the first barrier layer 121 and the second barrier layer 122 are both including, but not limited to, silicon oxide, silicon nitride, or a composite stack of the two, used to block impurities (such as alkali metal ions or water vapor) in the substrate 11 from diffusing to the active layer; the materials of the first electrode layer 13 include, but are not limited to, one or more of the following conductive materials: copper, molybdenum, titanium, titanium / copper, molybdenum-titanium / copper, titanium-tungsten / copper, silver, aluminum, titanium / aluminum, gold, molybdenum-titanium, and titanium; the buffer layer 14 covers the first electrode layer 13, and the materials of the buffer layer 14 include, but are not limited to, silicon nitride, silicon oxide, or a composite stack of the two, which have good water absorption and stress buffering capabilities, used to improve the adhesion and flatness of subsequent film layers.

[0032] The first active layer 15 is made of low-temperature polycrystalline silicon, which is formed by crystallizing amorphous silicon through methods such as excimer laser annealing. Because low-temperature polycrystalline silicon has a high carrier mobility, it is used to form the active portion of silicon semiconductor transistors to meet the requirements of high current and fast response in driving circuits.

[0033] The materials of the first gate insulating layer 16 and the second gate insulating layer 110 include, but are not limited to, silicon oxide, silicon nitride, or a stack of both, for achieving electrical insulation between the active layer and the gate; the materials of the second electrode layer 17 and the third electrode layer 111 include, but are not limited to, one or more of the following conductive materials: copper, molybdenum, titanium, titanium / copper, molybdenum-titanium / copper, titanium-tungsten / copper, silver, aluminum, titanium / aluminum, gold, molybdenum-titanium, and titanium.

[0034] The materials of the first interlayer insulating layer 18 and the second interlayer insulating layer 112 are, but are not limited to, silicon oxide, silicon nitride, or a stack of both, used to isolate electrical connections between different conductive layers; the material of the second active layer 19 is an oxide semiconductor material, including but not limited to indium gallium zinc oxide, and the second active layer 19 is used to form the active part of the oxide transistor to meet the low leakage current requirement in the pixel driving circuit 1100, thereby reducing the power consumption of the display panel 1 at low refresh rates and improving charge retention capability.

[0035] Specifically, the display panel 1 also includes a storage capacitor C1, which includes a first electrode C11 and a second electrode C12. The first electrode C11 and the second electrode C12 are disposed opposite to each other along the thickness direction of the display panel 1. The second electrode layer 17 includes the first electrode C11 of the storage capacitor C1. The second electrode C12 is disposed on the same layer as the second active part 2112.

[0036] Understandably, by placing the second electrode C12 of the storage capacitor C1 on the same layer as the second active portion 2112 of the oxide transistor, it is unnecessary to add a separate conductive layer for the electrode of the storage capacitor C1, thereby reducing the number of film layers in the display panel 1 and achieving a less-mask process. This simplifies the fabrication process of the display panel 1, improves fabrication efficiency, and reduces manufacturing costs.

[0037] Please continue to combine Figure 1 and Figure 2The gate driving circuit 210 further includes a second oxide transistor 2120. The distance between the second oxide transistor 2120 and the display area 100 is smaller than the distance between the first oxide transistor 2110 and the display area 100. Specifically, the second oxide transistor 2120 is located on the side of the first oxide transistor 2110 close to the third oxide transistor 1120. The second oxide transistor 2120 includes a third bottom gate 2121 and a third active portion 2122 disposed along the thickness direction of the display panel 1. The distance H3 between the third bottom gate 2121 and the substrate 11 is greater than the distance H1 between the fifth bottom gate 1121 and the substrate 11. The distance H3 between the third bottom gate 2121 and the substrate 11 is equal to the distance H2 between the second bottom gate 2111 and the substrate 11.

[0038] Specifically, the second active layer 19 includes the fifth active portion 1122 of the third oxide transistor 1120, the second active portion 2112 of the first oxide transistor 2110, and the third active portion 2122 of the second oxide transistor 2120. This allows the active portions of the oxide transistors to be formed simultaneously in the same photomask process, meaning that the active portions of each oxide transistor share the same photomask for etching, which helps to reduce the number of photomasks, simplify the process flow, and reduce manufacturing costs.

[0039] The first electrode layer 13 includes the fifth bottom gate 1121 of the third oxide transistor 1120; the second electrode layer 17 includes the second bottom gate 2111 of the first oxide transistor 2110 and the third bottom gate 2121 of the second oxide transistor 2120. The distance H3 between the third bottom gate 2121 and the substrate 11 is equal to the distance H2 between the second bottom gate 2111 and the substrate 11. This allows the bottom gates (second bottom gate 2111 and third bottom gate 2121) of the oxide transistors (first oxide transistor 2110 and second oxide transistor 2120) in the non-display area 200, which are close to the moisture intrusion path, to be disposed on different conductive layers from the bottom gate (fifth bottom gate 1121) of the oxide transistor (third oxide transistor 1120) in the display area 100. This also makes the bottom gates of the oxide transistors in the non-display area 200 relatively far away from the substrate 11, thereby reducing the risk of moisture corrosion of the bottom gates of the oxide transistors in the non-display area 200.

[0040] Understandably, since a barrier layer 12, a buffer layer 14, and a first gate insulating layer 16 are disposed between the second electrode layer 17 and the substrate 11, moisture, after invading from the edge of the substrate 11, needs to pass through the barrier layer 12, the buffer layer 14, and the first gate insulating layer 16 in sequence before reaching the bottom gate of the oxide transistor in the non-display area 200. During the process of moisture passing through the aforementioned layers, its concentration and diffusion rate gradually decrease, and its corrosiveness is reduced by the time it reaches the second electrode layer 17. This keeps the bottom gates of the oxide transistors in the non-display area 200, which are susceptible to corrosion, away from the moisture diffusion path, reducing the risk of corrosion of the bottom gates of the oxide transistors in the non-display area 200 and further improving the reliability of the display panel 1 in high-temperature and high-humidity environments.

[0041] It should be noted that the distance H3 between the third bottom gate 2121 and the substrate 11 is greater than the distance H1 between the fifth bottom gate 1121 and the substrate 11, but this is only for illustrative purposes; please refer to [link / reference]. Figure 3 In another embodiment, the distance H3 between the third bottom gate 2121 and the substrate 11 is equal to the distance H1 between the fifth bottom gate 1121 and the substrate 11.

[0042] Specifically, the first electrode layer 13 includes the fifth bottom gate 1121 of the third oxide transistor 1120 and the third bottom gate 2121 of the second oxide transistor 2120; the second electrode layer 17 includes the second bottom gate 2111 of the first oxide transistor 2110; the second active layer 19 includes the fifth active portion 1122 of the third oxide transistor 1120, the second active portion 2112 of the first oxide transistor 2110 and the third active portion 2122 of the second oxide transistor 2120, thereby moving the second bottom gate 2111 near the dicing channel to the second electrode layer 17 away from the substrate 11, so that the second bottom gate 2111 of the first oxide transistor 2110, which is susceptible to corrosion in the non-display area 200, is away from the diffusion path of moisture, reducing the corrosion risk of the second bottom gate 2111 of the first oxide transistor 2110 in the non-display area 200.

[0043] Meanwhile, the third bottom gate 2121, which is relatively close to the display area 100, and the fifth bottom gate 1121 in the display area 100 are kept on the same electrode layer. The third bottom gate 2121 and the fifth bottom gate 1121 can be made of the same material and formed synchronously through the same patterning process, which helps to reduce the number of masks and reduce manufacturing costs.

[0044] It is understandable that the first oxide transistor 2110 is located on the side of the gate drive circuit 210 away from the display area 100, and is closest to the dicing channel, thus having the greatest risk of corrosion. Therefore, moving the second bottom gate 2111 of the first oxide transistor 2110 to the second electrode layer 17 away from the substrate 11 can effectively block the direct contact between water vapor and the easily corroded electrode, thereby reducing the probability of corrosion of the second bottom gate 2111. The distance between the second oxide transistor 2120 and the display area 100 is smaller than the distance between the first oxide transistor 2110 and the display area 100. That is, the second oxide transistor 2120 is located on the side of the first oxide transistor 2110 closer to the display area 100. When water vapor reaches this position, it has already passed through a longer diffusion path, and the risk of corrosion is relatively small. Therefore, the third bottom gate 2121 can be retained in the first electrode layer 13 and set in the same layer as the fifth bottom gate 1121 of the third oxide transistor 1120 in the display area 100. Therefore, this embodiment differentiates the position of the bottom gate of the oxide transistor based on the difference in water vapor concentration at different locations of the display panel 1, thereby reducing the manufacturing cost of the display panel 1 while ensuring the anti-corrosion effect.

[0045] Please continue to combine Figure 1 and Figure 2 The pixel driving circuit 1100 further includes a second silicon semiconductor transistor 1110, which includes a fourth bottom gate 1111 and a fourth active portion 1112 disposed along the thickness direction of the display panel 1; the gate driving circuit 210 further includes a first silicon semiconductor transistor 2130, which includes a first bottom gate 2131 and a first active portion 2132 disposed along the thickness direction of the display panel 1; wherein, both the pixel driving circuit 1100 and the gate driving circuit 210 include silicon semiconductor transistors and oxide transistors, that is, the driving circuit layer 1000 of the display panel 1 adopts low temperature polycrystalline oxide technology to simultaneously utilize the high carrier mobility of low temperature polycrystalline silicon and the low leakage current characteristics of oxide semiconductor, thereby improving the response speed of the display panel 1 while reducing power consumption.

[0046] Specifically, the first electrode layer 13 also includes the fourth bottom gate 1111 of the second silicon semiconductor transistor 1110 and the first bottom gate 2131 of the first silicon semiconductor transistor 2130. The distance H4 between the fourth bottom gate 1111 and the substrate 11 is equal to the distance H5 between the first bottom gate 2131 and the substrate 11, so that the fourth bottom gate 1111 and the first bottom gate 2131 can be formed simultaneously in the same photomask process, that is, they share the same photolithography mask for etching, reducing the number of photomasks and reducing manufacturing costs. The first active layer 15 includes the fourth active portion 1112 of the second silicon semiconductor transistor 1110 and the first active portion 2132 of the first silicon semiconductor transistor 2130, so that the fourth active portion 1112 and the first active portion 2132 can be formed simultaneously in the same photomask process, further reducing the number of photomasks and reducing the manufacturing cost of the display panel 1.

[0047] It is understood that in this embodiment, by placing the fifth bottom gate 1121 of the third oxide transistor 1120, the fourth bottom gate 1111 of the second silicon semiconductor transistor 1110, and the first bottom gate 2131 of the first silicon semiconductor transistor 2130 within the first electrode layer 13, the bottom gates of the third oxide transistor 1120, the second silicon semiconductor transistor 1110, and the first silicon semiconductor transistor 2130 can be formed synchronously using the same material and the same patterning process. This is beneficial to ensuring the consistency of the film thickness, material properties, and electrical parameters of the bottom gates of each transistor. For the pixel driving circuit 1100, the consistency of the bottom gate electrical parameters helps to reduce the threshold voltage deviation between the SP driving transistors of each sub-pixel, thereby improving the uniformity of the display brightness. For the gate driving circuit 210, the consistency of the silicon semiconductor transistor bottom gate electrical parameters helps to ensure the stability and matching of the output signals of each shift register unit.

[0048] Meanwhile, the second bottom gate 2111 of the first oxide transistor 2110 and the third bottom gate 2121 of the second oxide transistor 2120 are both disposed in the second electrode layer 17, that is, further away from the substrate 11 than the first electrode layer 13, thereby reducing the risk of moisture corrosion of the bottom gate of the oxide transistor in the non-display area 200 and further improving the reliability of the display panel 1 in high temperature and high humidity environment.

[0049] Furthermore, the second electrode layer 17 also includes the fourth top gate 1113 of the second silicon semiconductor transistor 1110, the first top gate 2133 of the first silicon semiconductor transistor 2130, the second bottom gate 2111 of the first oxide transistor 2110, and the third bottom gate 2121 of the second oxide transistor 2120, thereby integrating the top gate of the silicon semiconductor transistor and the bottom gate of the oxide transistor in the non-display area 200 into the same conductive layer, realizing the upward movement of the bottom gate of the oxide transistor in the non-display area 200 without the need for additional film layers; the third electrode layer 111 includes the fifth top gate 1123 of the third oxide transistor 1120, the second top gate 2113 of the first oxide transistor 2110, and the third top gate 2123 of the second oxide transistor 2120, thereby providing a top gate for the oxide transistor to form a dual-gate structure, which is beneficial to enhance the control capability of the channel region and improve the electrical performance of the oxide transistor.

[0050] It is understood that in this embodiment, by placing the bottom gate of the oxide transistor and the top gate of the silicon semiconductor transistor in the same layer on the second electrode layer 17 within the non-display area 200, the second electrode layer 17 simultaneously performs two functions. This achieves the lifting of the bottom gate of the oxide transistor relative to the substrate 11 within the non-display area 200 while avoiding the need for additional conductive layers for the bottom gate lifting. Simultaneously, the top gate of the oxide transistor is independently disposed on the third electrode layer 111. This achieves a dual-gate structure to optimize transistor electrical performance while maintaining the flexibility to differentiate the bottom gate position, thus balancing device performance and process cost.

[0051] Furthermore, the fourth bottom gate 1111 of the second silicon semiconductor transistor 1110 and the fifth bottom gate of the first silicon semiconductor transistor 2130 both receive a ground voltage signal; the fifth bottom gate 1121 of the third oxide transistor 1120, the second bottom gate 2111 of the first oxide transistor 2110, and the third bottom gate 2121 of the second oxide transistor 2120 all receive a negative potential power supply signal.

[0052] It should be noted that in the display panel 1 of the related technology, the bottom gate of the oxide transistor and the bottom gate of the silicon semiconductor transistor are located in the same conductive layer. The bottom gate of the silicon semiconductor transistor receives a ground voltage signal, while the bottom gate of the oxide transistor receives a negative potential power supply signal. There is a potential difference between the two. After water vapor penetrates from the edge of the substrate 11, it forms an electrolyte film on the surface of the conductive layer, thereby causing electrochemical corrosion. Specifically, the bottom gate of the oxide transistor with a lower potential acts as the anode and undergoes an oxidation reaction, and the metal is continuously consumed. Meanwhile, the bottom gate of the silicon semiconductor transistor with a relatively higher potential acts as the cathode and is protected. As the corrosion reaction continues, the bottom gate of the oxide transistor with a lower potential is gradually worn away, eventually leading to an open circuit or breakage of the electrode at that point, causing device failure.

[0053] It is understood that in this embodiment, by moving the second bottom gate 2111 of the first oxide transistor 2110, which is close to the moisture intrusion path, from the first electrode layer 13 to the second electrode layer 17, and placing the second bottom gate 2111 and the fifth bottom gate 1121 in different conductive layers, the negative potential power signal is transferred from the conductive layer (first electrode layer 13) close to the substrate 11 to the conductive layer (second electrode layer 17) far from the substrate 11. This avoids the simultaneous existence of ground voltage signal and negative potential power signal in the same conductive layer, thereby preventing electrochemical corrosion and improving the long-term reliability of the display panel 1 in high temperature and high humidity environments.

[0054] Furthermore, please continue to combine Figure 1 and Figure 2 The display panel 1 also includes a fourth electrode layer 113, a first planarization layer 114, a fifth electrode layer 115, a second planarization layer 116, and a sixth electrode layer 117 stacked on the side of the second interlayer insulating layer 112 away from the third electrode layer 111. The material of the fourth electrode layer 113 includes, but is not limited to, one or more of the following conductive materials: copper, molybdenum, titanium, titanium / copper, molybdenum / titanium / copper, titanium / tungsten / copper, silver, aluminum, titanium / aluminum, gold, molybdenum / titanium, and titanium. The fourth electrode layer 113 may include the source and drain of the second silicon semiconductor transistor 1110, the first silicon semiconductor transistor 2130, the third oxide transistor 1120, the first oxide transistor 2110, and the second oxide transistor 2120. The specific structure and connection method of the source and drain are conventional designs in the art and will not be described in detail here.

[0055] The materials of the fifth electrode layer 115 and the sixth electrode layer 117 are both transparent conductive materials, including but not limited to indium tin oxide. The fifth electrode layer 115 includes a transition electrode 1151, which is connected to the first drain of the second silicon semiconductor transistor 1110. The fifth electrode layer 115 also includes a first electrode 1171, which is connected to the transition electrode 1151. The potential of the first drain of the second silicon semiconductor transistor 1110 can be led out to the fifth electrode layer 115, thereby providing a driving signal input for the first electrode 1171 of the subsequent light-emitting device.

[0056] Specifically, the display panel 1 further includes a pixel definition layer 118 and a barrier 119. The pixel definition layer 118 covers the fourth electrode layer 113 and the second planarization layer 116, and the pixel definition layer 118 has an opening 1181 at the position corresponding to the first electrode 1171, the opening 1181 exposing part of the first electrode 1171; the barrier 119 is disposed on the pixel definition layer 118 and located on the periphery of the opening 1181; the display panel 1 may also include a light-emitting device, the light-emitting device is disposed in the opening 1181 of the pixel definition layer 118, and the light-emitting device includes the first electrode 1171, and the pixel driving circuit 1100 is used to drive the light-emitting device to emit light.

[0057] Furthermore, please combine Figure 1 and Figure 4 The gate driving circuit 210 includes multiple sets of gate driving circuits 210, each set including a first set of gate driving circuits 2101 and multiple second sets of gate driving circuits 2102. The distance between the first set of gate driving circuits 2101 and the display area 100 is greater than the distance between the multiple second sets of gate driving circuits 2102 and the display area 100. That is, the first set of gate driving circuits 2101 is located on the side of the multiple second sets of gate driving circuits 2102 away from the display area 100. The first set of gate driving circuits 2101 includes a first oxide transistor 2110, and the second set of gate driving circuits 2102 includes a second oxide transistor 2120. Thus, the bottom gates of the oxide transistors in the first set of gate driving circuits 2101, which are closest to the moisture intrusion path, are all located within the second electrode layer 17.

[0058] It is understandable that, since a barrier layer 12, a buffer layer 14 and a first gate insulating layer 16 are provided between the second electrode layer 17 and the substrate 11, water vapor needs to pass through the above-mentioned multilayer film layers to reach the second bottom gate 2111 after it invades from the edge of the substrate 11. This prolongs the invasion path of water vapor to the second bottom gate 2111, reduces the contact probability between water vapor and the second bottom gate 2111, and thus reduces the corrosion risk of the bottom gate of the oxide transistor in the first set of gate driving circuits 2101.

[0059] Specifically, the multiple sets of gate driving circuits 210 include, but are not limited to, light-emitting control type gate driving circuits, N-type scanning type gate driving circuits, and P-type scanning type gate driving circuits; each of the multiple sets of second gate driving circuits 2102 can be selected from one of the light-emitting control type gate driving circuits, N-type scanning type gate driving circuits, or P-type scanning type gate driving circuits, and the types selected by different sets of second gate driving circuits 2102 are independent of each other; the first set of gate driving circuits 2101 is one of the light-emitting control type gate driving circuits, N-type scanning type gate driving circuits, or P-type scanning type gate driving circuits, and is disposed on the side of the multiple sets of second gate driving circuits 2102 away from the display area 100, so that the oxide transistors in the first set of gate driving circuits 2101 closest to the cutting channel are all first oxide transistors 2110.

[0060] It is understood that by placing the second bottom gate 2111 of the first oxide transistor 2110 within the second electrode layer 17, the intrusion path of moisture to the second bottom gate 2111 is extended, thereby reducing the risk of electrochemical corrosion of the bottom gate of the oxide transistor in the first set of gate drive circuits 2101.

[0061] It should be noted that the multiple gate driving circuits 210, including but not limited to light-emitting control type gate driving circuits, N-type scanning type gate driving circuits and P-type scanning type gate driving circuits, are only used as examples. This embodiment does not limit the specific type of gate driving circuit. Specifically, the gate driving circuit can be flexibly selected and set according to the actual driving requirements such as the size, resolution, refresh rate and power consumption requirements of the display panel 1.

[0062] The second group of gate driving circuits 2102 includes a second oxide transistor 2120, wherein the distance H3 between the third bottom gate 2121 and the substrate 11 is greater than or equal to the distance H1 between the fifth bottom gate 1121 and the substrate 11. Specifically, when the distance H3 between the third bottom gate 2121 and the substrate 11 is greater than the distance H1 between the fifth bottom gate 1121 and the substrate 11, the third bottom gate 2121 of the second oxide transistor 2120 and the second bottom gate 2111 of the first oxide transistor 2110 are disposed in the same layer (both located in the second electrode layer 17), that is, the bottom gates of the oxide transistors in the non-display area 200 are all moved up to the second electrode layer 17 away from the substrate 11, thereby reducing the corrosion risk of the oxide transistors of the gate driving circuit 210 in the non-display area 200.

[0063] When the distance H3 between the third bottom gate 2121 and the substrate 11 is equal to the distance H1 between the fifth bottom gate 1121 and the substrate 11, the third bottom gate 2121 and the fifth bottom gate 1121 are disposed in the same layer (both located in the first electrode layer 13). That is, the third bottom gate 2121 of the second oxide transistor 2120 of the second group gate driving circuit 2102, which is close to the display area 100, is located in the first electrode layer 13, while the second bottom gate 2111 of the first oxide transistor 2110 of the first driving unit, which is closest to the moisture intrusion path, is moved up to the second electrode layer 17. This ensures the corrosion protection effect and helps maintain the continuity of the existing process route, avoiding the introduction of additional process control points and uncertainties due to the use of different conductive layers in some areas (e.g., the distribution shift of transistor electrical parameters due to differences in conductive layers).

[0064] Furthermore, at least one second group of gate driving circuits 2102 also includes a first oxide transistor 2110, that is, the bottom gate of the oxide transistor in part of the second group of gate driving circuits 2102 is also moved up to the second electrode layer 17 away from the substrate 11, so that the layer position of the bottom gate of the oxide transistor in each gate driving circuit 210 can be flexibly adjusted according to the actual layout and corrosion risk level of different functional gate driving circuits 210.

[0065] It is understood that this embodiment sets the display panel to include multiple sets of gate driving circuits 210, and configures the bottom gate of the oxide transistors in the display panel differently according to the distance of each set of gate driving circuits 210 from the dicing channel. That is, the bottom gate of the first oxide transistor 2110 in the first set of gate driving circuits 2101 closest to the dicing channel is set on the second electrode layer 17, while the third bottom gate 2121 of the second oxide transistor 2120, whose water vapor concentration has decayed, can be selectively set on the first electrode layer 13 or the second electrode layer 17. This effectively reduces the risk of corrosion while taking into account the manufacturing cost and design flexibility of the display panel 1.

[0066] Please see Figure 5 The diagram below illustrates the circuit of a sub-pixel provided in this application embodiment. Taking each sub-pixel SP as an example, it includes 8 transistors and 2 capacitors. The 8 transistors are driving transistor T1, switching transistor T2, compensation transistor T3, first initialization transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second initialization transistor T7, and third initialization transistor T8. The 2 capacitors are first capacitor Cst and second capacitor Cboost.

[0067] Specifically, the gate of the switching transistor T2 is connected to the first scan signal line Pscan, and the first electrode of the switching transistor T2 is connected to the data line DATA.

[0068] The first electrode of the driving transistor T1 and the second electrode of the switching transistor T2 are connected to the first node A.

[0069] The gate of the compensation transistor T3 is connected to the second scan signal line Nscan1, the first electrode of the compensation transistor T3 is connected to the gate of the driving transistor T1 at the second node Q, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1.

[0070] The gate of the first initialization transistor T4 is connected to the third scan signal line Nscan2, the first electrode of the first initialization transistor T4 is connected to the first initialization signal line VI-G, and the second electrode of the first initialization transistor T4 is connected to the gate of the driving transistor T1 at the second node Q.

[0071] The gate of the first light-emitting control transistor T5 is connected to the light-emitting control signal line EM, the first electrode of the first light-emitting control transistor T5 is connected to the high-potential power supply line VDD, and the second electrode of the first light-emitting control transistor T5 is connected to the first electrode of the driving transistor T1 at the first node A.

[0072] The gate of the second light-emitting control transistor T6 is connected to the light-emitting control signal line EM, and the first electrode of the second light-emitting control transistor T6 is connected to the second electrode of the driving transistor T1 at the third node B.

[0073] The gate of the second initialization transistor T7 is connected to the fourth scan signal line Pscan2, the first electrode of the second initialization transistor T7 is connected to the second initialization signal line VI-ANO, and the second electrode of the second initialization transistor T7 is connected to the second electrode of the second light-emitting control transistor T6 at the fourth node C.

[0074] The gate of the third initialization transistor T8 is connected to the fourth scan signal line Pscan2, the first electrode of the third initialization transistor T8 is connected to the third initialization signal line VI3, and the second electrode of the third initialization transistor T8 is connected to the first electrode of the driving transistor T1 at the first node A.

[0075] One plate of the first capacitor Cst is connected to the high-potential power line VDD, and the other plate of the first capacitor Cst is connected to the gate of the driving transistor T1 at the second node Q.

[0076] One plate of the second capacitor Cboost is connected to the first scan signal line Pscan, and the other plate of the second capacitor Cboost is connected to the second electrode of the first initialization transistor T4.

[0077] The silicon semiconductor transistor includes a switching transistor T2, a driving transistor T1, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second initialization transistor T7, and a third initialization transistor T8; the oxide transistor includes a compensation transistor T3 and a first initialization transistor T4; the first capacitor Cst is a storage capacitor C1, and the second capacitor Cboost is a boost capacitor.

[0078] Optionally, the first plate of the storage capacitor C1 is configured to correspond to the gate of the driving transistor T1.

[0079] It should be noted that in the above embodiments, the first electrode of the transistor is the source and the second electrode is the drain; or in the above embodiments, the first electrode of the transistor is the drain and the second electrode is the source. The first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2, and the light emission control signal line EM can be connected to different gate driving circuits respectively. Specifically, five sets of gate driving circuits can be used to output signals to the first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2, and the light emission control signal line EM respectively. Among them, the gate driving circuit connected to the first scan signal line Pscan can be double-sided driving, and the other gate driving circuits are single-sided driving.

[0080] Please combine Figure 1 and Figure 6 This embodiment also provides a display device 2, which includes the display panel 1 in any of the above embodiments; wherein, the display device 2 may further include a middle frame 21, which is integrated with the display panel 1 to provide support, fixation and protection for the display panel 1.

[0081] It is understood that the display panel 1 has been described in detail in the above embodiments and will not be described again here; in particular, since the display device 2 adopts all the technical solutions of the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated here.

[0082] In specific applications, display device 2 includes, but is not limited to: mobile communication devices, such as smartphones, mobile phones and video phones; portable computing and entertainment devices, such as tablets, laptops, netbooks, workstations, personal digital assistants, portable media players and MP3 players; fixed computing devices, such as desktop computers and servers; digital imaging devices, such as cameras, digital cameras and game consoles; in-vehicle and public information devices, such as in-vehicle navigation systems, electronic billboards and ATMs; health and medical devices, such as mobile medical devices; and emerging wearable devices, i.e., wearable devices.

[0083] The above provides a detailed description of a display panel and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area located on at least one side of the display area. The display panel includes a substrate and a gate driving circuit located on one side of the substrate. The gate driving circuit is located in the non-display area and includes: The first silicon semiconductor transistor includes a first bottom gate and a first active portion disposed along the thickness direction of the display panel; A first oxide transistor is located on the side of the first silicon semiconductor transistor away from the substrate. The first oxide transistor includes a second bottom gate and a second active portion disposed along the thickness direction of the display panel. The distance between the second bottom gate and the substrate is greater than the distance between the first bottom gate and the substrate.

2. The display panel according to claim 1, characterized in that, The gate driving circuit further includes a second oxide transistor, the distance between the second oxide transistor and the display area is smaller than the distance between the first oxide transistor and the display area, and the second oxide transistor includes a third bottom gate and a third active portion disposed along the thickness direction of the display panel; The distance between the third bottom gate and the substrate is greater than or equal to the distance between the first bottom gate and the substrate.

3. The display panel according to claim 2, characterized in that, The distance between the third bottom gate and the substrate is equal to the distance between the second bottom gate and the substrate.

4. The display panel according to claim 2, characterized in that, The display panel includes multiple sets of gate driving circuits, which include a first set of gate driving circuits and multiple second sets of gate driving circuits. The distance between the first group of gate driving circuits and the display area is greater than the distance between the plurality of second group of gate driving circuits and the display area. The first group of gate driving circuits includes the first oxide transistor, and the second group of gate driving circuits includes the second oxide transistor.

5. The display panel according to claim 4, characterized in that, At least one of the second group of gate drive circuits further includes the first oxide transistor.

6. The display panel according to claim 1, characterized in that, The display panel includes: A first electrode layer is disposed on the substrate and includes the first bottom gate of the first silicon semiconductor transistor; A first active layer is disposed on the side of the first electrode layer away from the substrate, and includes the first active portion of the first silicon semiconductor transistor; The second electrode layer is disposed on the side of the first active layer away from the substrate, and includes the first top gate of the first silicon semiconductor transistor and the second bottom gate of the first oxide transistor. The second active layer is disposed on the side of the second electrode layer away from the substrate, and includes the second active portion of the first oxide transistor; A third electrode layer is disposed on the side of the second active layer away from the substrate, and includes the second top gate of the first oxide transistor.

7. The display panel according to claim 6, characterized in that, The display panel also includes a storage capacitor, which includes a first plate and a second plate, and the first plate and the second plate are disposed opposite to each other along the thickness direction of the display panel. The second electrode layer further includes the first electrode plate of the storage capacitor; the second electrode plate of the storage capacitor is disposed on the same layer as the second active part.

8. The display panel according to any one of claims 1 to 7, characterized in that, The display panel further includes a pixel driving circuit located in the display area, the pixel driving circuit comprising: The second silicon semiconductor transistor includes a fourth bottom gate and a fourth active portion disposed along the thickness direction of the display panel; The third oxide transistor includes a fifth bottom gate and a fifth active portion disposed along the thickness direction of the display panel; The spacing between the first bottom gate and the substrate, the spacing between the fourth bottom gate and the substrate, and the spacing between the fifth bottom gate and the substrate are all equal.

9. The display panel according to claim 8, characterized in that, The first bottom gate of the first silicon semiconductor transistor and the fourth bottom gate of the second silicon semiconductor transistor both receive a ground voltage signal; The second bottom gate of the first oxide transistor and the fifth bottom gate of the third oxide transistor both receive a negative potential power supply signal.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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