Pixel driving circuit and display panel

Abstract

The application discloses a pixel driving circuit and a display panel. The pixel driving circuit comprises a storage module and a driving module. The storage module is electrically connected to a data line and is used for storing gray scale data. The driving module is electrically connected to the storage module and a light emitting element, and is used for driving the light emitting element to emit light according to the gray scale data stored by the storage module. At least part of the storage units are set as dynamic random access storage units. Since the dynamic random access storage units can be formed by the upper metal layer of the pixel unit, the horizontal area is not occupied, the overall area occupation of the pixel driving circuit can be reduced, and the pixel density is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a pixel driving circuit and a display panel. Background Technology

[0002] In silicon-based micro-LED display technology, the design of the pixel driving circuit directly affects the grayscale accuracy, power consumption, and pixel density. To achieve high grayscale accuracy and low power consumption, a digital pixel driving circuit scheme based on an in-pixel memory architecture has been proposed in the prior art. This scheme integrates static random access memory (SRAM) within each sub-pixel unit and combines it with a time-division multiple-frame driving strategy to achieve grayscale display through precise control of the emission duty cycle of the micro-LED within a frame. A typical scheme uses an 8-bit grayscale depth, requiring each sub-pixel to integrate a SRAM unit capable of storing 8 bits of grayscale data, with six transistors constituting a single SRAM unit.

[0003] Static random access memory (SRAM) cells occupy a large area. Integrating multiple SRAM cells into each sub-pixel to achieve 8-bit storage significantly increases the circuit area of ​​a single pixel. As display resolution continues to increase, especially in near-eye display scenarios such as augmented reality and virtual reality where extremely high pixel density is required, it is difficult to accommodate a storage array composed of SRAM cells within a limited pixel area. This limits pixel density and fails to meet the needs of high-pixel-density silicon-based micro-LED displays.

[0004] Therefore, it is necessary to provide a pixel driving circuit and a display panel to improve this deficiency. Summary of the Invention

[0005] This application provides a pixel driving circuit and a display panel to solve the problem of large area occupation caused by integrating a storage module in the pixel driving circuit.

[0006] To achieve the above objectives, according to a first aspect of this application, a pixel driving circuit is provided, comprising: The storage module is electrically connected to the data cable and includes multiple storage units for storing grayscale data. A driving module is electrically connected to the storage module and the light-emitting element, and is used to drive the light-emitting element to emit light according to the grayscale data stored in the storage module; At least some of the plurality of storage units are dynamic random access storage units.

[0007] Optionally, the plurality of storage units includes a plurality of dynamic random access storage units and a plurality of static random access storage units, wherein the plurality of dynamic random access storage units and the plurality of static random access storage units are connected in parallel between the data line and the driver module.

[0008] Optionally, the plurality of dynamic random access memory units and the plurality of static random access memory units are arranged alternately along the extension direction of the data line; The pixel driving circuit further includes multiple row selection control lines, which are alternately connected to the dynamic random access memory unit and the static random access memory unit, and adjacent rows of the row selection control lines respectively control different types of memory units.

[0009] Optionally, the dynamic random access memory unit and the static random access memory unit are stacked along the film thickness direction.

[0010] Optionally, both the dynamic random access memory (DRAM) cell and the static random access memory (SRAM) cell include transistors, and the number of transistors in the DRAM cell is less than the number of transistors in the SRAM cell. The transistors in the dynamic random access memory (DRAM) unit are disposed on the same layer as the transistors in the static random access memory (SRAM) unit. The DRAM unit also includes a storage capacitor, which is stacked on the transistors.

[0011] Optionally, the pixel driving circuit further includes multiple switching modules. The switching modules are electrically connected between the storage unit and the driving module. The control terminal of the switching module is used to receive a pulse width modulation signal. The switching module is used to respond to the pulse width modulation signal and control the conduction state of the circuit between the storage unit and the driving module.

[0012] Optionally, the display frame period of the pixel driving circuit includes multiple subframes, and the duty cycle of the pulse width modulation signal corresponding to the multiple subframes increases in multiples. The multiple switching modules are used to respond to the pulse width modulation signal and sequentially control the circuit between the multiple storage units and the driving module to conduct, so that the driving module drives the light-emitting element to emit light according to the grayscale data.

[0013] Optionally, the plurality of storage units are all dynamic random access memory units, and the plurality of dynamic random access memory units are connected in parallel between the data line and the driving module, and are arranged in multiple rows and columns along the extension direction of the data line and in a direction perpendicular to the extension direction of the data line.

[0014] Optionally, the pixel driving circuit includes multiple row gating control lines electrically connected to the storage unit. The multiple row gating control lines are used to sequentially generate gating pulses during the data writing phase of the display frame cycle to sequentially latch and write the grayscale data input by the data line to the corresponding storage unit. The gating pulses of each adjacent row gating control line do not overlap in time.

[0015] Optionally, the pixel driving circuit further includes a row selection control line, a first power supply line, and a switch module, wherein the switch module is electrically connected between the storage unit and the driving module; The dynamic random access memory cell includes a transistor and a storage capacitor. The drain of the transistor is electrically connected to the data line, the source of the transistor is electrically connected to the storage capacitor and the switching module, the gate of the transistor is electrically connected to the row selection control line, and the storage capacitor is also electrically connected to the first power line.

[0016] According to a second aspect of this application, a display panel is provided, including the pixel driving circuit as described above.

[0017] In the pixel driving circuit of this application embodiment, by setting at least some of the storage units as dynamic random access memory units, since the dynamic random access memory units can be formed by the upper metal layer of the pixel units and do not occupy the horizontal area, the overall area occupied by the pixel driving circuit can be reduced, which is beneficial to improving the pixel density.

[0018] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0021] Figure 1 An architectural diagram of a first pixel driving circuit provided for embodiments of this application; Figure 2 A circuit diagram of a static random access memory cell in a first pixel driving circuit provided for an embodiment of this application; Figure 3A schematic diagram of the layout of the storage cells in a first pixel driving circuit provided for an embodiment of this application; Figure 4 Timing diagram of a pixel driving circuit provided for an embodiment of this application; Figure 5 A schematic diagram of the film structure of a first pixel driving circuit provided for an embodiment of this application; Figure 6 A schematic diagram of a second pixel driving circuit provided for embodiments of this application; Figure 7 A schematic diagram of the layout of the storage cells in a second pixel driving circuit provided for an embodiment of this application; Figure 8 A schematic diagram of a display panel provided for an embodiment of this application. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0023] An embodiment of this application provides a pixel driving circuit, which includes a storage module and a driving module. The storage module is electrically connected to a data line and is used to store grayscale data. The driving module is electrically connected to the storage module and a light-emitting element and is used to drive the light-emitting element to emit light according to the grayscale data stored in the storage module. The storage module includes multiple storage units, at least some of which are dynamic random access storage units.

[0024] In the embodiments of this application, by setting at least some of the storage units as dynamic random access memory units, since the dynamic random access memory units can be formed by the metal layer above the pixel units and do not occupy the horizontal area, the overall area occupied by the pixel driving circuit can be reduced, which is beneficial to improving the pixel density.

[0025] The technical solutions defined in the claims are described in detail below with reference to the accompanying drawings.

[0026] Please see Figure 1 , Figure 1The first pixel driving circuit provided in the embodiments of this application includes a data line Data, a light-emitting element 4, a storage module 1, and a driving module 2. The storage module 1 is electrically connected to the data line Data and is used to store grayscale data. The driving module 2 is electrically connected between the storage module 1 and the light-emitting element 4 and is used to drive the light-emitting element 4 to emit light according to the grayscale data stored in the storage module 1.

[0027] In some embodiments, please refer to Figure 1 The storage module 1 includes multiple storage units 10, which are connected in parallel between the data line Data and the drive module 2. The input terminals of the multiple storage units 10 are electrically connected to the same data line Data, and the output terminals of the multiple storage units 10 are electrically connected to the same control terminal of the drive module 2.

[0028] In some embodiments, a display frame period is divided into multiple subframes, each corresponding to a different grayscale weight. By controlling the emission duration of each subframe, precise control of multiple grayscale levels can be achieved. For example, if a display frame period is divided into 8 subframes, the storage module 1 may include 8 storage units 10, i.e., 8-bit storage units. 8 bits of grayscale data are written to the corresponding 8-bit storage unit 10 via data lines to complete data storage. The storage unit 10 plays a data retention role in the pixel driving circuit, ensuring data stability during display. Since each pixel driving circuit integrates a complete 8-bit storage unit 10, independent storage and control of grayscale data for each subframe can be achieved, thereby realizing high-precision grayscale display.

[0029] In some embodiments, please refer to Figure 1 At least a portion of the multiple memory cells 10 are Dynamic Random Access Memory (DRAM). DRAM can be formed from the metal layer above the pixel cells, without occupying horizontal area, thus reducing the overall area occupied by the pixel driving circuit and improving pixel density. Furthermore, DRAM has low power consumption in static state, consuming energy only during data refresh, thereby reducing the power consumption of the pixel driving circuit.

[0030] In some embodiments, the dynamic random access memory cell includes a transistor and a storage capacitor. The drain of the transistor is electrically connected to the data line, the source of the transistor is electrically connected to the storage capacitor and the switching module, the gate of the transistor is electrically connected to the row strobe control line, and the storage capacitor is also electrically connected to the first power line.

[0031] In some embodiments, the dynamic random access memory (DRAM) cell consists of a transistor and a storage capacitor, i.e., the dynamic random access memory (DRAM) cell adopts a 1T1C structure.

[0032] Specifically, please refer to Figure 1 The dynamic random access memory (DRAM) cell includes a seventh transistor T7 and a storage capacitor Cst. The drain of the seventh transistor T7 is electrically connected to the data line Data, the source is electrically connected to the first plate of the storage capacitor Cst, the gate is electrically connected to the row selection control line WS, the second plate of the storage capacitor Cst is electrically connected to the first power supply line VDD, and the first plate of the storage capacitor Cst is electrically connected to the driver module 2.

[0033] In some embodiments, please refer to Figure 1 The pixel driving circuit also includes multiple switch modules 3. The switch modules 3 are electrically connected between a storage unit 10 and the driving module 2. The control terminal of the switch module 3 is used to receive a pulse width modulation signal. The switch module 3 is used to respond to the pulse width modulation signal and control the conduction state of the circuit between the storage unit 10 and the driving module 2.

[0034] In some embodiments, please refer to Figure 1 The switching module 3 includes an eighth transistor T8, the drain of which is electrically connected to the first plate of the storage capacitor Cst and the source of the seventh transistor T7, the source of which is electrically connected to the driving module 2, and the gate of which is electrically connected to the pulse width modulation signal line.

[0035] In some embodiments, please refer to Figure 1 The driving module 2 includes a driving transistor T0, and the pixel driving circuit also includes a ninth transistor T9. The drain of the ninth transistor T9 is electrically connected to the first power supply line VDD, the source is electrically connected to the drain of the driving transistor T0, the gate of the ninth transistor T9 is electrically connected to the reference signal VREF, the gate of the driving transistor T0 is electrically connected to the drain of the eighth transistor T8, the source is electrically connected to the anode of the light-emitting element 4, and the cathode of the light-emitting element 4 is electrically connected to the second power supply line VSS.

[0036] In some embodiments, please refer to Figure 1 The storage module comprises multiple storage units, including multiple dynamic random access (DRAM) units and multiple static random access (SRAM) units, employing a hybrid storage structure of DRAM and SRAM. These DRAM and SRAM units are connected in parallel between the data line and the driver module, allowing each storage unit to independently receive grayscale data bits from the data line and independently output the stored grayscale data bits to the driver module.

[0037] In this embodiment, the advantages of static random access memory (SRAM) – stable data retention and no need for refresh operations – are utilized to store grayscale data with high significant bits, ensuring that grayscale display accuracy is not affected by data fluctuations. Meanwhile, the advantage of dynamic random access memory (DRAM) – which can be formed from the upper metal layer of the pixel unit – is leveraged by stacking DRAM on top of SRAM along the film thickness direction. This allows DRAM to occupy no horizontal area, enabling it to be used to store grayscale data with low significant bits. Even with slight charge leakage under limited refresh conditions, the impact on the overall grayscale display effect is relatively limited. Therefore, by combining the structural characteristics of both types of memory units within the same pixel unit and rationally allocating the grayscale data storage task, the overall area occupied by the storage module can be effectively reduced while maintaining grayscale display accuracy, thereby increasing pixel density.

[0038] In some embodiments, please refer to Figure 1 Multiple dynamic random access memory (DRAM) cells and multiple static random access memory (SRAM) cells are alternately arranged along the extension direction of the data line. The pixel driving circuit also includes multiple row selection control lines (WS), which are alternately connected to the DRAM and SRAM cells, and adjacent row selection control lines (WS) control different types of memory cells respectively.

[0039] In some embodiments, please refer to Figure 1 Static random access memory (SRAM) cells are coupled to row select control lines with odd bit order, while dynamic random access memory (DRAM) cells are coupled to row select control lines with even bit order, or vice versa.

[0040] In one embodiment, please refer to Figure 1 Storage module 1 stores 8 bits of grayscale data. Storage module 1 includes four dynamic random access memory (DRAM) cells and four static random access memory (SRAM) cells, which are alternately arranged along the extension direction of the data line Data. The pixel driving circuit includes eight row selection control lines WS. The four SRAM cells are connected to the first row selection control line WS1, the third row selection control line WS3, the fifth row selection control line WS5, and the seventh row selection control line WS7, respectively. The four DRAM cells are connected to the second row selection control line WS2, the fourth row selection control line WS4, the sixth row selection control line WS6, and the eighth row selection control line WS8, respectively.

[0041] During the data writing phase of a display frame cycle, multiple row gating control lines (WS) sequentially generate gating pulses, latching and writing the grayscale data input from the data lines into the corresponding memory cells in turn. The gating pulses can be either high-level or low-level pulses. By alternating the arrangement of dynamic random access memory (DRAM) and static random access memory (SRAM) cells, and coordinating the alternating connection of the row gating control lines, time-division writing of each bit of grayscale data can be achieved, optimizing the space utilization of the pixel circuit while ensuring grayscale display accuracy.

[0042] In some embodiments, Static Random Access Memory (SRAM) is used to store grayscale data in the most significant bits, and Dynamic Random Access Memory (DRAM) is used to store grayscale data in the least significant bits. Since the grayscale data in the most significant bits has a greater impact on the grayscale accuracy of the display, storing it in SRAM, which has more stable data retention characteristics, helps ensure the accuracy of grayscale display; while storing the grayscale data in the less significant bits in the smaller DRAM helps save pixel area.

[0043] In some embodiments, please refer to Figure 1 and Figure 2 , Figure 2 The circuit diagram of a static random access memory (SRAM) cell in a first pixel driving circuit provided in the embodiments of this application is shown. The SRAM cell consists of six transistors, including a first inverter, a second inverter, a first access transistor T1, and a second access transistor T2. The first inverter is composed of a first pull-up transistor T5 and a first pull-down transistor T3 connected in series. The second inverter is composed of a second pull-up transistor T6 and a second pull-down transistor T4 connected in series. The output terminal of the first inverter is coupled to the input terminal of the second inverter, and the output terminal of the second inverter is coupled to the input terminal of the first inverter, forming a cross-coupled latch structure for latching one bit of grayscale data. The gate of the first access transistor T1 is coupled to the corresponding row selection control line WS, the drain of the first access transistor T1 is coupled to the data line Data, and the source of the first access transistor T1 is coupled to the output of the first inverter. The gate of the second access transistor T2 is coupled to the same row selection control line WS, the drain of the second access transistor T2 is coupled to the complementary data line Data', and the source of the second access transistor T2 is coupled to the output of the second inverter. When the selection pulse on the row selection control line WS is valid, the first access transistor T1 and the second access transistor T2 are simultaneously turned on, and the grayscale data bits on the data line Data and their complementary signals are written to the cross-coupled latch structure through the first access transistor T1 and the second access transistor T2, respectively. When the selection pulse is invalid, the first access transistor T1 and the second access transistor T2 are turned off, and the cross-coupled latch structure maintains the stored grayscale data bits unchanged.

[0044] In some embodiments, dynamic random access memory (DRAM) and static random access memory (SRAM) are stacked along the film thickness direction.

[0045] In some embodiments, please refer to Figure 3 , Figure 3 This is a schematic diagram of the layout of the memory cells in a first pixel driving circuit provided in an embodiment of this application. In the hybrid memory scheme, the static random access memory (SRAM) cells are located in the lower region of the pixel circuit, and the dynamic random access memory (DRAM) cells are stacked in the upper region of the SRAM cells. In this way, while ensuring 8-bit grayscale data display, the overall area occupied by the pixel driving circuit can be reduced, and the pixel density can be increased.

[0046] In some embodiments, please refer to Figure 5 , Figure 5 The first pixel driving circuit provided in the embodiments of this application is a schematic diagram of the film structure. The pixel driving circuit includes a substrate 11, a gate insulating layer 12, a gate layer 13, a multilayer metal layer stacked on the gate layer 13, and an interlayer dielectric layer for insulating and separating the gate layer 13 from the metal layer or adjacent metal layer.

[0047] In some embodiments, please refer to Figure 5 The substrate 11 includes the active portion of the seventh transistor T7, and the material of the substrate 11 is monocrystalline silicon. The gate layer 13 includes the gate of the seventh transistor T7, and the material of the gate layer 13 is polycrystalline silicon. The transistors of the dynamic random access memory cell (DRAM) are fabricated using a silicon-based complementary metal-oxide-semiconductor (CMOS) process. Their gates are made of polycrystalline silicon, the active region layer serves as the channel, and the source and drain are located in the first metal layer closest to the gate layer among the multilayer metal layers.

[0048] In some embodiments, please refer to Figure 5 The pixel driving circuit includes a substrate 11, a gate insulating layer 12, a gate layer 13, a first interlayer dielectric layer IL1, a first metal layer M1, a second interlayer dielectric layer IL2, a second metal layer M2, a third interlayer dielectric layer IL3, a third metal layer M3, a fourth interlayer dielectric layer IL4, a fourth metal layer M4... an eighth metal layer M8 and a ninth interlayer dielectric layer IL9 stacked along the film thickness direction. The first metal layer M1 includes the source and drain of the seventh transistor T7. The storage capacitor of the dynamic random access memory cell DRAM can be formed into a parallel plate capacitor through the second metal layer M2 to the eighth metal layer M8.

[0049] In other embodiments, the number of metal layers in the pixel driving circuit is not limited to the eight metal layers in the above embodiments, but may also have three or more metal layers, with dielectric layers separating adjacent metal layers for insulation. The storage capacitor Cst can form a parallel-plate capacitor structure through at least two metal layers above the first metal layer M1.

[0050] In some embodiments, please refer to Figure 5 The gate of the transistor in the Static Random Access Memory (SRAM) cell is located on the gate layer 13, and the active portion is located on the substrate 11. The source and drain are located on the first metal interconnect layer. The storage capacitor of the Dynamic Random Access Memory (DRAM) cell utilizes the second metal layer M2 to the eighth metal layer M8 located above the SRAM cell to form a parallel plate capacitor structure. The space between the second metal layer M2 to the eighth metal layer M8 is filled with an insulating medium, which may include silicon dioxide or silicon nitride.

[0051] In some embodiments, please refer to Figure 5 The transistors of the Dynamic Random Access Memory (DRAM) and the Static Random Access Memory (SRAM) can be disposed on the same layer, that is, the gates of both are located on the gate layer 13, the active parts of both are located on the substrate 11, and the source and drain of both are located on the first metal layer M1. This allows the transistors of the DRAM and the SRAM to share the same film layer, simplifying the process steps. The storage capacitors of the DRAM are stacked on top of the transistors, forming a capacitor structure in the vertical direction using multiple metal layers. This achieves high-density data storage within a limited planar area, significantly reducing the layout area of ​​the pixel unit.

[0052] In some embodiments, please refer to Figure 1 and Figure 4 , Figure 4 The timing diagram of the pixel driving circuit provided in the embodiments of this application shows that, within one display frame period, the control timing of the pixel driving circuit includes a data writing stage t1 and an emission stage t2. In the data writing stage t1, multiple row gating control lines WS are used to sequentially generate gating pulses to latch and write the grayscale data input from the data lines into the corresponding memory cells in sequence, and the gating pulses of adjacent row gating control lines do not overlap in time. Taking an 8-bit grayscale display scheme as an example, row gating control lines WS1 to WS8 sequentially generate gating pulses, and the data lines load the corresponding bits of grayscale data at the corresponding times, thereby writing the 8 bits of grayscale data into the corresponding 8 memory cells. The gating pulses can be high-level pulses or low-level pulses.

[0053] In some embodiments, the display frame period includes multiple subframes, and the duty cycles of the pulse width modulation signals corresponding to the multiple subframes increase exponentially. For example, for an 8-bit grayscale display scheme, there are 8 subframes, and the duty cycles of the pulse width modulation signals corresponding to each subframe are 1 / 2, 1 / 4, 1 / 8, 1 / 16, 1 / 32, 1 / 64, and 1 / 128, respectively, meaning that the light emission duration of each subframe increases with binary weights. In each subframe, multiple switching modules are used to respond to the pulse width modulation signals corresponding to each subframe, sequentially selecting the corresponding dynamic random access memory (DRAM) or static random access memory (SRAM) units, causing the driving module to drive the light-emitting element to emit light according to the grayscale data bits stored in the DRAM or SRAM units. By superimposing the light emission durations of each subframe, grayscale display levels from 0 to 255 can be achieved.

[0054] It should be noted that for schemes including dynamic random access memory (DRAM), since DRAM relies on storage capacitors to retain data, the charge in the capacitors gradually leaks over time. Therefore, periodic refresh operations are required to maintain data accuracy. In the embodiments of this application, the pixel driving circuit can perform refresh operations when grayscale data changes, and not perform refresh operations when grayscale data remains unchanged, thereby further reducing dynamic power consumption and improving energy efficiency.

[0055] In some embodiments, see [link to relevant documentation]. Figure 6 and Figure 7 , Figure 6 A second pixel circuit architecture diagram provided for embodiments of this application. Figure 7 A schematic diagram of the layout of the memory cell in the second pixel driving circuit provided in the embodiments of this application, the structure of which is similar to... Figures 1 to 5 The structure of the first pixel driving circuit shown is roughly the same, the difference being that: the multiple storage cells 10 in the storage module 1 are all dynamic random access memory (DRAM), each DRAM consisting of a transistor and a capacitor, i.e., a 1T1C structure. The multiple DRAMs are connected in parallel between the data line and the driving module, and are arranged in multiple rows and columns along the extension direction of the data line and in directions perpendicular to the extension direction of the data line.

[0056] In this embodiment, by setting all memory cells as dynamic random access memory (DRAM) cells, each DRAM cell requires only one transistor and one capacitor. Compared to the existing structure where each static random access memory (SRAM) cell requires six transistors, the overall area occupied by the pixel driving circuit can be reduced. Simultaneously, DRAM cells consume extremely low power when static, only consuming energy during data refresh, reducing power consumption by 30% to 50% compared to SRAM cells.

[0057] It should be noted that, due to the significant reduction in the area of ​​dynamic random access memory (DRAM) cells, the pixel circuit layout is more compact, allowing for a more flexible process node for the pixel driving circuit. For example, compared to existing technologies requiring a 20nm process node, this embodiment can utilize 40nm or higher CMOS processes, such as 55nm or 90nm. This more flexible process node reduces manufacturing costs per unit area while improving the yield and reliability of the display panel.

[0058] In some embodiments, please refer to Figure 6 The pixel driving circuit includes multiple row selection control lines WS, which are sequentially electrically connected to the corresponding memory cells 10. For example, the memory cells 10 include eight dynamic random access memory (DRAM) cells, and the pixel driving circuit includes eight row selection control lines WS. The eight row selection control lines WS are respectively the first row selection control line WS1, the second row selection control line WS2, ..., and the eighth row selection control line WS8. The first row selection control line WS1, the second row selection control line WS2, ..., and the eighth row selection control line WS8 are respectively electrically connected to the gate of the seventh transistor T7 of the corresponding dynamic random access memory (DRAM) cell.

[0059] In some embodiments, please refer to Figure 4 and Figure 6 A display frame cycle includes a data writing phase t1 and an emission phase t2. Multiple row gating control lines WS are used to sequentially generate gating pulses during the data writing phase t1 of the display frame cycle, so as to sequentially latch and write the grayscale data input by the data lines Data into the corresponding dynamic random access memory (DRAM) units. The gating pulses of adjacent row gating control lines WS do not overlap in time, and the gating pulses can be high-level pulses or low-level pulses. The DRAM units can play a data holding role in the pixel driving circuit, ensuring the stability of data during the display process, so as to realize independent storage and control of grayscale data for each sub-frame, thereby achieving a high-precision grayscale display effect.

[0060] In some embodiments, the pixel driving circuit includes multiple pulse width modulation signal lines (PWM), which are sequentially electrically connected to the gate of the eighth transistor T8 of the corresponding switching module 3. For example, the pixel driving circuit includes eight dynamic random access memory (DRAM) cells and eight switching modules 3. The pixel driving circuit includes eight pulse width modulation signal lines (PWM), which are respectively a first pulse width modulation signal line PWM1, a second pulse width modulation signal line PWM2, ..., and an eighth pulse width modulation signal line PWM8. The first pulse width modulation signal line PWM1, the second pulse width modulation signal line PWM2, ..., and the eighth pulse width modulation signal line PWM8 are respectively electrically connected to the gate of the eighth transistor T8 of the corresponding switching module 3.

[0061] In some embodiments, please refer to Figure 4 and Figure 6 A display frame cycle consists of multiple subframes, each corresponding to a different grayscale weight. The pixel driving circuit includes a pulse width modulation module, which generates pulse width modulation signals with different duty cycles to achieve time-division driving of multiple subframes.

[0062] In some embodiments, please refer to Figure 4 The duty cycles of the pulse width modulation (PWM) signals corresponding to multiple subframes increase exponentially. For example, in an 8-bit grayscale display scheme, there are 8 subframes, and the duty cycles of the PWM signals corresponding to each subframe are 1 / 2, 1 / 4, 1 / 8, 1 / 16, 1 / 32, 1 / 64, and 1 / 128, respectively. That is, the emission duration of each subframe increases with binary weights. In each subframe, the switching module responds to the PWM signal corresponding to that subframe, sequentially selecting the corresponding dynamic random access memory (DRAM) unit, causing the driving module to drive the light-emitting element to emit light according to the grayscale data bits stored in the DRAM unit. By superimposing the emission durations of each subframe, grayscale display levels from 0 to 255 can be achieved.

[0063] In some embodiments, please refer to Figure 4 and Figure 6 Multiple switching modules 3 are used to respond to pulse width modulation signals and sequentially control the circuit between multiple storage units 10 and driving module 2 to make driving module 2 drive the light-emitting element to emit light according to grayscale data.

[0064] In some embodiments, the dynamic random access memory (DRAM) cell includes a seventh transistor T7 and a storage capacitor Cst. The storage capacitor Cst is stacked on the seventh transistor T7 along the film thickness direction, which can further reduce the overall area occupied by the pixel driving circuit and help to further improve the pixel density.

[0065] In one embodiment, please refer to Figure 5 The pixel driving circuit includes a substrate 11, a gate insulating layer 12, a gate layer 13, multiple metal layers stacked on the gate layer 13, and an interlayer dielectric layer for insulating and separating the gate layer 13 from the metal layers or adjacent metal layers.

[0066] In some embodiments, please refer to Figure 5 The substrate 11 includes the active portion of the seventh transistor T7, and the material of the substrate 11 is monocrystalline silicon. The gate layer 13 includes the gate of the seventh transistor T7, and the material of the gate layer 13 is polycrystalline silicon. The transistors of the dynamic random access memory cell (DRAM) are fabricated using a silicon-based complementary metal-oxide-semiconductor (CMOS) process. Their gates are made of polycrystalline silicon, the active region layer serves as the channel, and the source and drain are located in the first metal layer closest to the gate layer among the multilayer metal layers.

[0067] In some embodiments, please refer to Figure 5 The pixel driving circuit includes a substrate 11, a gate insulating layer 12, a gate layer 13, a first interlayer dielectric layer IL1, a first metal layer M1, a second interlayer dielectric layer IL2, a second metal layer M2, a third interlayer dielectric layer IL3, a third metal layer M3, a fourth interlayer dielectric layer IL4, a fourth metal layer M4... an eighth metal layer M8 and a ninth interlayer dielectric layer IL9 stacked along the film thickness direction. The first metal layer M1 includes the source and drain of the seventh transistor T7. The storage capacitor of the dynamic random access memory cell DRAM can be formed into a parallel plate capacitor through the second metal layer M2 to the eighth metal layer M8.

[0068] In other embodiments, the number of metal layers in the pixel driving circuit is not limited to the eight metal layers in the above embodiments, but may also have three or more metal layers, with dielectric layers separating adjacent metal layers for insulation. The storage capacitor Cst can form a parallel-plate capacitor structure through at least two metal layers above the first metal layer M1.

[0069] Based on the pixel driving circuit provided in the above embodiments of this application, embodiments of this application also provide a display panel. Please refer to [link to relevant documentation]. Figure 8 , Figure 8 This is a schematic diagram of a display panel provided for an embodiment of the present application. The display panel includes a pixel driving circuit as provided in any of the above embodiments.

[0070] In some embodiments, the display panel can be a silicon-based micro-light-emitting diode display panel, suitable for near-eye display scenarios such as augmented reality and virtual reality, which require high pixel density. The display panel provided in the embodiments of this application, by employing the aforementioned pixel driving circuit, can achieve high-resolution display within a small pixel area, while also having low power consumption and manufacturing costs.

[0071] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide a pixel driving circuit and a display panel. The pixel driving circuit includes a storage module and a driving module. The storage module is electrically connected to a data line and is used to store grayscale data. The driving module is electrically connected to the storage module and a light-emitting element and is used to drive the light-emitting element to emit light according to the grayscale data stored in the storage module. By setting at least some storage units as dynamic random access memory units, since the dynamic random access memory units can be formed by the upper metal layer of the pixel unit and do not occupy the horizontal area, the overall area occupied by the pixel driving circuit can be reduced, which is beneficial to improving the pixel density.

[0072] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0073] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0074] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0075] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A pixel driving circuit, characterized in that, include: The storage module is electrically connected to the data cable and includes multiple storage units for storing grayscale data. A driving module is electrically connected to the storage module and the light-emitting element, and is used to drive the light-emitting element to emit light according to the grayscale data stored in the storage module; At least some of the plurality of storage units are dynamic random access storage units.

2. The pixel driving circuit as described in claim 1, characterized in that, The plurality of storage units include a plurality of dynamic random access storage units and a plurality of static random access storage units, wherein the plurality of dynamic random access storage units and the plurality of static random access storage units are connected in parallel between the data line and the driver module.

3. The pixel driving circuit as described in claim 2, characterized in that, The plurality of dynamic random access memory units and the plurality of static random access memory units are arranged alternately along the extension direction of the data line; The pixel driving circuit further includes multiple row selection control lines, which are alternately connected to the dynamic random access memory unit and the static random access memory unit, and adjacent rows of the row selection control lines respectively control different types of memory units.

4. The pixel driving circuit as described in claim 2, characterized in that, The dynamic random access memory unit and the static random access memory unit are stacked along the film thickness direction.

5. The pixel driving circuit as described in claim 2, characterized in that, Both the dynamic random access memory (DRAM) unit and the static random access memory (SRAM) unit include transistors, and the number of transistors in the DRAM unit is less than the number of transistors in the SRAM unit. The transistors in the dynamic random access memory (DRAM) unit are disposed on the same layer as the transistors in the static random access memory (SRAM) unit. The DRAM unit also includes a storage capacitor, which is stacked on the transistors.

6. The pixel driving circuit as described in claim 1, characterized in that, The pixel driving circuit also includes multiple switching modules. The switching modules are electrically connected between the storage unit and the driving module. The control terminal of the switching module is used to receive a pulse width modulation signal. The switching module is used to respond to the pulse width modulation signal and control the conduction state of the circuit between the storage unit and the driving module.

7. The pixel driving circuit as described in claim 6, characterized in that, The display frame period of the pixel driving circuit includes multiple subframes, and the duty cycle of the pulse width modulation signal corresponding to the multiple subframes increases exponentially. The multiple switching modules are used to respond to the pulse width modulation signal and sequentially control the circuit between the multiple storage units and the driving module to conduct, so that the driving module drives the light-emitting element to emit light according to the grayscale data.

8. The pixel driving circuit as described in claim 1, characterized in that, The plurality of storage units are all dynamic random access memory units, which are connected in parallel between the data line and the driver module, and are arranged in multiple rows and columns along the extension direction of the data line and in a direction perpendicular to the extension direction of the data line.

9. The pixel driving circuit as described in any one of claims 1 to 8, characterized in that, The pixel driving circuit includes multiple row selection control lines, which are electrically connected to the storage unit. The multiple row selection control lines are used to generate selection pulses sequentially during the data writing phase of the display frame cycle, so as to latch and write the grayscale data input by the data line into the corresponding storage unit in sequence. The selection pulses of each adjacent row selection control line do not overlap in time.

10. The pixel driving circuit as described in any one of claims 1 to 8, characterized in that, The pixel driving circuit also includes a row selection control line, a first power line, and a switch module, wherein the switch module is electrically connected between the storage unit and the driving module; The dynamic random access memory cell includes a transistor and a storage capacitor. The drain of the transistor is electrically connected to the data line, the source of the transistor is electrically connected to the storage capacitor and the switching module, the gate of the transistor is electrically connected to the row selection control line, and the storage capacitor is also electrically connected to the first power line.

11. A display panel, characterized in that, Includes the pixel driving circuit as described in any one of claims 1 to 10.

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