Shift register, gate driving circuit, display panel and driving method

Abstract

Embodiments of the present application disclose a shift register, a gate drive circuit, a display panel and a driving method. The shift register comprises a control module, a stage transmission output module and a driving output module; the control module is connected with the stage transmission output module; at least one of the control module and the stage transmission output module is connected with the driving output module; the control module is used for controlling the stage transmission output module to output a stage transmission signal; the driving output module is connected with at least two first type clock signals; and the same output end of the driving output module outputs at least two effective level pulses corresponding to effective level pulses of the at least two first type clock signals. Embodiments of the present application can realize output of multiple pulse signals with different phases in a row.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a shift register, a gate driving circuit, a display panel, and a driving method. Background Technology

[0002] Organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display panels needs improvement. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the above background, this application provides a shift register, a gate driving circuit, a display panel, and a driving method, which aim to improve the performance of the display panel.

[0005] This application provides a shift register, including: a control module, a stage output module, and a drive output module;

[0006] The control module is connected to the stage output module, and at least one of the control module and the stage output module is connected to the drive output module. The control module is used to transmit signals from the control stage to the output stage of the module. The drive output module is connected to at least two Type I clock signals, and the same output terminal of the drive output module outputs at least two valid level pulses corresponding to the valid level pulses of the at least two Type I clock signals.

[0007] This application also provides a gate driving circuit, including the shift register provided in any embodiment of this application.

[0008] This application also provides a display panel, including the gate driving circuit provided in any embodiment of this application.

[0009] This application also provides a driving method, applied to the shift register or the gate driving circuit provided in this application, the driving method including: The drive output module is connected to at least two first-type clock signals, and each output terminal of at least one of the drive output modules outputs at least two valid level pulses corresponding to the valid level pulses of the at least two first-type clock signals.

[0010] The shift register in this embodiment includes a control module, a stage output module, and a drive output module. The control module is connected to the stage output module, and at least one of the control module and the stage output module is connected to the drive output module. The control module is used to control the stage output module to output stage transmission signals. The drive output module is connected to at least two first-type clock signals. The same output terminal of the drive output module outputs at least two valid level pulses corresponding to the valid level pulses of the at least two first-type clock signals, which can realize the output of pulses with different phases to achieve normal driving of the pixel circuit. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of a shift register provided in an embodiment of this application.

[0013] Figure 2 The timing waveform diagram of a shift register provided in an embodiment of this application is shown.

[0014] Figure 3 This is a schematic diagram of another shift register provided in an embodiment of this application.

[0015] Figure 4 The timing waveform diagram of another shift register provided in the embodiments of this application.

[0016] Figure 5 The timing waveform diagram of another shift register provided in the embodiments of this application.

[0017] Figure 6 This is a schematic diagram of another shift register provided in an embodiment of this application.

[0018] Figure 7a This is a schematic diagram of another shift register provided in an embodiment of this application.

[0019] Figure 7b This is a schematic diagram of another shift register provided in an embodiment of this application.

[0020] Figure 7c This is a schematic diagram of another shift register provided in an embodiment of this application.

[0021] Figure 8a This is a schematic diagram of another shift register provided in an embodiment of this application.

[0022] Figure 8b This is a schematic diagram of another shift register provided in an embodiment of this application.

[0023] Figure 9 This is a schematic diagram of another shift register provided in an embodiment of this application.

[0024] Figure 10 This is a schematic diagram of another shift register provided in an embodiment of this application.

[0025] Figure 11 This is a schematic diagram of another shift register provided in an embodiment of this application.

[0026] Figure 12a The timing waveform diagram of another shift register provided in the embodiments of this application.

[0027] Figure 12b This is a schematic diagram of another shift register provided in an embodiment of this application.

[0028] Figure 12c This is a schematic diagram of another shift register provided in an embodiment of this application.

[0029] Figure 12d This is a schematic diagram of another shift register provided in an embodiment of this application.

[0030] Figure 12e This is a schematic diagram of another shift register provided in an embodiment of this application.

[0031] Figure 13 This is a schematic diagram of a gate driving circuit provided in an embodiment of this application.

[0032] Figure 14 The timing waveform diagram is provided for a gate driving circuit according to an embodiment of this application.

[0033] Figure 15 The timing waveform diagram is provided for another gate drive circuit according to an embodiment of this application.

[0034] Figure 16 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application.

[0035] Figure 17 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0037] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0038] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0039] For ease of understanding, the accompanying diagram shows the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction relative to the plane containing the X and Y directions. Furthermore, a view where various elements are observed parallel to the plane containing the X and Y directions is called a top view. Alternatively, the planes in the X and Y directions can be planes parallel to the display surface of the display panel, and the Z-direction can be a direction parallel to the thickness direction of the display panel.

[0040] For certain elements, terms such as "above" or "over" are sometimes used when describing the position of an element located in the Z direction, and "below" or "under" are used when describing the position of an element located in the opposite direction. Furthermore, when using terms such as "above," "over," "below," "under," and "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly connected, but also the state where the two elements are separated by a gap or other elements. Additionally, the terms "first," "second," and "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance or order. At least one may include one or more. At least one may include one or more. At least part may include part or all. The first direction and the second direction intersect, for example, they may be perpendicular. At least one may include one or more. The connection may include a direct connection or an indirect connection. The connection may be an electrical connection. Equal or identical means equal or identical within a reasonable range of errors such as manufacturing errors, process errors, and measurement errors. The transistor may be a P-type transistor or an N-type transistor. A P-type transistor is turned on when its gate is connected to a low level and turned off when its gate is connected to a high level. An N-type transistor conducts when its gate is connected to a high level and turns off when its gate is connected to a low level. One of the first and second terminals of the same transistor can be the source, and the other can be the drain. P-type transistors can include polysilicon transistors. N-type transistors can include metal-oxide transistors, such as IGZO (indium gallium zinc oxide) transistors. For example, all transistors in a shift register have the same channel type, and the active layer material of each (or all) transistor in the shift register is the same, thus simplifying the fabrication process. Two overlapping pulses correspond to at least a portion of the time periods corresponding to the two pulses being the same time period.

[0041] This application provides a shift register. Figure 1 This is a schematic diagram of a shift register provided in an embodiment of this application. Figure 2 A timing waveform diagram of a shift register provided in an embodiment of this application. See also... Figure 1 and Figure 2 The shift register 401 includes: a control module 10, a stage output module 20, and a drive output module 30.

[0042] The control module 10 is connected to the stage output module 20, and at least one of the control module 10 and the stage output module 20 is connected to the drive output module 30.

[0043] The control module 10 is used to transmit the Carry signal from the output stage of the control stage to the output stage of the module 20.

[0044] The drive output module 30 receives at least two first-type clock signals (e.g., it may include a first clock signal SCK1 and a second clock signal SCK2). The same output terminal Sout of the drive output module 30 (e.g., each of at least one output terminal of the drive output module 30) outputs at least two valid level pulses (e.g., pulses P1 and P2) corresponding to (e.g., overlapping or synchronous, one-to-one, or one-to-one overlapping or one-to-one synchronous) the valid level pulses (e.g., pulses P4 and P5) of the at least two first-type clock signals. For example, at least one output terminal of the drive output module 30 may include at least a portion of the output terminals of the drive output module 30.

[0045] For example, the output terminal Sout of the drive output module 30 can output a first valid level pulse P1. The first valid level pulse P1 corresponds to the valid level pulse P4 of the first clock signal SCK1, for example, they overlap, or they are synchronized, for example, the pulse start time is the same and the pulse end time is the same. This is equivalent to transmitting the valid level pulse P4 of the first clock signal SCK1 to the output terminal Sout of the drive output module 30 as the first valid level pulse P1.

[0046] For example, the output terminal Sout of the drive output module 30 can output a second valid level pulse P2, which corresponds to the valid level pulse P5 of the second clock signal SCK2. For example, they may overlap, be synchronized, or have the same start and end times. This is equivalent to transmitting the valid level pulse P5 of the second clock signal SCK2 to the output terminal Sout of the drive output module 30 as the second valid level pulse P2.

[0047] For example, the drive output module 30 may include one or more output terminals Sout. At least two output terminals Sout correspond to the same at least two Type I clock signals, or at least two output terminals Sout correspond to different at least two Type I clock signals.

[0048] For example, the at least two first-type clock signals connected to the drive output module 30 can be at least two first-type clock signals with the same frequency but different phases.

[0049] In related technologies, scanning circuits can only provide pulse signals of equal phase, meaning that multiple pulses output by two adjacent shift registers are set at equal intervals. In this embodiment, the output terminal Sout of shift register 401 can output dual pulse signals of different phases within a row. That is, the output terminal Sout of the same shift register 401 can output at least two pulses within Tc1 / 2, where Tc1 can be the period of the first clock signal SCK1. The multiple pulses output by two adjacent shift registers 401 can be set at unequal intervals, or a mode switch can be performed. In the first mode, the multiple pulses output by two adjacent shift registers can be set at unequal intervals; in the second mode, the multiple pulses output by two adjacent shift registers 401 can be set at equal intervals. For example, this can be achieved by adjusting the phase relationship of the first type of clock signal. The different phase pulses output by the output terminal Sout of shift register 401 in this embodiment can meet the driving requirements of the corresponding pixel circuit.

[0050] The shift register 401 in this embodiment includes a control module 10, a stage output module 20, and a drive output module 30. The control module 10 is connected to the stage output module 20, and at least one of the control module 10 and the stage output module 20 is connected to the drive output module 30. The control module 10 is used to control the stage output module 20 to output the stage transmission signal Carry. The drive output module 30 is connected to at least two first-type clock signals. The same output terminal Sout of the drive output module 30 outputs at least two valid level pulses corresponding to the valid level pulses of the at least two first-type clock signals, which can realize the output of pulses with different phases to achieve normal driving of the pixel circuit.

[0051] For example, the drive output module 30 receives k first-type clock signals (e.g., it may include a first clock signal SCK1 and a second clock signal SCK2). The same output terminal Sout of the drive output module 30 (e.g., each of at least one output terminal of the drive output module 30) outputs k valid level pulses (e.g., pulses P4 and P5) corresponding to (e.g., overlapping or synchronizing) the valid level pulses of the k first-type clock signals (e.g., pulses P4 and P5). Here, k is an integer greater than or equal to 2, for example, k equals 2, 3, 4, 5, 6, 7, 8, 9, or 10. For example, within the corresponding half-cycle Tc1, the valid level pulses of the k first-type clock signals are set in a one-to-one correspondence with the k valid level pulses. Tc1 can be the period of the first-type clock signals.

[0052] For example, when k is greater than or equal to 3, the k valid level pulses output by the same output terminal Sout of the drive output module 30, which correspond to the valid level pulses of the k first-type clock signals, can be set at equal intervals or at unequal intervals.

[0053] Figure 3 A schematic diagram of another shift register provided in an embodiment of this application. For example, see... Figure 3 The drive output module 30 includes a first output unit 31 and a second output unit 32. At least two first-type clock signals include a first clock signal SCK1 and a second clock signal SCK2.

[0054] The first terminal of the first output unit 31 is connected to the first clock signal SCK1, the second terminal of the first output unit 31 is connected to the output terminal Sout of the drive output module 30, and the first control terminal G11 of the first output unit 31 is connected (may include direct connection or indirect connection, for example, indirect connection may include connection through an inverter) to at least one of the control module 10 and the stage transmission output module 20.

[0055] The first terminal of the second output unit 32 is connected to the second clock signal SCK2, the second terminal of the second output unit 32 is connected to the output terminal of the drive output module 30, and the first control terminal G21 of the second output unit 32 is connected (may include direct connection or indirect connection, for example, indirect connection may include connection through an inverter) to at least one of the control module 10 and the stage transmission output module 20.

[0056] The first output unit 31 is used to output a first valid level pulse P1 corresponding to (e.g., overlapping, or synchronized) the valid level pulse P4 of the first clock signal SCK1 to the output terminal Sout of the drive output module 30. For example, the first output unit 31 is used to transmit the valid level pulse P4 of the first clock signal SCK1 as the first valid level pulse P1 to the output terminal Sout of the drive output module 30.

[0057] The second output unit 32 is used to output a second valid level pulse P2 corresponding to (e.g., overlapping, or synchronized) the valid level pulse P5 of the second clock signal SCK2 to the output terminal Sout of the drive output module 30. For example, the second output unit 32 is used to transmit the valid level pulse P5 of the second clock signal SCK2 as the second valid level pulse P2 to the output terminal Sout of the drive output module 30.

[0058] The first effective level pulse P1 is either before or after the second effective level pulse P2.

[0059] For example, the first output unit 31 and the second output unit 32 can be turned on in a time-division manner so that the output terminal Sout of the drive output module 30 outputs the first effective level pulse P1 and the second effective level pulse P2 in a time-division manner.

[0060] For example, when the first output unit 31 is turned on, it is equivalent to the first end and the second end of the first output unit 31 being connected.

[0061] For example, when the second output unit 32 is turned on, it is equivalent to the first and second ends of the second output unit 32 being connected.

[0062] For example, the first clock signal SCK1 and the second clock signal SCK2 have the same frequency but different phases, such as a phase difference greater than 180 degrees or less than 180 degrees.

[0063] For example, the effective level pulse P4 of the first clock signal SCK1 does not overlap with the effective level pulse P5 of the second clock signal SCK2.

[0064] For example, the effective level pulses of k first-type clock signals input to the drive output module 30 do not overlap.

[0065] For example, the drive output module 30 receives k first-type clock signals with the same frequency.

[0066] Figure 4 A timing waveform diagram of another shift register provided in an embodiment of this application. For example, see... Figure 4 The effective level pulse P3 of the transmission signal Carry overlaps with the first effective level pulse P1.

[0067] For example, see Figure 4 The effective level pulse P3 of the transmission signal Carry overlaps with the second effective level pulse P2.

[0068] For example, see Figure 4 The adjacent first effective level pulse P1 and second effective level pulse P2 overlap with the same effective level pulse P3 of the stage transmission signal Carry.

[0069] For example, the time interval D1 between adjacent first valid level pulse P1 and second valid level pulse P2 is less than half of the period Tc1 (which can be the first period) of the first clock signal SCK1. For example, the sum of the pulse width of adjacent first valid level pulse P1 and second valid level pulse P2 and the time interval D1 between them is less than or equal to Tc1 / 2, that is, 2W1+D1 is less than or equal to Tc1 / 2, that is, the output terminal Sout of the drive output module 30 outputs at least two pulses in the row.

[0070] For example, the width of the first effective level pulse P1 (which can be W1) is less than the pulse width of the stage transmission signal Carry (which can be W2).

[0071] For example, the width of the second effective level pulse P2 (which can be W1) is less than the pulse width of the stage transmission signal Carry (which can be W2).

[0072] For example, the sum of the widths of the first valid level pulse P1 and the second valid level pulse P2 is less than W2. For example, 2W1 is less than W2. For example, 2W1+D1 is less than W2.

[0073] For example, the width of the first effective level pulse P1 is the same as the width of the effective level pulse P4 of the first clock signal SCK1, for example, both are W1.

[0074] For example, the width of the second effective level pulse P2 is the same as the width of the effective level pulse P5 of the second clock signal SCK2, for example, both are W1.

[0075] For example, see Figure 3 The first output unit 31 includes a first transistor T1 and a second transistor T2.

[0076] The first transistor T1 and the second transistor T2 are connected in series between the first terminal and the second terminal of the first output unit 31, and the gate of the first transistor T1 serves as the first control terminal G11 of the first output unit 31.

[0077] The second output unit 32 includes a third transistor T3 and a fourth transistor T4.

[0078] The third transistor T3 and the fourth transistor T4 are connected in series between the first and second terminals of the second output unit 32, and the gate of the third transistor T3 serves as the first control terminal G21 of the second output unit 32.

[0079] By setting the second transistor T2 and the fourth transistor T4, a short circuit can be avoided between the input terminals of the first clock signal SCK1 and the second clock signal SCK2 corresponding to the first output unit 31 and the second output unit 32.

[0080] For example, during the period when the output terminal Sout of the drive output module 30 outputs the first valid level pulse P1 (e.g., the first time period), the first transistor T1 and the second transistor T2 are turned on, and the fourth transistor T4 is turned off. This configuration avoids a short circuit between the input terminals of the first clock signal SCK1 and the second clock signal SCK2. If the fourth transistor T4 and the third transistor T3 are turned on during the period when the output terminal Sout of the drive output module 30 outputs the first valid level pulse P1, and the voltage of the second clock signal SCK2 is different from that of the first clock signal SCK1 at this time, a short circuit will occur. For example, during the period when the output terminal Sout of the drive output module 30 outputs the first valid level pulse P1, the third transistor T3 is turned on.

[0081] For example, the gate of the first transistor T1 is connected to the gate of the third transistor T3. For example, the first transistor T1 and the third transistor T3 have the same channel type, such as both being P-type or N-type transistors. For example, the first transistor T1 and the third transistor T3 have the same switching state, such as being simultaneously turned on and simultaneously turned off.

[0082] For example, during the period when the output terminal Sout of the drive output module 30 outputs the second valid level pulse P2 (e.g., the second time period), the third transistor T3 and the fourth transistor T4 are turned on, while the second transistor T2 is turned off. This configuration prevents a short circuit between the input terminals of the first clock signal SCK1 and the second clock signal SCK2. If the fourth transistor T4 and the third transistor T3 are turned on during the period when the output terminal Sout of the drive output module 30 outputs the second valid level pulse P2, and the voltage of the second clock signal SCK2 is different from the voltage of the first clock signal SCK1 at this time, a short circuit will occur. For example, during the period when the output terminal Sout of the drive output module 30 outputs the second valid level pulse P2, the first transistor T1 is turned on.

[0083] For example, the gate of the second transistor T2 serves as the second control terminal of the first output unit 31, the gate of the fourth transistor T4 serves as the second control terminal of the second output unit 32, the second control terminal of the first output unit 31 is connected to the first control signal SW1, and the second control terminal of the second output unit 32 is connected to the second control signal SW2.

[0084] Figure 5 A timing waveform diagram of another shift register provided in an embodiment of this application. For example, see... Figure 5 The first control signal SW1 and the second control signal SW2 are clock signals. The first control signal SW1 and the second control signal SW2 have the same frequency but different phases, for example, the phase difference is greater than 180 degrees or less than 180 degrees.

[0085] For example, the effective level pulse of the first control signal SW1 overlaps with the first effective level pulse P1.

[0086] For example, the effective level pulse of the second control signal SW2 overlaps with the second effective level pulse P2.

[0087] For example, the width of the effective level pulse of the first control signal SW1 (which can be W3) is greater than the width of the first effective level pulse P1 (which can be W1).

[0088] For example, the width of the effective level pulse of the second control signal SW2 (which can be W3) is greater than the width of the second effective level pulse P2 (which can be W1).

[0089] For example, the effective level pulse of the first control signal SW1 overlaps with the effective level pulse of the first clock signal SCK1. With this configuration, the first effective level pulse P1 can be output at the output terminal Sout of the first time period drive output module 30.

[0090] The effective level pulse of the second control signal SW2 overlaps with the effective level pulse of the second clock signal SCK2. This configuration allows the output terminal Sout of the second time period drive output module 30 to output the second effective level pulse P2.

[0091] For example, the frequency of the first control signal SW1 (which can be 1 / Tc2) is greater than the frequency of the first clock signal SCK1 (which can be 1 / Tc1). Tc2 can be the period of the first control signal SW1, and Tc2 can be the second period.

[0092] For example, the frequency of the first control signal SW1 is twice the frequency of the first clock signal SCK1. For example, Tc1 is equal to twice Tc2.

[0093] For example, the effective level pulse of the first control signal SW1 is the turn-on pulse of the second transistor T2. The effective level pulse of the second control signal SW2 is the turn-on pulse of the fourth transistor T4.

[0094] For example, the width of the effective level pulse of the first control signal SW1 is equal to the width of the effective level pulse of the second control signal SW2, for example, both are W3.

[0095] For example, the width of the effective level pulse of the first clock signal SCK1 is equal to the width of the effective level pulse of the second clock signal SCK2, for example, both are W1.

[0096] For example, the width of the first effective level pulse P1 is equal to the width of the second effective level pulse P2, for example, both are W1.

[0097] For example, the width W3 of the effective level pulse of the first control signal SW1 is greater than or equal to half the period of the first control signal SW1. For example, W3 is greater than Tc2 / 2. With this setting, the time period corresponding to the effective level pulse P4 of the first clock signal SCK1 is within the time period corresponding to the effective level pulse of the first control signal SW1, so as to ensure that the effective level pulse P4 of the first clock signal SCK1 is completely output to the output terminal Sout of the drive output module 30, thus obtaining the first effective level pulse P1.

[0098] For example, the width W3 of the effective level pulse of the second control signal SW2 is greater than half the period of the second control signal SW2. For example, W3 is greater than Tc2 / 2. Tc2 can be the period of the second control signal SW2. The time period corresponding to the effective level pulse P5 of the second clock signal SCK2 can be within the time period corresponding to the effective level pulse of the second control signal SW2, so as to ensure that the effective level pulse P5 of the second clock signal SCK2 is completely output to the output terminal Sout of the drive output module 30, thus obtaining the second effective level pulse P2.

[0099] For example, the first control terminal G11 of the first output unit 31 is connected to the first control terminal G21 of the second output unit 32.

[0100] For example, the first terminal of the first transistor T1 is connected to the first terminal of the first output unit 31, and the second terminal of the first transistor T1 is connected to the second terminal of the first output unit 31 via the second transistor T2.

[0101] For example, the first terminal of the third transistor T3 is connected to the first terminal of the second output unit 32, and the second terminal of the third transistor T3 is connected to the second terminal of the second output unit 32 via the fourth transistor T4. For example, the absolute value of the effective level pulse of the first control signal SW1 (which can be VGL2) is greater than the absolute value of the effective level pulse of the first clock signal SCK1 (which can be VGL1). This configuration allows the second transistor T2 to be fully turned on.

[0102] For example, the effective level of the effective level pulse of the first control signal SW1 is low, the effective level of the effective level pulse of the first clock signal SCK1 is low, and the effective level of the effective level pulse of the first control signal SW1 is lower than the effective level of the effective level pulse of the first clock signal SCK1.

[0103] For example, the difference between the absolute value of the effective level pulse of the first control signal SW1 and the absolute value of the effective level pulse of the first clock signal SCK1 is greater than the absolute value of the threshold voltage Vth2 of the second transistor T2. This setting allows the second transistor T2 to be fully turned on, enabling the effective level pulse of the first clock signal SCK1 to be output losslessly to the output terminal Sout of the drive output module 30, resulting in the first effective level pulse P1. For example, VGL2 is less than VGL1 - Vth2.

[0104] For example, the absolute value of the effective level pulse of the second control signal SW2 (which can be VGL2) is greater than the absolute value of the effective level pulse of the second clock signal SCK2 (which can be VGL1). This setting allows the fourth transistor T4 to be fully turned on.

[0105] For example, the effective level of the effective level pulse of the second control signal SW2 is low, the effective level of the effective level pulse of the second clock signal SCK2 is low, and the effective level of the effective level pulse of the second control signal SW2 is lower than the effective level of the effective level pulse of the second clock signal SCK2.

[0106] For example, the difference between the absolute value of the effective level pulse of the second control signal SW2 and the absolute value of the effective level pulse of the second clock signal SCK2 is greater than the absolute value of the threshold voltage Vth4 of the fourth transistor T4. This setting allows the fourth transistor T4 to be fully turned on, enabling the effective level pulse of the second clock signal SCK2 to be output losslessly to the output terminal Sout of the drive output module 30, resulting in the second effective level pulse P2. For example, VGL2 is less than VGL1 - Vth4.

[0107] For example, the first transistor T1 may include a P-type transistor or an N-type transistor.

[0108] For example, the second transistor T2 may include a P-type transistor or an N-type transistor.

[0109] For example, the third transistor T3 may include a P-type transistor or an N-type transistor.

[0110] For example, the fourth transistor T4 may include a P-type transistor or an N-type transistor.

[0111] For example, the second transistor T2 may include a P-type transistor, and the low level VGL2 of the first control signal SW1 is lower than the low level VGL1 of the first clock signal SCK1 or the second clock signal SCK2. For example, the absolute value of the difference between the low level VGL2 of the first control signal SW1 and the low level VGL1 of the first clock signal SCK1 or the second clock signal SCK2 is greater than the absolute value of the threshold voltage Vth2 of the second transistor T2. For example, the low level VGL2 of the first control signal SW1 is lower than VGL1-Vth2. This configuration allows the second transistor T2 to be fully turned on, enabling the effective level pulse P4 of the first clock signal SCK1 to be output losslessly to the output terminal Sout of the drive output module 30, thus obtaining the first effective level pulse P1.

[0112] For example, the second transistor T2 may include an N-type transistor, and the high level VGH2 of the first control signal SW1 is higher than the high level VGH1 of the first clock signal SCK1 or the second clock signal SCK2. For example, the difference between the high level VGH2 of the first control signal SW1 and the high level VGH1 of the first clock signal SCK1 or the second clock signal SCK2 is greater than the absolute value of the threshold voltage Vth2 of the second transistor T2. For example, the high level VGH2 of the first control signal SW1 is higher than VGH1 + Vth2. This configuration allows the second transistor T2 to be fully turned on, enabling the effective level pulse P4 of the first clock signal SCK1 to be output losslessly to the output terminal Sout of the drive output module 30, thus obtaining the first effective level pulse P1.

[0113] For example, the fourth transistor T4 may include a P-type transistor, and the low level VGL2 of the second control signal SW2 is lower than the low level VGL1 of the first clock signal SCK1 or the second clock signal SCK2. For example, the absolute value of the difference between the low level VGL2 of the second control signal SW2 and the low level VGL1 of the first clock signal SCK1 or the second clock signal SCK2 is greater than the absolute value of the threshold voltage Vth4 of the fourth transistor T4. For example, the low level VGL2 of the second control signal SW2 is lower than VGL1-Vth4. This setting allows the fourth transistor T4 to be fully turned on, so that the effective level pulse P5 of the second clock signal SCK2 can be output to the output terminal Sout of the drive output module 30 without loss, resulting in the second effective level pulse P2.

[0114] For example, the fourth transistor T4 may include an N-type transistor, and the high level VGH2 of the second control signal SW2 is higher than the high level VGH1 of the first clock signal SCK1 or the second clock signal SCK2. For example, the difference between the high level VGH2 of the second control signal SW2 and the high level VGH1 of the first clock signal SCK1 or the second clock signal SCK2 is greater than the absolute value of the threshold voltage Vth4 of the fourth transistor T4. For example, the high level VGH2 of the second control signal SW2 is higher than VGH1 + Vth4. This configuration allows the fourth transistor T4 to be fully turned on, enabling the effective level pulse P5 of the second clock signal SCK2 to be output losslessly to the output terminal Sout of the drive output module 30, resulting in the second effective level pulse P2.

[0115] For example, see Figure 3 The drive output module 30 also includes a third output unit 33.

[0116] The first terminal of the third output unit 33 is connected to the first potential signal V1 (e.g., a high level VGH), the second terminal of the third output unit 33 is connected to the output terminal Sout of the drive output module 30, and the control terminal of the third output unit 33 is connected to at least one of the control module 10 and the stage transmission output module 20.

[0117] For example, when the third output unit 33 is turned on, the first potential signal V1 (e.g., a high level VGH) can be transmitted to the output terminal Sout of the drive output module 30.

[0118] For example, during the period when the first valid level pulse P1 is output at the output terminal Sout of the drive output module 30, and / or during the period when the second valid level pulse P2 is output at the output terminal Sout of the drive output module 30, the third output unit 33 is turned off.

[0119] For example, the third output unit 33 includes a fifth transistor T5, the first terminal of the fifth transistor T5 is connected to the first terminal of the third output unit 33, the second terminal of the fifth transistor T5 is connected to the second terminal of the third output unit 33, and the gate of the fifth transistor T5 is connected to the control terminal of the third output unit 33.

[0120] For example, the fifth transistor T5 may include a P-type transistor or an N-type transistor.

[0121] The effective level of the effective level pulse (e.g., P1, P2) output by the output terminal Sout of the drive output module 30 and the first potential signal 1 are either high or low.

[0122] For example, the effective level of the valid level pulses (e.g., P1, P2) output by the output terminal Sout of the drive output module 30 is low. For example, the first potential signal V1 can be high.

[0123] For example, see Figure 3 The level transmission output module 20 includes a fourth output unit 21.

[0124] The first terminal of the fourth output unit 21 is connected to the third clock signal SCK3, the second terminal of the fourth output unit 21 is connected to the output terminal of the stage transmission output module 20, and the control terminal of the fourth output unit 21 is connected to the first output terminal of the control module 10. For example, the control terminal of the fourth output unit 21 and the first output terminal of the control module 10 are electrically connected to the first node N1.

[0125] For example, when the fourth output unit 21 is turned on, the effective level pulse P6 of the third clock signal SCK3 can be transmitted to the output terminal of the stage transmission output module 20 to obtain the effective level pulse P3 of the stage transmission signal Carry.

[0126] For example, see Figure 4 The effective level pulse P3 of the transmission signal Carry overlaps with the effective level pulse P6 of the third clock signal SCK3.

[0127] For example, see Figure 4 The first valid level pulse P1 overlaps with the valid level pulse P6 of the third clock signal SCK3.

[0128] For example, see Figure 4 The second effective level pulse P2 overlaps with the effective level pulse P6 of the third clock signal SCK3.

[0129] For example, at least two of the first output terminal of the control module 10, the first control terminal G11 of the first output unit 31, the first control terminal G21 of the second output unit 32, and the control terminal of the third output unit 33 are connected.

[0130] For example, the first output terminal CW1 of the control module 10 or the control terminal of the fourth output unit 21 or the output terminal of the stage transmission output module 20 is connected to the first control terminal G11 of the first output unit 31.

[0131] For example, the first output terminal CW1 of the control module 10 or the control terminal of the fourth output unit 21 or the output terminal of the stage transmission output module 20 is connected to the first control terminal G21 of the second output unit 32.

[0132] For example, the second output terminal of the control module 10 is connected to the control terminal of the third output unit 33.

[0133] For example, the fourth output unit 21 includes a sixth transistor T6. The first terminal of the sixth transistor T6 is connected to the first terminal of the fourth output unit 21, the second terminal of the sixth transistor T6 is connected to the second terminal of the fourth output unit 21, and the gate of the sixth transistor T6 is connected to the control terminal of the fourth output unit 21. For example, at least two of the gates of the first transistor T1, the third transistor T3, and the sixth transistor T6 are connected. This configuration simplifies the gate routing design.

[0134] For example, at least two of the first transistor T1, the third transistor T3, and the sixth transistor T6 have the same switching state, such as being simultaneously on and simultaneously off.

[0135] For example, the first transistor T1, the third transistor T3, and the sixth transistor T6 have the same switching state, such as being simultaneously turned on and simultaneously turned off.

[0136] For example, at least two of the first transistor T1, the third transistor T3, and the sixth transistor T6 have the same channel type, such as either a P-type transistor or an N-type transistor.

[0137] For example, the first transistor T1, the third transistor T3, and the sixth transistor T6 have the same channel type, such as either a P-type transistor or an N-type transistor.

[0138] For example, the sixth transistor T6 may include a P-type transistor or an N-type transistor.

[0139] For example, the stage output module 20 also includes a fifth output unit 22.

[0140] The first terminal of the fifth output unit 22 is connected to the first potential signal V1 (for example, it can be a high level VGH), the second terminal of the fifth output unit 22 is connected to the output terminal of the stage transmission output module 20, and the control terminal of the fifth output unit 22 is connected to the second output terminal of the control module 10.

[0141] For example, the control terminal of the fifth output unit 22 and the second output terminal of the control module 10 are electrically connected to the third node N3.

[0142] For example, the control terminal of the third output unit 33 is connected to the control terminal of the fifth output unit 22.

[0143] For example, the third output unit 33 and the fifth output unit 22 have the same switching state, such as being simultaneously turned on and simultaneously turned off.

[0144] For example, during the period when the first valid level pulse P1 is output at the output terminal Sout of the drive output module 30, and / or during the period when the second valid level pulse P2 is output at the output terminal Sout of the drive output module 30, the fifth output unit 22 is turned off.

[0145] For example, the fifth output unit 22 includes a seventh transistor T7, the first terminal of the seventh transistor T7 is connected to the first terminal of the fifth output unit 22, the second terminal of the seventh transistor T7 is connected to the second terminal of the fifth output unit 22, and the gate of the seventh transistor T7 is connected to the control terminal of the fifth output unit 22.

[0146] For example, the seventh transistor T7 may include a P-type transistor or an N-type transistor.

[0147] For example, the fifth transistor T5 and the seventh transistor T7 have the same switching state, such as being on and off at the same time.

[0148] For example, the fifth transistor T5 and the seventh transistor T7 have the same channel type, such as both being P-type or N-type transistors.

[0149] For example, the shift register also includes a first capacitor C1, which is connected between the second terminal of the fourth output unit 21 and the control terminal.

[0150] For example, the shift register also includes a second capacitor C2, which is connected between the first terminal and the control terminal of the fifth output unit 22.

[0151] For example, the shift register also includes a protection module 25, and the first output terminal of the control module 10 is connected to the stage output module 20 via the protection module 25. For example, the first output terminal of the control module 10 is connected to the control terminal of the fourth output unit 21 via the protection module 25. For example, the first output terminal of the control module 10 is connected to the first control terminal G11 of the first output unit 31 via the protection module 25. For example, the first output terminal of the control module 10 is connected to the first control terminal G21 of the second output unit 32 via the protection module 25.

[0152] For example, the protection module 25 includes a thirteenth transistor T13. The first output terminal of the control module 10 is connected to the control terminal of the fourth output unit 21 via the thirteenth transistor T13. The gate of the thirteenth transistor T13 is connected to a second potential signal V1 (e.g., a low level VGL).

[0153] The protection module 25 can be a normally open module. The second potential signal V1 (e.g., a low level VGL) can be the on level of the protection module 25.

[0154] By setting up the protection module 25 to isolate the first node N1 from the transistor in the control module 10, it is possible to prevent the voltage of the first node N1 from being too low and damaging the transistor in the control module 10 connected to the first node N1.

[0155] For example, the thirteenth transistor T13 may include a P-type transistor or an N-type transistor.

[0156] For example, one of the first potential signal V1 and the second potential signal V2 is at a high level, and the other is at a low level.

[0157] For example, the first potential signal V1 is at a high level, and the second potential signal V2 is at a low level.

[0158] For example, the first output terminal of the control module 10 is connected to the first terminal of the protection module 25, for example, to the second node N2. For example, the control terminal of the fourth output unit 21 is connected to the second terminal of the protection module 25, for example, to the first node N1.

[0159] For example, the first control terminal G11 of the first output unit 31 is connected to the second terminal of the protection module 25, for example, connected to the first node N1.

[0160] For example, the first control terminal G21 of the second output unit 32 is connected to the second terminal of the protection module 25, for example, connected to the first node N1.

[0161] For example, see Figure 4 and Figure 5 The width of the effective level pulse P3 of the transmission signal Carry (which can be W2) is greater than the width of the effective level pulse (which can be W1) of the first type of clock signal (e.g., SCK1, SCK2).

[0162] For example, at least one of the control module 10 and the stage transmission output module 20 is connected to a second type of clock signal (e.g., a third clock signal SCK3), and the width of the effective level pulse (e.g., P6) of the second type of clock signal (which may be W2) is greater than the width of the effective level pulse (e.g., SCK3) of the first type of clock signal (which may be W1).

[0163] For example, the frequency of the first type of clock signal (e.g., SCK1, SCK2) is the same as the frequency of the second type of clock signal (e.g., SCK3).

[0164] For example, the width (which may be W2) of the effective level pulse of the second type clock signal (e.g., SCK3) is greater than the sum of the widths (which may be W1) of the effective level pulses of at least two first type clock signals (e.g., SCK1, SCK2). And / or, the effective level pulse of at least one second type clock signal (e.g., SCK3) overlaps with the effective level pulses of at least two first type clock signals (e.g., SCK1, SCK2). And / or, the width (which may be W2) of the effective level pulse P3 of the stage transmission signal Carry is greater than the sum of the widths of the effective level pulses of at least two first type clock signals (e.g., SCK1, SCK2). And / or, the effective level pulse P3 of the stage transmission signal Carry overlaps with the effective level pulses (e.g., P4, P5) of at least two first type clock signals (e.g., SCK1, SCK2).

[0165] For example, in the at least two valid level pulses output by the output terminal Sout of the drive output module 30 that correspond to the valid level pulses of at least two first-type clock signals (e.g., SCK1, SCK2), the time interval D1 between adjacent valid level pulses (e.g., P1, P2) is less than half of the period Tc1 of the first-type clock signals (e.g., SCK1, SCK2).

[0166] For example, the width (which can be W1) of the effective level pulse of the first type of clock signal (e.g., SCK1, SCK2) is less than half of the period Tc1 of the first type of clock signal.

[0167] For example, the width of the effective level pulse of the second type of clock signal (e.g., SCK3) (which can be W2) is less than half of the period Tc2 of the second type of clock signal.

[0168] For example, at least two first-class clock signals include a first clock signal SCK1 with the same frequency but different phases and a second clock signal SCK2.

[0169] The drive output module 30 is used to output, in a time-division manner, a first effective level pulse P1 that overlaps with the effective level pulse P4 of the first clock signal SCK1 and a second effective level pulse P2 that overlaps with the effective level pulse P5 of the second clock signal SCK2.

[0170] For example, the effective level pulse P3 of the stage transmission signal Carry overlaps with the effective level pulse P4 of the first clock signal SCK1.

[0171] For example, the effective level pulse P3 of the stage transmission signal Carry overlaps with the effective level pulse P5 of the second clock signal SCK2.

[0172] For example, the second type of clock signal includes the third clock signal SCK3, and at least one of the control module 10 and the stage transmission output module 20 is connected to the third clock signal SCK3.

[0173] For example, the width of the effective level pulse of the third clock signal SCK3 (which can be W2) is greater than the sum of the width of the effective level pulse of the first clock signal SCK1 (which can be W1) and the width of the effective level pulse of the second clock signal SCK2 (which can be W1).

[0174] For example, the effective level pulse P4 of the first clock signal SCK1 overlaps with the effective level pulse P6 of the third clock signal SCK3.

[0175] The effective level pulse P5 of the second clock signal SCK2 overlaps with the effective level pulse P6 of the third clock signal SCK3.

[0176] For example, the effective level pulse P4 of the first clock signal SCK1 does not overlap with the effective level pulse P5 of the second clock signal SCK2.

[0177] For example, the effective level pulse P4 of the adjacent first clock signal SCK1 and the effective level pulse P5 of the second clock signal SCK2 overlap with the same effective level pulse P6 of the third clock signal SCK3.

[0178] For example, the time interval (which may be equal to D1) between the effective level pulse P4 of the adjacent first clock signal SCK1 and the effective level pulse P5 of the second clock signal SCK2 is less than half of the period Tc1 of the third clock signal SCK3.

[0179] For example, the frequency of the first clock signal SCK1 is equal to the frequency of the third clock signal SCK3. For example, the period of the first clock signal SCK1 is equal to the period of the third clock signal SCK3, both being Tc1.

[0180] For example, the width of the effective level pulse P6 of the third clock signal SCK3 is equal to the width of the effective level pulse P3 of the stage transmission signal Carry, for example, both are W2.

[0181] For example, the width of the effective level pulse P3 of the stage transmission signal Carry (which can be W2) is greater than the sum of the width of the effective level pulse of the first clock signal SCK1 (which can be W1) and the width of the effective level pulse of the second clock signal SCK2 (which can be W1).

[0182] For example, the second type of clock signal includes the fourth clock signal SCK4, and the control module 10 is connected to the fourth clock signal SCK4.

[0183] For example, control module 10 is connected to the third clock signal SCK3 and the fourth clock signal SCK4. For example, stage output module 20 is connected to the third clock signal SCK3.

[0184] For example, the width of the effective level pulse of the fourth clock signal SCK4 is greater than the sum of the widths of the effective level pulses of the first clock signal SCK1 and the second clock signal SCK2.

[0185] For example, the effective level pulses of the first clock signal SCK1 and the effective level pulses of the fourth clock signal SCK4 do not overlap.

[0186] The effective level pulses of the second clock signal SCK2 and the fourth clock signal SCK4 do not overlap.

[0187] For example, the time interval between the effective level pulses of the adjacent first clock signal SCK1 and the effective level pulses of the second clock signal SCK2 is less than half of the period Tc1 of the fourth clock signal SCK4.

[0188] For example, the width of the effective level pulse P6 (e.g., P61) of the third clock signal SCK3 is equal to the width of the effective level pulse P62 of the fourth clock signal SCK4, for example, both are W2.

[0189] For example, the effective level pulse P6 (e.g., P61) of the third clock signal SCK3 does not overlap with the effective level pulse P62 of the fourth clock signal SCK4.

[0190] For example, see Figure 3 The control module 10 includes an input unit 11, a first control terminal, and a second control unit 13.

[0191] The input unit 11 is used to control the third control signal output by the first output terminal CW1 of the control module 10 according to the input signal SIN and the fourth clock signal SCK4.

[0192] The first control unit 12 is used to control the fourth control signal output by the second output terminal CW2 of the control module 10 according to the fourth clock signal SCK4 and the third control signal.

[0193] The second control unit 13 is used to control the third control signal output by the first output terminal CW1 of the control module 10 according to the third clock signal SCK3 and the fourth control signal.

[0194] For example, input unit 11 includes an eighth transistor T8. The first terminal of the eighth transistor T8 is connected to the input signal SIN, and the second terminal of the eighth transistor T8 is connected to the first output terminal CW1 of the control module 10. The gate of the eighth transistor T8 is connected to the fourth clock signal SCK4.

[0195] For example, the first control unit 12 includes a ninth transistor T9 and a tenth transistor T10. The first terminal of the ninth transistor T9 is connected to the fourth clock signal SCK4, the second terminal of the ninth transistor T9 is connected to the second output terminal CW2 of the control module 10, and the gate of the ninth transistor T9 is connected to the first output terminal CW1 of the control module 10. The first terminal of the tenth transistor T10 is connected to the second potential signal, the second terminal of the tenth transistor T10 is connected to the second output terminal CW2 of the control module 10, and the gate of the tenth transistor T10 is connected to the fourth clock signal SCK4.

[0196] For example, the second control unit 13 includes an eleventh transistor T11 and a twelfth transistor T12. The second terminals of the eleventh transistor T11 and the twelfth transistor T12 are connected. One of the first terminals of the eleventh transistor T11 and the twelfth transistor T12 is connected to the first output terminal CW1 of the control module 10, and the other is connected to the first potential signal V1. One of the gates of the eleventh transistor T11 and the twelfth transistor T12 is connected to the second output terminal CW2 of the control module 10, and the other is connected to the third clock signal SCK3.

[0197] For example, the first terminal of the eleventh transistor T11 is connected to the first output terminal CW1 of the control module 10 or the second terminal of the protection module 25. The first terminal of the twelfth transistor T12 is connected to the first potential signal V1. The gate of the eleventh transistor T11 is connected to the third clock signal SCK3. The gate of the twelfth transistor T12 is connected to the second output terminal CW2 of the control module 10.

[0198] For example, one of the first potential signal V1 and the second potential signal V2 is at a high level, and the other is at a low level.

[0199] For example, the first potential signal V1 is at a high level, and the second potential signal V2 is at a low level.

[0200] For example, the third clock signal SCK3 and the fourth clock signal SCK4 have the same frequency but different phases.

[0201] For example, the third clock signal SCK3 and the fourth clock signal SCK4 are out of phase.

[0202] For example, the ninth transistor T9 may include a P-type transistor or an N-type transistor.

[0203] For example, the tenth transistor T10 may include a P-type transistor or an N-type transistor.

[0204] For example, the eleventh transistor T11 may include a P-type transistor or an N-type transistor.

[0205] For example, the twelfth transistor T12 may include a P-type transistor or an N-type transistor.

[0206] See Figure 3 and Figure 5 The text describes the operation of shift registers, including the first-stage shift register, noting that the operating principles of each stage are similar. The display frame may include stages t1, t2, t3, t4, t5, and t6. Figure 3 An example diagram is drawn showing the case where all transistors are P-type transistors. The effective level pulses for each signal are low-level pulses. Figure 5 The waveforms of the voltage at the first node N1, the voltage at the second node N2, and the voltage at the third node N3 are examples.

[0207] During at least a portion of the first stage t1, the input signal SIN is low, the fourth clock signal SCK4 is low, and the first clock signal SCK1, second clock signal SCK2, third clock signal SCK3, first control signal SW1, and second control signal SW2 are all high. The voltages of the first node N1, second node N2, and third node N3 are all VGL-Vth, where Vth is the threshold voltage of the transistor. The third output unit 33 (which can be the fifth transistor T5) is turned on, and the fifth output unit 22 (which can be the seventh transistor T7) is turned on. The signal Carry at the output terminal of the stage output module 20 is the first potential signal V1, for example, a high level VGH. The output terminal Sout of the drive output module 20 outputs the first potential signal V1, for example, a high level VGH. The first transistor T1 and the third transistor T3 are turned on, and the second transistor T2 and the fourth transistor T4 are turned off.

[0208] During at least a portion of the second phase t2, the input signal SIN, the fourth clock signal SCK4, the second clock signal SCK2, and the second control signal SW2 are all high, while the first clock signal SCK1, the third clock signal SCK3, and the first control signal SW1 are all low. The voltage at the first node N1 is VGL-Vth, and the voltage at the second node N2 is 2. With VGL-Vth-VGH, the voltage at the third node N3 is VGH. Transistors T1, T2, and T3 are turned on, while transistors T4 and T5 are turned off. The first clock signal SCK1 is output through transistors T1 and T2 to the output terminal Sout of the drive output module 20, resulting in the first valid level pulse P1. The signal Carry at the output terminal of the stage output module 20 is low, meaning the valid level pulse P3 is started. The third output unit 33 (which can be the fifth transistor T5) is turned off, and the fifth output unit 22 (which can be the seventh transistor T7) is also turned off.

[0209] During at least a portion of the third stage t3, the first clock signal SCK1 transitions to a high level, and the rest is similar to the second stage t2. Then, the Carry signal at the output terminal of the stage output module 20 is low, and the Sout signal at the output terminal of the drive output module 20 is high. The third output unit 33 (which may be the fifth transistor T5) is turned off, and the fifth output unit 22 (which may be the seventh transistor T7) is turned off.

[0210] During at least a portion of the fourth phase t4, the input signal SIN, the fourth clock signal SCK4, the first clock signal SCK1, and the first control signal SW1 are all high, while the second clock signal SCK2, the second control signal SW2, and the third clock signal SCK3 are all low. The voltage at the first node N1 is VGL-Vth, and the voltage at the second node N2 is 2Vth. With VGL-Vth-VGH, the voltage of the third node N3 is VGH. The first clock signal SCK1, the third clock signal SCK3, and the first control signal SW1 are all low. The first transistor T1, the third transistor T3, and the fourth transistor T4 are turned on, while the second transistor T2 and the fifth transistor T5 are turned off. The second clock signal SCK2 is output to the output terminal Sout of the drive output module 20 via the third transistor T3 and the fourth transistor T4, resulting in the second effective level pulse P2, which can be a low frequency. The signal Carry at the output terminal of the stage transmission output module 20 is low, i.e., the output effective level pulse P3 is output. The third output unit 33 (which can be the fifth transistor T5) is turned off, and the fifth output unit 22 (which can be the seventh transistor T7) is turned off.

[0211] During at least a portion of the fifth stage t5, the input signal SIN, the first clock signal SCK1, the second clock signal SCK2, and the third clock signal SCK3 are all high, the fourth clock signal SCK4 is low, the potentials of the first node N1 and the second node N2 are high, the potential of the third node N3 is VGL-Vth, the third output unit 33 (which may be the fifth transistor T5) is turned on, the first transistor T1 and the third transistor T3 are turned off, and the first control signal SW1 and the second control signal SW2, whether high or low, do not affect the voltage of the output terminal Sout of the drive output module 20. The first potential signal V1 (which may be high) is output to the output terminal Sout of the drive output module 20 via the fifth transistor T5, and the signal Carry at the output terminal of the stage output module 20 is high. The fifth output unit 22 (which may be the seventh transistor T7) is turned on.

[0212] During at least a portion of the sixth stage t6, the input signal SIN, the first clock signal SCK1, the second clock signal SCK2, and the fourth clock signal SCK4 are all at high levels, the third clock signal SCK3 is at a low level, the potentials of the first node N1 and the second node N2 are at high levels, the potential of the third node N3 is VGL-Vth, and the potentials of the first node N1, the second node N2, and the third node N3 are consistent with those of the fifth stage t5. The output terminal Sout of the drive output module 20 outputs a high level, and the signal Carry at the output terminal of the stage transmission output module 20 is at a high level.

[0213] The cycle then repeats through stages 5 (t5) and 6 (t6) until the input signal SIN goes low again, entering stage 1 (t1).

[0214] In some embodiments, it may be Figure 5 By swapping the high and low levels in the signal and replacing the P-type transistor with a P-type transistor, the effective level pulse can be changed into a high level pulse.

[0215] For example, see Figure 3 The first control terminal G11 of the first output unit 31 is connected to the first output terminal CW1 of the control module 10 and / or the stage transmission output module 20 (e.g., the control terminal of the fourth output unit 11 or the output terminal of the stage transmission output module 20).

[0216] For example, see Figure 3 The first control terminal G21 of the second output unit 32 is connected to the first output terminal CW1 of the control module 10 and / or the stage transmission output module 20 (e.g., the control terminal of the fourth output unit 11 or the output terminal of the stage transmission output module 20).

[0217] Figure 6A schematic diagram of another shift register provided in an embodiment of this application. For example, see... Figure 6 The first control terminal G11 of the first output unit 31 is connected to the output terminal of the transmission module 20.

[0218] For example, see Figure 6 The first control terminal G21 of the second output unit 32 is connected to the output terminal of the transmission module 20.

[0219] Figure 5 Applicable to Figure 6 Shift registers. Figure 5 and Figure 6 Corresponding technical solutions and Figure 3 and Figure 5 The corresponding technical solutions work on similar principles, so they will not be elaborated here. The difference lies in... Figure 5 and Figure 6 In the corresponding technical solution, in the first stage t1, the first transistor T1 and the third transistor T3 are turned off. Figure 3 and Figure 5 In the corresponding technical solution, during the first stage t1, the first transistor T1 and the third transistor T3 are turned on.

[0220] Figure 7a A schematic diagram of another shift register provided in an embodiment of this application. For example, see... Figure 7a The first terminal of the first transistor T1 is connected to the first terminal of the first output unit 31 via the second transistor T2, and the second terminal of the first transistor T1 is connected to the second terminal of the first output unit 31.

[0221] For example, see Figure 7a The first terminal of the third transistor T3 is connected to the first terminal of the second output unit 32 via the fourth transistor T4, and the second terminal of the third transistor T3 is connected to the second terminal of the second output unit 32.

[0222] Figure 5 Applicable to Figure 7a Shift registers. Figure 5 and Figure 7a Corresponding technical solutions and Figure 3 and Figure 5 The working principles of the corresponding technical solutions are similar, and will not be elaborated here.

[0223] Compared to Figure 3 , Figure 6 or Figure 7a The technical solution can reduce the load on the first output terminal CW1 of the control module 10, reduce the risk of overload on the first output terminal CW1 of the control module 10, and balance the load on the first output terminal CW1 of the control module 10 and the load on the output terminal of the stage transmission output module 20.

[0224] Figure 7b A schematic diagram of another shift register provided in an embodiment of this application. For example, see... Figure 7b The first transistor T1 has its first terminal connected to the first terminal of the first output unit 31, and its second terminal connected to the second terminal of the first output unit 31. The first terminal of the second transistor T2 is connected to the second control terminal of the first output unit 31 and / or receives the first control signal SW1. The gate of the second transistor T2 is connected to the first control terminal G11 of the first output unit 31; for example, the gate of the second transistor T2 can serve as the first control terminal G11 of the first output unit 31. The second terminal of the second transistor T2 is connected to the gate of the first transistor T1. The second control terminal of the first output unit 31 can receive the first control signal SW1. For example, the first control terminal G11 of the first output unit 31 is connected to the control module 10 and / or the stage transmission output module 20.

[0225] For example, see Figure 7b During the period when the output terminal Sout of the drive output module 30 outputs the first valid level pulse P1 (e.g., the first time period), the first transistor T1 and the second transistor T2 are turned on, and the third transistor T3 is turned off. This configuration avoids a short circuit between the input terminals of the first clock signal SCK1 and the second clock signal SCK2. If the fourth transistor T4 and the third transistor T3 are turned on during the period when the output terminal Sout of the drive output module 30 outputs the first valid level pulse P1, and the voltage of the second clock signal SCK2 is different from that of the first clock signal SCK1 at this time, a short circuit will occur. For example, during the period when the output terminal Sout of the drive output module 30 outputs the first valid level pulse P1 (e.g., the first time period), the fourth transistor T4 is turned on.

[0226] For example, see Figure 7b The first terminal of the third transistor T3 is connected to the first terminal of the second output unit 32, and the second terminal of the third transistor T3 is connected to the second terminal of the second output unit 32. The first terminal of the fourth transistor T4 is connected to the second control terminal of the second output unit 32 and / or receives the second control signal SW2. The gate of the fourth transistor T4 is connected to the first control terminal G21 of the second output unit 32; for example, the gate of the fourth transistor T4 can serve as the first control terminal G21 of the second output unit 32. The second terminal of the fourth transistor T4 is connected to the gate of the third transistor T3. For example, the first control terminal G21 of the second output unit 32 is connected to the control module 10 and / or the stage transmission output module 20.

[0227] For example, see Figure 7bDuring the period when the output terminal Sout of the drive output module 30 outputs the second valid level pulse P2 (e.g., the second time period), the third transistor T3 and the fourth transistor T4 are turned on, and the first transistor T1 is turned off. This configuration avoids a short circuit between the input terminals of the first clock signal SCK1 and the second clock signal SCK2. If the fourth transistor T4 and the third transistor T3 are turned on during the period when the output terminal Sout of the drive output module 30 outputs the second valid level pulse P2, and the voltage of the second clock signal SCK2 is different from that of the first clock signal SCK1 at this time, a short circuit will occur. For example, during the period when the output terminal Sout of the drive output module 30 outputs the second valid level pulse P2 (e.g., the second time period), the second transistor T2 is turned on.

[0228] For example, see Figure 7b The first output unit 31 may further include a fourteenth transistor T31. The first terminal of the fourteenth transistor T31 is connected to a first potential signal V1 (e.g., the off-level of the first transistor T1), and the second terminal of the fourteenth transistor T31 is connected to the gate of the first transistor T1. The gate of the fourteenth transistor T31 may be connected to the control terminal of the third output unit 33 and / or the second output terminal CW2 of the control module 10 or the control terminal of the fifth control unit 22. And / or, the potential of the gate of the fourteenth transistor T31 is the same as the potential of at least one of the control terminals of the third output unit 33, the second output terminal CW2 of the control module 10, and the control terminal of the fifth control unit 22. By setting the fourteenth transistor T31, the first transistor T1 can be reliably turned off during periods when the fifth stage of output is not required.

[0229] For example, see Figure 7b The second output unit 32 may further include a fifteenth transistor T32. The first terminal of the fifteenth transistor T32 is connected to a first potential signal V1 (e.g., the off-state level of the third transistor T3), and the second terminal of the fifteenth transistor T32 is connected to the gate of the third transistor T3. The gate of the fifteenth transistor T32 may be connected to the control terminal of the third output unit 33 and / or the second output terminal CW2 of the control module 10 or the control terminal of the fifth control unit 22. And / or, the potential of the gate of the fifteenth transistor T32 is the same as the potential of at least one of the control terminals of the third output unit 33, the second output terminal CW2 of the control module 10, and the control terminal of the fifth control unit 22. By setting the fifteenth transistor T32, the third transistor T3 can be reliably turned off during periods when the fifth stage of output is not required.

[0230] Figure 5 Applicable to Figure 7b Shift registers. Figure 5 and Figure 7b Corresponding technical solutions and Figure 3 and Figure 5 The working principles of the corresponding technical solutions are similar, and will not be elaborated here. The difference lies in... Figure 5 and Figure 7b In the corresponding technical solution, during at least a portion of the first stage t1, the second transistor T2, the fourth transistor T4, the first transistor T1, and the third transistor T3 are turned off. The fourteenth transistor T31 and the fifteenth transistor T32 are turned on. During at least a portion of the second stage t2, the fourteenth transistor T31 and the fifteenth transistor T32 are turned off, and the first transistor T1, the second transistor T2, and the fourth transistor T4 are turned on. When the first transistor T1 transmits the effective level pulse (e.g., a low-level pulse) of the first clock signal SCK1 to the output terminal Sout of the drive output module 20, the third transistor T3 is turned off because the second control signal SW2 transmitted by the fourth transistor T4 is at a shutdown level (e.g., a high level) to avoid a short circuit. During at least a portion of the third stage t3, the fourteenth transistor T31 and the fifteenth transistor T32 are turned off, and the first transistor T1, the third transistor T3, the second transistor T2, and the fourth transistor T4 are turned on. The high levels of the first clock signal SCK1 and the second clock signal SCK2 can be transmitted to the output terminal Sout of the drive output module 20. During at least a portion of the fourth stage t4, transistors fourteenth T31 ​​and fifteenth T32 are off, while transistors third T3, second T2, and fourth T4 are on. When transistor third T3 transmits a valid level pulse (e.g., a low-level pulse) of the second clock signal SCK2 to the output terminal Sout of the drive output module 20, transistor first T1 is turned off because the first control signal SW1 transmitted by transistor second T2 is at a shutdown level (e.g., a high level) to avoid a short circuit. During at least a portion of the fifth stage t5, transistors second T2 and fourth T4 are off, while transistors fourteenth T31 ​​and fifteenth T32 are on, and transistors first T1 and third T3 are off. During at least a portion of the sixth stage t6, transistors second T2 and fourth T4 are off, while transistors fourteenth T31 ​​and fifteenth T32 are on, and transistors first T1 and third T3 are off.

[0231] Figure 7c A schematic diagram of another shift register provided in an embodiment of this application. For example, see... Figure 7b The second terminal of the fourteenth transistor T31 is connected to the gate of the third transistor T3. This configuration reduces the number of transistors, simplifies the circuit structure, reduces the bezel width, and achieves a narrow bezel.

[0232] Figure 5 Applicable to Figure 7c Shift registers. Figure 5 and Figure 7c Corresponding technical solutions and Figure 3 and Figure 5 The working principles of the corresponding technical solutions are similar, and will not be elaborated here. Figure 5 and Figure 7c Corresponding technical solutions and Figure 5 and Figure 7b The working principles of the corresponding technical solutions are similar, and will not be elaborated here.

[0233] Figure 8a This is a schematic diagram of another shift register provided in an embodiment of this application. Figure 8b A schematic diagram of another shift register provided in an embodiment of this application. For example, see... Figure 8a or Figure 8b The shift register 401 may also include at least one inverter 34. At least one of the second output terminal CW2 of the control module 10, the control terminal of the fifth output unit 22, and the control terminal of the third output unit 33 is connected to the input terminal of the inverter 34 (which may be the first inverter), and the output terminal of the inverter 34 (which may be the first inverter) is connected to the first control terminal G11 of the first output unit 31.

[0234] The first output CW1 and the second output CW2 of control module 10 have different potentials. For example, when the first output CW1 of control module 10 is high, the second output CW2 of control module 10 is low, and vice versa. When the first output CW1 of control module 10 changes from high to low, the second output CW2 of control module 10 changes from low to high; conversely, when the first output CW1 of control module 10 changes from low to high, the second output CW2 of control module 10 changes from high to low. Therefore, by setting an inverter 34, the potential of the first control terminal G11 of the first output unit 31 and the potential of the control terminal of the fourth output unit 21 can be made the same.

[0235] For example, see Figure 8a or Figure 8b One or more of the second output terminal CW2 of the control module 10, the control terminal of the fifth output unit 22, and the control terminal of the third output unit 33 are connected to the input terminal of the inverter 34 (which may be the second inverter). The output terminal of the inverter 34 (which may be the second inverter) is connected to the first control terminal G21 of the second output unit 32. The inverter 34 can be configured so that the potential of the first control terminal G21 of the second output unit 32 is the same as the potential of the control terminal of the fourth output unit 21.

[0236] Figure 5 Applicable to Figure 8a or Figure 8b Shift registers. Figure 5 and Figure 8a or Figure 8b Corresponding technical solutions and Figure 3 and Figure 5 The working principles of the corresponding technical solutions are similar, and will not be elaborated here.

[0237] For example, see Figure 8b The control module 10 may include transistors T14 to T23.

[0238] Figure 9 A schematic diagram of another shift register provided in an embodiment of this application. For example, see... Figure 9 One or more of the following: the first output terminal CW1 of the control module 10, the control terminal of the fourth output unit 21, the first control terminal G11 of the first output unit 31, and the first control terminal G21 of the second output unit 32, are connected to the input terminal of the inverter 34 (which may be the third inverter). The output terminal of the inverter 34 (which may be the third inverter) is connected to the control terminal of the third output unit 33. The inverter 34 can be configured so that the potential of the control terminal of the third output unit 33 is the same as the potential of the control terminal of the fifth output unit 22.

[0239] Figure 5 Applicable to Figure 9 Shift registers. Figure 5 and Figure 9 Corresponding technical solutions and Figure 3 and Figure 5 The working principles of the corresponding technical solutions are similar, and will not be elaborated here.

[0240] Figure 10 A schematic diagram of another shift register provided in an embodiment of this application. For example, see... Figure 10 One or more of the output terminals of the first output module 20, the first control terminal G11 of the first output unit 31, and the first control terminal G21 of the second output unit 32 are connected to the input terminal of the inverter 34 (which may be the third inverter). The output terminal of the inverter 34 (which may be the third inverter) is connected to the control terminal of the third output unit 33. The inverter 34 can be configured so that the potential of the control terminal of the third output unit 33 is the same as the potential of the control terminal of the fifth output unit 22.

[0241] Figure 5 Applicable to Figure 10 Shift registers. Figure 5 and Figure 10 Corresponding technical solutions and Figure 3 and Figure 5 The working principles of the corresponding technical solutions are similar, and will not be elaborated here.

[0242] For example, one of the first control terminal G11 of the first output unit 31 and the first control terminal G21 of the second output unit 32 can be connected to the output terminal of the stage transmission module 20, the first control terminal G11 of the first output unit 31, and the control terminal of the fourth output unit 21; the other of the first control terminal G11 of the first output unit 31 and the first control terminal G21 of the second output unit 32 can be connected to the output terminal of the stage transmission module 20, the first control terminal G11 of the first output unit 31, and the control terminal of the fourth output unit 21.

[0243] For example, one of the first control terminal G11 of the first output unit 31 and the first control terminal G21 of the second output unit 32 can be connected to the output terminal of the stage transmission module 20 and the control terminal of the fourth output unit 21, and the other of the first control terminal G11 of the first output unit 31 and the first control terminal G21 of the second output unit 32 can be connected to the output terminal of the stage transmission module 20 and the control terminal of the fourth output unit 21.

[0244] Figure 11 This is a schematic diagram of another shift register provided in an embodiment of this application. Figure 12a A timing waveform diagram of another shift register provided in an embodiment of this application. For example, see... Figure 11 and Figure 12a The effective level pulses of P1, P2, P3, P4, and P5 can be high-level pulses, and the effective level pulse of P6 can be a low-level pulse. The first terminal of the third output unit 33 is connected to the first potential signal V1, which can be, for example, a low-level VGL. The first terminal of the fourth output unit 21 is connected to the second potential signal V2, which can be, for example, a high-level VGH. The first terminal of the fifth output unit 22 is connected to the first potential signal V1, which can be a low-level VGL. The first terminal of the fourth output unit 21 is connected to the second potential signal V2, which can be, for example, a high-level VGH. Figure 11 The output terminal of the intermediate transmission output module 20 and the second output terminal CW2 of the control module 10 are both at a high level and at a low level. The potentials of the second output terminal CW2 of the control module 10 and the output terminal of the intermediate transmission output module 20 are different. When one is at a high level, the other is at a low level.

[0245] Figure 12b This is a schematic diagram of another shift register provided in an embodiment of this application. Figure 12c This is a schematic diagram of another shift register provided in an embodiment of this application. Figure 12d This is a schematic diagram of another shift register provided in an embodiment of this application. Figure 12e A schematic diagram of another shift register provided in an embodiment of this application. For example, see... Figures 11 to 12eThe control terminal of the third output unit 33 is connected to one or more of the output terminal of the stage transmission module 20, the second output terminal CW2 of the control module 10, and the control terminal of the fifth output unit 22. Alternatively, one or more of the first output terminal CW1 of the control module 10 and the control terminal of the fourth output unit 21 are connected to the input terminal of the inverter 34 (which may be the third inverter), and the output terminal of the inverter 34 (which may be the third inverter) is connected to the control terminal of the third output unit 33.

[0246] For example, see Figures 11 to 12e One or more of the output terminal of the transmission module 20, the second output terminal CW2 of the control module 10, and the control terminal of the fifth output unit 22 are connected to the input terminal of the inverter 34 (which may be the first inverter). The output terminal of the inverter 34 (which may be the first inverter) is connected to the first control terminal G11 of the first output unit 31. Alternatively, one or more of the first output terminal CW1 of the control module 10 and the control terminal of the fourth output unit 21 are connected to the first control terminal G11 of the first output unit 31.

[0247] For example, see Figures 11 to 12e One or more of the output terminal of the transmission module 20, the second output terminal CW2 of the control module 10, and the control terminal of the fifth output unit 22 are connected to the input terminal of the inverter 34 (which may be the second inverter). The output terminal of the inverter 34 (which may be the second inverter) is connected to the first control terminal G21 of the second output unit 32. Alternatively, one or more of the first output terminal CW1 of the control module 10 and the control terminal of the fourth output unit 21 are connected to the first control terminal G21 of the second output unit 32.

[0248] For example, see Figure 11 The control module 10 may include transistors T8 to T16.

[0249] The structure of the control module 10, which matches the level transmission output module 20, can be configured as needed, but this application embodiment does not limit this.

[0250] For example, the effective level and the ineffective level of the same signal are both high and low.

[0251] For example, at least some (e.g., at least two) of the signals may have an effective level of high, and / or, at least some (e.g., at least two) of the signals may have an effective level of low. For example, at least some (e.g., at least two) of the signals may have the same effective level, and / or, at least some (e.g., at least two) of the signals may have different effective levels. The channel type of the transistor (e.g., P-type or N-type) and the corresponding effective level type of the signal (e.g., high or low) can be set as needed.

[0252] This application provides a gate driving circuit. Figure 13 This is a schematic diagram of a gate driving circuit provided in an embodiment of this application. The gate driving circuit 400 includes multiple cascaded shift registers 401 provided in the embodiments of this application, possessing the beneficial effects of the shift registers 401 in any embodiment of this application, which will not be repeated here. This embodiment can be combined with some or all of the features in the above embodiments, which will not be repeated here.

[0253] Figure 14 A timing waveform diagram of a gate drive circuit provided in an embodiment of this application. For example, see... Figure 13 and Figure 14 Within a corresponding first cycle Tc1 (e.g., the cycle of the first clock signal SCK1 or the cycle of the third clock signal SCK3), at the end of the output of the driver output module 30 of the i-th stage (e.g., the first stage) shift register 401, at least two (e.g., k) valid level pulses (e.g., P11, P12) are output at the output of the driver output module 30 of the (i+1)-th stage (e.g., the second stage) shift register, and before the start of the output of the driver output module 30 of the (i+1)-th stage (e.g., the second stage) shift register. Here, i is an integer greater than or equal to 1. That is, within a corresponding first cycle Tc1, after the output of the driver output module 30 of the i-th stage shift register 401, at least two (e.g., k) valid level pulses are output at the output of the driver output module 30 of the (i+1)-th stage shift register.

[0254] For example, within a corresponding first cycle Tc1, the end time when the output terminal Sout of the drive output module 30 of the i-th stage (e.g., the first stage) shift register 401 outputs all (e.g., k) valid level pulses is before the start time when the output terminal of the drive output module 30 of the i+1-th stage (e.g., the second stage) outputs all (e.g., k) valid level pulses (e.g., P21, P22).

[0255] Figure 15 A timing waveform diagram of another gate drive circuit provided in an embodiment of this application. For example, see... Figure 14 or Figure 15Within a corresponding first cycle Tc1, the time interval D2 between the end of the output Sout of the drive output module 30 of the i-th stage shift register 401 completely outputting at least two (e.g., k) valid level pulses and the start of the output Sout of the drive output module 30 of the (i+1)-th stage shift register 401 starting to output at least two (e.g., k) valid level pulses is different from the time interval D1 between adjacent valid level pulses output by the output Sout of the drive output module 30 of the i-th stage shift register 401. That is, the interval between pulses output by adjacent shift registers 401 is not completely equal, meaning the output pulses are not of equal phase.

[0256] Figure 15 The output pulses of the first to fourth stage shift registers 401, Sout_1 to Sout_4, are illustrated as an example.

[0257] For example, at least two Class I clock signals include a first clock signal SCK1 and a second clock signal SCK2.

[0258] In the i-th stage shift register 401, the input terminal of the first clock signal SCK1 of the drive output module 30 is connected to the first clock line L1, and the input terminal of the second clock signal SCK2 of the drive output module 30 is connected to the second clock line L2. That is, the first clock line L1 provides the first clock signal SCK1 to the i-th stage shift register 401, and the second clock line L2 provides the second clock signal SCK2 to the i-th stage shift register 401.

[0259] In the (i+1)th stage shift register 401, the input terminal of the first clock signal SCK1 of the drive output module 30 is connected to the third clock line L3, and the input terminal of the second clock signal SCK2 of the drive output module 30 is connected to the fourth clock line L4. That is, the third clock line L3 provides the first clock signal SCK1 to the (i+1)th stage shift register 401, and the fourth clock line L4 provides the second clock signal SCK2 to the (i+1)th stage shift register.

[0260] For example, within a corresponding first cycle Tc1, the phases of the effective level pulses (e.g., P41, P51, P42, P52) of the signals on the first clock line L1, the second clock line L2, the third clock line L3, and the fourth clock line L4 are sequentially delayed.

[0261] For example, within a corresponding first cycle Tc1, the effective level pulses (e.g., P41, P51, P42, P52) of any two of the signals from the first clock line L1, the second clock line L2, the third clock line L3, and the fourth clock line L4 do not overlap.

[0262] For example, within a corresponding first cycle Tc1, the phase difference between the effective level pulses (e.g., P41, P51) of the signals on the first clock line L1 and the second clock line L2 is different from the phase difference between the effective level pulses (e.g., P51, P42) of the signals on the second clock line L2 and the third clock line L3. That is, the time interval D1 between the effective level pulses (e.g., P41, P51) of the signals on the first clock line L1 and the second clock line L2 is different from the time interval D2 between the effective level pulses (e.g., P51, P42) of the signals on the second clock line L2 and the third clock line L3.

[0263] For example, within a corresponding first cycle Tc1, the phase difference between the effective level pulses (e.g., P41, P51) of the signals on the first clock line L1 and the second clock line L2 is equal to the phase difference between the effective level pulses (e.g., P42, P52) of the signals on the third clock line L3 and the fourth clock line L4. That is, the time interval D1 between the effective level pulses (e.g., P41, P51) of the signals on the first clock line L1 and the second clock line L2 is equal to the time interval D1 between the effective level pulses (e.g., P42, P52) of the signals on the third clock line L3 and the fourth clock line L4.

[0264] For example, the first clock signal SCK1 (e.g., SCK1_1) of the i-th stage (e.g., the first stage) shift register 401 has the same frequency but opposite phase as the first clock signal SCK1 (e.g., SCK1_2) of the (i+1)-th stage (e.g., the second stage) shift register 401. And / or, the signal on the first clock line L1 (e.g., SCK1_1) and the signal on the third clock line L3 (e.g., SCK1_2) have the same frequency but opposite phase.

[0265] For example, the second clock signal SCK2 (e.g., SCK2_1) of the i-th stage (e.g., the first stage) shift register 401 has the same frequency but opposite phase as the second clock signal SCK2 (e.g., SCK2_2) of the (i+1)-th stage (e.g., the first stage) shift register 401. And / or, the signal on the second clock line L2 (e.g., SCK2_1) and the signal on the fourth clock line L4 (e.g., SCK2_2) have the same frequency but opposite phase.

[0266] For example, in the i-th stage (e.g., the first stage) shift register 401, the input terminal of the third clock signal SCK3 (e.g., SCK3_1) of the stage output module 20 is connected to the fifth clock line L5. That is, the fifth clock line L5 provides the third clock signal SCK3 to the i-th stage shift register 401.

[0267] In the (i+1)th stage (e.g., the second stage) shift register 401, the input terminal of the third clock signal SCK3 (e.g., SCK3_2) of the stage output module 20 is connected to the sixth clock line L6. That is, the sixth clock line L6 provides the third clock signal SCK3 to the (i+1)th stage shift register 401.

[0268] For example, in the i-th stage (e.g., the first stage) shift register 401, the input terminal of the fourth clock signal SCK4 (e.g., SCK4_1) of the control module 10 is connected to the sixth clock line L6. That is, the sixth clock line L6 provides the fourth clock signal SCK4 to the i-th stage shift register 401.

[0269] In the (i+1)th stage (e.g., the second stage) shift register 401, the input terminal of the fourth clock signal SCK4 (e.g., SCK4_2) of the control module 10 is connected to the fifth clock line L5. That is, the fifth clock line L5 provides the fourth clock signal SCK4 to the (i+1)th stage shift register 401.

[0270] For example, the second control terminal (accessible to the first control signal SW1) of the first output unit 31 in the i-th stage (e.g., the first stage) shift register 401 is connected to the seventh clock line L7, and the second control terminal (accessible to the first control signal SW1) of the first output unit 31 in the (i+1)-th stage (e.g., the second stage) shift register 401 is also connected to the seventh clock line L7. The seventh clock line L7 can provide (accessible to the first control signal SW1).

[0271] For example, the second control terminal (which can be connected to the second control signal SW2) of the second output unit 32 in the i-th stage (e.g., the first stage) shift register 401 is connected to the eighth clock line L8. The second control terminal (which can be connected to the second control signal SW2) of the second output unit 32 in the (i+1)-th stage (e.g., the second stage) shift register 401 is also connected to the eighth clock line L8. The eighth clock line L8 can provide the second control signal SW2.

[0272] For example, i is an odd number.

[0273] In some embodiments, i is an even number.

[0274] For example, the input signal SIN_1 of the first-stage shift register 401 is provided through the start signal line L0.

[0275] For example, the stage pass signal Carry of the i-th stage shift register 401 is used as the input signal SIN of the (i+1)-th stage shift register 401.

[0276] This application provides a display panel. Figure 16This is a schematic diagram of a display panel provided in an embodiment of this application. The display panel 300 includes the gate driving circuit 400 provided in any of the above embodiments, and possesses the beneficial effects of the gate driving circuit 400 in any of the embodiments of this application, which will not be repeated here. This embodiment can be combined with some or all of the features in the above embodiments, which will not be repeated here.

[0277] For example, the display panel 300 may include a display area 301 and a non-display area 302. The gate driving circuit 400 may be located in the non-display area 302.

[0278] For example, the display panel 300 may include pixel circuitry 200, which may be located in the display area 301.

[0279] For example, the display panel includes a plurality of pixel circuits 200 arranged in an array. For example, each column of pixel circuits 200 includes a plurality of pixel circuits 200 arranged along a second direction Y.

[0280] For example, the multiple rows of pixel circuits 200 are arranged along the second direction Y. For example, each row of pixel circuits 200 includes a plurality of pixel circuits 200 arranged along the first direction X.

[0281] Optionally, the display panel 300 includes gate lines, and the pixel circuit 200 is connected to the gate lines, which extend along a first direction X. For example, multiple gate lines are arranged along a second direction Y. The first direction X and the second direction Y intersect, for example, perpendicularly. For example, multiple data lines may extend along the second direction Y and be arranged along the first direction X. The gate driving circuit 400 is connected to the pixel circuit 200 through the gate lines.

[0282] This application provides a driving method. This driving method can be applied to the shift register 401 or the gate driving circuit 400 provided in this application. The driving method includes: In step S110, the drive output module 30 is connected to at least two first-type clock signals, and each output terminal of at least one output terminal of the drive output module 30 outputs at least two valid level pulses corresponding to the valid level pulses of the at least two first-type clock signals.

[0283] The driving method of this application embodiment can be applied to the shift register 401 provided in this application embodiment, the gate driving circuit 400 of any embodiment of this application, or the display panel 300 of any embodiment of this application, and has the beneficial effects of the shift register 401 or the gate driving circuit 400 of any embodiment of this application, which will not be described again here. This embodiment can be combined with some or all of the features in the above embodiments, which will not be described again here.

[0284] For example, the driving method further includes: after the output terminal Sout of the driving output module 30 of the i-th stage shift register 401 outputs k valid level pulses in a corresponding first cycle Tc1, the output terminal of the driving output module 30 of the i+1 stage shift register outputs k valid level pulses.

[0285] For example, the driving method further includes: within a corresponding first cycle Tc1, the time interval D2 between the end time of the output terminal Sout of the i-th stage shift register 401's driving output module 30 outputting the last valid level pulse and the start time of the output terminal Sout of the (i+1)-th stage shift register 401's driving output module 30 starting to output the first valid level pulse is different from the time interval D1 between adjacent valid level pulses among the at least two (e.g., k) valid level pulses output by the output terminal Sout of the i-th stage shift register 401's driving output module 30.

[0286] Figure 17 This is a schematic diagram of a display device provided in an embodiment of this application. This application also provides a display device 1, including the display panel 300 provided in any embodiment of this application.

[0287] For example, the display device includes a photosensitive element and a display panel provided in any embodiment of this application. The photosensitive element is used to receive light transmitted through the light-transmitting area. The photosensitive element may include one or more of a camera, a fingerprint recognition module, an ambient light sensor, an infrared sensor, etc.

[0288] Display devices include, but are not limited to, mobile phones, personal digital assistants (PDAs), tablets, e-books, televisions, access control systems, smart landlines, consoles, laptops, wearable devices, in-vehicle displays, virtual reality (VR) and augmented reality (AR) and other near-eye display devices with display functions.

[0289] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0290] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0291] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A shift register, characterized in that, include: Control module, stage output module, and drive output module; The control module is connected to the stage transmission output module, and at least one of the control module and the stage transmission output module is connected to the drive output module. The control module is used to control the output of the stage transmission module to output the stage transmission signal. The drive output module is connected to at least two first-type clock signals, and the same output terminal of the drive output module outputs at least two valid level pulses corresponding to the valid level pulses of the at least two first-type clock signals.

2. The shift register according to claim 1, characterized in that, The drive output module includes a first output unit and a second output unit, and the at least two first-type clock signals include a first clock signal and a second clock signal. The first terminal of the first output unit is connected to the first clock signal, the second terminal of the first output unit is connected to the output terminal of the drive output module, and the first control terminal of the first output unit is connected to at least one of the control module and the stage transmission output module. The first terminal of the second output unit is connected to the second clock signal, the second terminal of the second output unit is connected to the output terminal of the drive output module, and the first control terminal of the second output unit is connected to at least one of the control module and the stage transmission output module. The first output unit is used to output a first valid level pulse corresponding to the valid level pulse of the first clock signal to the output terminal of the drive output module; The second output unit is used to output a second valid level pulse corresponding to the valid level pulse of the second clock signal to the output terminal of the drive output module; The first valid level pulse occurs before or after the second valid level pulse; Preferably, the first clock signal and the second clock signal have the same frequency but different phases; Preferably, the effective level pulses of the first clock signal and the effective level pulses of the second clock signal do not overlap; Preferably, the effective level pulse of the cascaded signal overlaps with the first effective level pulse; The effective level pulse of the staged transmission signal overlaps with the second effective level pulse; Preferably, adjacent first effective level pulses and second effective level pulses overlap with the same effective level pulse of the transmission signal; Preferably, the time interval between adjacent first valid level pulses and second valid level pulses is less than half the period of the first clock signal; Preferably, the width of the first effective level pulse is the same as the width of the effective level pulse of the first clock signal; The width of the second valid level pulse is the same as the width of the valid level pulse of the second clock signal.

3. The shift register according to claim 2, characterized in that, The first output unit includes a first transistor and a second transistor. The first transistor and the second transistor are connected in series between the first terminal and the second terminal of the first output unit, and the gate of the first transistor serves as the first control terminal of the first output unit. The second output unit includes a third transistor and a fourth transistor. The third transistor and the fourth transistor are connected in series between the first terminal and the second terminal of the second output unit, and the gate of the third transistor serves as the first control terminal of the second output unit. During the period when the first valid level pulse is output at the output terminal of the drive output module, the first transistor and the second transistor are turned on, and the fourth transistor is turned off; During the period when the second valid level pulse is output at the output terminal of the drive output module, the third transistor and the fourth transistor are turned on, and the second transistor is turned off; Preferably, the gate of the second transistor serves as the second control terminal of the first output unit, and the gate of the fourth transistor serves as the second control terminal of the second output unit. And / or, the second control terminal of the first output unit is connected to the first control signal, and the second control terminal of the second output unit is connected to the second control signal. The first control signal and the second control signal are clock signals, and the first control signal and the second control signal have the same frequency but different phases; Preferably, the effective level pulse of the first control signal overlaps with the first effective level pulse; And / or, the effective level pulse of the second control signal overlaps with the second effective level pulse; Preferably, the width of the effective level pulse of the first control signal is greater than the width of the first effective level pulse; And / or, the width of the effective level pulse of the second control signal is greater than the width of the second effective level pulse; Preferably, the effective level pulse of the first control signal overlaps with the effective level pulse of the first clock signal; And / or, the effective level pulse of the second control signal overlaps with the effective level pulse of the second clock signal; Preferably, the frequency of the first control signal is greater than the frequency of the first clock signal; Preferably, the frequency of the first control signal is twice the frequency of the first clock signal; Preferably, the effective level pulse of the first control signal is the turn-on pulse of the second transistor; The effective level pulse of the second control signal is the turn-on pulse of the fourth transistor; Preferably, the width of the effective level pulse of the first control signal is greater than half the period of the first control signal; Preferably, the first control terminal of the first output unit is connected to the first control terminal of the second output unit; Preferably, the first terminal of the first transistor is connected to the first terminal of the first output unit, and the second terminal of the first transistor is connected to the second terminal of the first output unit via the second transistor; The first terminal of the third transistor is connected to the first terminal of the second output unit, and the second terminal of the third transistor is connected to the second terminal of the second output unit via the fourth transistor. Preferably, the second transistor includes a P-type transistor, and the low level of the first control signal is lower than the low level of the first clock signal; preferably, the absolute value of the difference between the low level of the first control signal and the low level of the first clock signal is greater than the absolute value of the threshold voltage of the second transistor. Alternatively, the second transistor may include an N-type transistor, wherein the high level of the first control signal is higher than the high level of the first clock signal, and preferably, the difference between the high level of the first control signal and the high level of the first clock signal is greater than the absolute value of the threshold voltage of the second transistor. Preferably, the drive output module further includes a third output unit. The first terminal of the third output unit is connected to the first potential signal, the second terminal of the third output unit is connected to the output terminal of the drive output module, and the control terminal of the third output unit is connected to at least one of the control module and the stage transmission output module. Preferably, the third output unit is turned off during the period when the first valid level pulse is output at the output terminal of the drive output module, and / or during the period when the second valid level pulse is output at the output terminal of the drive output module; Preferably, the third output unit includes a fifth transistor, the first terminal of the fifth transistor is connected to the first terminal of the third output unit, the second terminal of the fifth transistor is connected to the second terminal of the third output unit, and the gate of the fifth transistor is connected to the control terminal of the third output unit; The effective level of the effective level pulse output by the output terminal of the drive output module and the first potential signal are both either high or low. Preferably, the effective level of the effective level pulse output by the output terminal of the drive output module is low.

4. The shift register according to claim 3, characterized in that, The stage transmission output module includes a fourth output unit. The first terminal of the fourth output unit is connected to the third clock signal, the second terminal of the fourth output unit is connected to the output terminal of the stage transmission output module, and the control terminal of the fourth output unit is connected to the first output terminal of the control module. Preferably, the effective level pulse of the transmission signal overlaps with the effective level pulse of the third clock signal; Preferably, the first valid level pulse overlaps with the valid level pulse of the third clock signal; Preferably, the second valid level pulse overlaps with the valid level pulse of the third clock signal; Preferably, the first output terminal of the control module, the control terminal of the fourth output unit, or the output terminal of the stage transmission module is connected to the first control terminal of the first output unit. The first output terminal of the control module, the control terminal of the fourth output unit, or the output terminal of the stage transmission module is connected to the first control terminal of the second output unit. The second output terminal of the control module is connected to the control terminal of the third output unit; Preferably, the fourth output unit includes a sixth transistor, the first terminal of the sixth transistor is connected to the first terminal of the fourth output unit, the second terminal of the sixth transistor is connected to the second terminal of the fourth output unit, and the gate of the sixth transistor is connected to the control terminal of the fourth output unit; Preferably, the first transistor, the third transistor, and the sixth transistor have the same switching state; Preferably, the stage transmission output module further includes a fifth output unit. The first terminal of the fifth output unit is connected to the first potential signal, the second terminal of the fifth output unit is connected to the output terminal of the stage transmission output module, and the control terminal of the fifth output unit is connected to the second output terminal of the control module. Preferably, the control terminal of the third output unit is connected to the control terminal of the fifth output unit, and the switching states of the third output unit and the fifth output unit are the same; Preferably, the fifth output unit includes a seventh transistor, the first terminal of the seventh transistor is connected to the first terminal of the fifth output unit, the second terminal of the seventh transistor is connected to the second terminal of the fifth output unit, and the gate of the seventh transistor is connected to the control terminal of the fifth output unit; Preferably, the shift register further includes a first capacitor, which is connected between the second terminal of the fourth output unit and the control terminal; And / or, the shift register further includes a second capacitor connected between the first terminal and the control terminal of the fifth output unit; Preferably, the shift register further includes a protection module, and the first output terminal of the control module is connected to the stage output module via the protection module; Preferably, the protection module includes a thirteenth transistor, the first output terminal of the control module is connected to the control terminal of the fourth output unit via the thirteenth transistor, and the gate of the thirteenth transistor is connected to a second potential signal; One of the first potential signal and the second potential signal is at a high level, and the other is at a low level; Preferably, the first potential signal is at a high level and the second potential signal is at a low level.

5. The shift register according to claim 1, characterized in that, The width of the effective level pulse of the stage transmission signal is greater than the width of the effective level pulse of the first type of clock signal; and / or, at least one of the control module and the stage transmission output module is connected to a second type of clock signal, the width of the effective level pulse of the second type of clock signal is greater than the width of the effective level pulse of the first type of clock signal; Preferably, the frequency of the first type of clock signal is the same as the frequency of the second type of clock signal; Preferably, the width of the effective level pulse of the second type of clock signal is greater than the sum of the widths of the effective level pulses of the at least two first type of clock signals; and / or, at least one effective level pulse of the second type of clock signal overlaps with the effective level pulses of the at least two first type of clock signals; and / or, the width of the effective level pulse of the cascaded signal is greater than the sum of the widths of the effective level pulses of the at least two first type of clock signals; and / or, the effective level pulse of the cascaded signal overlaps with the effective level pulses of the at least two first type of clock signals. Preferably, in the at least two valid level pulses output by the output terminal of the drive output module that correspond to the valid level pulses of the at least two first-type clock signals, the time interval between adjacent valid level pulses is less than half the period of the first-type clock signal; Preferably, the width of the effective level pulse of the first type of clock signal is less than half the period of the first type of clock signal; Preferably, the width of the effective level pulse of the second type of clock signal is less than half the period of the second type of clock signal; Preferably, the at least two first-type clock signals include a first clock signal and a second clock signal with the same frequency but different phases. The drive output module is used to output, in a time-division manner, a first effective level pulse that overlaps with the effective level pulse of the first clock signal and a second effective level pulse that overlaps with the effective level pulse of the second clock signal; Preferably, the effective level pulse of the transmission signal overlaps with the effective level pulse of the first clock signal; The effective level pulse of the transmission signal overlaps with the effective level pulse of the second clock signal; The effective level pulse of the transmission signal overlaps with the first effective level pulse; The effective level pulse of the staged transmission signal overlaps with the second effective level pulse; Preferably, the second type of clock signal includes a third clock signal, and at least one of the control module and the stage transmission output module is connected to the third clock signal. The width of the effective level pulse of the third clock signal is greater than the sum of the width of the effective level pulse of the first clock signal and the width of the effective level pulse of the second clock signal; Preferably, the effective level pulse of the first clock signal overlaps with the effective level pulse of the third clock signal; The effective level pulse of the second clock signal overlaps with the effective level pulse of the third clock signal; Preferably, the effective level pulses of the first clock signal and the effective level pulses of the second clock signal do not overlap; Preferably, the effective level pulses of adjacent first clock signals and second clock signals overlap with the same effective level pulse of the third clock signal; Preferably, the time interval between adjacent effective level pulses of the first clock signal and the second clock signal is less than half the period of the third clock signal; Preferably, the frequency of the first clock signal is equal to the frequency of the third clock signal.

6. The shift register according to claim 1, characterized in that, The control module includes an input unit, a first control terminal, and a second control unit. The input unit is used to control the third control signal output by the first output terminal of the control module according to the input signal and the fourth clock signal; The first control unit is used to control the fourth control signal output by the second output terminal of the control module according to the fourth clock signal and the third control signal; The second control unit is used to control the third control signal output by the first output terminal of the control module according to the third clock signal and the fourth control signal; Preferably, the input unit includes an eighth transistor, the first terminal of which is connected to the input signal, and the second terminal of which is connected to the first output terminal of the control module; the gate of the eighth transistor is connected to the fourth clock signal. The first control unit includes a ninth transistor and a tenth transistor. The first terminal of the ninth transistor is connected to the fourth clock signal, the second terminal of the ninth transistor is connected to the second output terminal of the control module, and the gate of the ninth transistor is connected to the first output terminal of the control module. The first terminal of the tenth transistor is connected to a second potential signal, the second terminal of the tenth transistor is connected to the second output terminal of the control module, and the gate of the tenth transistor is connected to the fourth clock signal. The second control unit includes an eleventh transistor and a twelfth transistor. The second terminals of the eleventh transistor and the twelfth transistor are connected. One of the first terminals of the eleventh transistor and the twelfth transistor is connected to the first output terminal of the control module, and the other is connected to a first potential signal. One of the gates of the eleventh transistor and the twelfth transistor is connected to the second output terminal of the control module, and the other is connected to the third clock signal. One of the first potential signal and the second potential signal is at a high level, and the other is at a low level; Preferably, the third clock signal and the fourth clock signal have the same frequency but different phases; Preferably, the third clock signal and the fourth clock signal are out of phase.

7. A gate driving circuit, characterized in that, This includes multiple cascaded shift registers as described in any one of claims 1-6.

8. The gate driving circuit according to claim 7, characterized in that, The stage-transmitted signal of the shift register of stage i is used as the input signal of the shift register of stage i+1; where i is an integer greater than or equal to 1; Preferably, the end time of the output of at least two valid level pulses at the output terminal of the drive output module of the i-th stage shift register is before the start time of the output of at least two valid level pulses at the output terminal of the drive output module of the (i+1)-th stage shift register. Preferably, the time interval between the end time when the output terminal of the drive output module of the i-th stage shift register fully outputs at least two valid level pulses and the start time when the output terminal of the drive output module of the (i+1)-th stage shift register begins to output at least two valid level pulses is different from the time interval between adjacent valid level pulses in the at least two valid level pulses output by the output terminal of the drive output module of the i-th stage shift register. Preferably, the at least two first-type clock signals include a first clock signal and a second clock signal with the same frequency but different phases; In the i-th stage shift register, the input terminal of the first clock signal of the drive output module is connected to the first clock line, and the input terminal of the second clock signal of the drive output module is connected to the second clock line. In the (i+1)th level shift register, the input terminal of the first clock signal of the drive output module is connected to the third clock line, and the input terminal of the second clock signal of the drive output module is connected to the fourth clock line. Preferably, the phases of the effective level pulses of the signals on the first clock line, the second clock line, the third clock line, and the fourth clock line are sequentially delayed; The effective level pulses of the signals of any two of the first clock line, the second clock line, the third clock line, and the fourth clock line do not overlap; Preferably, the phase difference of the effective level pulses of the signals on the first clock line and the second clock line is different from the phase difference of the effective level pulses of the signals on the second clock line and the third clock line; the phase difference of the effective level pulses of the signals on the first clock line and the second clock line is equal to the phase difference of the effective level pulses of the signals on the third clock line and the fourth clock line; preferably, the first clock signal of the i-th stage shift register and the first clock signal of the (i+1)-th stage shift register have the same frequency but opposite phase; and / or, the signals on the first clock line and the signals on the third clock line have the same frequency but opposite phase. Preferably, the second clock signal of the i-th stage shift register has the same frequency and opposite phase as the second clock signal of the (i+1)-th stage shift register; and / or, the signal on the second clock line has the same frequency and opposite phase as the signal on the fourth clock line; Preferably, in the i-th stage shift register, the input terminal of the third clock signal of the stage output module is connected to the fifth clock line. In the (i+1)th stage shift register, the input terminal of the third clock signal of the stage output module is connected to the sixth clock line. Preferably, in the i-th stage shift register, the input terminal of the fourth clock signal of the control module is connected to the sixth clock line. In the (i+1)th level shift register, the input terminal of the fourth clock signal of the control module is connected to the fifth clock line; Preferably, the second control terminal of the first output unit in the i-th stage shift register is connected to the seventh clock line, the second control terminal of the first output unit in the (i+1)-th stage shift register is connected to the seventh clock line, the second control terminal of the second output unit in the i-th stage shift register is connected to the eighth clock line; and the second control terminal of the second output unit in the (i+1)-th stage shift register is connected to the eighth clock line. Preferably, i is an odd number.

9. A display panel, characterized in that, Includes the gate drive circuit as described in claim 7 or 8.

10. A driving method, characterized in that, Applied to a shift register as described in any one of claims 1-6 or a gate drive circuit as described in claim 7 or 8, the driving method includes: The drive output module is connected to at least two first-type clock signals, and each output terminal of at least one of the drive output modules outputs at least two valid level pulses corresponding to the valid level pulses of the at least two first-type clock signals.

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