Pixel circuit, driving method and display panel

Abstract

The application relates to the technical field of display, and particularly provides a pixel circuit and a driving method and a display panel. The pixel circuit comprises a light emitting device, one end of the light emitting device is electrically connected with an anode voltage end, and the other end of the light emitting device is electrically connected with a cathode voltage end. The pixel circuit comprises a reset stage, a data collection stage and a light emitting stage arranged in sequence. In the data collection stage of the pixel circuit, the anode voltage end is in a high resistance state and / or the cathode voltage end is in a high voltage state. According to the application, the anode voltage end is set to the high resistance state and / or the cathode voltage end is set to the high voltage state in the data collection stage, threshold voltage compensation function is realized, an additional compensation transistor is not needed, the pixel circuit structure is simplified, and the advantages of improving the pixel density and reducing the frame of the display panel are achieved.

Description

Technical Field

[0001] This application belongs to the field of display technology, and more specifically, relates to a pixel circuit and driving method, and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) display technology is considered the most promising next-generation display technology. Compared with liquid crystal display technology, OLED display technology has advantages such as low energy consumption, low cost, self-illumination, wide viewing angle, and fast response speed.

[0003] Traditional OLED display devices have a large number of components in their pixel circuits, resulting in a low pixel density (Pixels Per Inch, PPI). Therefore, the manufacturing process performance of current OLED display panels needs improvement. Summary of the Invention

[0004] This application provides a pixel circuit and driving method, and a display panel, to improve the process performance of the display panel to at least a certain extent.

[0005] To achieve the above objectives, the technical solution adopted in this application is as follows: In a first aspect, this application provides a pixel circuit, comprising: A light-emitting device, wherein one end of the light-emitting device is electrically connected to an anode voltage terminal and the other end of the light-emitting device is electrically connected to a cathode voltage terminal; The pixel circuit includes a reset stage, a data acquisition stage, and a light emission stage arranged sequentially. During the data acquisition stage of the pixel circuit, the anode voltage terminal is in a high-resistance state and / or the cathode voltage terminal is in a high-voltage state.

[0006] In some embodiments of this application, the pixel circuit further includes: A first switching element, one end of which is electrically connected to the anode voltage terminal, and the other end of which is electrically connected to the light-emitting device, is used to conduct during the light-emitting phase to drive the light-emitting device to emit light; The second switch has one end electrically connected to the data signal terminal and the other end connected between the first switch and the anode voltage terminal. The second switch is used to turn on during the data acquisition phase to output a data signal to the first switch. A third switching element, one end of which is electrically connected to the control electrode of the first switching element, and the other end of which is connected between the first switching element and the light-emitting device; During the data acquisition phase, the first switching element is activated based on the data signal. The third switch is used to output a voltage compensation signal when the first switch acquires the data signal; During the light-emitting phase, the first switching element is turned on based on the voltage difference between the voltage compensation signal and the anode voltage signal at the anode voltage terminal.

[0007] In some embodiments of this application, the pixel circuit further includes a storage capacitor, one end of which is electrically connected to the anode voltage terminal, and the other end of which is electrically connected to the control electrode of the first switching element. The storage capacitor is used to store the voltage compensation signal during the data acquisition phase and to output the voltage compensation signal to the control electrode of the first switching element during the light emission phase.

[0008] In some embodiments of this application, the pixel circuit further includes a fourth switch, one end of which is electrically connected to an initialization voltage terminal, and the other end of which is electrically connected to the control electrode of a first switch. During the reset phase, the fourth switch is used to write the initialization voltage signal of the initialization voltage terminal to the control electrode of the first switch to reset the control electrode of the first switch.

[0009] In some embodiments of this application, the pixel circuit is applied on a display panel, and the display panel includes multiple pixel rows; the control electrode of the fourth switch is connected to the first scan signal line, and the control electrodes of the second switch and the third switch are connected to the second scan signal line; The first scan signal line is the scan signal line corresponding to the current nth pixel row, and the second scan signal line is the scan signal line corresponding to the (n+1)th pixel row; Alternatively, the scanning signal on the first scanning signal line is the same global signal output by the display driver integrated circuit of the display panel to multiple pixel rows, and the second scanning signal line is the scanning signal line corresponding to the current pixel row.

[0010] In some embodiments of this application, during the reset phase, the fourth switch is turned on based on the scan signal of the first scan signal line, thereby resetting the control electrode of the first switch and / or the anode of the light-emitting device.

[0011] In some embodiments of this application, the pixel circuit further includes a fourth switch, one end of which is electrically connected to the initialization voltage terminal, and the other end of which is connected between the third switch and the first switch. During the reset phase, the fourth switch is used to write the initialization voltage signal of the initialization voltage terminal to the control electrode of the first switch through the third switch to reset the control electrode of the first switch.

[0012] In some embodiments of this application, the pixel circuit is applied on a display panel, and the display panel includes multiple pixel rows; the control electrode of the fourth switch is connected to the first scan signal line, the control electrode of the third switch is connected to the second scan signal line, and the control electrode of the second switch is connected to the third scan signal line. The first scan signal line is the scan signal line corresponding to the current nth pixel row, the second scan signal line is the scan signal line corresponding to the (n+1)th pixel row, and the third scan signal line is the scan signal line corresponding to the (n+2)th pixel row.

[0013] In some embodiments of this application, the pixel circuit further includes a fifth switch, which is connected in series with the first switch and the light-emitting device between the anode voltage terminal and the cathode voltage terminal; the control electrode of the fifth switch is electrically connected to the light-emitting control signal line, and the fifth switch is used to connect the anode voltage terminal, the first switch, the light-emitting device and the cathode voltage terminal when the light-emitting control signal line outputs a light-emitting control signal.

[0014] In some embodiments of this application, the pixel circuit is applied on a display panel, and the display panel includes multiple pixel circuits. The light emission control signal is the same global signal output by the display driver integrated circuit of the display panel to multiple pixel circuits.

[0015] In some embodiments of this application, at least one of the first switch, the second switch, the third switch, the fourth switch, and the fifth switch is any one of a thin-film transistor, a MOSFET, and a bipolar transistor.

[0016] In some embodiments of this application, under the high voltage state, the cathode voltage terminal outputs a preset high voltage, which is higher than the output voltage of the cathode voltage terminal during the light emission stage.

[0017] A second aspect of this application also provides a driving method for a pixel circuit, applied to the pixel circuit described above; the driving method for the pixel circuit includes: During the data acquisition phase between the reset phase and the light emission phase, the anode voltage terminal is set to a high-resistivity state and / or the cathode voltage terminal is set to a high-voltage state.

[0018] A third aspect of the embodiments of this application also provides a display panel, the display panel including the pixel circuits as described in the third description.

[0019] The beneficial effects of the pixel circuit, driving method, and display panel provided in this application are as follows: Compared with related technologies, the pixel circuit of this application includes a light-emitting device, one end of which is electrically connected to the anode voltage terminal, and the other end of which is electrically connected to the cathode voltage terminal; the pixel circuit includes a reset stage, a data acquisition stage, and a light-emitting stage arranged sequentially. In the data acquisition stage of the pixel circuit, the anode voltage terminal is in a high-resistivity state and / or the cathode voltage terminal is in a high-voltage state; this application achieves the threshold voltage compensation function by setting the anode voltage terminal to a high-resistivity state and / or the cathode voltage terminal to a high-voltage state in the data acquisition stage, without the need for additional compensation transistors, which has the advantages of simplifying the pixel circuit structure and improving pixel density and reducing the bezel of the display panel. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application, and therefore should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A schematic diagram of the pixel circuit provided in an optional embodiment of this application; Figure 2 A schematic diagram of the pixel circuit provided in an optional embodiment of this application; Figure 3 A schematic diagram of the pixel circuit provided in an optional embodiment of this application; Figure 4 A timing diagram of a pixel circuit provided for an optional embodiment of this application; Figure 5 A schematic diagram of the pixel circuit provided in an optional embodiment of this application; Figure 6 A timing diagram of the pixel circuit provided in an optional embodiment of this application; Figure 7 A schematic diagram of the pixel circuit provided in an optional embodiment of this application; Figure 8 A timing diagram of the pixel circuit provided in an optional embodiment of this application; Figure 9 A timing diagram of the pixel circuit provided in an optional embodiment of this application; Figure 10 This is a timing diagram of a pixel circuit provided in an optional embodiment of this application.

[0022] Component symbol explanation: Vdata - Data signal terminal, EM - Light emission control signal terminal, ELVDD - Anode voltage terminal, ELVSS - Cathode voltage terminal, VREFN - Initialization signal terminal. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0024] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0025] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0026] Furthermore, the terms "first," "second," and "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0027] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between components; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0028] In the AMOLED display technology field, the pixel circuit architecture design has a decisive impact on the performance of the display panel. The widely used 7T1C pixel circuit architecture, comprising seven thin-film transistors and one storage capacitor, faces significant challenges in addressing the trend towards higher pixel density and narrower bezels in display panels. Specifically, as pixel density continues to increase, the physical area of ​​each sub-pixel continues to shrink, while the layout area requirements of the seven thin-film transistors and their interconnections in the 7T1C architecture make circuit layout within the limited sub-pixel area extremely difficult. Furthermore, the 7T1C architecture requires scanning signal GIP circuits and light emission control signal GIP circuits on the left and right bezels of the display panel, respectively, making it difficult to further compress the bezel width. More critically, implementing threshold voltage compensation in existing architectures requires dedicated compensation transistors, further increasing circuit complexity and component count. These technological bottlenecks collectively constrain the development of AMOLED display panels towards higher pixel density and narrower bezels.

[0029] Without resolving the aforementioned technical challenges, AMOLED display panels will struggle to meet the market's ongoing demand for higher pixel densities and narrower bezels. Increased pixel density will be severely limited by physical layout design, hindering the achievement of desired display effects. Bezel width reduction will also be limited by the number of GIP circuits, impacting the appearance design and user experience of end products. Furthermore, the implementation of threshold voltage compensation relies on additional transistors, increasing manufacturing costs and potentially causing display uniformity issues, as variations in transistor parameters due to process variations directly affect the compensation effect. Increased complexity in drive control also leads to difficulties in signal timing coordination, potentially triggering display anomalies. The cumulative effect of these problems will severely restrict the further development of AMOLED display technology in high-end applications.

[0030] Based on this, this application improves the pixel circuit and driving method, and the display panel in the related technology. It should be noted that, in this document, T1 is the first switch, T2 is the second switch, T3 (T3_1 and T3_2) is the fourth switch, T4 (T4_1 and T4_2) is the fourth switch, and T5 is the fifth switch.

[0031] Please see Figure 1 The pixel circuit of this application embodiment includes a light-emitting device. One end of the light-emitting device is electrically connected to the anode voltage terminal ELVDD, and the other end of the light-emitting device is electrically connected to the cathode voltage terminal ELVSS. The pixel circuit includes a reset stage, a data acquisition stage, and a light-emitting stage arranged sequentially. In the data acquisition stage of the pixel circuit, the anode voltage terminal ELVDD is in a high-resistance state and / or the cathode voltage terminal ELVSS is in a high-voltage state.

[0032] It's important to explain that a pixel circuit refers to the electronic circuitry that makes up each individual pixel unit in a display panel. This circuit is responsible for receiving data signals and driving the light-emitting devices to produce the required brightness. In active matrix display technology, each pixel circuit operates independently, ensuring precise control and uniformity of the displayed content.

[0033] A light-emitting device is an electronic component that converts electrical energy into light energy. In AMOLED display panels, this light-emitting device is typically an organic light-emitting diode (OLED). The brightness of an OLED is directly related to the amount of current flowing through it; therefore, the pixel circuitry needs to precisely control the current flowing through the OLED.

[0034] The anode voltage terminal ELVDD is the power supply connection point that provides a forward bias voltage to the anode of the light-emitting device. In pixel circuits, this anode voltage terminal ELVDD is typically connected to a high-potential power supply to provide the operating voltage for the light-emitting device.

[0035] The cathode voltage terminal ELVSS is the power supply connection point that provides a negative bias voltage or ground reference to the cathode of the light-emitting device. In the pixel circuit, this cathode voltage terminal ELVSS is usually connected to a low-potential power supply or ground, and together with the anode voltage terminal ELVDD, it forms the driving circuit of the light-emitting device.

[0036] The reset phase refers to the stage at the beginning of each frame cycle when the pixel circuit initializes or clears residual charges from internal critical nodes (such as the gates of driving transistors). By resetting these nodes to a preset reference voltage, it is ensured that subsequent data acquisition and light emission processes start from a defined initial state, thereby improving display consistency and accuracy.

[0037] The data acquisition stage refers to the phase where the pixel circuit receives external data signals and adjusts the state of its internal driving components based on these signals. During this stage, the pixel circuit typically performs threshold voltage compensation to eliminate the influence of inherent differences in the driving transistors on the brightness of the light emitted, ensuring display uniformity.

[0038] The light-emitting stage refers to the phase in which the pixel circuit drives the light-emitting device to continuously emit light to display the image based on the acquired and compensated data signal. In this stage, a stable driving current flows through the light-emitting device, producing the required brightness.

[0039] A high-impedance state refers to a circuit node or signal line being in a floating state, exhibiting extremely high impedance to the outside world. In this state, the node or signal line can neither provide effective drive current nor absorb significant current; its potential is mainly determined by the charge accumulation or coupling effect of other circuit elements connected to it.

[0040] A high-voltage state refers to a power supply terminal whose voltage is set to a value much higher than its normal operating voltage. Taking the cathode voltage terminal ELVSS as an example, its voltage may be at a low potential or negative during normal light emission, while in a high-voltage state, its voltage will be boosted to a higher positive voltage to achieve a specific circuit function, such as preventing the light-emitting device from conducting.

[0041] Understandably, in related technologies, additional compensation transistors are typically introduced to achieve threshold voltage compensation for driving elements. For example, in a typical 7T1C pixel circuit, a dedicated compensation transistor is used to short-circuit the gate and drain of the driving transistor, forming a diode connection during the data writing phase. While effective, this method increases the number of transistors in the pixel circuit, thereby increasing the layout area of ​​each pixel unit and limiting further improvements in the pixel density (PPI) of the display panel.

[0042] The pixel circuit in this embodiment cleverly utilizes the operating mode of the power supply signal to replace the function of a traditional compensation transistor by setting the anode voltage terminal ELVDD to a high-impedance state and / or setting the cathode voltage terminal ELVSS to a high-voltage state during the data acquisition phase. For example, in the data acquisition phase of the above example, by placing the anode voltage terminal ELVDD in a high-impedance state or raising the cathode voltage terminal ELVSS to a high voltage, the light-emitting device is effectively isolated, and the current path between the source and drain of the driving element is limited, thereby allowing the driving element to naturally enter diode connection mode, and its control terminal potential is precisely charged to the sum of the data signal and the threshold voltage.

[0043] This allows pixel circuits to achieve the same or even better threshold voltage compensation effect as existing technologies without adding additional compensation transistors. For example, in the example above, this method effectively eliminates the threshold voltage difference of the driving elements, ensuring brightness uniformity among different pixels in the display panel. This method directly reduces the number of transistors required by the pixel circuit, providing a key architectural foundation for achieving display panels with higher pixel density (PPI). Simultaneously, the reduced component count also simplifies the design of panel bezel driving circuits (such as GIP circuits), thus facilitating the realization of narrow bezel displays.

[0044] Please continue reading. Figure 1This application further proposes a pixel circuit, which includes a first switch, a second switch, and a third switch. One end of the first switch is electrically connected to the anode voltage terminal ELVDD, and the other end is electrically connected to a light-emitting device. The first switch is turned on during the light-emitting phase to drive the light-emitting device to emit light. One end of the second switch is electrically connected to the data signal terminal Vdata, and the other end is connected between the first switch and the anode voltage terminal ELVDD. The second switch is turned on during the data acquisition phase to output a data signal to the first switch. One end of the third switch is electrically connected to the control electrode of the first switch, and the other end is connected between the first switch and the light-emitting device. During the data acquisition phase, the first switch is turned on based on the data signal, and the third switch is used to output a voltage compensation signal when the first switch acquires the data signal. During the light-emitting phase, the first switch is turned on based on the voltage difference between the voltage compensation signal and the anode voltage signal of the anode voltage terminal ELVDD.

[0045] It is understood that this embodiment introduces a first switch, a second switch, and a third switch, and utilizes the third switch to output a voltage compensation signal during the data acquisition phase. This enables the first switch to conduct during the light-emitting phase based on the voltage difference between the voltage compensation signal and the anode voltage signal. This compensation mechanism effectively eliminates or reduces the influence of the first switch's own characteristics (such as threshold voltage drift) on the driving current of the light-emitting device, thereby significantly improving the driving accuracy and consistency of the light-emitting device. This solves the problem of uneven brightness and degraded display quality in existing pixel circuits, ensuring the image quality and stability of the display panel.

[0046] Please continue reading. Figure 1 The embodiments of this application further propose that the pixel circuit also includes a storage capacitor, one end of which is electrically connected to the anode voltage terminal ELVDD, and the other end of which is electrically connected to the control electrode of the first switching element. The storage capacitor is used to store voltage compensation signals during the data acquisition stage and to output voltage compensation signals to the control electrode of the first switching element during the light emission stage.

[0047] It should be explained that a storage capacitor is a passive electronic component capable of storing electrical charge, and its charge storage capacity is determined by its capacitance value. The other end of the storage capacitor is electrically connected to the control electrode of the first switch. This connection allows the storage capacitor to directly apply the stored voltage signal to the control electrode of the first switch to precisely control its conduction state and current. The storage capacitor is used to store voltage compensation signals during the data acquisition phase. This means that during data acquisition, when a voltage compensation signal is generated, the storage capacitor can capture and maintain the voltage value of the signal, ensuring that the transient nature of the signal does not affect the driving of subsequent phases. The storage capacitor is also used to output voltage compensation signals to the control electrode of the first switch during the light-emitting phase. This function ensures that during the light-emitting phase, the storage capacitor can continuously and stably provide the previously stored voltage compensation signal to the control electrode of the first switch to maintain stable operation of the first switch.

[0048] It is understood that the present application's embodiments, by introducing a storage capacitor, make the driving mechanism of the pixel circuit more stable and accurate. During the data acquisition phase, the second switch is turned on, a data signal is input, and simultaneously, the first switch begins to conduct based on this data signal. At this time, the third switch, upon receiving the data signal from the first switch, generates and outputs a voltage compensation signal. This voltage compensation signal is captured and stored by the storage capacitor. One end of the storage capacitor is electrically connected to the anode voltage terminal ELVDD, and the other end is electrically connected to the control electrode of the first switch. This connection method allows the storage capacitor to effectively store the voltage compensation signal as charge and form a stable voltage across its terminals. When the pixel circuit enters the light-emitting phase, the storage capacitor continuously outputs its stored voltage compensation signal to the control electrode of the first switch. Because the storage capacitor has the ability to maintain voltage, even after the data acquisition phase ends, the control electrode of the first switch can still receive a stable and accurate voltage compensation signal. During the light-emitting phase, the first switch conducts based on the voltage difference between this stable voltage compensation signal and the anode voltage signal of the anode voltage terminal ELVDD, thereby driving the light-emitting device to emit light.

[0049] Please continue reading. Figure 1 The pixel circuit of this application also includes a fourth switch, one end of which is electrically connected to the initialization voltage terminal, and the other end of which is electrically connected to the control electrode of the first switch. During the reset phase, the fourth switch is used to write the initialization voltage signal of the initialization voltage terminal to the control electrode of the first switch to reset the control electrode of the first switch.

[0050] It is understood that, in this embodiment of the application, by introducing a fourth switch and an initialization voltage terminal, the fourth switch is turned on during the reset phase of the pixel circuit, thereby connecting the initialization voltage signal provided by the initialization voltage terminal to the control electrode of the first switch. The initialization voltage signal forces the control electrode of the first switch to a preset initial potential. This operation ensures that the control electrode of the first switch is in a known and stable initial state before entering the data acquisition phase, eliminating any residual charge or uncertain potential that may remain from the previous operation cycle. By effectively resetting the control electrode of the first switch, it can be ensured that the data signal output by the second switch to the first switch can be accurately written during the data acquisition phase, and that the third switch can output a precise voltage compensation signal based on the accurate data signal. This is crucial for the precise conduction of the first switch based on the voltage difference between the voltage compensation signal and the anode voltage signal of the anode voltage terminal ELVDD in the subsequent light emission phase, thereby ensuring that the light-emitting device can emit light uniformly with the expected brightness.

[0051] During the pixel circuit reset phase, the fourth switch accurately writes the initialization voltage signal from the initialization voltage terminal to the control electrode of the first switch, effectively resetting the control electrode of the first switch. This ensures that the control electrode of the first switch is at a defined and stable initial potential at the beginning of each operating cycle, avoiding error accumulation caused by residual charge or uncertain states. Therefore, in the subsequent data acquisition phase, the writing of data signals and the generation of voltage compensation signals will be more precise, resulting in more accurate and stable control of the driving current and brightness of the light-emitting device. This significantly improves the driving accuracy of the pixel circuit and the brightness uniformity of the display panel, thereby enhancing the overall display performance and image quality.

[0052] Please continue reading. Figure 1 And see Figure 2 In this embodiment, the pixel circuit is applied to a display panel, and the display panel includes multiple pixel rows; the control electrode of the fourth switch is connected to the first scan signal line, and the control electrodes of the second and third switches are connected to the second scan signal line; wherein, the first scan signal line is the scan signal line corresponding to the current nth pixel row, and the second scan signal line is the scan signal line corresponding to the (n+1)th pixel row; or, the scan signal on the first scan signal line is the same global signal output by the display driver integrated circuit of the display panel to multiple pixel rows, and the second scan signal line is the scan signal line corresponding to the current pixel row.

[0053] It should be explained that the application of pixel circuits on a display panel means that the pixel circuit is the basic display unit of the display panel. A display panel is typically composed of a large number of pixel circuits arranged in a matrix, forming multiple pixel rows and columns. The control electrode of the fourth switch is connected to the first scan signal line, indicating that the conduction and cutoff of the fourth switch are controlled by the first scan signal line. The first scan signal line is usually output by a display driver integrated circuit and is used to control specific operations of the pixel circuit line-by-line or globally. The control electrodes of the second and third switches are connected to the second scan signal line, indicating that the conduction and cutoff of the second and third switches are controlled by the second scan signal line. The second scan signal line is also output by a display driver integrated circuit and is used to control another set of operations of the pixel circuit.

[0054] Understandably, when the first scan signal line corresponds to the current nth pixel row and the second scan signal line corresponds to the (n+1)th pixel row, this means that for a pixel circuit located in the nth pixel row, the reset operation of its fourth switch is controlled by the scan signal of the nth pixel row, while the data acquisition and voltage compensation operations of its second and third switches are controlled by the scan signal of the (n+1)th pixel row. This timing arrangement achieves time-staggered operation of different operation stages; that is, the reset operation of the nth row pixel circuit and the data acquisition operation of the nth row pixel circuit are not triggered simultaneously by the scan signal of the same row, but are controlled by the scan signals of adjacent rows.

[0055] Alternatively, when the scan signal on the first scan signal line is the same global signal output by the display driver IC of the display panel to multiple pixel rows, it indicates that the fourth switch in all pixel rows can be controlled simultaneously. This global signal is typically used to implement operations such as global reset or pre-charge. In this case, the second scan signal line is the scan signal line corresponding to the current pixel row, meaning that data acquisition and voltage compensation operations are still performed row by row, controlled by the scan signal line of each pixel row itself.

[0056] This embodiment of the application achieves precise timing control of key operations such as reset, data acquisition, and voltage compensation in the pixel circuit by electrically connecting the control electrode of the fourth switch to the first scan signal line, and electrically connecting the control electrodes of the second and third switches to the second scan signal line. With the first configuration, where the first scan signal line corresponds to the current nth pixel row and the second scan signal line corresponds to the (n+1)th pixel row, effective separation and pipelined processing of the reset and data acquisition operations can be achieved in time. For example, when the reset operation of the nth row pixel circuit is completed, the scan signal of the (n+1)th row pixel circuit triggers the data acquisition and voltage compensation of the nth row pixel circuit, thus avoiding timing conflicts between different operations and providing sufficient completion time for each operation. With the second configuration, where the first scan signal line is a global signal and the second scan signal line is the scan signal line corresponding to the current pixel row, global reset of all pixel circuits can be achieved, followed by row-by-row data acquisition and voltage compensation. This helps simplify the drive circuit design and improves reset efficiency. The reset, data acquisition, and voltage compensation operations of the pixel circuit can be precisely and flexibly timed. This control method effectively solves the timing conflict problem that may exist between different operation stages in multi-pixel row display panels, ensuring that the pixel circuit can stably and accurately receive and process signals during the scanning process of the display panel.

[0057] This application proposes that, during the reset phase, a fourth switching element is turned on based on the scan signal of the first scan signal line, thereby resetting the control electrode of the first switching element and / or the anode of the light-emitting device. Specifically, the conduction of the fourth switching element is controlled by the scan signal of the first scan signal line. When the scan signal is at an effective level (e.g., high or low), the fourth switching element is activated and turned on, thereby performing its reset function. The reset operation aims to place the control electrode of the first switching element and / or the anode of the light-emitting device at a preset initial level. Resetting the control electrode of the first switching element ensures that the switching transistor driving the light-emitting device is in a known and stable initial state at the beginning of each working cycle, eliminating the influence of data from the previous frame. Resetting the anode of the light-emitting device can clear any residual charge that may exist on the anode of the light-emitting device, or set its voltage to a specific value (e.g., a voltage that completely cuts it off), thereby avoiding weak light emission or afterimages in the non-light-emitting phase, ensuring the purity and uniformity of the displayed image.

[0058] Specifically, during the reset phase of the pixel circuit, the first scan signal line outputs a specific scan signal. When this scan signal is applied to the control terminal of the fourth switch, the fourth switch is activated and turned on. Once the fourth switch is turned on, it applies the initialization voltage signal from the initialization voltage terminal to the control electrode of the first switch, thereby resetting the control electrode of the first switch to a preset initial level. Alternatively, the turning on of the fourth switch can also connect the anode of the light-emitting device to a reset level (e.g., ground or a lower voltage) to clear residual charge or set its voltage to a specific value. In this way, not only is the driving state of the first switch initialized, but the light-emitting device itself is also effectively reset, ensuring that the entire pixel circuit is in a clean and consistent initial state before entering the data acquisition and light emission phases.

[0059] During the reset phase, the fourth switch not only resets the control electrode of the first switch but also resets the anode of the light-emitting device. This dual or optional reset mechanism ensures that the driving transistors and light-emitting devices are in a defined and consistent initial state at the beginning of each display cycle. This significantly reduces display inhomogeneity, ghosting, or trailing caused by residual charge or uncertain states from the previous frame, thereby improving the uniformity, stability, and overall display quality of the image.

[0060] Please see Figure 3 The pixel circuit in this embodiment further includes a fourth switch, one end of which is electrically connected to the initialization voltage terminal, and the other end of which is connected between the third switch and the first switch. During the reset phase, the fourth switch is used to write the initialization voltage signal of the initialization voltage terminal to the control electrode of the first switch through the third switch to reset the control electrode of the first switch.

[0061] Understandably, during the pixel circuit's reset phase, the fourth switch is turned on, introducing the initialization voltage signal into the circuit. This initialization voltage signal passes through the fourth switch, and further through the third switch, ultimately being written to the control electrode of the first switch. In this way, the potential of the first switch's control electrode is forcibly set to the level of the initialization voltage signal, thus achieving an effective reset of the first switch's control electrode. This reset operation ensures that the first switch's control electrode is cleared of all residual charge or the influence of the previous frame's data before entering the data acquisition phase, ensuring it always starts operating from a known, stable initial state.

[0062] During the pixel circuit reset phase, a fourth switch is introduced to write the initialization voltage signal from the initialization voltage terminal to the control electrode of the first switch via a third switch, thus achieving precise reset of the control electrode of the first switch. This effectively solves the problem of uncertain initial state of the control electrode of the first switch due to residual charge or the influence of data from the previous frame, thereby ensuring accurate acquisition of the voltage compensation signal.

[0063] Please continue reading. Figure 3 The pixel circuit of this application embodiment is applied on a display panel, and the display panel includes multiple pixel rows; the control electrode of the fourth switch is connected to the first scan signal line, the control electrode of the third switch is connected to the second scan signal line, and the control electrode of the second switch is connected to the third scan signal line; the first scan signal line is the scan signal line corresponding to the current nth pixel row, the second scan signal line is the scan signal line corresponding to the (n+1)th pixel row, and the third scan signal line is the scan signal line corresponding to the (n+2)th pixel row.

[0064] It should be explained that the pixel circuit is applied to the display panel, and the display panel includes multiple pixel rows. This indicates that the pixel circuit of this application is integrated into the array of the display panel, which consists of multiple horizontally arranged pixel rows. In a multi-pixel row display panel, pixels are typically addressed and controlled row by row or region by region through scanning. The control electrode of the fourth switch is connected to the first scan signal line, meaning that the on / off state of the fourth switch is controlled by the electrical signal on the first scan signal line. The control electrode of the third switch is connected to the second scan signal line, meaning that the switching state of the third switch is controlled by the electrical signal on the second scan signal line. Similar to the first scan signal line, the second scan signal line can also be a gate line or scan line in the display panel, used to provide specific timing control signals. The control electrode of the second switch is connected to the third scan signal line, indicating that the switching state of the second switch is controlled by the electrical signal on the third scan signal line. The third scan signal line can also be a gate line or scan line in the display panel, its function being to precisely control the timing of data signal writing. The first scan signal line corresponds to the current nth pixel row, clarifying that it controls the currently processed nth pixel row. This means that when the display panel's scanning operation reaches the nth row, the first scan signal line corresponding to that row will be activated, thereby controlling the fourth switch connected to it. The second scan signal line corresponds to the (n+1)th pixel row, indicating that it controls the (n+1)th pixel row. This means that for the third switch in the nth pixel row, its control signal does not come from this row, but from the scan signal line of the next row (n+1). The third scan signal line corresponds to the (n+2)th pixel row, further clarifying that it controls the (n+2)th pixel row. This means that for the second switch in the nth pixel row, its control signal comes from the scan signal line of the next row (n+2).

[0065] It is understood that this embodiment achieves a fine and staggered control timing by connecting the control electrodes of the fourth, third, and second switches to the scan signal lines corresponding to different pixel rows, namely the first scan signal line (nth pixel row), the second scan signal line (n+1th pixel row), and the third scan signal line (n+2th pixel row). This connection method allows the pixel circuit's reset phase, voltage compensation signal processing phase, and data acquisition phase to be performed sequentially and without interference using the inherent line-by-line scanning mechanism of the display panel. Specifically, when the display panel's scanning operation reaches the nth pixel row, the first scan signal line corresponding to the nth pixel row first activates the fourth switch, thereby writing the initialization voltage signal to the control electrode of the first switch through the third switch, completing the reset operation. Subsequently, as the scanning progresses, when scanning reaches the n+1th pixel row, the second scan signal line corresponding to the n+1th pixel row activates the third switch in the nth pixel row. At this time, after the first switch acquires the data signal, the third switch can output a voltage compensation signal. Finally, when scanning reaches the (n+2)th pixel row, the third scan signal line corresponding to the (n+2)th pixel row activates the second switch in the nth pixel row, thereby accurately inputting the data signal into the pixel circuit. This row-by-row staggered control strategy cleverly utilizes the scanning timing of the display panel, ensuring the independence and accuracy of each operation stage, avoiding signal conflicts, and simplifying the control logic within the pixel.

[0066] By connecting the control electrodes of the fourth, third, and second switches to the scan signal lines corresponding to the current pixel row, the next pixel row, and the pixel row after that, respectively, this application provides an efficient and reliable pixel circuit control scheme. This staggered scanning control mechanism ensures that critical operations such as pixel circuit reset, voltage compensation signal processing, and data acquisition are strictly separated in time, effectively avoiding signal interference and timing conflicts between different operation stages. This scheme fully utilizes the progressive scan characteristics of the display panel, eliminating the need to integrate complex timing generators or additional global control lines within each pixel, thereby simplifying the pixel circuit structure design and reducing manufacturing difficulty. This precise timing control helps improve the overall uniformity and stability of the display panel, ensuring that each pixel is accurately initialized and written with data at the correct time, thus improving the quality and reliability of the displayed image.

[0067] Please continue reading. Figure 1The pixel circuit in this embodiment further includes a fifth switch. The fifth switch, the first switch, and the light-emitting device are connected in series between the anode voltage terminal ELVDD and the cathode voltage terminal ELVSS. The control electrode of the fifth switch is electrically connected to the light-emitting control signal line. The fifth switch is used to connect the anode voltage terminal ELVDD, the first switch, the light-emitting device, and the cathode voltage terminal ELVSS when the light-emitting control signal line outputs a light-emitting control signal.

[0068] It is understood that by introducing a fifth switching element into the pixel circuit and connecting it in series in the light-emitting circuit, and controlling it through a light-emitting control signal line, the solution of this application can achieve precise on / off control of the light-emitting device. This allows the display panel to manage the light-emitting state of the pixels more flexibly. For example, during non-display cycles or specific display modes, the light-emitting device can be forcibly turned off, effectively avoiding weak light emission caused by residual charge or leakage current in the driving circuit, thereby significantly improving the contrast and purity of the displayed image. In addition, this globally or locally controllable light-emitting switching mechanism also helps to reduce overall power consumption, especially when displaying black or low-brightness images. By completely cutting off the light-emitting path, a deeper black and higher energy efficiency can be achieved.

[0069] The pixel circuits in this application embodiment are applied on a display panel, and the display panel includes multiple pixel circuits. The light emission control signal is the same global signal output by the display driver integrated circuit of the display panel to multiple pixel circuits.

[0070] This application's solution applies pixel circuits to a display panel and utilizes a display driver integrated circuit to generate and output a unified global light-emitting control signal, thereby uniformly controlling the light-emitting behavior of multiple pixel circuits within the display panel. Specifically, during the overall operation of the display panel, the display driver integrated circuit generates a unified light-emitting control signal based on the display timing and image data. This light-emitting control signal is wired to the control terminals of the fifth switches of all pixel circuits on the display panel that require its control. When the global light-emitting control signal is enabled, all fifth switches receiving the signal will simultaneously conduct, thereby connecting the anode voltage terminal ELVDD, the first switch, the light-emitting device, and the cathode voltage terminal ELVSS, enabling the light-emitting device to emit light according to its driving state. Conversely, when the global light-emitting control signal is disabled, the fifth switches will simultaneously turn off, cutting off the power supply path to the light-emitting device and stopping it from emitting light. This global control mechanism ensures that the light-emitting behavior of all pixel circuits on the display panel is highly synchronized and consistent, avoiding timing deviations or unevenness caused by independent control signals.

[0071] Furthermore, by utilizing the display driver integrated circuit to output the same global light emission control signal to multiple pixel circuits, the problem of complex wiring and excessive driving burden caused by independently controlling the light emission of each pixel circuit in a display panel containing a large number of pixel circuits is effectively solved. This global control method significantly simplifies the control logic and wiring structure of the display panel, which is beneficial for the narrow bezel design of the display panel.

[0072] In the pixel circuit of this application embodiment, at least one of the first switch, the second switch, the third switch, the fourth switch, and the fifth switch is any one of a thin-film transistor, a MOSFET, and a transistor.

[0073] Specifically, a thin-film transistor (TFT) is a field-effect transistor made by depositing thin-film materials (such as semiconductor layers, dielectric layers, and metal contacts) on a non-conductive substrate. Its implementation can include amorphous silicon (a-Si) TFTs, polycrystalline silicon (poly-Si) TFTs (such as low-temperature polycrystalline silicon LTPS and high-temperature polycrystalline silicon HTPS), or oxide TFTs (such as IGZO). TFTs are widely used in flat panel displays due to their ability to be fabricated on large-area substrates, providing excellent switching characteristics and integration capabilities. A MOSFET (metal-oxide-semiconductor field-effect transistor) is a field-effect transistor whose conductivity is controlled by the gate voltage; its current conduction is accomplished by only one type of charge carrier (electron or hole). Its implementation can include N-type MOSFETs, P-type MOSFETs, or complementary MOS (CMOS) structures. MOSFETs are known for their high input impedance, low power consumption, and high switching speed, making them suitable for integrated circuits and various switching applications. A bipolar junction transistor (BJT) is a three-terminal semiconductor device used to amplify or switch electronic signals and electrical power. Its current conduction is accomplished by both electrons and holes. Its implementation can include NPN transistors and PNP transistors. Transistors have good current amplification and switching capabilities, and are often used in discrete circuits or applications requiring high current drive.

[0074] This application further proposes that, under the aforementioned high voltage condition, the cathode voltage terminal ELVSS outputs a preset high voltage, which is higher than the output voltage of the cathode voltage terminal ELVSS during the light emission stage.

[0075] It's important to clarify that the high-voltage state refers to the potential state of the cathode voltage terminal ELVSS during a specific operating phase (data acquisition phase), where its voltage value is relatively high. The preset high voltage refers to a pre-set voltage value output by the cathode voltage terminal ELVSS when it is in the high-voltage state. This preset high voltage, higher than the output voltage of the cathode voltage terminal ELVSS during the light-emitting phase, clearly defines the relative magnitude of the cathode voltage during the data acquisition phase and the cathode voltage during the light-emitting phase. This helps ensure that the voltage difference across the light-emitting device is effectively cut off during the data acquisition phase, preventing accidental light emission. Simultaneously, during the light-emitting phase, the cathode voltage decreases, allowing the light-emitting device to conduct and emit light normally. This differentiated voltage setting helps to precisely control the operating state of the light-emitting device, improving display performance.

[0076] Understandably, in the data acquisition phase, the pixel circuit of this application sets the cathode voltage terminal ELVSS to a high voltage state, specifically specifying that the preset high voltage output of the cathode voltage terminal ELVSS in this high voltage state is higher than the output voltage of the cathode voltage terminal ELVSS during the light emission phase. This design raises the cathode potential of the light-emitting device to a relatively high level during the data acquisition phase. Since the anode of the light-emitting device is usually also at a relatively high potential, when the cathode potential is raised, the voltage difference across the light-emitting device decreases, even to the point of being insufficient to enable it to conduct and emit light. This effectively ensures that the light-emitting device is in a cutoff or weakly conductive state during data acquisition, thereby avoiding unnecessary light emission during data writing or voltage compensation, and ensuring accurate writing and storage of data signals. When the pixel circuit enters the light emission phase, the voltage output of the cathode voltage terminal ELVSS drops below the preset high voltage of the data acquisition phase. At this time, the voltage difference across the light-emitting device increases, enabling it to conduct and emit light normally according to the drive signal.

[0077] Example 1: Please continue reading Figure 1This embodiment provides a 5T1C pixel circuit, which includes five P-type thin-film transistors (T1~T5) and one storage capacitor (C1). In this embodiment, the anode of the OLED is electrically connected to the second electrode of the fifth switch T5, and the cathode of the OLED is electrically connected to the cathode voltage terminal ELVSS. The first electrode of the fifth switch T5 is electrically connected to the anode voltage terminal ELVDD, and the control electrode of the fifth switch T5 is electrically connected to the light emission control signal line EM. The first electrode of the first switch T1 is electrically connected to the anode voltage terminal ELVDD, and the second electrode of the first switch T1 is electrically connected to the anode of the OLED (in this embodiment, indirectly connected via the fifth switch T5). The first electrode of the second switch T2 is electrically connected to the data signal terminal Vdata, the second electrode of the second switch T2 is electrically connected to the first electrode of the first switch T1, and the control electrode of the second switch T2 is electrically connected to the second scan signal line S2. The first terminal of the third switch T3 is electrically connected to the control terminal of the first switch T1, and the second terminal of the third switch T3 is electrically connected to the second terminal of the first switch T1. The control terminal of the third switch T3 is electrically connected to the second scan signal line S2. The first terminal of the fourth switch T4 is electrically connected to the initialization voltage terminal Vinit, and the second terminal of the fourth switch T4 is electrically connected to the control terminal (M node) of the first switch T1. The control terminal of the fourth switch T4 is electrically connected to the first scan signal line S1. The first terminal of the storage capacitor Cst is electrically connected to the anode voltage terminal ELVDD, and the second terminal of the storage capacitor Cst is electrically connected to the control terminal of the first switch T1.

[0078] Specifically, the first scan signal line S1 is the scan signal line corresponding to the current nth pixel row, and the second scan signal line S2 is the scan signal line corresponding to the (n+1)th pixel row. The light emission control signal on the light emission control signal line EM is the same global signal output by the display driver integrated circuit (DDIC) of the display panel to multiple pixel circuits. The first switch T1 acts as a driving transistor, and its control electrode potential (i.e., the M node potential) determines the magnitude of the driving current flowing through the OLED light-emitting device. The second switch T2 acts as a data write switch, used to transmit the data signal Vdata to the first electrode of the first switch T1 during the data acquisition phase. The third switch T3 acts as a compensation switch, used to short-circuit the control electrode and the second electrode of the first switch T1 during the data acquisition phase, making the first switch T1 form a diode connection to compensate for the threshold voltage Vth. The fourth switch T4 acts as a reset switch, used to write the initialization voltage Vinit to the M node during the reset phase. The fifth switch T5 acts as a light emission control switch, used to connect the entire driving circuit during the light emission phase.

[0079] The pixel circuit in Example 1 sequentially undergoes three phases within one display frame cycle: a reset phase (Phase 1), a data acquisition phase (Phase 2), and a light emission phase (Phase 3). Its driving timing is as follows: Figure 4 The timing diagram is shown.

[0080] During the reset phase, the first scan signal line S1 outputs a low level (active level), the second scan signal line S2 outputs a high level (inactive level), and the light emission control signal line EM outputs a high level. The fourth switch T4 is turned on because its control electrode is connected to the low level of S1, writing the initialization voltage signal Vinit output from the initialization voltage terminal Vinit into the control electrode (M node) of the first switch T1, thus resetting the M node potential to Vinit. At this time, the second switch T2 and the third switch T3 are in the off state because their control electrodes are connected to the high level of S2. The fifth switch T5 is in the off state because its control electrode is connected to the high level of EM; therefore, no current flows through the OLED light-emitting device, and it does not emit light.

[0081] During the data acquisition phase, the first scan signal line S1 returns to a high level, the second scan signal line S2 outputs a low level, and the light emission control signal line EM remains high. Crucially, in this phase, the anode voltage terminal ELVDD is set to a high-impedance state (Hiz), meaning ELVDD neither provides nor absorbs current, and its potential is in a floating state. At this time, the second switch T2 is turned on because its control electrode is connected to the low level of S2, transmitting the data signal Vdata from the data signal terminal to the first electrode of the first switch T1. The third switch T3 is also turned on because its control electrode is also connected to the low level of S2, shorting the control electrode (M node) of the first switch T1 to its second electrode, making the first switch T1 form a diode connection. Because ELVDD is in a high-impedance state, no current path can be provided from the ELVDD terminal, and the data signal Vdata charges the M node through the path formed by the second switch T2, the first switch T1, and the third switch T3. The potential of node M rises from the reset voltage Vinit until the first switch T1 is turned off (i.e., the difference between the potential of node M and the first electrode potential of the first switch T1 equals the threshold voltage Vth of the first switch T1), at which point charging stops. At this point, the potential of node M is Vdata + Vth (for a P-type TFT, Vth is negative; here, Vth refers to the absolute value of the threshold voltage), achieving threshold voltage compensation. The storage capacitor Cst stores the compensation voltage signal Vdata + Vth of node M.

[0082] During the light-emitting phase, both the first scan signal line S1 and the second scan signal line S2 return to high level, while the fourth switch T4, the second switch T2, and the third switch T3 are all in the off state. The anode voltage terminal ELVDD returns to the normal driving voltage (e.g., positive voltage 4.6V). The light-emitting control signal line EM outputs a low level, and the fifth switch T5 is turned on. At this time, the driving current I_oled flows from ELVDD through the fifth switch T5, the first switch T1, and the light-emitting device OLED to ELVSS. The gate-source voltage Vgs of the first switch T1 is the difference between the M node potential and the ELVDD voltage, i.e., Vgs = (Vdata + Vth) - ELVDD. The first switch T1 operates in the saturation region, thereby achieving complete compensation for the threshold voltage offset and ensuring the uniformity of the light-emitting brightness of each pixel.

[0083] Compared to the existing 7T1C pixel circuit, the 5T1C pixel circuit in Embodiment 1 reduces the number of thin-film transistors by two, significantly shrinking the layout area and facilitating the realization of a high pixel density (PPI) display panel. Simultaneously, the EM signal is uniformly output as a global signal by the DDIC, eliminating the need for separate EM GIP circuits on the left and right bezels of the panel. This saves one GIP circuit on each side, requiring only one Scan GIP circuit on each side to complete all scan control, thus enabling narrow bezels on the left and right sides of the display panel. Furthermore, by setting ELVDD to a high-impedance state during the data acquisition phase, threshold voltage compensation is achieved using the diode connection effect of the first switching element T1 itself, eliminating the need for additional compensation transistors. This simplifies the circuit structure while ensuring compensation accuracy.

[0084] Example 2: Please refer to Figure 5 and Figure 6 Example 2 provides a 5T1C pixel circuit that uses an ELVSS high-voltage scheme to achieve threshold voltage compensation. Example 2 has a similar circuit topology to Example 1, the main difference being the compensation control strategy used in the data acquisition phase. The pixel circuit in Example 2 also sequentially undergoes a reset phase, a data acquisition phase, and a light emission phase within one display frame cycle, with its driving timing as follows: Figure 6 The timing diagram is shown.

[0085] During the reset phase, the first scan signal line S1 outputs a low level, the second scan signal line S2 outputs a high level, and the EM signal line outputs a high level. The fourth switch T4 is turned on, writing Vinit to the control electrode (M node) of the first switch T1, thus completing the reset of the M node. All other switches are in the off state.

[0086] During the data acquisition phase, the first scan signal line S1 returns to a high level, the second scan signal line S2 outputs a low level, and the EM signal line remains high. Crucially, in this phase, the cathode voltage terminal ELVSS is set to a high voltage state, meaning that ELVSS outputs a preset high voltage PVGH. This preset high voltage PVGH is higher than the normal output voltage of ELVSS during the light emission phase. For example, if the voltage of ELVSS is -3V during the light emission phase, the voltage of ELVSS during the data acquisition phase is boosted to +5V or a higher positive voltage PVGH.

[0087] It should be explained that by setting ELVSS to a preset high voltage PVGH, the cathode potential of the OLED is significantly increased. During the data acquisition phase, the initial voltage Vinit of node M is typically a low voltage (e.g., -1V). The first switch T1 is in the ON state, and the second and third switches T2 and T3 are also ON due to the low level of S2. The data signal Vdata can charge node M through switches T2, T1, and T3. However, because ELVSS is at a high potential PVGH, the voltage difference across the OLED is insufficient for forward conduction (i.e., the OLED's conduction threshold voltage is not reached), and the OLED is effectively in the OFF state. This means that the charge injected by the data signal Vdata will not leak through the OLED to ELVSS, ensuring the integrity of the charging process for node M and allowing the node potential to accurately reach Vdata + Vth. The fifth switch T5 is in the OFF state because its control electrode is connected to a high level of EM, further ensuring that the ELVDD terminal does not interfere with the charging process. The storage capacitor Cst stores the compensation voltage signal of node M during the data acquisition phase.

[0088] During the light-emitting phase, both the first scan signal line S1 and the second scan signal line S2 return to a high level, and the fourth switch T4, the second switch T2, and the third switch T3 are all turned off. The cathode voltage terminal ELVSS returns to the normal light-emitting voltage (e.g., -3V or lower negative voltage). The light-emitting control signal line EM outputs a low level, and the fifth switch T5 is turned on. The driving current flows from ELVDD through the fifth switch T5, the first switch T1, and the light-emitting device OLED to ELVSS, and the light-emitting device OLED emits light normally. The current flowing through the light-emitting device OLED is exactly the same as in Embodiment 1, and is also independent of the threshold voltage Vth of the first switch T1, thus achieving threshold voltage compensation.

[0089] The beneficial effects of this embodiment are basically the same as those of Embodiment 1, the difference being that: Embodiment 1 eliminates the leakage path of the OLED by setting the anode voltage terminal ELVDD to a high-resistivity state, while Embodiment 2 achieves the same purpose—preventing data signal charge from leaking through the OLED—by raising the cathode voltage terminal ELVSS to a preset high voltage PVGH. The solution in Embodiment 2 does not require high-resistivity switching control of the ELVDD driving circuit, making it easier to implement in some power management chip (PMIC) designs. Simultaneously, the PVGH setting can also protect the reverse bias of the OLED during the data acquisition phase, suppressing the OLED aging effect caused by long-term positive stress.

[0090] Example 3: Please refer to Figure 7 and Figure 8 Example 3 provides a 4T1C pixel circuit that simultaneously employs a dual control strategy of ELVDD high impedance state and ELVSS high voltage to achieve threshold voltage compensation.

[0091] Please see Figure 7 The pixel circuit of this embodiment includes: an OLED light-emitting device, a first switch T1, a second switch T2, a third switch T3, a fourth switch T4, and a storage capacitor Cst, totaling four thin-film transistors and one storage capacitor, forming a 4T1C architecture. Compared with Embodiments 1 and 2, this embodiment omits the fifth switch T5 (light-emitting control transistor), further simplifying the circuit structure.

[0092] In this embodiment, the anode of the OLED light-emitting device is directly electrically connected to the second electrode of the first switching element T1, and the cathode of the OLED light-emitting device is electrically connected to the cathode voltage terminal ELVSS. The first electrode of the first switching element T1 is electrically connected to the anode voltage terminal ELVDD. The first electrode of the second switching element T2 is electrically connected to the data signal terminal Vdata, the second electrode of the second switching element T2 is electrically connected to the first electrode of the first switching element T1, and the control electrode of the second switching element T2 is electrically connected to the second scan signal line S2. The first electrode of the third switching element T3 is electrically connected to the control electrode of the first switching element T1, the second electrode of the third switching element T3 is electrically connected to the second electrode of the first switching element T1, and the control electrode of the third switching element T3 is electrically connected to the second scan signal line S2. The first electrode of the fourth switching element T4 is electrically connected to the initialization voltage terminal Vinit, the second electrode of the fourth switching element T4 is electrically connected to the control electrode of the first switching element T1, and the control electrode of the fourth switching element T4 is electrically connected to the first scan signal line S1. The first terminal of the storage capacitor Cst is electrically connected to the anode voltage terminal ELVDD, and the second terminal of the storage capacitor Cst is electrically connected to the control electrode of the first switching element T1.

[0093] Please see Figure 8During the reset phase, the first scan signal line S1 outputs a low level, and the second scan signal line S2 outputs a high level. The fourth switch T4 is turned on, writing the initialization voltage Vinit to node M (the control electrode of the first switch T1), completing the reset of node M. At this time, the first switch T1 is turned on (because the potential of node M is low), but since the second switch T2 and the third switch T3 are both turned off, no data signal is injected. The anode voltage terminal ELVDD provides the normal voltage, and the cathode voltage terminal ELVSS provides the normal light emission voltage.

[0094] During the data acquisition phase, the first scan signal line S1 returns to a high level, and the fourth switch T4 is turned off. The second scan signal line S2 outputs a low level, and the second switch T2 and the third switch T3 are simultaneously turned on. Crucially, in this phase, the anode voltage terminal ELVDD is set to a high-resistance state (Hi-Z), while the cathode voltage terminal ELVSS is set to a high-voltage state (outputting a preset high voltage PVGH), i.e., a dual control strategy. Under this dual control strategy, the data signal Vdata charges node M through the path formed by the second switch T2, the first switch T1, and the third switch T3. Because ELVDD is in a high-resistance state, no charging current is introduced from the ELVDD terminal, ensuring that the charging process is driven only by Vdata. Simultaneously, because ELVSS is at the preset high voltage PVGH, the light-emitting device OLED is reverse-biased or has not reached the conduction threshold, and no leakage current flows from the OLED to ELVSS. This dual protection mechanism ensures the integrity and accuracy of the charging process, and the potential of node M can accurately reach Vdata + Vth, achieving reliable threshold voltage compensation. The storage capacitor Cst stores the compensation voltage signal.

[0095] During the light-emitting phase, both the first scan signal line S1 and the second scan signal line S2 return to high level, and the fourth switch T4, the second switch T2, and the third switch T3 are all turned off. The anode voltage terminal ELVDD returns to the normal driving voltage, and the cathode voltage terminal ELVSS returns to the normal light-emitting voltage. At this time, since there is no fifth switch (light-emitting control transistor), the driving current flows directly from ELVDD through the first switch T1 and the light-emitting device OLED to ELVSS to form a loop. The first switch T1 is turned on based on the difference between the compensation voltage signal output by the storage capacitor Cst and the ELVDD voltage. The current flowing through the light-emitting device OLED is independent of the threshold voltage Vth of the first switch T1, thus achieving compensation.

[0096] Compared to the 5T1C circuits of Embodiments 1 and 2, the 4T1C pixel circuit of this embodiment further reduces one thin-film transistor, resulting in a more streamlined circuit structure. By omitting the light-emitting control transistor T5, the layout area of ​​each pixel unit is further reduced, which is more conducive to achieving a high PPI. Furthermore, since the EM signal line and EM GIP circuit are no longer needed, the wiring requirements of the panel bezel are further reduced; only one Scan GIP circuit is required on each of the left and right bezels to complete all scanning control. The simultaneous use of a dual control strategy of ELVDD high impedance and ELVSS high voltage during the data acquisition stage provides redundant leakage protection. Even if the effectiveness of one control strategy is weakened due to process fluctuations or power supply ripple, the other control strategy can still ensure the accuracy and reliability of threshold voltage compensation.

[0097] Example 4: Please continue reading Figure 2 and see Figure 9 Example 4 provides a 4T1C pixel circuit, which employs a dual control strategy of a global reset signal S0 and a high-impedance state ELVDD + high-voltage state ELVSS to achieve threshold voltage compensation. The pixel circuit in this example is similar to the 4T1C architecture of Example 3, including an OLED light-emitting device, a first switch T1, a second switch T2, a third switch T3, a fourth switch T4, and a storage capacitor Cst. The main difference from Example 3 lies in the connection and control method of the fourth switch T4.

[0098] In this embodiment, the anode of the OLED light-emitting device is electrically connected to the second electrode of the first switch T1, and the cathode of the OLED is electrically connected to the cathode voltage terminal ELVSS. The first electrode of the first switch T1 is electrically connected to the anode voltage terminal ELVDD. The first electrode of the second switch T2 is electrically connected to the data signal terminal Vdata, the second electrode of the second switch T2 is electrically connected to the first electrode of the first switch T1, and the control electrode of the second switch T2 is electrically connected to the second scan signal line S2. The first electrode of the third switch T3 is electrically connected to the control electrode of the first switch T1, the second electrode of the third switch T3 is electrically connected to the second electrode of the first switch T1, and the control electrode of the third switch T3 is electrically connected to the second scan signal line S2. The first electrode of the fourth switch T4 is electrically connected to the initialization voltage terminal Vinit, the second electrode of the fourth switch T4 is connected at the node between the second electrode of the third switch T3 and the second electrode of the first switch T1 (i.e., the connection node between T3 and T1), and the control electrode of the fourth switch T4 is electrically connected to the global reset signal line S0. The first terminal of the storage capacitor Cst is electrically connected to the anode voltage terminal ELVDD, and the second terminal of the storage capacitor Cst is electrically connected to the control electrode of the first switching device T1.

[0099] It should be explained that in this embodiment, the first scan signal line is the global reset signal line S0, meaning that the scan signal on S0 is the same global signal output by the display driver integrated circuit (DDIC) of the display panel to multiple pixel rows. This means that the control electrode of the fourth switch T4 of all pixel rows is connected to the same global reset signal line S0, and the M-node reset operation of all pixel rows is executed synchronously when the S0 signal is at an active level. The second scan signal line S2 is the scan signal line (line-by-line scan signal line) corresponding to the current nth pixel row.

[0100] Please see Figure 9 During the reset phase, the global reset signal line S0 outputs a low level (active level). This low-level signal simultaneously acts on the control electrode of the fourth switch T4 in all pixel rows of the display panel, causing the fourth switch T4 in all pixel rows to conduct simultaneously. For each pixel row, the initialization voltage Vinit is transmitted through the first and second electrodes of the fourth switch T4 to the connection node between the third switch T3 and the first switch T1. Since the second scan signal line S2 has not yet output an active level at this time, the third switch T3 is in the off state. Vinit is directly written to the control electrode (M node) of the first switch T1 through the fourth switch T4, completing the reset of the M node.

[0101] The global reset signal line S0 returns to a high level, and the fourth switch T4 of all pixel rows is turned off. Thereafter, data acquisition is performed row by row: for the nth pixel row, the second scan signal line S2 outputs a low level (S2 is the scan signal line corresponding to the nth pixel row), and the second switch T2 and the third switch T3 are simultaneously turned on. The anode voltage terminal ELVDD is set to a high-impedance state (Hiz), and the cathode voltage terminal ELVSS is set to a high-voltage state (outputting a preset high voltage PVGH). The data signal Vdata charges node M to Vdata+Vth through the path T2→T1→T3, achieving threshold voltage compensation. The storage capacitor Cst stores the compensation voltage signal.

[0102] The second scan signal lines of all pixel rows return to high level, and both the second switch T2 and the third switch T3 are turned off. The anode voltage terminal ELVDD returns to the normal driving voltage, and the cathode voltage terminal ELVSS returns to the normal light-emitting voltage. The driving current flows directly from ELVDD through the first switch T1 and the light-emitting device OLED to ELVSS. The light-emitting device OLED emits light normally, and the current is also independent of Vth.

[0103] This embodiment uses a global reset signal S0 to control all pixel rows to synchronously execute M-node reset. Compared with the row-by-row reset schemes of embodiments one to three, it has the following technical advantages: First, the global reset signal S0 is directly output to the panel from the DDIC, eliminating the need for independent reset scanning GIP circuits on the left and right bezels of the panel, further reducing the wiring area on the left and right bezels and facilitating a narrower bezel. Second, global reset simplifies the design of the reset timing sequence. All pixel rows complete the M-node reset at the same time, eliminating inter-row coupling interference that may be caused by row-by-row reset. Third, the global reset method ensures that the M-nodes of all pixels are in a completely consistent initial state before the panel enters the data acquisition stage, which is beneficial to improving the uniformity of the full-screen brightness. Fourth, since the second electrode of the fourth switch T4 is connected between T3 and T1, rather than directly connected to the M-node, the reset current path passes through the channel of T1. Resetting while the T1 channel is conducting helps to eliminate trap charges that may exist in the T1 channel, improving the stability of the driving transistor.

[0104] Example 5: Please continue reading Figure 3 and see Figure 10 Embodiment 5 provides a 4T1C pixel circuit, which adopts a three-scan-line misalignment control scheme and simultaneously resets the control electrode of the first switching device and the anode of the light-emitting device during the reset phase.

[0105] Please see Figure 3The pixel circuit of this embodiment includes: an OLED light-emitting device, a first switch T1, a second switch T2, a third switch T3, a fourth switch T4, and a storage capacitor Cst, forming a 4T1C architecture. Similar to Embodiment 4, in this embodiment, the second electrode of the fourth switch T4 is connected to the connection node between the second electrode of the third switch T3 and the second electrode of the first switch T1. The anode of the OLED is electrically connected to the second electrode of the first switch T1 (sharing a common node with the second electrodes of the third switch T3 and the fourth switch T4), and the cathode of the OLED is electrically connected to the cathode voltage terminal ELVSS. The first electrode of the first switch T1 is electrically connected to the anode voltage terminal ELVDD. The first electrode of the second switch T2 is electrically connected to the data signal terminal Vdata, the second electrode of the second switch T2 is electrically connected to the first electrode of the first switch T1, and the control electrode of the second switch T2 is electrically connected to the third scan signal line S3. The first terminal of the third switch T3 is electrically connected to the control terminal (M node) of the first switch T1. The second terminal of the third switch T3 is electrically connected to the second terminal of the first switch T1 (and shares a node with the second terminal of the fourth switch T4 and the anode of the OLED). The control terminal of the third switch T3 is electrically connected to the second scan signal line S2. The first terminal of the fourth switch T4 is electrically connected to the initialization voltage terminal Vinit. The second terminal of the fourth switch T4 is connected at the node between the second terminal of the third switch T3 and the second terminal of the first switch T1. The control terminal of the fourth switch T4 is electrically connected to the first scan signal line S1. The first terminal of the storage capacitor Cst is electrically connected to the anode voltage terminal ELVDD. The second terminal of the storage capacitor Cst is electrically connected to the control terminal of the first switch T1.

[0106] In Example 5, the pixel circuit sequentially undergoes a reset phase, a data acquisition phase, and a light emission phase within one display frame cycle. Its driving timing is as follows: Figure 10 The timing diagram is shown.

[0107] During the reset phase, both the first scan signal line S1 and the second scan signal line S2 corresponding to the (n+1)th row output a low level (active level), while the third scan signal line S3 outputs a high level. The fourth switch T4 is turned on due to the low level of S1, and the third switch T3 is turned on due to the low level of S2. At this time, the initialization voltage Vinit is written to the control electrode (M node) of the first switch T1 through the fourth switch T4 and the third switch T3, completing the reset of the M node.

[0108] It is particularly important to note that during this reset phase, since the fourth switch T4 and the third switch T3 are simultaneously turned on, the initialization voltage Vinit is also applied directly through the fourth switch T4 to the common node between the second electrode of the first switch T1 and the anode of the OLED, thereby simultaneously resetting the anode of the OLED. In other words, the reset phase of this embodiment simultaneously achieves the reset of the M node (the control electrode of the first switch T1) and the reset of the OLED anode—both are completed by the same initialization voltage Vinit, the same fourth switch T4, and the same reset timing. However, the reset path of the OLED anode does not pass through T3 (because T3 is also turned on, creating a direct path) or is performed via both the direct path and the T3 path. This design avoids the need for additional transistors and scan signal lines to separately reset the OLED anode in existing technologies, further saving on the number of components.

[0109] During the data acquisition phase, the first scan signal line S1 first returns to a high level, the fourth switch T4 is turned off, and node M maintains its initial potential (Vinit) after reset. Subsequently, the second scan signal line S2 returns to a high level, and the third switch T3 is turned off. Next, the third scan signal line S3 outputs a low level, and the second switch T2 is turned on. The anode voltage terminal ELVDD is set to a high impedance state (Hi-Z), and the cathode voltage terminal ELVSS is set to a high voltage state (outputting a preset high voltage PVGH). The data signal Vdata is transmitted to the first terminal of the first switch T1 through the second switch T2. Since the potential of node M is Vinit (a lower potential), the first switch T1 is turned on, and the data signal Vdata charges node M through the first switch T1.

[0110] It should be explained that during the data acquisition phase of this embodiment, the third switch T3 was turned off before the second switch T2. This means that the first switch T1 did not form a diode connection, and the charging of node M was completed through the source-gate parasitic capacitance coupling of the first switch T1 and the combined effect of the channel current. Although the charging path is different from embodiments one to four, since ELVDD is in a high-resistance state and ELVSS is in a high-voltage state, and the OLED light-emitting device has no leakage path, the final charging potential of node M can still accurately reflect the information of the data signal Vdata and the threshold voltage Vth of the first switch T1—the potential of node M is approximately Vdata + Vth_eff, where Vth_eff is the equivalent compensation voltage after considering parasitic effects.

[0111] During the light-emitting phase, all scan signal lines S1, S2, and S3 return to high level, and the fourth switch T4, the third switch T3, and the second switch T2 are all turned off. The anode voltage terminal ELVDD returns to the normal driving voltage, and the cathode voltage terminal ELVSS returns to the normal light-emitting voltage. The driving current flows from ELVDD through the first switch T1 and the light-emitting device OLED to ELVSS, and the light-emitting device OLED emits light normally. Since the storage capacitor Cst stores the compensated M-node voltage signal, the light-emitting current is also basically independent of the threshold voltage Vth of the first switch T1, achieving the compensation effect.

[0112] The three-scan-line misalignment control scheme (S1 corresponds to row n, S2 corresponds to row n+1, and S3 corresponds to row n+2) in this embodiment has the following technical effects: First, during the reset phase, by utilizing the window period when S1 and S2 are both low, the M-node reset and OLED anode reset are completed synchronously through the same fourth switch T4 and the same initialization voltage Vinit, eliminating the need for an additional reset transistor and saving layout area. Second, the three-scan-line misalignment timing design ensures that the reset, compensation, and data writing operations are strictly separated in time, avoiding signal interference and timing conflicts between operations. Third, since the OLED anode is forcibly discharged to Vinit during the reset phase, no charge from the previous frame remains on the OLED anode, effectively suppressing ghosting and trailing phenomena. Fourth, the three-level misalignment of S1, S2, and S3 fully utilizes the natural timing characteristics of the progressive scan of the display panel, eliminating the need to integrate additional timing control logic within each pixel, resulting in a simple and reliable circuit implementation.

[0113] Furthermore, to better implement the pixel circuit in any of the above embodiments, this application proposes a pixel circuit driving method based on the pixel circuit of the above embodiments, applied to the above pixel circuit. The pixel circuit driving method includes setting the anode voltage terminal to a high-resistance state and / or setting the cathode voltage terminal to a high-voltage state during a data acquisition phase between a reset phase and a light-emitting phase.

[0114] Understandably, in related technologies, to achieve threshold voltage compensation for the driving transistor, it is usually necessary to introduce an additional compensation transistor. For example, in a typical 7T1C pixel circuit, a dedicated compensation transistor (such as T4) is used to short-circuit the gate and drain of the driving transistor, forming a diode connection during the data writing phase. While this method is effective, it increases the number of transistors in the pixel circuit, thereby increasing the layout area of ​​each pixel unit and limiting further improvements in the pixel density (PPI) of the display panel.

[0115] This embodiment sets the anode voltage terminal to a high-resistance state and / or the cathode voltage terminal to a high-voltage state during the data acquisition phase, enabling the driving transistor to naturally form a diode connection during the data acquisition phase, thereby achieving threshold voltage compensation without the need for additional compensation transistors. This solves the technical problem of ensuring threshold voltage compensation function while simplifying the pixel circuit architecture, achieving the effects of reducing the number of thin-film transistors, increasing pixel density (PPI), and achieving narrow bezels.

[0116] Specifically, during the data acquisition phase, when the anode voltage terminal is set to a high-impedance state, the power supply originally connected to the anode of the light-emitting device no longer provides a stable voltage or current, but instead remains in a floating state. This means that the current path from the source of the driving transistor to the anode voltage terminal is blocked, and no effective driving current can be provided. Alternatively, when the cathode voltage terminal is set to a high-voltage state, it is boosted to a positive voltage higher than the maximum value of the data signal. Under this voltage condition, the light-emitting device is reverse-biased and cut off, blocking the current path from the drain of the driving transistor through the light-emitting device to the cathode voltage terminal.

[0117] When the anode voltage terminal is in a high-resistance state and / or the cathode voltage terminal is in a high-voltage state, the light-emitting device cannot conduct normally even if a data signal is written to the pixel circuit. This power supply configuration utilizes the characteristics of the driving transistor inside the pixel circuit, enabling it to operate in a diode-connected mode during data acquisition. In this mode, the gate potential of the driving transistor adaptively adjusts according to the written data signal and the driving transistor's own threshold voltage. For example, the gate potential of the driving transistor eventually stabilizes at the sum of the data signal voltage and the driving transistor's threshold voltage. This process achieves effective compensation for the driving transistor's threshold voltage, ensuring that even if there are differences in the manufacturing process of the driving transistors in different pixels, their final driving characteristics remain consistent.

[0118] During the light-emitting phase, the anode and cathode voltage terminals return to their normal operating voltages. At this point, the light-emitting device begins to emit light based on its internal potential, which has been compensated during the data acquisition phase. Since the threshold voltage of the driving transistor has been effectively compensated, the magnitude of the current flowing through the light-emitting device will depend solely on the written data signal and is independent of the threshold voltage of the driving transistor itself.

[0119] This application achieves effective compensation of the threshold voltage of the driving transistor without adding additional compensation transistors. Compared to the prior art, which requires a dedicated compensation transistor to short-circuit the gate and drain of the driving transistor to achieve diode connection, this application replaces the function of some transistors by changing the operating mode of the power supply signal, achieving the same circuit function with fewer transistors. This allows the pixel circuit to adopt a simplified 4T1C or 5T1C architecture, significantly reducing the number of thin-film transistors compared to the existing 7T1C architecture. This facilitates accommodating all circuit elements within the limited area of ​​each sub-pixel, thereby improving PPI. Simultaneously, the reduced number of transistors also makes it possible to simplify the design of panel bezel driving circuits (e.g., GIP circuits), thus facilitating the achievement of narrow bezels.

[0120] Furthermore, in order to better implement the pixel circuit in any of the above embodiments, this application proposes a display panel that includes the pixel circuit described above, based on the pixel circuit of the above embodiments.

[0121] Furthermore, in order to better implement the display panel in any of the above embodiments, this application proposes a display device based on the display panel in the above embodiments, which includes the display panel as described above.

[0122] The display device in this embodiment can be a smartphone, tablet computer, laptop computer, desktop computer, in-vehicle display, smartwatch, smart bracelet, virtual reality device or augmented reality device, or other products or components with display functions. Since the display panel in the display device has the beneficial effects of any one or more of the above-mentioned display panels, the specific effects are described in the foregoing embodiments and will not be repeated here.

[0123] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0124] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A pixel circuit, characterized in that, include: A light-emitting device, wherein one end of the light-emitting device is electrically connected to an anode voltage terminal and the other end of the light-emitting device is electrically connected to a cathode voltage terminal; The pixel circuit includes a reset stage, a data acquisition stage, and a light emission stage arranged sequentially. During the data acquisition stage of the pixel circuit, the anode voltage terminal is in a high-resistance state and / or the cathode voltage terminal is in a high-voltage state.

2. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes: A first switching element, one end of which is electrically connected to the anode voltage terminal, and the other end of which is electrically connected to the light-emitting device, is used to conduct during the light-emitting phase to drive the light-emitting device to emit light; The second switch has one end electrically connected to the data signal terminal and the other end connected between the first switch and the anode voltage terminal. The second switch is used to turn on during the data acquisition phase to output a data signal to the first switch. A third switching element, one end of which is electrically connected to the control electrode of the first switching element, and the other end of which is connected between the first switching element and the light-emitting device; During the data acquisition phase, the first switching element is activated based on the data signal. The third switch is used to output a voltage compensation signal when the first switch acquires the data signal; During the light-emitting phase, the first switching element is turned on based on the voltage difference between the voltage compensation signal and the anode voltage signal at the anode voltage terminal.

3. The pixel circuit according to claim 2, characterized in that, The pixel circuit further includes a storage capacitor, one end of which is electrically connected to the anode voltage terminal, and the other end of which is electrically connected to the control electrode of the first switching element. The storage capacitor is used to store the voltage compensation signal during the data acquisition phase and to output the voltage compensation signal to the control electrode of the first switching element during the light emission phase.

4. The pixel circuit according to claim 2, characterized in that, The pixel circuit further includes a fourth switch, one end of which is electrically connected to the initialization voltage terminal, and the other end of which is electrically connected to the control electrode of the first switch. During the reset phase, the fourth switch is used to write the initialization voltage signal of the initialization voltage terminal to the control electrode of the first switch to reset the control electrode of the first switch.

5. The pixel circuit according to claim 4, characterized in that, The pixel circuit is applied on the display panel, and the display panel includes multiple pixel rows; the control electrode of the fourth switch is connected to the first scan signal line, and the control electrodes of the second switch and the third switch are connected to the second scan signal line; The first scan signal line is the scan signal line corresponding to the current nth pixel row, and the second scan signal line is the scan signal line corresponding to the (n+1)th pixel row; Alternatively, the scanning signal on the first scanning signal line is the same global signal output by the display driver integrated circuit of the display panel to multiple pixel rows, and the second scanning signal line is the scanning signal line corresponding to the current pixel row.

6. The pixel circuit according to claim 5, characterized in that, During the reset phase, the fourth switch is turned on based on the scan signal of the first scan signal line, thereby resetting the control electrode of the first switch and / or the anode of the light-emitting device.

7. The pixel circuit according to claim 2, characterized in that, The pixel circuit further includes a fourth switch, one end of which is electrically connected to the initialization voltage terminal, and the other end of which is connected between the third switch and the first switch. During the reset phase, the fourth switch is used to write the initialization voltage signal of the initialization voltage terminal to the control electrode of the first switch through the third switch to reset the control electrode of the first switch.

8. The pixel circuit according to claim 7, characterized in that, The pixel circuit is applied on the display panel, and the display panel includes multiple pixel rows; the control electrode of the fourth switch is connected to the first scan signal line, the control electrode of the third switch is connected to the second scan signal line, and the control electrode of the second switch is connected to the third scan signal line. The first scan signal line is the scan signal line corresponding to the current nth pixel row, the second scan signal line is the scan signal line corresponding to the (n+1)th pixel row, and the third scan signal line is the scan signal line corresponding to the (n+2)th pixel row.

9. The pixel circuit according to any one of claims 4 to 8, characterized in that, The pixel circuit further includes a fifth switch, which is connected in series with the first switch and the light-emitting device between the anode voltage terminal and the cathode voltage terminal; the control electrode of the fifth switch is electrically connected to the light-emitting control signal line, and the fifth switch is used to connect the anode voltage terminal, the first switch, the light-emitting device and the cathode voltage terminal when the light-emitting control signal line outputs a light-emitting control signal.

10. The pixel circuit according to claim 9, characterized in that, The pixel circuit is applied on the display panel, and the display panel includes multiple pixel circuits. The light emission control signal is the same global signal output by the display driver integrated circuit of the display panel to multiple pixel circuits.

11. The pixel circuit according to claim 9, characterized in that, At least one of the first switching device, the second switching device, the third switching device, the fourth switching device, and the fifth switching device is any one of a thin-film transistor, a MOSFET, and a bipolar transistor.

12. The pixel circuit according to any one of claims 1 to 11, characterized in that, Under the high voltage condition, the cathode voltage terminal outputs a preset high voltage, which is higher than the output voltage of the cathode voltage terminal during the light emission stage.

13. A driving method for a pixel circuit, characterized in that, Applied to the pixel circuit as described in any one of claims 1 to 12; The driving method for the pixel circuit includes: During the data acquisition phase between the reset phase and the light emission phase, the anode voltage terminal is set to a high-resistivity state and / or the cathode voltage terminal is set to a high-voltage state.

14. A display panel, characterized in that, The display panel includes the pixel circuitry as described in any one of claims 1 to 12.

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