Mram-based floating-point multiply-accumulate in-memory computing circuit structure and implementation method thereof

Abstract

The application discloses a kind of based on magnetoresistive random access memory (MRAM) floating point multiply-accumulate operation in-memory computing implementation method and its circuit structure.The application is discharged to bit line by being connected in parallel by the unit structure of several integrated MRAM devices and transistor computing column, cooperate capacitor array, realize basic multiply-accumulate computing function;The application is split to floating point multiply-accumulate operation process, and special computing mechanism is designed for the multiply-accumulate operation of floating point mantissa, can support the expansibility application of reconfigurable multi-precision operation under the premise of no additional circuit overhead.The application provides a kind of high-density, high energy efficiency in-memory computing solution for the high-precision floating point matrix operation scene of edge device.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, specifically to an in-memory computing circuit structure for floating-point multiplication and accumulation operations based on MRAM and its implementation method. Background Technology

[0002] With the rapid development of artificial intelligence technology, high-performance AI algorithms, represented by the Transformer model, have been widely applied in fields such as image processing and natural language processing, demonstrating outstanding performance. Simultaneously, this has created an urgent need for energy-efficient matrix operation capabilities. The traditional von Neumann architecture, which separates storage and computation, suffers from a severe "memory wall" bottleneck when handling data-intensive matrix operation tasks. Compute-in-memory (CIM) technology, by integrating computational functions into the edge of the storage array or within storage units, effectively reduces data transfer energy consumption and latency, significantly improving the efficiency of large-scale matrix operations. As algorithm complexity continues to increase, traditional integer operations are gradually failing to meet the precision requirements of data processing, making the exploration of CIM technology for floating-point operations a key research focus.

[0003] Floating-point numbers consist of three parts: a sign bit, an exponent bit, and a mantissa bit. The exponent bit determines the dynamic range of the data, while the mantissa bit determines the precision of the floating-point number. Floating-point multiplication and accumulation operations require a series of steps: unpacking the data, XORing the sign bit, multiplying the mantissa, adding the exponent, and normalizing and encapsulating the data. Compared to integer calculations, this is more complex and difficult to implement.

[0004] Non-volatile memories such as resistive random access memory (ReRAM), phase-change memory (PCM), and magnetoresistive random access memory (MRAM) can achieve persistent data storage without static power consumption, making them suitable for building in-memory computing arrays. Among them, MRAM has advantages such as fast read and write speeds, high durability, and good compatibility with CMOS processes, making it an ideal core device for realizing in-memory computing, especially analog domain in-memory computing (DCIM).

[0005] The core component of MRAM, the Magnetic Tunnel Junction (MTJ), consists of a fixed layer, a tunnel barrier layer, and a free layer. When the free layer and the fixed layer are magnetized in the same direction, the MRAM exhibits a low-resistivity state; when their magnetization directions are opposite, the MRAM exhibits a high-resistivity state. The storage of 0s and 1s is achieved by utilizing these two stable resistance states of the MRAM. Currently, mainstream MRAM-based in-memory computing solutions fall into two main categories: charge-domain and current-domain solutions. The charge-domain solution determines the amount of charge to be applied to the computing capacitor through multiplication calculations, and then performs addition operations through charge sharing and redistribution among the computing capacitors. This solution offers high accuracy, but requires additional transistors to control the charging and discharging of the capacitors. Furthermore, due to the limitation of low TMR (magnetoresistive ratio), to balance analog-to-digital conversion resolution and hardware power consumption, the capacitance of the computing capacitor often needs to be increased, leading to increased cell area and decreased storage and computing density. A typical current-domain scheme represents the result of multiplying and accumulating the input and weights as different current magnitudes. The calculation is completed by discharging the node capacitors with currents of different amplitudes. However, existing schemes are susceptible to errors such as resistance distribution dependence, which cause the readout results to deviate from the ideal results and cause errors. Alternatively, the nonlinear characteristics of analog signals place strict requirements on the design of analog-to-digital conversion circuits, which greatly increases the difficulty of circuit design and implementation cost. Summary of the Invention

[0006] To address the shortcomings of the existing technologies, this invention aims to improve the computational performance of large-scale matrix multiplication. It proposes an in-memory computation method and circuit structure for floating-point multiplication and accumulation operations based on MRAM. The technical solution proposed by this invention is as follows:

[0007] The single bit cell structure designed in this invention is as follows: Figure 1 As shown, the circuit consists of four NMOS transistors and two MTJs. The gate of the first NMOS transistor (N1) is connected to a dedicated control signal Dch, and its drain is connected to the bit line BL. The second NMOS transistor (N2) and the first magnetic tunnel junction (MTJ1) form one branch A, and the third NMOS transistor (N3) and the second magnetic tunnel junction (MTJ2) form another branch B. The two branches are connected in parallel. The source of N1 is connected to the parallel head node X of the two branches, and the drains of N2 and N3 are both connected to the parallel tail node Y. The source of N2 is connected to the top electrode of MTJ1, and the source of N3 is connected to the top electrode of MTJ2. The bottom electrodes of MTJ1 and MTJ2 are connected to the parallel node Y and then to the source line SL through node Y. The gate of N2 is connected to the word line WL, and the gate of N3 is connected to another inverting word line WLB. The fourth NMOS transistor (N4) acts as the write transistor for MTJ2, with its drain connected to the bit line BL, its source connected to the write terminal of MTJ2, and its gate connected to the write control line WWL.

[0008] Basic multiplication operations can be implemented using a single bit cell structure. The following section details its working principle using the basic matrix multiplication scenario of the Transformer model. In this structure, WL and WLB are driven by the input signal Input. When Input=0, WL is pulled high and WLB is pulled low; when Input=1, WLB is pulled high and WL is pulled low. This structure uses the resistance of MTJ as the neural network weight, where MTJ1 is fixed in a low-resistance state and is not written to during storage and computation. The weight data is stored in the resistance state of MTJ2. The final equivalent resistance value exhibited by the bit cell is the output, satisfying the operation Output=Input×Weight. The truth table for input, weight, and output is shown in Table 1, where V... DD R is the voltage value. L Indicates the low-resistance state of MTJ, R H This indicates that the MTJ is in a high-resistance state (the on-resistance of the MOSFET is ignored in an ideal state).

[0009] Table 1

[0010]

[0011] Multiple bit cell structures are connected in parallel to form a computation column, such as Figure 2 As shown, the overall circuit can realize multiplication and accumulation operations by relying on the bit line charging and discharging mechanism. The overall workflow is mainly divided into two working stages—the pre-charging stage and the discharging stage. Before the calculation begins, the weight data to be calculated has been pre-written into the MTJ2 of each bit cell.

[0012] During the pre-charge phase, all NMOS transistors in the turn-off cell structure are switched off, cutting off the cell's conduction path and completing the charging of BL to V. DD The charging voltage source is then disconnected. During the discharge phase, the Dch signal controls N1 to turn on, and controls N2 or N3 to turn on based on the logic state of the input signal Input. The corresponding branch is turned on, and a low-resistance or a high-resistance is introduced into the calculation column of the corresponding group. The equivalent resistance of all bit cells connected in parallel constitutes a total equivalent resistance R. com .

[0013] The parasitic capacitance C of the bit line BL itself res The capacitor array C for the binary weights used in the successive approximation analog-to-digital converter (SAR ADC) for voltage successive approximation. adc Together they form a fixed total capacitance C com BL through R com and C com The RC circuit formed discharges to the source line SL (ground terminal), and the discharge rate is determined by the total equivalent resistance R. comThe resistance value is determined by R. com The resistance value is determined by the number of low-resistance and high-resistance units in the parallel calculation column. When the discharge duration reaches the preset threshold, the Dch signal is set to 0, N1 is turned off, and the discharge terminates. At this time, the stable voltage V of BL... com That is, the output of the multiplication and accumulation operation. sum The analog voltage value is converted from analog to digital to obtain the corresponding digital multiplication and accumulation result. sum .

[0014] As described above, this invention uses a SAR ADC to convert analog voltage to digital signal and relies on a binary-weighted capacitor array for successive voltage approximation. This invention innovatively reuses this capacitor array as the core discharge capacitor in the multiply-accumulate calculation discharge stage, and simultaneously performs precise matching design for bit-line parasitic capacitance, setting the parasitic capacitance of BL to the smallest capacitance unit of the binary-weighted array, i.e., C. adc and C res The following relationship must be satisfied:

[0015]

[0016] In the formula, N represents the number of bits used in the ADC conversion. Capacitor array C adc The upper plate and parasitic capacitance C res The equivalent upper plates are both connected to BL. During the pre-charging phase of the computation column's multiplication and accumulation operations, the upper plates of both are synchronously charged to V. DD During the discharge phase, the upper plates of both electrodes also discharge to ground synchronously, eventually stabilizing at a voltage V. com During the analog-to-digital conversion stage, C adc A portion of the lower electrode plate is connected to a three-way switch. The three-way switch switches the potential of the lower electrode plate according to the result of each stage comparison, thereby regulating the voltage of the upper electrode plate. In conjunction with SAR logic settings, a high-precision successive approximation analog-to-digital conversion process is completed.

[0017] The discharge characteristic formula for an RC circuit is as follows:

[0018]

[0019] V(t) represents the voltage value at time t after discharge, and V0 represents the initial voltage value. As can be seen from the formula, the initial attenuation slope of the RC discharge curve is relatively large, decreasing with time, and the overall voltage exhibits an exponential decay law over time. This invention, by precisely selecting the discharge duration t, extracts an approximately linearly changing voltage range from the discharge curve, allowing the acquired analog voltage value to be compared with the total equivalent resistance and the digital domain summation result. sumAll satisfy a one-to-one correspondence and a linear relationship. This invention generates a narrow pulse control signal Dch through circuits such as a delay chain, so that the discharge voltage of the bit line BL stabilizes within an approximately linear range, which facilitates ADC quantization processing.

[0020] Based on the above circuit structure, the present invention can realize the vector-matrix multiplication operation shown in Formula 3:

[0021]

[0022]

[0023]

[0024]

[0025]

[0026] The following uses the BF16 data format as an example to explain in detail the implementation process of the vector matrix multiplication operation of this invention. The input matrix is ​​split into groups of 16 columns and the weight matrix into groups of 16 rows. Taking the calculation of the output result OUT1 as an example, before starting the operation, the input... ~ Weight ~ After completing the exponent pre-alignment and mantissa shift preprocessing, the processed weighted mantissa bits are then written bit by bit into the bit cells of the array. Specifically, when the mantissa bit is 0, the MTJ2 writes to the low-impedance state R. L When the mantissa is 1, MTJ2 writes to the high-impedance state R. H .

[0027] During the pre-charge phase, all MOSFETs in the bit cell structure are turned off, and the bit line BL voltage is charged to V. DD Total capacitance C com The upper electrode plates also returned to V. DD Each bit line used for computation is independently matched with a set of ADC circuits, and the ADC is in the off state during this stage. After pre-charging, different paths are selected according to the logic state of the corresponding bit of the input signal; the narrow pulse signal Dch controls N1 to conduct for a short time, so that the 16 parallel bit units discharge synchronously to the bit line. At this time, the ADC is still in the off state to avoid interference from the ADC during the discharge process; after the Dch signal is reset to a low level, N1 is turned off, the discharge stops, and the bit line voltage is maintained at the corresponding analog voltage V to be measured. com Turn on the ADC, process the voltage value to obtain the partial output of a single operation. sum1The input and weight signals are processed bit-by-bit according to logic, cycle by cycle, to obtain partial sums with different weights. Finally, the complete vector-matrix multiplication output is obtained through integration processing by external digital circuitry. sum .

[0028] This invention relies on reconfigurable circuit design and uses digital circuit configuration to switch the writing strategy of input and weight data, as well as the integration strategy of staged calculation results. It is compatible with multiplication and accumulation operations of different data formats, including integers and floating-point numbers. Figure 3 Taking a compute cluster containing 8 compute columns as an example, the weight writing scheme under the BF16 data format is shown. Table 2 shows the corresponding input data writing scheme, where IN a,b and W a,b In this context, subscript 'a' represents the data sequence number, and subscript 'b' represents the specific bit sequence number in the mantissa of a single input or weight data (8 bits in total, ranging from 0 to 7); similarly, Figure 4 Taking the same computing cluster as an example, the weight writing scheme for FP8 (E4M3) data format is shown, and Table 3 shows the corresponding input data writing scheme. This invention can be extended to support multiply-accumulate operations in formats such as INT4 / INT8 / FP8 (E5M2) / FP16.

[0029] Table 2

[0030]

[0031] Table 3

[0032]

[0033] This invention allows for the switching of different stage result retention and carry scheme strategies through the logic configuration of external digital circuits, thereby outputting calculation results with varying degrees of precision. Figure 3 Taking the calculation process corresponding to Table 2 as an example, if all parts and results generated by all 8 computation columns in a computation cluster within 8 cycles are retained and integrated, a full-precision calculation result can be obtained. If only the first computation column participates in the operation of cycle 1, the second computation column only participates in the operation of cycles 1 and 2, and so on, with the eighth computation column participating in the operation of all 8 cycles, and the corresponding parts and results are retained and integrated, a coarse-precision calculation result can be obtained. Through the design of other different schemes, results with more different precision can be obtained.

[0034] Based on the above vector-matrix multiplication mechanism, the complete matrix multiplication operation can be implemented through matrix decomposition, that is, the high-order matrix multiplication is split into multiple sets of parallel vector-matrix multiplier operations, and the overall matrix operation is completed through array parallel computing capabilities.

[0035] The advantages of this invention, compared to existing solutions, are as follows:

[0036] This invention optimizes the structure of the computation column and computation unit, avoiding the need for a reference column in traditional solutions, reducing circuit area overhead, and effectively reducing the impact of MOS transistor parameters and resistance distribution-dependent errors on the operation of the in-memory computing unit, thus significantly improving accuracy and stability. By reusing the function of the same capacitor array, this invention reduces hardware area while eliminating independent sampling timing, effectively compressing sampling time. Through precise discharge timing control and time interception strategies, this invention significantly reduces the design complexity, area, and energy consumption of the back-end ADC circuit. Based on the array structure, combined with digital circuit control input and data configuration schemes and result integration schemes, this invention allows for flexible adaptation to various data formats and multiplication-accumulation operation scenarios of different precisions using the same circuit without additional overhead. This invention provides a new high-density, high-efficiency, and highly adaptable in-memory computing solution for high-precision floating-point matrix operations. Attached Figure Description

[0037] Figure 1 This is a structural diagram of a single bit cell used in this invention to implement in-memory calculations for floating-point multiplication and accumulation operations.

[0038] Figure 2 This is a diagram of a single-path computation column structure for implementing in-memory floating-point multiplication and accumulation operations, as described in this invention. It includes multiple such... Figure 1 The parallel bit unit, capacitor array, and the rest of the SAR ADC circuit are shown.

[0039] Figure 3 This document provides an example of the weight writing scheme under the BF16 data format of the present invention, using a computing cluster as an example.

[0040] Figure 4 The weight writing scheme under the FP8 (E4M3) data format of the present invention is illustrated with an example of a computing cluster. Detailed Implementation

[0041] The present invention will be further described in detail below through specific embodiments.

[0042] The overall computing array constructed in this invention comprises 8×8 computing clusters, each capable of performing computational tasks independently and in parallel. Each computing cluster consists of 8 computational columns, each computational column as follows: Figure 2 As shown, it contains 16 parallel units, as... Figure 1 The bit cell structure shown is matched with a successive approximation analog-to-digital converter.

[0043] Example 1

[0044] Taking vector-matrix multiplication as an example, the matrix operation parameters are set to m=128 and n=64. The input data IN and the weight data W are both in BF16 floating-point data format.

[0045]

[0046] Before starting the calculation, Divide the data into 8 groups of 16 columns each. Divide the data into 8 groups of 16 rows each, and perform exponent pre-alignment and mantissa shift operations on each group. ~ Processed mantissa reference Figure 3 The scheme shown is to write bit by bit into the computing cluster CIM. 1,1 When the mantissa of the weight in the bit cell of the array is 0, MTJ2 writes to R. L When the mantissa of the weight is 1, MTJ2 writes to R H .

[0047] After the operation begins, it first enters the pre-charging phase and then shuts down. Figure 1 All MOS transistors in the bit cell structure shown are charged to V by the bit line voltage. DD The corresponding ADC is in the off state; after the pre-charge is completed, N2 and N3 select to turn on and off according to the logic state of the corresponding bit of the input data, thereby switching different paths. The narrow pulse signal of Dch controls N1 to turn on briefly, the bit line discharges, the voltage decays, and the ADC is still in the off state; after the Dch signal is reset to a low level, the discharge is cut off, the ADC is turned on, and the measured voltage V of the bit line is stabilized. com Modular-to-digital conversion is performed to obtain the partial result and the final result of a single operation.

[0048] According to the scheme shown in Table 2, the bits of the input signal with different weights are traversed through the timing cycle to obtain multiple sets of operational sums corresponding to different weights. The output is then processed by the external digital circuitry. psum1,1 Simultaneously, the computational cluster CIM 1,2 Synchronous generation of Output psum1,2 ..., Output psum1,n Output is obtained through back-end digital circuit integration and processing. 1,1 Further processing yields Out1.

[0049] The remaining output results are calculated and processed using the same procedure described above.

[0050] Example 2

[0051] Taking vector-matrix multiplication as an example, the matrix operation parameters are set to m=128 and n=128. The input data IN and the weight data W both adopt the FP8 (E5M3) floating-point data format.

[0052]

[0053] Before starting the calculation, Divide the data into 8 groups of 16 columns each. Divide the data into 8 groups of 16 rows each, and perform exponent pre-alignment and mantissa shift operations on each group. ~ and ~ Processed mantissa reference Figure 4 The scheme shown is to write bit by bit into the computing cluster CIM. 1,1 When the mantissa of the weight in the bit cell of the array is 0, MTJ2 writes to R. L When the mantissa of the weight is 1, MTJ2 writes to R H .

[0054] After the operation begins, it first enters the pre-charging phase and then shuts down. Figure 1 All MOS transistors in the bit cell structure shown are charged to V by the bit line voltage. DD The corresponding ADC is in the off state; after the pre-charge is completed, N2 and N3 select to turn on and off according to the logic state of the corresponding bit of the input data, thereby switching different paths. The narrow pulse signal of Dch controls N1 to turn on briefly, the bit line discharges, the voltage decays, and the ADC is still in the off state; after the Dch signal is reset to a low level, the discharge is cut off, the ADC is turned on, and the measured voltage V of the bit line is stabilized. com Modular-to-digital conversion is performed to obtain the partial result and the final result of a single operation.

[0055] According to the scheme shown in Table 3, the bits of the input signal with different weights are traversed through the timing cycle to obtain multiple sets of operational sums corresponding to different weights. The output is then processed by the external digital circuitry. psum1,1 and Output psum1,2 Simultaneously, the computational cluster CIM 1,2 Generate Output psum1,3 and Output psum1,4 ..., Output psum1,n Output is obtained through back-end digital circuit integration and processing. 1，1 Further processing yields Out1.

[0056] The remaining output results are calculated and processed using the same procedure described above.

[0057] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Those skilled in the art can modify or make equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention. The protection scope of the present invention should be determined by the claims.

Claims

1. A floating-point multiplication-accumulation in-memory computing circuit structure based on MRAM, characterized in that, The computation column is composed of multiple parallel bit cells. With the help of a dedicated control circuit and a successive approximation analog-to-digital converter (SAR ADC), the multiplication and accumulation operation is realized through RC circuit discharge. It includes four NMOS transistors and two magnetic tunnel junctions MTJ, namely the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, the first magnetic tunnel junction MTJ1, and the second magnetic tunnel junction MTJ2. Among them, MTJ1 is fixed in a low-resistance state and its state remains unchanged during reading, writing, and calculation. The first NMOS transistor N1 has its gate connected to a dedicated control signal Dch, its drain connected to bit line BL, and its source connected to parallel node X. The second NMOS transistor N2 and MTJ1 form branch A, and the third NMOS transistor N3 and MTJ2 form branch B. Branches A and B are connected in parallel and their top ends are connected to parallel node X. The gate of the second NMOS transistor N2 is connected to word line WL, and the gate of the third NMOS transistor N3 is connected to the inverting word line WLB. The bottom electrodes of MTJ1 and MTJ2 are connected to parallel node Y, which is connected to the source line SL. The fourth NMOS transistor N4 is a dedicated write transistor, with its drain connected to bit line BL, its source connected to the write terminal of MTJ2, and its gate connected to write control line WWL. The discharge capacitor of the RC circuit is all the capacitors connected to the bit line BL, including the binary weighted capacitor array C used by the SAR ADC for successive approximation. adc Parasitic capacitance C of bit line BL res The C res As the smallest capacitance unit of a binary weighted capacitor array, C adc With C res It satisfies the mathematical matching relationship of ADC bit width.

2. The in-memory computing circuit structure for floating-point multiplication and accumulation operations based on MRAM according to claim 1, characterized in that, Multiple computing columns are integrated to form computing clusters, and multiple computing clusters form a complete computing array; a single computing cluster contains 8 computing columns, and a single computing column is configured with 16 sets of parallel bit cell structures and independently matched with a SAR ADC; the computing array is an 8×8 array arrangement of computing cluster structures, used to implement multi-channel parallel vector matrix multiplication operations.

3. A method for implementing in-memory calculation of floating-point multiplication and accumulation operations based on MRAM, applied to the circuit structure described in claims 1-2, characterized in that, Includes the following steps: S1. Input and weight preprocessing: Before the operation begins, the floating-point format input data and weight data are grouped according to the strategy corresponding to the specific data format and the exponent pre-alignment and mantissa shift operation are completed. The mantissa of the weight after the operation is written into the corresponding bit unit bit by bit. If the mantissa bit is 0, it is written into the low impedance state, and if the mantissa bit is 1, it is written into the high impedance state. S2, Pre-charge phase: Turn off all NMOS transistors in the bit cell, disconnect the cell's conduction path, and charge the bit line BL (including the upper plate of the capacitor array connected to BL and the equivalent upper plate of the parasitic capacitance of BL) to the operating voltage V. DD During this stage, the SAR ADC is turned off; S3, Discharge Stage: The conduction branch is switched according to the logic level of the input signal Input. When Input is 0, the N2 branch is turned on, and when Input is 1, the N3 branch is turned on. The narrow pulse Dch signal generated by the delay chain circuit turns on N1 for a short time, so that the total equivalent resistance of the parallel bit units and the total capacitance on BL form an RC discharge circuit, and the bit line BL discharges to ground. When the Dch signal is set to 0, N1 is turned off to terminate the discharge. During this stage, the SAR ADC remains off. S4. Analog-to-digital conversion stage: After setting the Dch signal to 0 and turning off N1, the bit line voltage stabilizes at the analog voltage under test, V. com Enable the SAR ADC to perform analog-to-digital conversion on the voltage value and obtain the partial result and outcome of a single calculation. S5. Result Integration Stage: Input different input signals and weight bits cycle by cycle according to the writing strategy corresponding to the data format, obtain multiple sets of partial sums, complete the accumulation, calibration and integration through the array external digital circuit, and output the final floating-point multiplication and accumulation operation result.

4. The method for implementing in-memory calculation of floating-point multiplication and accumulation operations based on MRAM according to claim 3, characterized in that, During the discharge phase, the narrow pulse discharge duration is determined by observing and calculating the RC discharge curve, and the approximate linear interval of the RC discharge curve is accurately extracted. This ensures that the extracted stable value of the measured voltage and the result of the multiplication and accumulation operation maintain a linear mapping relationship, while the overall trend is linear, thus reducing the complexity of ADC design.

5. The method for implementing in-memory calculation of floating-point multiplication and accumulation operations based on MRAM according to claim 3, characterized in that, The capacitor array and parasitic capacitance of the bit line connection are fully reused, which not only undertakes the voltage successive approximation function of SAR ADC analog-to-digital conversion, but also serves as the discharge capacitor for multiply-accumulate operations, realizing the reuse of hardware resources.

6. The method for implementing in-memory calculation of floating-point multiplication and accumulation operations based on MRAM according to claim 3, characterized in that, The method switches carry operation strategies through external digital circuits, retains a portion of the corresponding cycle and inputs the operation results into subsequent digital circuits for integrated processing, and adapts to multiple working modes such as full-precision operation output and coarse-precision operation output.

7. The method for implementing in-memory calculation of floating-point multiplication and accumulation operations based on MRAM according to claim 3, characterized in that, The method uses an external digital circuit to switch the writing strategy of input and weight data, and completes the writing of different bits in different periods. Combined with the integration strategy of staged calculation results, it is compatible with multiply-accumulate operations of multiple data formats, including FP8 (E4M3), FP8 (E5M2), BF16, FP16, INT4, INT8 and other data formats, without the need for additional hardware circuit overhead to reconstruct the array.

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