Refresh method of memory and memory system

Abstract

The application provides a refresh method of a memory and a memory system. The memory comprises a plurality of memory array blocks. A length of time between two adjacent operations performed on a same target memory array block is recorded as an operation interval time. A frequency of the operation on the target memory array block is divided into a plurality of levels based on the length of the operation interval time, and each level comprises a first level to an Nth level, wherein N is an integer greater than or equal to 2. The refresh method comprises: in a use process, accumulating a number of occurrences of each level in the plurality of levels respectively; and performing a data refresh operation on a memory cell in the target memory array block in response to at least one of M accumulated conditions being met. In this way, the operation interval time is monitored, and the frequency of the refresh is dynamically adjusted, so that the write disturbance (WD) can be alleviated, and the wear of the memory included in the memory system can also be reduced.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a memory refresh method and memory system. Background Technology

[0002] Memory is the foundation of information technology. Phase-change memory (PCM) has attracted widespread attention due to its advantages such as high-speed read / write cycles, high erasure / write cycles, non-volatility, small component size, low power consumption, and resistance to strong shocks and radiation, especially 3D PCM. Therefore, using PCM as the storage unit in high-capacity memory systems has become a trend. However, write disturbance (WD) is a significant problem in PCM. Frequent refreshes of the PCM to manage WD accelerate its wear and tear. Summary of the Invention

[0003] This application provides a memory refresh method and memory system that can alleviate WD (wear and tear) and also reduce PCM wear caused by frequent refreshes.

[0004] On one hand, this application provides a method for refreshing a memory, the memory including multiple memory array blocks, each memory array block including multiple memory cells; the time length between two consecutive operations performed on the same target memory array block is denoted as the operation interval time; based on the length of the operation interval time, the frequency of operations on the target memory array block is divided into multiple levels, wherein the multiple levels include a first level to a Nth level, where N is an integer greater than or equal to 2, and the shorter the operation interval time, the higher the corresponding level; the refresh method includes: during use, accumulating the occurrence count of each of the multiple levels; in response to at least one of M accumulation conditions being met, performing a data refresh operation on the memory cells in the target memory array block; wherein M is less than or equal to N, and the i-th accumulation condition is that the cumulative sum from the occurrence count corresponding to the first level to the occurrence count corresponding to the i-th level is greater than the i-th threshold, where i is an integer between 1 and M, and the i-th threshold increases as i increases.

[0005] In the above scheme, N is 3, and the multiple levels are respectively the first level, the second level, and the third level; M is 3, and the M cumulative conditions are respectively the first cumulative condition, the second cumulative condition, and the third cumulative condition; the refresh method further includes: accumulating the number of occurrences of the first level, denoted as the first cumulative value; accumulating the number of occurrences of the second level, denoted as the second cumulative value; accumulating the number of occurrences of the third level, denoted as the third cumulative value; determining whether at least one of the following three cumulative conditions is satisfied: the first cumulative condition: whether the first cumulative value is greater than a first threshold; the second cumulative condition: whether the sum of the first cumulative value and the second cumulative value is greater than a second threshold; the third cumulative condition: whether the sum of the first cumulative value, the second cumulative value, and the third cumulative value is greater than a third threshold; wherein, the first threshold is less than the second threshold, and the second threshold is less than the third threshold.

[0006] In the above scheme, two adjacent operations are respectively the first operation and the second operation, with the first operation preceding the second operation; the refresh method further includes: recording the end time of the first operation and recording the start time of the second operation; determining the length of the time difference between the start time and the end time, and recording it as the operation interval time.

[0007] In the above scheme, the refresh method includes: in response to the operation interval time being less than or equal to a first time length, assigning the operation frequency level to a first level; in response to the operation interval time being less than a second time length and greater than the first time length, assigning the operation frequency level to a second level; and in response to the operation interval time being greater than or equal to the second time length, assigning the operation frequency level to a third level.

[0008] In the above scheme, the refresh method further includes: during the use process, if the operation interval time recorded each time is less than or equal to the first time length, the first cumulative value is incremented by 1; if the operation interval time recorded each time is less than the second time length and greater than the first time length, the second cumulative value is incremented by 1; if the operation interval time recorded each time is greater than or equal to the second time length, the third cumulative value is incremented by 1.

[0009] In the above scheme, the refresh method further includes: in response to at least one of the M cumulative conditions being met, performing a data refresh operation on all storage cells in the target storage array block.

[0010] In the above scheme, the refresh method further includes: after each data refresh operation is completed for all storage units in the target storage array block, resetting the cumulative occurrence count of each of the multiple levels to 0.

[0011] In the above scheme, the storage unit is a phase-change storage unit.

[0012] In the above scheme, the operation is a write operation, which includes a set operation and / or a reset operation.

[0013] On the other hand, embodiments of this application provide a memory system including a memory and a controller coupled to the memory, wherein the controller is configured to perform a refresh method as described in any of the preceding claims.

[0014] The embodiments of this application have the following beneficial effects: the frequency of operations is divided into multiple levels based on the length of the operation interval between two adjacent operations, and the occurrence of each level is accumulated during use. M accumulation conditions are designed based on the occurrence of multiple levels, and if at least one of the M accumulation conditions is met, a data refresh operation is performed on the storage cells in the specified storage array block (i.e., the target storage array block). In this way, by dynamically monitoring the operation interval, WD can be classified and managed to alleviate WD, and the wear and tear on the memory contained in the memory system caused by frequent refresh can also be reduced. Attached Figure Description

[0015] Figure 1 This is a functional block diagram of the memory system provided in the embodiments of this application; Figure 2 This is a functional block diagram of the peripheral circuit of the phase-change memory provided in the embodiments of this application; Figure 3 This is a circuit diagram of the storage array of the phase-change memory provided in the embodiments of this application; Figure 4 This is a schematic diagram of the structure of the phase-change memory unit provided in the embodiments of this application. Figure 1 ; Figure 5 This is a schematic diagram of the structure of the phase-change memory unit provided in the embodiments of this application. Figure 2 ; Figure 6 This is a flowchart illustrating the memory refresh method provided in the embodiments of this application. Figure 1 ; Figure 7 This is an exemplary schematic diagram of two adjacent operations provided in an embodiment of this application; Figure 8 This is a flowchart illustrating the memory refresh method provided in the embodiments of this application. Figure 2 .

[0016] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] It should be understood that when one component is "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe the relationships between components should be interpreted in a similar way.

[0019] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform bonding structure with a thickness less than the thickness of the bonding structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers, as well as one or more dielectric layers.

[0020] It should be noted that the illustrations provided in the embodiments of this application are only schematic representations of the basic concept of this application. Although the illustrations only show components relevant to this application and are not drawn according to the actual number, shape, and size of components in implementation, the shape, quantity, and proportion of each component in actual implementation can be arbitrarily changed, and the component layout may also be more complex. This application uses Cartesian coordinates to represent directions. With the substrate as the reference, "Z" represents the first direction, which is perpendicular to the substrate; "X" represents the second direction parallel to the substrate; and "Y" represents the third direction parallel to the substrate and perpendicular to "X".

[0021] See Figure 1 This illustrates a functional block diagram of a memory system provided in an embodiment of this application. For example... Figure 1The memory system 10 provided in this embodiment may include a controller 100 and a memory 200. The controller 100 is electrically connected to the memory 200 and configured to control the memory 200. The memory 200 may include peripheral circuitry 201 and a memory array 202. The peripheral circuitry 201 controls the memory array 202, and can control each memory cell (see below) in the memory array 202. Figure 4 It can perform various operations, such as write operations, read operations, etc.

[0022] In some embodiments, the memory system 10 may be implemented as a memory module, a solid-state drive (SSD), a high-bandwidth memory (HBM), universal flash storage (UFS), a multimedia card (MMC), an embedded multimedia card (eMMC), or a reduced-size multimedia card (RS). MMC (Reduced Size Multi MediaCard) and Micro MMC, Secure Digital (SD) cards, Mini SD, Micro SD, PCMCIA (Personal Computer Memory Card International Association) card type storage devices, Peripheral Component Interconnect (PCI) type storage devices, High Speed ​​PCI (or PCI) type storage devices. Storage devices of type E (Peripheral Component Interconnect Express), such as Compact Flash (CF) cards, Smart Media Cards, or Memory Sticks.

[0023] See Figure 2 This shows a functional block diagram of the memory. For example... Figure 2As shown, the memory 200 may include a memory array 202 and peripheral circuitry 201. The peripheral circuitry 201 may include a row decoder 2011, a word line voltage generator 2012, a word line driver 2013, a column decoder 2014, a bit line voltage generator 2015, a reference current / voltage generator 2016, a sensitive amplifier comparator 2017, a bit line driver 2018, a data latch 2019, a bus 2020, an I / O interface 2021, and a logic control module 2022. The row decoder 2011 receives row address signals from the bus 2020 and decodes the row address signals to select the address word lines. Here, the word line driver 2013 is connected to multiple word lines WL<0:m>, the word line voltage generator 2012, and the row decoder 2011. The word line driver 2013 receives the row address select signal and the word line drive voltage, and outputs the word line drive voltage to multiple word lines WL according to the row address select signal. <m>At least one word line WL in the memory is connected to at least one row of memory cells. The bit line driver 2018, bit line voltage generator 2015, and column decoder 2014 belong to the column driver circuit and are as follows: Figure 2 The connections are shown. The bit line voltage generator 2015 and column decoder 2014 are connected to the logic control module 2022 to receive control from the logic control module 2022. The column decoder 2014 receives the column address signal and decodes it to select the address bit line connected to the target memory cell. The bit line voltage generator 2015 generates the voltage required for each selected bit line BL and outputs the set voltage to each corresponding selected bit line BL. The bit line driver 2018 is connected to multiple bit lines BL, the bit line voltage generator 2015, and the column decoder 2014. The bit line driver 2018 receives the bit line voltage and the column address selection signal, and outputs the set bit line voltage to the multiple bit lines BL according to the column address selection signal. <n>At least one column of memory cells is connected by at least one bit line BL.

[0024] The sensitive amplifier comparator 2017 is connected to the reference current / voltage generator 2016 and multiple bit lines BL<0:n>, and is also connected to the data latch 2019. When reading data, the sensitive amplifier comparator 2017 compares the received data with the reference value generated by the reference current / voltage generator 2016 to determine the data stored in the selected memory cell. The data is then stored in the data latch 2019 and, together with the data read from other bit lines, is output to the data bus 2020 via the input / output I / O interface 2021.

[0025] Based on the aforementioned structural design of the peripheral circuit 201 of the memory, operations on the memory 200 can include erase operations, read operations, and programming operations, or write operations (including set operations and reset operations). Furthermore, during these operations, the controller 100 receives logical address information according to a logical address to physical address (L2P) mapping table, and then sends out the physical address (or actual address) according to the L2P mapping table. After receiving the actual address, the peripheral circuit 201 selects appropriate word lines WL and bit lines BL through row decoder 2011 and column decoder 2014 to address the memory cells in the memory array 202. Then, it biases the selected word lines WL and bit lines BL through word line driver 2013 and bit line driver 2018 to perform various operations on the selected memory cells. Moreover, in some embodiments, during addressing, logical addresses are arranged in the order of word line WL and bit line BL addresses, for example... Figure 3 As shown, a storage array 202 will first address on a WL, traverse different BLs, and then switch to the next WL for addressing.

[0026] In some embodiments, the storage array 202 may include a plurality of storage cells arranged in a multi-row, multi-column array, and word lines WL and bit lines BL connecting the plurality of storage cells in multiple rows and columns on a plane. Each row of storage cells includes a plurality of storage cells arranged along the row direction. Each column of storage cells includes a plurality of storage cells arranged along the column direction (i.e., the second direction). In other embodiments, the storage array 202 may include a plurality of storage array blocks, each storage array block including at least one storage cell.

[0027] It should be understood that the memory cells in the memory array 202 can be memory cells of various structures, such as floating gate memory cells, ONO memory cells, resistive RAM (RRAM) memory cells, phase change memory cells (PCM / PCRAM / SOM), etc. This application does not limit them, but this application is particularly applicable to phase change memory cells. Therefore, the following will use phase change memory cells as an example for illustration, but it should be understood that it is not limited thereto.

[0028] For example, please continue to refer to Figure 3 , Figure 3 A circuit diagram of an example of a memory array 202 provided according to some embodiments of this application. Figure 3 The illustrated memory array 202 may include a plurality of phase-change memory cells 301 arranged in a multi-row, multi-column array, and word lines WL and bit lines BL connecting the plurality of phase-change memory cells 301 in multiple rows and columns on a plane. Each row of phase-change memory cells 301 includes a plurality of phase-change memory cells 301 arranged along the row direction. Each column of memory cells includes a plurality of phase-change memory cells 301 arranged along the column direction (i.e., the second direction). It should be understood that... Figure 3 Only three lines of WLn are shown. 1~WLn+1 and three columns BLn The memory unit 200 contains a range of 1 to BLn+1, where n represents any positive integer greater than 2. In practice, the number of rows and columns of phase-change memory units in the memory 200 depends on its storage capacity.

[0029] Please continue reading Figure 3 As shown, the storage array 202 can be divided into four storage array blocks by two dashed lines, namely storage array block A, storage array block B, storage array block C, and storage array block D. Each storage array block includes at least one phase-change memory cell 301. It should be understood that... Figure 3 Only four memory array blocks are shown; the actual number of memory array blocks contained in memory array 202 depends on the capacity of memory 200.

[0030] Please continue reading Figure 3 As shown, the phase-change memory unit 301 may include a bidirectional threshold switch 3011 and a phase-change memory element 3012 connected in series between the word line WL and the bit line BL. The bidirectional threshold switch 3011 and the phase-change memory element 3012 are both made of phase-change material.

[0031] Regarding the structure of the phase-change memory cell 301, see some embodiments. Figure 4 As shown, it illustrates an exemplary structure of a phase-change memory cell. It should be noted that... Figure 4 This is a partial three-dimensional structural diagram of a three-dimensional phase-change memory array. Each memory group may contain two phase-change memory cells 301, one above the other, sharing the same word line. Each phase-change memory cell 301 may include a top electrode 401 and a bottom electrode 402 connected to the WL direction in the X direction and the BL direction in the Y direction, respectively, and a phase-change memory element 3012 located between the top electrode 401 and the bottom electrode 402 in the Z direction, an intermediate electrode 403, and a bidirectional threshold switch 3011. It should be understood that in some embodiments, the intermediate electrode 403 may be omitted; therefore, this application does not limit the structure of the phase-change memory cell 301. The phase-change memory element 3012 may include, for example, germanium-based... antimony Tellurium (Ge Sb One or more phase change materials (PCDs) can be selected from materials containing Te, such as Ge2Sb2Te5. PCDs can exhibit a large resistivity contrast between different phases (e.g., crystalline and amorphous phases). For example, a PCD may exhibit relatively low resistivity in a crystalline phase but relatively high resistivity in an amorphous phase, and the resistivity of the PCD in the amorphous phase can be hundreds to thousands of times higher than that in the crystalline phase. When heated, the PCD can switch between different phases to enable the writing of information (data) (including setting and resetting). In some embodiments, the top electrode 401 and the intermediate electrode 403 can heat the PCD memory element 3012 via a bidirectional threshold switch 3011 to change the phase of the heated region 404 in the PCD memory element 3012, thereby reducing the resistance of the PCD memory element 3012 (setting). The top electrode 401 and the bottom electrode 402 are arranged opposite to each other, and their positions can be interchanged and overlapped with the outer bit line BL and word line WL to form a three-dimensional (3D) phase change memory.

[0032] In some embodiments, the bidirectional threshold switch 3011 is made of, for example, Ge Te As When the phase change material is composed of Si, the threshold voltage Vth of the bidirectional threshold switch 3011 will change under the control of the applied voltage polarity. More specifically, the threshold voltage ΔVth changes with the change of the applied voltage polarity. Using this ΔVth, even without the phase change memory element 3012, setting and resetting can still be achieved. The bidirectional threshold switch 3011 can be used independently as a binary storage device; therefore, in this example, the bidirectional threshold switch 3011 is referred to as Selector Only Memory (SOM) or Self-Select Memory (SSM). (Selecting Memory). Therefore, it can be understood that the phase change memory (PCM) described in this application may include various modified PCMs, such as Xpoint type PCMs, and SOMs or SSMs composed of the aforementioned OTSs, and may include various phase change memories arranged in two-dimensional (2D) and three-dimensional (3D) configurations, as well as PCMs with single-level or multi-level storage.

[0033] It should be noted that the upper and lower phase-change memory cells 301 in the memory array 202 can also share a bit line; see the specific structure for details. Figure 5 This shows another exemplary three-dimensional partial schematic diagram of the word line and bit line of the phase change memory unit 301 provided in an embodiment of the present invention.

[0034] In some embodiments of this application, when performing read / write operations on a phase-change memory cell 301, for example... Figure 3 The phase-change memory cell 301(S) applies a higher voltage bias, such as Vhh and VII, to the corresponding selected WLn (word line) and BLn (bit line); for the unselected WLn+1 / n... 1 and BLn+1 / n 1. Maintain zero or low bias voltage, for example, apply Vuw and Vub respectively, to ensure a non-conductive state.

[0035] In other embodiments of this application, for example, selecting the... Figure 3 When performing a write operation on phase-change memory cell 301(S), a write voltage Vwrite is applied to the selected BLn (bit line), and a zero bias voltage V0 is applied to WLn (word line); for unselected adjacent phase-change memory cells 301(a) and 301(b), a write voltage Vwrite is applied to the corresponding word line and bit line WLn+1 / n. 1 and BLn+1 / n A low bias voltage, such as Vwrite / 2, is applied to phase-change memory (PCM) cell 301. Under this write operation, other unselected PCM cells 301 on the same WLn and BLn as the selected PCM cell 301(S), although not selected for conduction or writing, will still have a certain bias voltage across them. These PCM cells 301 will experience bias drift. This is the threshold voltage drift caused by the bias voltage on the same bit line word line affecting other memory cells, also known as bias drift (WD). In other words, WD can refer to the heat generated during a write operation on a PCM cell (especially a high-current reset operation, i.e., changing the cell from a crystalline to an amorphous state), which can unexpectedly affect the state of adjacent memory cells that should not be operated on. This phenomenon can corrupt the correctness of the data already stored in adjacent cells, leading to data errors. In reality, the damage of WD to adjacent PCM cells is slowly cumulative. If the data of the affected cell is actively read and rewritten (i.e., refreshed) before the accumulated amount reaches the error threshold, its correct state can be restored. Therefore, it is necessary to perform a data refresh operation on the relevant phase change memory cell 301 under certain conditions or for a certain period of time. The refresh operation is essentially a rewrite, which restores the phase change memory cell to a very clear crystalline or amorphous state, eliminating the errors accumulated by previous interference.

[0036] However, further research in this application revealed that frequent refreshes of the phase-change memory cells 301 in the memory 200 by WD management will accelerate the wear and tear of the memory 200 and affect its lifespan. In other words, frequent refreshes of the memory 200 at a fixed refresh rate will accelerate the aging of the memory 200. Therefore, WD's management needs to consider the impact on the lifespan of the memory 200.

[0037] To address the aforementioned problems, this application provides a memory refresh method. First, the time interval between two consecutive operations on the same target memory array block is denoted as the operation interval. Based on the length of the operation interval, the frequency of operations on the target memory array block is divided into multiple levels, including levels one through N, where N is an integer greater than or equal to 2, and the shorter the operation interval, the higher the corresponding level. Then, during use (i.e., during normal operation of the memory system 10), the occurrence frequency of each level is accumulated, and M accumulation conditions are set. When at least one of the M accumulation conditions is met, a data refresh operation is performed on the memory cells in the target memory array block. In this way, the operation interval is monitored, and the refresh frequency is dynamically adjusted, which can alleviate write interference (WD) and also reduce the frequency of memory refreshes, thereby reducing memory wear.

[0038] Specifically, see Figure 6 It illustrates a flowchart of the memory refresh method provided in an embodiment of this application. Figure 1 .like Figure 6 As shown, the refresh method may include steps 601 to 602.

[0039] Step 601: During use, accumulate the number of occurrences of each of the multiple levels.

[0040] Step 602: In response to the fulfillment of at least one of the M cumulative conditions, perform a data refresh operation on the storage cells in the target storage array block; wherein, M is less than or equal to N, and the i-th cumulative condition is the cumulative sum of the occurrence counts from the first level to the i-th level being greater than the i-th threshold, i is an integer between 1 and M, and the i-th threshold increases as i increases.

[0041] It should be noted that further research in this application revealed a correlation between the impact of write operations (WD) and the interval between write operations. Specifically, the longer the interval between two adjacent operations on a memory array block, the smaller the impact of WD. In light of this phenomenon, embodiments of this application propose monitoring the interval between two adjacent operations on a memory array block and setting a series of cumulative conditions to determine the timing of data refresh operations. This dynamically adjusts the refresh frequency of the target memory array block, thereby reducing its refresh rate. Here, the target memory array block can be any one of the plurality of memory array blocks. In other words, by refreshing each memory array block using the aforementioned refresh method, the refresh frequency of each memory array block can be reduced, thus reducing wear and tear on the memory.

[0042] In some embodiments, the operation may be a write operation, wherein the write operation may include the aforementioned set operation and / or reset operation.

[0043] In other embodiments, two adjacent operations are respectively a first operation and a second operation, with the first operation preceding the second operation; the refresh method may further include: recording the end time of the first operation and recording the start time of the second operation; determining the length of the time difference between the start time and the end time, and recording it as the operation interval time.

[0044] For example, such as Figure 7 As shown, the two adjacent operations can be a first operation op1 and a second operation op2, respectively, with the first operation op1 preceding the second operation op2. Further, as... Figure 7 As shown, the operation interval time This can refer to the length of the time difference between the start time T_Start of the second operation and the end time T_End of the first operation. Specifically, the time length between T_End and T_0 is the execution time of the first operation op1, and the time length between T1 and T_Start is the execution time of the second operation op2.

[0045] In some embodiments, the start time T_Start and the end time T_End are stored in register 1 and register 2, respectively. During normal operation of the memory system 10, whenever a write operation is completed, the end time T_End of that write operation is recorded and stored in register 2; and for the next write operation, the start time T_Start of that next write operation is recorded and stored in register 1. It should be noted that the updates to the start time T_Start in register 1 and the updates to the end time T_End in register 2 may be asynchronous. The end time T_End in register 2 is updated after the current write operation is completed. However, the update to the start time T_Start in register 1 waits until the next write operation begins; therefore, the updates to register 1 and register 2 are asynchronous.

[0046] In some embodiments, the end time T_End can be the system time at which the write pulse application is completed, as confirmed by the controller 100. The start time T_Start can be the system time at which the controller 100 issues the write pulse for the next write operation.

[0047] It should be noted that the controller 100 internally includes a crystal oscillator, which can generate stable electrical pulse signals at a fixed frequency. Each electrical pulse signal constitutes one clock cycle. The controller 100 can obtain the system time by recording the number of electrical pulse signals and multiplying this number by the clock cycle. That is, the end time T_End can be obtained by the controller 100 by obtaining the current number of electrical pulse signals when the write pulse time is completed, and then using the current number equal to the clock cycle to obtain the system time when the write pulse application is completed. The start time T_Start can also be obtained in the aforementioned manner, and will not be repeated here.

[0048] In some embodiments, the first operation and the second operation may be for the same storage cell in the target storage array block or for different storage cells in the target storage cell block.

[0049] In some embodiments, the plurality of levels may include a first level to an Nth level, where N is an integer greater than or equal to 2, and the shorter the operation interval, the higher the corresponding level.

[0050] It should be noted that the shorter the operation interval, the more frequent the operations on the target storage array block. In this case, the impact of WD is greater. Therefore, data refresh operations on the storage cells in the target storage array block need to be performed as early as possible, resulting in a higher corresponding level. That is, the levels from the first level to the Nth level decrease sequentially.

[0051] In some embodiments, the cumulative condition is a condition for determining whether to perform a data refresh operation on the target storage array block. Furthermore, a data refresh operation can be performed on the target storage array block when at least one of the M cumulative conditions is true. Here, M is less than or equal to N, and the i-th cumulative condition is that the cumulative sum of the occurrence counts from the first level to the i-th level is greater than the i-th threshold, where i is an integer between 1 and M, and the i-th threshold increases as i increases.

[0052] It should be noted that when M is less than M, only the Mth level participates in setting the cumulative conditions. That is, only the first M levels out of N levels participate in setting the cumulative conditions; levels M+1 to N do not. When N equals M, both the first and Mth levels participate in setting the cumulative conditions. The following explanation uses N equal to M as an example to illustrate the setting and use of cumulative conditions.

[0053] That is, in some embodiments, N can be 3, and the multiple levels are respectively a first level, a second level, and a third level; M can be 3, and the M cumulative conditions are respectively a first cumulative condition, a second cumulative condition, and a third cumulative condition. Based on this, the refresh method may further include: accumulating the number of occurrences of the first level, denoted as a first cumulative value C_fast; accumulating the number of occurrences of the second level, denoted as a second cumulative value C_med; accumulating the number of occurrences of the third level, denoted as a third cumulative value C_slow; and determining whether at least one of the following three cumulative conditions is satisfied: the first cumulative condition: whether the first cumulative value is greater than a first threshold TH1; the second cumulative condition: whether the sum of the first cumulative value C_fast and the second cumulative value C_med is greater than a second threshold TH2; and the third cumulative condition: whether the sum of the first cumulative value C_fast, the second cumulative value C_med, and the third cumulative value C_slow is greater than a third threshold TH3; wherein, the first threshold TH1 is less than the second threshold TH2, and the second threshold TH2 is less than the third threshold TH3.

[0054] In some embodiments, for the settings of the first level, the second level, and the third level, the refresh method may include: responding to the operation interval time. If the operation frequency is less than or equal to the first time length L1, the operation frequency is assigned to the first level; in response to the operation interval time If the operation interval is less than the second time length L2 and greater than the first time length L1, the operation frequency is assigned to the second level; in response to the operation interval time If the frequency of the operation is greater than or equal to the second time length L2, the frequency level of the operation is assigned to the third level.

[0055] In some embodiments, the refresh method may further include, for the calculation of the first cumulative value, the second cumulative value, and the third cumulative value, the method comprising: recording the operation interval time each time during the usage process. If the first cumulative value is less than or equal to the first time length L1, the first cumulative value is incremented by 1; the operation interval time recorded each time. If the time interval is less than the second time length L2 and greater than the first time length L1, the second cumulative value is incremented by 1; the operation interval time recorded each time. If the third cumulative value is greater than or equal to the second time length L2, then the third cumulative value is incremented by 1.

[0056] In some embodiments, the refresh method may further include: performing a data refresh operation on all storage cells in the target storage array block in response to at least one of the M cumulative conditions being met. It should be noted that, based on the foregoing description, the storage cells corresponding to the write operations for each accumulation of the first cumulative value, the second cumulative value, and the third cumulative value cannot be distinguished as belonging to any specific storage cell in the target storage array block. Therefore, when at least one of the M cumulative conditions is met, a data refresh operation is performed on all storage cells in the target storage array block.

[0057] In some embodiments, the refresh method may further include: after each data refresh operation is completed on all storage cells in the target storage array block, resetting the cumulative occurrence count of each of the plurality of levels to 0.

[0058] It should be noted that, To understand this application, as Figure 8 The diagram illustrates a flowchart of a memory refresh method provided in an embodiment of this application. Figure 2 It should be noted that, in Figure 8 In this context, N=M=3. The refresh method provided in this application embodiment may include the following steps.

[0059] Step 801: The first cumulative value C_fast, the second cumulative value C_med, and the third cumulative value C_slow are reset to 0.

[0060] Step 802: After the (i-1)th write operation to the target storage array block ends, record the end time T_End of the (i-1)th write operation.

[0061] Step 803: At the start of the i-th write operation on the target storage array block, record the start time T_Start of the i-th write operation.

[0062] Step 804: Obtain the operation interval between the start time T_Start and the end time T_End. That is, T_Start - T_End, and determine the operation interval. The level.

[0063] Step 805: If it is the operation interval time For the first level, the first cumulative value is increased by 1.

[0064] Step 806 is the operation interval time For the second level, the second cumulative value is increased by 1.

[0065] Step 807: If it is the operation interval time For the third level, the third cumulative value is increased by 1.

[0066] Step 808: Determine whether at least one of the following three cumulative conditions is satisfied: First cumulative condition: whether the first cumulative value is greater than the first threshold TH1; Second cumulative condition: whether the sum of the first cumulative value C_fast and the second cumulative value C_med is greater than the second threshold TH2; Third cumulative condition: whether the sum of the first cumulative value C_fast, the second cumulative value C_med, and the third cumulative value C_slow is greater than the third threshold TH3.

[0067] Step 809: If yes, perform a data refresh operation on all storage cells in the target storage array block, and return to re-execute steps 801 to 809. If no, return to re-execute the judgment of steps 802 to 809.

[0068] Based on this, WD devices can be categorized and managed relatively easily based on the intervals between operations, reducing the frequency of refreshes. Compared to traditional solutions, this mitigates the additional wear and tear caused by frequent WD refreshes.

[0069] Based on the memory refresh methods provided in the foregoing embodiments, some embodiments of this application also provide a corresponding method such as... Figure 1 and Figure 5 The memory system 10 shown may include: a memory and a controller 100 coupled to the memory, wherein the controller 100 is configured to perform the refresh method as described above.

[0070] It should be noted that the phase-change memory is an example of the aforementioned memory 200. The steps of the refresh method in the memory system 10 are described in detail in the corresponding refresh method described above, and can be implemented in conjunction with the controller 100 and firmware, so they will not be repeated here. Please refer to the previous description for details.

[0071] The memory system 10 provided in this application embodiment can also classify and manage WD by dynamically monitoring the operation interval time, thereby alleviating WD and reducing wear and tear on the memory contained in the memory system caused by frequent refreshes.

[0072] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.< / n> < / m>

Claims

1. A method for refreshing a memory, characterized in that, The memory includes multiple memory array blocks, and each memory array block includes multiple memory cells; the time between two consecutive operations performed on the same target memory array block is denoted as the operation interval time. The frequency of operations on the target storage array block is divided into multiple levels based on the length of the operation interval. These multiple levels include levels one through N, where N is an integer greater than or equal to 2. The shorter the operation interval, the higher the corresponding level. The refresh method includes: During use, the number of occurrences of each of the multiple levels is accumulated. In response to the fulfillment of at least one of the M cumulative conditions, a data refresh operation is performed on the storage cells in the target storage array block; wherein M is less than or equal to N, and the i-th cumulative condition is that the cumulative sum of the occurrence counts from the first level to the i-th level is greater than the i-th threshold, i is an integer between 1 and M, and the i-th threshold increases as i increases.

2. The refresh method according to claim 1, characterized in that, N is 3, and the multiple levels are respectively the first level, the second level, and the third level; M is 3, and the M cumulative conditions are the first cumulative condition, the second cumulative condition, and the third cumulative condition, respectively. The refresh method further includes: The cumulative number of occurrences of the first level is recorded as the first cumulative value; The cumulative number of occurrences of the second level is recorded as the second cumulative value; The cumulative number of occurrences of the third level is recorded as the third cumulative value; Determine whether at least one of the following three cumulative conditions is satisfied: The first cumulative condition: whether the first cumulative value is greater than the first threshold; The second cumulative condition: whether the sum of the first cumulative value and the second cumulative value is greater than the second threshold; The third cumulative condition is whether the sum of the first cumulative value, the second cumulative value, and the third cumulative value is greater than a third threshold. Wherein, the first threshold is less than the second threshold, and the second threshold is less than the third threshold.

3. The refresh method according to claim 2, characterized in that, Two adjacent operations are respectively the first operation and the second operation, with the first operation preceding the second operation; the refresh method further includes: Record the end time of the first operation and the start time of the second operation; The length of the time difference between the start time and the end time is determined and denoted as the operation interval time.

4. The refresh method according to claim 2, characterized in that, The refresh method includes: In response to the operation interval being less than or equal to a first time length, the frequency of the operation is assigned a first level; In response to the operation interval being less than the second time length and greater than the first time length, the operation frequency is assigned a second level; In response to the operation interval being greater than or equal to the second time length, the operation frequency is assigned a third level.

5. The refresh method according to claim 4, characterized in that, The refresh method further includes: During the usage process, if the recorded operation interval is less than or equal to the first time length, the first cumulative value is incremented by 1; If the interval between each recorded operation is less than the second time length but greater than the first time length, the second cumulative value is incremented by 1. If the interval between each recorded operation is greater than or equal to the second time length, the third cumulative value is incremented by 1.

6. The refresh method according to claim 2, characterized in that, The refresh method further includes: in response to at least one of the M cumulative conditions being met, performing a data refresh operation on all storage cells in the target storage array block.

7. The refresh method according to claim 6, characterized in that, The refresh method further includes: after each data refresh operation is completed on all storage units in the target storage array block, resetting the cumulative occurrence count of each of the multiple levels to 0.

8. The refresh method according to any one of claims 1 to 7, characterized in that, The storage unit is a phase-change storage unit.

9. The refresh method according to claim 8, characterized in that, The operation is a write operation, which includes a set operation and / or a reset operation.

10. A memory system, characterized in that, include: A memory and a controller coupled to the memory, wherein the controller is configured to refresh the memory by performing a refresh method as described in any one of claims 1 to 9.

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