SLC flash memory adaptive data correction method and system based on block-level lifetime evaluation

Abstract

The application discloses a kind of SLC flash memory adaptive data error correction method and system based on block level life evaluation, obtains the current erase-write cycle number and historical write speed of the flash memory block in target single-layer cell flash memory, determines life stage by wear classification processing and preset mapping relation table inquiry, extracts historical error quantity to calculate error probability, determines error correction intensity according to the comparison result of error probability and preset probability threshold value, to generate initial coding rule to encode target write data to obtain first check information, account the redundant space occupied by first check information, determine target redundancy according to the comparison result of redundant space and preset space threshold value and re-encode to obtain second check information, and merge target write data stream with target write data.The application realizes that error correction intensity and flash memory block life state dynamically match, and improves single-layer cell flash memory full life cycle data storage reliability.

Description

Technical Field

[0001] This invention relates to the field of intelligent chip storage reliability technology, specifically to an adaptive data error correction method and system for SLC flash memory based on block-level lifetime assessment. Background Technology

[0002] Single-Level Cell (SLC) flash memory is widely used in demanding fields such as industrial control and automotive electronics due to its advantages of fast read / write speeds and high stability. Existing SLC flash memory controllers generally employ a BCH encoding scheme with fixed error correction capabilities during the data writing process, generating verification information uniformly for the flash memory block according to the factory-set error correction bit depth.

[0003] BCH encoding schemes with fixed error correction capabilities are designed for consumer-grade storage scenarios where the bit error rate is stable at the time of manufacture, and the number of error correction bits is calibrated once based on the error rate at the time of manufacture. However, in scenarios such as smart chips, the insulating oxide layer of the flash memory block gradually degrades with the accumulation of erase and write cycles. The bit error probability within the flash memory block is low in the early stages but rises sharply in the later stages. The number of error correction bits calibrated once cannot dynamically keep up with the aging process. Although increasing the number of error correction bits can cover the increased error rate in the later stages, the length of the parity bit also increases. However, the parity information can only be stored in the spare area of ​​the physical page with a fixed capacity at the time of manufacture. With the increase in the number of error correction bits, the parity information is likely to exceed the available space in the spare area, resulting in write failure.

[0004] Therefore, existing technologies suffer from the problem that the error correction strength cannot be adjusted as the flash memory block ages, resulting in insufficient data storage reliability of a single-layer cell flash memory throughout its entire lifecycle. Summary of the Invention

[0005] The purpose of this invention is to provide an adaptive data error correction method and system for SLC flash memory based on block-level lifetime assessment, so as to solve the problem that the error correction intensity cannot be adjusted with the aging process of the flash memory block, resulting in insufficient data storage reliability of single-layer cell flash memory throughout its entire life cycle.

[0006] In a first aspect, the present invention provides an adaptive data error correction method for SLC flash memory based on block-level lifetime assessment, comprising: Obtain the current erase / write cycle count and historical write speed of the flash memory block in the target single-layer cell flash memory; The wear level of the flash memory block is obtained by classifying wear based on the current erase / write cycle count and the historical write speed, and the lifespan stage of the flash memory block is determined by querying a preset mapping table according to the wear level. The number of historical errors of the flash memory block is extracted according to the lifetime stage, the error probability of the flash memory block in the lifetime stage is calculated based on the number of historical errors, and the error correction intensity is determined based on the comparison result of the error probability and the preset probability threshold. An initial encoding rule matching the flash memory block is generated based on the error correction strength, and the target written data is encoded using the initial encoding rule to obtain the first verification information; The redundant space occupied by the first verification information in the flash memory block is calculated. The target redundancy is determined based on the comparison result between the redundant space and the preset space threshold. The target write data is re-encoded according to the target redundancy to obtain the second verification information. The second verification information and the target write data are merged to obtain the target write data stream.

[0007] In a second aspect, the present invention provides an SLC flash memory adaptive data error correction system based on block-level lifetime assessment, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the SLC flash memory adaptive data error correction method based on block-level lifetime assessment as described above.

[0008] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the SLC flash memory adaptive data error correction method based on block-level lifetime assessment as described above.

[0009] Compared with the prior art, the present invention has the following beneficial effects: (1) The present invention uses the current number of erase / write cycles and the historical write speed of the flash memory block as input to classify wear and map it to the life stage. Then, the error probability is calculated from the number of historical errors in the life stage. This makes the error correction strength based on the actual degradation data at the block level rather than using the fixed configuration calibrated once at the factory. The error correction capability is improved synchronously with the aging process of the flash memory block, avoiding the omission of error correction due to insufficient error correction bits in the aged flash memory block, thereby improving the data storage reliability of the single-layer cell flash memory throughout its entire life cycle.

[0010] (2) After generating the first verification information, the present invention first calculates the redundant space occupied by the verification information according to the physical page capacity, the minimum programming unit and the available storage unit, and then determines the target redundancy based on the comparison result of the redundant space and the preset space threshold and re-encodes it, so that the encoding strength is adjusted back according to the real physical layout before writing, and avoids the verification information from exceeding the available range of the spare area and failing to be written.

[0011] (3) The present invention weights the initial error frequency by a preset smoothing coefficient and then converts it into an error probability by a probability conversion function, so that the burst read and write load in a single statistical period does not increase the error correction intensity; and calculates the data interleaving depth according to the data length ratio to interleave the target written data and the second verification information, so that the verification information is distributed in a dispersed manner on the physical storage unit, thereby improving the ability to correct burst bit errors. Attached Figure Description

[0012] Figure 1 This is a flowchart illustrating an adaptive data error correction method for SLC flash memory based on block-level lifetime assessment, provided in an embodiment of the present invention.

[0013] Figure 2 This is a schematic diagram of flash memory block wear classification for an SLC flash memory adaptive data error correction method based on block-level lifetime assessment, provided in an embodiment of the present invention.

[0014] Figure 3 This diagram illustrates the error probability of a flash memory block in an SLC flash memory adaptive data error correction method based on block-level lifetime assessment, as provided in an embodiment of the present invention.

[0015] Figure 4 This is a schematic diagram of the redundancy space for verification information in an SLC flash memory adaptive data error correction method based on block-level lifetime assessment, provided in an embodiment of the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] like Figure 1 As shown, an embodiment of the present invention provides an adaptive data error correction method for SLC flash memory based on block-level lifetime assessment, including steps S11 to S15: S11, obtain the current erase / write cycle count and historical write speed of the flash memory block in the target single-layer cell flash memory; S12, the wear level of the flash memory block is obtained by performing wear classification processing based on the current erase / write cycle count and the historical write speed, and the lifespan stage of the flash memory block is determined by querying a preset mapping table according to the wear level; S13, extract the number of historical errors of the flash memory block according to the lifespan stage, calculate the error probability of the flash memory block in the lifespan stage based on the number of historical errors, and determine the error correction intensity based on the comparison result of the error probability and the preset probability threshold. S14, Generate an initial encoding rule matching the flash memory block according to the error correction strength, and encode the target written data using the initial encoding rule to obtain the first verification information; S15, calculate the redundant space occupied by the first verification information in the flash memory block, determine the target redundancy based on the comparison result of the redundant space and the preset space threshold, re-encode the target write data according to the target redundancy to obtain the second verification information, and merge the second verification information with the target write data to obtain the target write data stream.

[0018] In step S11, the current erase / write cycle count and historical write speed of the flash memory block in the target single-layer cell flash memory are obtained, including: The erase count field in the block-level metadata area maintained by the flash translation layer of the target single-layer cell flash memory is read to obtain the current erase / write cycle number; The cumulative amount of data written and the cumulative writing time of the flash memory block are collected according to a preset statistical period. The historical write speed is calculated based on the cumulative amount of data written and the cumulative write time.

[0019] Specifically, the insulating oxide layer of a single-cell flash memory is subjected to high-voltage electron tunneling during each erase and programming operation. The accumulated tunneling forms trapped charges in the oxide layer, which reduces the ability to retain floating gate charges. This degradation is irreversible and the degradation process varies from flash memory block to flash memory block.

[0020] It should be noted that the flash translation layer, located between the host file system and the flash physical array, is responsible for logical address mapping, garbage collection, and wear leveling, and maintains a block-level metadata area for each flash block. The erase count field increments by one time after each block erase operation. Each block erase operation corresponds to one complete erase / write cycle; therefore, the erase count field value represents the cumulative number of erase / write cycles since the flash block was manufactured, characterizing its P / E cycle life. In a specific example, the erase count field value of a flash block reads as 65000, meaning the current erase / write cycle count is 65000.

[0021] The preset statistical period is the time interval at which the flash memory controller performs block-level data aggregation; in this embodiment, it is set to 3600 seconds. A period that is too short will result in insufficient write samples and speed estimation will be affected by large single-block writes; a period that is too long will make it difficult to track load changes and the write speed will lag behind the actual state. Setting it to 3600 seconds allows the cumulative write volume per cycle to reach gigabyte levels under typical industrial control loads; the value range is 600 to 7200 seconds.

[0022] Within each preset statistical period, the flash memory controller accumulates the total number of data bytes written by all programming operations on the flash memory block to obtain the cumulative written data volume, and accumulates the time from the issuance of the programming instruction to the return of readiness in the status register for each programming operation to obtain the cumulative write time. Dividing the cumulative written data volume by the cumulative write time yields the historical write speed.

[0023] In a specific example, the capacity of the flash memory block is 16 megabytes. A certain flash memory block completes 100 erase-write cycles within a preset statistical period, writing the entire block of data each time. The cumulative amount of data written is 16 megabytes multiplied by 100, which is 1600 megabytes. The cumulative writing time is 100 seconds. Dividing these values, the historical writing speed is 16 megabytes per second.

[0024] It should be noted that the historical write speed can reflect the degree of degradation because after the accumulation of oxide layer trap charge, the number of programming pulses required to charge the floating gate to the target threshold voltage increases, the programming verification cycle is prolonged, and the programming time per unit data volume increases, which macroscopically manifests as a decrease in write speed. Using both the current erase / write cycle count and the historical write speed as inputs for wear classification processing can avoid misjudging lightly loaded, long-life flash memory blocks when relying solely on the erase / write cycle count.

[0025] In step S12, the wear level of the flash memory block is obtained by classifying wear based on the current erase / write cycle count and the historical write speed. The lifespan stage of the flash memory block is then determined by querying a preset mapping table according to the wear level, including: A feature vector is constructed based on the current erase / write cycle count and the historical write speed; The feature vector is input into a preset wear classification model for classification processing to obtain the wear level label of the flash memory block, and the wear degree of the flash memory block is determined according to the wear level label; The stage identifier code corresponding to the wear level is extracted by querying the preset mapping table, and the life stage of the flash memory block is determined according to the stage identifier code.

[0026] It should be noted that wear level and lifespan stage are two different objects generated sequentially in this step and cannot be used interchangeably. Wear level is a degradation grade obtained by classifying operational data, characterizing the degree of wear on the component; lifespan stage is a lifespan interval obtained by mapping wear level, characterizing its position within its usable lifespan. The former is the classification result, while the latter is the stage assignment obtained by looking up a table.

[0027] The criteria for classifying the two are also different: the wear level is based on online measurable operational characteristics, determined by the current erase / write cycle count and historical write speed through a branch threshold, without needing prior knowledge of the nominal total erase / write cycle count; the lifespan stage is based on the proportion of remaining lifespan calibrated offline, with the interval boundary defined by the factory calibration experiment according to the proportion of remaining erasable / write cycles to the nominal total erase / write cycle count. The purpose of the preset mapping table is to convert the wear level determined by online operational characteristics into a lifespan interval with the same calibrated range as the factory calibration, ensuring that the statistical interval boundary for subsequent historical error extraction is consistent with the factory calibration experiment.

[0028] It should be noted that the correspondence between wear level and stage identification code is assigned separately for each chip model, and is not a constant, step-by-step correspondence: when the nominal total number of erase / write cycles is different, the remaining lifespan ratio corresponding to the same wear level label changes accordingly, and the corresponding stage identification code is also adjusted accordingly. The nominal total number of erase / write cycles used in this embodiment is 75,000.

[0029] Specifically, the feature vector is constructed by concatenating the current erase / write cycle count and the historical write speed in a fixed order. The first component is the current erase / write cycle count, and the second is the historical write speed. The total dimension of the vector is 2. Following the example above, the feature vector is (65000, 35). The first component is in units of times and on the order of tens of thousands, while the second component is in units of megabytes per second and on the order of tens. Although the dimensions and orders of magnitude of the two components are different, this embodiment does not require normalization or standardization because the following preset wear classification model compares each component to its own specific threshold to complete the branch judgment, without performing weighted summation or distance calculation. Therefore, the difference in order of magnitude will not amplify or obscure any component.

[0030] The preset wear classification model is a decision tree model, with a structure of a binary tree of depth 2: the root node compares the first component of the feature vector with a preset number of write cycles, the two child nodes compare the second component with a preset speed threshold, and the four branches converge into four leaf nodes, which output wear level labels for the initial, stable, transitional, and decay stages, respectively. The input of the preset wear classification model is a feature vector composed of the current number of erase / write cycles and the historical write speed, and the output is the wear level label. During the model training phase, accelerated aging experimental data of the same type of flash memory is used for labeling, and the wear level labels are divided according to the remaining number of erase / write cycles. During the online operation phase, classification is completed only based on the input features.

[0031] The training data for the model was taken from accelerated aging test records of the same model of single-layer cell flash memory chip. Each sample contains two features: the current number of erase / write cycles and the historical write speed, as well as a manually labeled wear level. The label was determined as follows: the accelerated aging test continuously erased and wrote each flash memory block until it was judged as a bad block, and the cumulative number of erase / write cycles at the time of failure was recorded; the remaining number of erase / write cycles at a certain sampling point is equal to the cumulative number of erase / write cycles at the time of failure minus the number of cycles already completed at that sampling point, that is, the number of erase / write cycles that can be tolerated before the final failure at that sampling point.

[0032] The sample label is determined by the ratio of the remaining number of erasable and rewritable cycles at the sampling point to the nominal total number of erasable and rewritable cycles: a ratio higher than 60% is labeled as the initial wear level, 40% to 60% as the stable wear level, 20% to 40% as the transition wear level, and less than 20% as the degradation wear level.

[0033] The model is trained using a classification and regression tree algorithm, selecting splitting features and splitting points layer by layer based on minimizing the Gini index. Training terminates when the tree depth reaches 2, the number of leaf node samples is less than 500, or the Gini index decrease during a single split is less than 0.01; splitting stops when any one of these conditions is met. During the usage phase, the feature vector is input from the root node, compared layer by layer along the branch nodes, and the wear level label is output at the leaf node.

[0034] It should be noted that the preset number of times threshold and the preset speed threshold are the split points determined in two dimensions in the above training process. In this embodiment, they are 60,000 times and 40 megabytes per second, respectively.

[0035] The calibration samples were obtained from accelerated aging test records of the same model of single-layer cell flash memory chips under two ambient temperatures of 25 degrees Celsius and 85 degrees Celsius, and under two types of loads of sequential write and random write. The exclusion conditions were to exclude flash memory blocks marked as bad blocks at the factory and records of power loss during erasure or programming. The sample size was 120 flash memory blocks, with 1,000 sampling points collected from each block, for a total of 120,000 samples. The quantity was based on the fact that the decision tree needs to locate a split point in each of the two dimensions to form 4 partition regions. Based on the assumption that each region should have no less than 500 samples, at least 2,000 samples were required. The 120,000 samples ensured that the sample size of each region exceeded the lower limit by two orders of magnitude, and the relative fluctuation of repeated calibration of the two split points was less than 2%.

[0036] In a specific example, the feature vector (65000, 35) is input into a preset wear classification model. The root node compares the values ​​and finds that 65000 is greater than the preset number threshold of 60000, so it moves to the right child node. The right child node compares the values ​​and finds that 35 is less than the preset speed threshold of 40, so it falls into the leaf node that outputs the decay stage wear level label. Based on this, the wear degree of the flash memory block is determined to be at the decay stage level.

[0037] For example, Figure 2 This is a schematic diagram of flash memory block wear classification. The diagram shows the classification results of the initial, stable, transitional and decay phases corresponding to the current erase / write cycle count and historical write speed. The classification accuracy of the test set is 97.64%.

[0038] The preset mapping table stores the correspondence between wear levels and stage identifier codes. In this embodiment, it contains four rows: the initial wear level corresponds to stage identifier code 1, and the stable period, transition period, and decay period correspond to 2, 3, and 4 respectively. The stage identifier code is an enumeration encoding of the lifespan stages by the flash memory controller firmware. The values ​​1 to 4 represent the initial, stable, transition, and decay periods respectively, and are stored in the block-level metadata area as 1 byte, which facilitates subsequent table lookup by code without the need to transmit strings.

[0039] The mapping table is established based on the factory calibration experiment: the flash memory blocks of the same batch are erased and written throughout their entire life cycle until failure. The remaining number of erasable and rewritable cycles at each sampling point is calculated according to the same measurement method in step S12. The proportion of the remaining number of erasable and rewritable cycles corresponding to each wear level to the nominal total number of erasable and rewritable cycles is statistically analyzed. A proportion higher than 60% is classified as the initial stage, 40% to 60% as the stable stage, 20% to 40% as the transition stage, and less than 20% as the decay stage. The correspondence between wear level and stage identification code is solidified accordingly. The calibration sample consists of 120 flash memory blocks of the same batch. The arrangement conditions and quantity are based on the wear classification model in step S12.

[0040] Following the example above, the preset mapping table is queried based on the wear level during the degradation period. The corresponding stage identifier code is 4, which determines that the flash memory block is in the degradation period. Continuous physical degradation is grouped into discrete lifespan stages, so that the extraction of subsequent historical error counts has clear statistical interval boundaries, avoiding the distortion of error probability caused by mixed statistics across degradation levels.

[0041] In step S13, the number of historical errors of the flash memory block is extracted according to the lifetime stage, the error probability of the flash memory block in the lifetime stage is calculated based on the number of historical errors, and the error correction intensity is determined based on the comparison result of the error probability and a preset probability threshold, including: Extract the number of historical errors corresponding to each error type in the flash memory block during the lifespan stage, and sum the historical error numbers according to a preset error weight to obtain the weighted total number of errors; The initial error frequency is calculated based on the weighted total number of errors and the total number of read / write operations and erase operations of the flash memory block during the lifetime stage. Obtain the historical smoothing frequency corresponding to the previous preset statistical period, and calculate the smoothed error frequency by weighting the initial error frequency and the historical smoothing frequency according to the preset smoothing coefficient. The error probability of the flash memory block during its lifetime is calculated by inputting the smoothed error frequency into a preset probability conversion function.

[0042] Specifically, the historical error count is derived from the block-level error log maintained by the flash memory controller. During the error correction decoding of each read operation, the write verification of each programming operation, and the erase verification of each erase operation, the flash memory controller counts failure events by type and writes them to the block-level error log, while also recording the stage identifier code at the time the event occurred. During extraction, the current stage identifier code is used as the filtering condition to retrieve the accumulated historical error count for each error type since entering the stated lifespan stage.

[0043] This embodiment distinguishes three error types: read interference errors, which refer to bit flips that cause the target memory cell threshold voltage to drift due to repeated readings of adjacent word lines; programming failure errors, which refer to the failure to charge the memory cell to the target threshold voltage even after the maximum number of pulses in the programming verification cycle; and erase failure errors, which refer to the detection of incompletely erased memory cells after block erasure. In a specific example, the number of read interference errors, programming failure errors, and erase failure errors extracted from the flash memory block during the decay period was 150, 12, and 3 respectively.

[0044] It should be noted that the three error types pose different threats to data reliability. Simply adding them together would mask the weight of serious errors. Therefore, a weighted sum is calculated based on preset error weights. The formula for calculating the total weighted error count is as follows: ; In the formula, The weighted total number of errors is dimensionless and is measured in terms of the equivalent number of errors, with a value ranging from 0 to 100,000. In this embodiment, it is 240. The number of error types is dimensionless and ranges from 2 to 8; in this embodiment, it is 3. For the first The preset error weights corresponding to the error types are dimensionless and range from 1 to 20. In this embodiment, read interference error is set to 1, programming failure error is set to 5, and erase failure error is set to 10. For the first The number of historical errors of the type of error during the said lifespan stage, in units of times, with a value range of 0 to 10000. In this embodiment, the numbers are 150, 12, and 3 respectively.

[0045] The preset error weights are determined by the ratio of the conditional probability that each type of error will cause data to be unrecoverable: read interference errors can be recovered by adjusting the read voltage and retrying, so a base weight of 1 is taken; programming failure errors require the data to be rewritten to a spare page, and the data will be lost if power is lost during the rewriting process. The measured conditional probability of it causing an unrecoverable read error is about 5 times that of read interference errors, so 5 is taken; erase failure errors mean that the flash memory block has degenerated into a bad block, and the measured conditional probability is about 10 times that of read interference errors, so 10 is taken.

[0046] The calibration samples were all error events recorded in accelerated aging experiments of single-layer cell flash memory chips of the same model. The inclusion and exclusion conditions were to include only records that completed a full readback verification within 24 hours after the event occurred, and to exclude records that were powered off or interrupted during the verification period. The sample size was 8,600 error events. The weights were determined by the ratio of the conditional probabilities of the three types of errors. The erase failure error, which had the smallest sample size, accounted for about 1%, corresponding to 86 errors. The relative standard error of its conditional probability was estimated to be about 11% according to the binomial distribution. The weight ratio obtained from this was less than 1 and did not affect the rounding of the weights.

[0047] Specifically, the total number of read and write operations is taken from the read and write count field in the block-level metadata area, and the number of erase operations is taken from the erase count field. The statistical range of both is consistent with the number of historical errors, and both are cumulative values ​​after entering the stated lifespan stage. The initial error frequency is obtained by dividing the weighted total number of errors by the sum of the total number of read and write operations and the number of erase operations, with the ratio truncated at the upper limit in the range of 0 to 1.

[0048] It should be noted that the total number of weighted errors, after being amplified by a preset error weight, can exceed the sum of the total number of read / write operations and the number of erase operations under extreme error-intensive conditions. Therefore, the above ratio must be truncated with an upper limit of 1 to ensure that the initial error frequency remains constant within the range of 0 to 1, thus connecting with the value range of subsequent smoothing and probability conversion. In a specific example, the total number of read / write operations and the number of erase operations in the flash memory block during the decay period are 80,000 and 500, respectively. Dividing 240 by 80,500 yields 0.0030, which is less than 1 and does not require truncation; that is, the initial error frequency is 0.0030.

[0049] It should be noted that the daily read / write load of flash memory blocks is prone to sudden changes, and the initial error frequency within a single preset statistical period is easily affected by concentrated read / write operations, deviating from the true level. Therefore, a historical smoothing frequency is introduced for weighted smoothing. The historical smoothing frequency is the smoothed error frequency calculated and stored in the block-level metadata area in the previous preset statistical period. When the flash memory block first enters a certain lifespan stage, this frequency is filled with the initial calibration value for that stage. The initial calibration value is the average error frequency measured when entering that stage, calibrated by stage according to the factory aging test. The formula for calculating the smoothed error frequency is: ; In the formula, The smoothed error frequency is dimensionless and ranges from 0 to 1; in this embodiment, it is 0.0028. The preset smoothing coefficient is dimensionless and ranges from 0.2 to 0.8; in this embodiment, it is 0.5. The initial error frequency is dimensionless and ranges from 0 to 1; in this embodiment, it is 0.0030. The historical smoothing frequency is dimensionless and ranges from 0 to 1; in this embodiment, it is 0.0026. The smoothing coefficient is determined based on the range of error frequency changes within the historical statistical period and is selected while ensuring the continuity of adjacent statistical periods. The specific value is obtained through statistical analysis of historical operating data.

[0050] The preset smoothing coefficient is determined based on the equivalent average window length: the equivalent window length for exponential smoothing is equal to 2 divided by the smoothing coefficient and then minus 1. When the coefficient is 0.5, the equivalent window is 3 preset statistical periods, meaning that the current period's measured value and the historical values ​​of the previous 2 periods jointly determine the result. If the value is too large, the smoothing effect will be insufficient, and sudden load increases will affect the result; if the value is too small, it will lag behind the degradation trend, and the increase in the error rate of aging blocks will not be reflected in time. A value of 0.5 balances both. The engineering calibration uses the historical error frequency sequence accumulated from the block-level error log as a sample. After removing records from power outage periods, the coefficient is searched based on the criterion of minimizing the mean square error of one-step prediction. In this embodiment, the search result is 0.5.

[0051] Specifically, the preset probability transformation function multiplies the smoothed error frequency by the error growth coefficient corresponding to the current lifetime stage, and then truncates it to the upper limit within the range of 0 to 1 to obtain the error probability of the flash memory block in the lifetime stage. The calculation formula is as follows: ; In the formula, The error probability is dimensionless and ranges from 0 to 1; in this embodiment, it is 0.0029. The smoothed error frequency is dimensionless and ranges from 0 to 1; in this embodiment, it is 0.0028. This is the error growth coefficient corresponding to the lifespan stage of the flash memory block. It is dimensionless and ranges from 1.00 to 1.50. In this embodiment, the decay stage is taken as 1.05. The upper bound truncation ensures that the error probability always falls within the range of 0 to 1: In this embodiment, the product of 0.0028 and 1.05 is 0.0029, which is less than 1, so no truncation is required.

[0052] The reason for introducing the error growth factor is that the smoothed error frequency is statistically analyzed based on the number of read and write operations, reflecting the density of errors that have occurred; the error probability needs to reflect the possibility that the next written data will be corrupted during the retention period. For the same error density, the later the lifetime stage, the stronger the temporal clustering of errors and the higher the possibility that a single codeword will suffer multiple bit errors.

[0053] It should be noted that the error growth coefficient is an empirical mapping coefficient calibrated from historical samples, not a rigorous conversion relationship derived from probability theory. Its input is the smoothed error frequency calculated based on the number of operations, and its output is an engineering estimate of the codeword-level error risk. The calibration method is as follows: at each lifespan stage, the smoothed error frequency and the measured codeword-level error rate of the same type of flash memory block are statistically analyzed, and the median of the ratio is taken as the error growth coefficient for that stage. Correspondingly, the error probability is an engineering estimate obtained according to the above empirical mapping, and is only used to compare with a preset probability threshold to select the error correction intensity level.

[0054] The error growth coefficient is assigned a value based on the stage identifier code, with stage identifier codes 1 to 4 taking values ​​of 1.00, 1.02, 1.03, and 1.05 respectively, ranging from 1.00 to 1.50. The calibration sample consists of 12,000 codeword-level readback records measured at each lifespan stage, excluding bad blocks and power-loss records. The quantity is based on ensuring that the estimated relative fluctuation of the codeword-level error rate at each stage is less than 5%. The 12,000 codeword-level readback records are derived from actual test records at each lifespan stage and are used to statistically analyze the error rate variation range within the stage. The judgment of relative fluctuation less than 5% is calculated based on the statistical results of the sample at that stage.

[0055] In one implementation, determining the error correction intensity based on the comparison result between the error probability and a preset probability threshold includes: When the error probability is greater than a preset probability threshold, the error correction intensity is determined as the first error correction intensity; When the error probability is not greater than a preset probability threshold, the error correction intensity is determined as the second error correction intensity; The redundancy corresponding to the first error correction intensity is greater than the redundancy corresponding to the second error correction intensity.

[0056] Specifically, the preset probability threshold is the upper bound of the error probability that the second error correction strength can tolerate; in this embodiment, it is 0.0020, with a value range of 0.0005 to 0.0050. The determination is based on reverse calculation using reliability indicators. The encoding parameters used are: a single encoding information bit length of 4096 bits, a check bit length of 128 bits, and a total codeword length of 4224 bits. Under the following simulation conditions, the empirical error correction capability is 12 error bits per codeword.

[0057] Industrial control scenarios require that the uncorrectable probability of a single codeword not exceed 10 to the power of -9. Based on the inverse solution of a codeword-level error model where the number of erroneous bits within a codeword follows a binomial distribution, with a code length of 4224 bits and 12 correctable erroneous bits, the upper bound of the allowable raw bit error rate to ensure the uncorrectable probability of a codeword does not exceed 10 to the power of -9 is 2.8 multiplied by 10 to the power of -4. The raw bit error rate refers to the probability of a bit flip occurring during the readback of a single memory cell, and is measured by the flash memory controller during the read verification stage as the ratio of erroneous bits to the total number of bits read back.

[0058] The conversion relationship between the error probability and the original bit error rate is given by the factory calibration experiment. In this embodiment, the conversion factor is 7.5, that is, the error probability equals the original bit error rate multiplied by 7.5. This factor is determined by taking the median of the ratio of the measured error probability at each lifespan stage to the measured original bit error rate during the same period. Based on this, the upper bound of the original bit error rate is converted to an upper bound of the error probability of 0.0021. Considering the estimated fluctuation of the calibration sample, a 5% protection band is taken and rounded down to 0.0020. The conversion factor is only used to map the bit error rate obtained from the experimental statistics to the selection basis of the error correction intensity, and is not used as a theoretical derivation parameter of the physical error probability of flash memory.

[0059] The calibration samples were obtained from readback verification records of the same model of single-layer cell flash memory chip under two ambient temperatures; the sorting conditions were to exclude bad blocks and power-down records; the sample size was 200,000 barcode-level readback records.

[0060] The basis for this number is that the calibration sample is used to estimate the error probability itself rather than to observe uncorrectable events on the order of 10 to the power of -9. In this embodiment, the error probability estimate is on the order of 10 to the power of -3. According to the binomial distribution, to control the relative standard error of the error probability estimate within 5%, at least 400 error events need to be observed. With 200,000 records, approximately 420 error events can be observed on this order of magnitude, which meets the requirement.

[0061] The reliability target of codeword-level uncorrectable probability not exceeding 10 to the power of negative 9 is derived from the codeword-level error model by extrapolation from the original bit error rate, without relying on sample observations, and the fluctuation is controlled by taking the mean of 3 sets of independent calibrations.

[0062] It should be noted that there are two sets of thresholds on the same judgment chain in this scheme: the preset number threshold and the preset speed threshold are applied to step S12 to divide the continuous physical operation data into discrete wear levels, which are intermediate classification thresholds; the preset probability threshold is applied to this step to determine the level of error correction resources to be deployed under the premise of known error probability, which are final decision thresholds.

[0063] The two sets of thresholds differ in their stringency: the wear classification threshold takes the point of minimum classification error, allowing for bidirectional misclassification, as the consequence of misclassification is only a one-stage shift in lifespan, and the subsequent error probability is still based on the actual number of errors measured; the preset probability threshold, on the other hand, is unidirectionally strict, preferring to select a high redundancy configuration when the error probability is close to the threshold, because the consequence of failing to select high redundancy is unrecoverable data, while mistakenly selecting high redundancy only occupies more spare space. This trade-off in the project is the origin of the aforementioned 5% protection band rounding down.

[0064] In a specific example, the error probability of the flash memory block during the decay period is 0.0029, which is greater than the preset probability threshold of 0.0020. Based on this, the error correction intensity is determined as the first error correction intensity. The redundancy corresponding to the first error correction intensity is 0.0625, and the redundancy corresponding to the second error correction intensity is 0.03125, with the former being greater than the latter.

[0065] The reasons for using two levels of redundancy, 0.0625 and 0.03125, are as follows: According to the above conversion factor, the error probability of 0.0029 during the decay period corresponds to an original bit error rate of 3.9 multiplied by 10 to the power of -4, and the parity bit length corresponding to 0.0625 can ensure that the probability of codeword uncorrectability is no higher than 10 to the power of -9 under this error rate; the measured error probability during the stable period does not exceed 0.0021, corresponding to an original bit error rate of no more than 2.8 multiplied by 10 to the power of -4, and the parity bit length corresponding to 0.03125 is sufficient to meet the same reliability target; the two levels differ by a factor of 1, which facilitates scaling the number of rows of the base matrix in an integer multiple under a quasi-cyclic structure without the need to rebuild the encoder.

[0066] For example, Figure 3 This is a schematic diagram of the error probability of flash memory blocks. The diagram shows the error probability distribution of 240 flash memory blocks in four wear stages, of which 159 blocks use the first error correction intensity and 81 blocks use the second error correction intensity.

[0067] In step S14, an initial encoding rule matching the flash memory block is generated based on the error correction strength. The target write data is encoded using this initial encoding rule to obtain first verification information, including: Construct a generation matrix based on the redundancy corresponding to the error correction intensity; The information bit length and check bit length are determined by the generated matrix, and the initial encoding rule is generated based on the information bit length and check bit length. The target data is divided into blocks according to the initial encoding rules to obtain data blocks, and the data blocks are encoded according to the generator matrix to obtain the first verification information.

[0068] Specifically, this embodiment employs a quasi-cyclic low-density parity check structure. Each element of the parity check basis matrix is ​​either a cyclic shift exponent or a zero element. Each non-zero element is replaced by a cyclic permutation matrix of the lifting factor order (obtained by right-shifting the identity matrix by its cyclic shift exponent), and each zero element is replaced by a zero matrix of the same order. After lifting and expansion, the binary parity check matrix is ​​obtained. ,Depend on Solve for the satisfaction System generation matrix This is used to encode the data written to the target.

[0069] The parity check basis matrix is ​​constructed according to an array-type quasi-cyclic rule, as follows: Let the row number of the basis matrix be... Column number is The number of rows is The enhancement factor is The serial number starts from 0. The column row number is right The remainder, and the sum of the remainder and the first preset row offset, are compared. The remainder, and the sum of the remainder and the second preset row offset, are compared. The remainder is used to determine the three non-zero positions, and the remaining positions are set to zero, ensuring that the number of non-zero elements in each column is always 3; the two preset row offsets are distinct and are related to... Coprime integers; in this embodiment, 5 and 11 are used. The cyclic shift exponents of each non-zero element are... and product pair The remainder determines the result.

[0070] After construction, eliminate cycles of length 4 according to the following rule: Traverse the four positions where any two rows and two columns intersect. If all four positions are non-zero elements and the difference between the cycle shift indices of two elements in the same row and the difference between the cycle shift indices of the corresponding two elements in the other row is equal to the difference between the cycle shift indices of the two elements in the other row, then... If congruent, one of the non-zero elements in the four positions is shifted sequentially along the column direction to the next empty position in that column, until no quadruplets satisfying the congruence condition are found. This construction rule is uniquely determined by the number of rows and columns of the base matrix and the lifting factor. The encoder and decoder are generated according to the same rule, without the need to store the entire matrix table.

[0071] The boost factor is set to 16 because it determines the adjustment step size of the check bit length. The range of 8 to 64 is determined by the balancing observations from the factory aging test. The redundancy space adjustment step size and the balancing results of the last sector margin are recorded when the boost factor is 8, 16, 32 and 64 respectively. When the value is smaller, the step size is finer, but the reduction requires multiple iterations and the convergence is slow. When the value is larger, the step size is coarser than the available margin of the check sector and it is difficult to balance finely. Therefore, 16 is a compromise value that balances the adjustment granularity and the balancing efficiency.

[0072] Redundancy is defined as the ratio of the parity bit length to the information bit length. Following the example above, the error correction strength of the flash memory block is determined to be the first error correction strength, corresponding to a redundancy of 0.0625. In this embodiment, the single-encoding information bit length is 4096 bits, or 512 bytes. With a redundancy of 0.0625, the parity bit length is calculated to be 4096 multiplied by 0.0625, which is 256 bits. The total codeword length is 4096 plus 256, or 4352 bits.

[0073] It should be noted that the information bit length of 4096 bits is based on the alignment with the physical page main area capacity: the physical page main area capacity is 16384 bits, and dividing it into 4096 bits results in exactly 4 data blocks, so that one physical page carries 4 codewords, and the data part of each codeword fills the main area without any zero padding.

[0074] It should be noted that the parity check basis matrix and the binary matrix after lifting expansion are two different objects, differing in the number of rows and columns by a lifting factor, and should not be used interchangeably. (The binary parity check matrix is ​​then used.) After Gaussian elimination, it becomes The system generation matrix obtained by solving the formal problem. It is a binary matrix with 4096 rows and 4352 columns, and its form is: ,in A 4096th order identity matrix It is a binary matrix with 4096 rows and 256 columns. The initial encoding rule is defined by the information bit length of 4096 bits and the parity bit length of 256 bits, which clarifies the upper limit of the effective payload that can be accommodated in a single encoding operation and the additional redundancy overhead required.

[0075] It should be noted that before encoding, the continuously arriving target data is divided into segments of equal information bit length. In a specific example, the total length of the target data is 16384 bits, which is divided into four data blocks of 4096 information bits each, with the data portion exactly filling the main area of ​​a physical page. For each data block, it is used as a 1-row, 4096-column input vector and combined with the generated matrix. Performing matrix multiplication over a binary finite field yields a codeword vector with 1 row and 4352 columns. The following 256 bits constitute the first checksum of this data block. Each of the four data blocks generates a 256-bit first checksum, totaling 1024 bits within the same physical page.

[0076] In step S15, the redundant space occupied by the first verification information in the flash memory block is calculated, the target redundancy is determined based on the comparison result of the redundant space and the preset space threshold, the target write data is re-encoded according to the target redundancy to obtain the second verification information, and the second verification information is merged with the target write data to obtain the target write data stream, including: The verification bit width specification is extracted based on the first verification information, and the verification bit width specification is matched with the physical page capacity of the flash memory block to obtain the verification information writing start point; The first verification information is divided into verification sector size and boundary address based on the verification information writing start point and the smallest programming unit of the flash memory block; The boundary address is aligned according to the available storage units of the flash memory block to obtain the space occupied by the first verification information after alignment by the minimum programming unit. The redundant space occupied by the first verification information in the flash memory block is calculated based on the occupied space.

[0077] Specifically, the check bit width specification is the bit length of the first check information. In this embodiment, a single data block is 256 bits. The physical page capacity of the flash memory block is 17408 bits, consisting of a main area and a spare area: the main area is 16384 bits, or 2048 bytes, used to store data blocks; the spare area is 1024 bits, or 128 bytes, used to store check information and block-level metadata.

[0078] It should be noted that the redundancy space is calculated based on the entire physical page: the main area of ​​a physical page carries 4 data blocks, each of which generates a 256-bit first check information, totaling 1024 bits. All 4 first check information must be stored in the spare area of ​​the same physical page. Therefore, when the check bit width specification matches the physical page capacity, the total length of the 4 first check information of the entire page, 1024 bits, is used as the calculation object, and it is not calculated based on a single check information.

[0079] The smallest programming unit of the flash memory block is 256 bits. Programming operations are performed at a granularity of 256 bits, and write addresses are aligned to 256 bits. The spare area is divided into four smallest programming units. The first programming unit (addresses 0 to 255) is used to store block-level metadata, including erase count field, stage identifier code, read / write count field, historical smoothing frequency, and reserved entries for the bad block remapping table. Verification information is stored starting from address 256 of the second programming unit, meaning the verification information is written from address 256 and the alignment offset is 256 bits.

[0080] In this embodiment, the parity sector is divided according to the smallest programming unit, and the parity sector size is 256 bits. Based on the starting point of writing the parity information at 256 bits, the first parity information of the entire page of 1024 bits requires 4 parity sectors. The parity sectors are 256 to 511 bits, 512 to 767 bits, 768 to 1023 bits, and 1024 to 1279 bits respectively, starting from 256 bits. The boundary addresses are 512 bits, 768 bits, 1024 bits, and 1280 bits respectively. Each of the 4 parity sectors carries 256 bits of the first parity information of one data block, and all are fully loaded.

[0081] It should be noted that the available space in the flash memory block for storing verification information is 768 bits, from bits 256 to 1023, in the spare area. The fourth verification sector mentioned above, starting from bit 1024, exceeds the spare area capacity of 1024 bits. That is, the first verification information of the entire 1024-bit page, after being aligned to 256 bits, requires four minimum programming units, totaling 1024 bits, exceeding the available verification space by 768 bits. The redundancy space calculation result is excessive, and the encoding redundancy must be reduced based on a preset space threshold.

[0082] In one implementation, the step of determining the target redundancy based on the comparison result between the redundancy space and a preset space threshold, re-encoding the target write data according to the target redundancy to obtain second verification information, and merging the second verification information with the target write data to obtain a target write data stream includes: When the redundancy space is greater than a preset space threshold, the redundancy of the initial encoding rule is reduced to obtain the target redundancy. When the redundancy space is not greater than the preset space threshold, the redundancy of the initial encoding rule is used as the target redundancy. Based on the target redundancy, the row vectors in the parity check matrix corresponding to the generator matrix are removed, and the target generator matrix is ​​re-solved. The target data is re-encoded using the target generation matrix to obtain the second verification information. The data interleaving depth is calculated based on the data length ratio of the target write data and the second verification information. The target write data and the second verification information are then interleaved and arranged according to the data interleaving depth to obtain the target write data stream. The target data stream is written into the flash memory block.

[0083] Specifically, the preset space threshold is the upper bound of the space that verification information is allowed to occupy in the spare area, which is 768 bits in this embodiment. The determination is based on the space allocation calculation of the spare area: the spare area has a total of 1024 bits, and the first smallest programming unit (256 bits) is used to store block-level metadata. This already includes a reserved entry in the bad block remapping table for recording the physical address of the replacement block when the flash memory block degrades into a bad block. Therefore, the upper bound of the space that verification information is allowed to occupy is the spare area capacity of 1024 bits minus 256 bits, resulting in 768 bits. This threshold is derived from the physical page structure parameters and does not require experimental calibration.

[0084] Using the example above, the first verification information of the entire page, aligned to 256 bits, requires 4 minimum programming units, totaling 1024 bits of space, which is greater than the preset space threshold of 768 bits. Therefore, the redundancy of the initial encoding rule is reduced to obtain the target redundancy.

[0085] The reduction amount is calculated based on space constraints, that is, the redundant space does not exceed 768 bits, which is equivalent to the minimum number of programming units occupied by the full page of check information not exceeding 3. The length of the full page of check bits must not exceed 256 multiplied by 3, which equals 768 bits. This means that the length of the check bits of a single data block does not exceed 768 divided by 4, which equals 192 bits. The current length of the check bits of a single data block is 256 bits, so at least 64 bits must be reduced.

[0086] Each row vector removed from the parity check matrix corresponds to a reduction of one lift factor in the parity bits, i.e., 16 bits. Therefore, at least four row vectors must be removed. Accordingly, the number of rows in the parity check matrix is ​​reduced from 16 to 12, the parity bit length of a single data block is reduced from 256 bits to 192 bits, and the parity bit length of the entire page is reduced from 1024 bits to 768 bits. The target redundancy is 192 divided by 4096, i.e., 0.046875.

[0087] It should be noted that reducing redundancy must simultaneously satisfy both space constraints and reliability constraints: the space constraint means that the space occupied by the aforementioned full-page check information does not exceed a preset space threshold; the reliability constraint means that the target redundancy must not be lower than the minimum redundancy, which is the ratio of the minimum check bit length to the information bit length required to ensure that the probability of codeword uncorrectability is not higher than 10 to the power of -9 under the original bit error rate measured in the current lifetime stage. The target redundancy is taken as the larger of the redundancy calculated according to the space constraint and the minimum redundancy, so that the reduction of redundancy does not offset the error correction requirement selected in step S13.

[0088] Using the example above, the measured original bit error rate during the decay period is 3.9 times 10 to the power of -4. According to the codeword-level error model, the minimum parity bit length required to meet the above reliability target is 128 bits, and the corresponding minimum redundancy is 128 divided by 4096, which is 0.03125. The redundancy of 0.046875 calculated according to the space constraint is greater than the minimum redundancy, so the target redundancy is taken as 0.046875.

[0089] The selection of deletion targets is based on minimizing the loss of the minimum code distance: Gaussian elimination is performed on the parity check matrix to determine each candidate row vector; the minimum code distance of the new parity check matrix after deleting any four row vectors is enumerated; and the group of four row vectors that minimizes the decrease in the minimum code distance after deletion is selected and deleted to obtain the target parity check matrix; the target parity check matrix is ​​then re-solved to satisfy the following conditions. The target generation matrix is ​​used to re-encode the target data.

[0090] The selection criteria and error correction capability data were both verified by simulation during the factory calibration stage. The simulation conditions were as follows: the decoding algorithm adopted minimum sum iterative decoding, the maximum number of iterations was 50, the channel model adopted a binary symmetric channel, the error distribution was set according to the distribution of error bits in the codeword measured by the accelerated aging sample, and the judgment caliber was consistent with the aforementioned reliability indicators, so that the probability of the codeword being uncorrectable was no higher than 10 to the power of -9.

[0091] It should be noted that the error correction capability during iterative decoding varies with channel conditions and decoding parameters. Therefore, it is not expressed as a fixed number of error bits that can be carried, but rather as the range of empirical error correction capability that satisfies a specified uncorrectable probability under the given channel model and decoding parameters. In a specific example, before reduction, this empirical error correction capability is 20 error bits per codeword, and after reduction, it is 16 error bits per codeword. Under the measured original bit error rate of 3.9 multiplied by 10 to the power of -4 during the fading period, the expected number of error bits per codeword after reduction is approximately 1.7. The uncorrectable probability of the codeword calculated according to the codeword-level error model is approximately 10 to the power of -12, which is better than the reliability target of 10 to the power of -9, and the error correction capability retains a margin.

[0092] It should be noted that the target generated matrix is ​​used to re-encode the target data. This involves using each data block as a 1x4096 column input vector and performing matrix multiplication with the target generated matrix over a binary finite field. Each data block yields 192 bits of second check information, and the total second check information for the four data blocks on the same physical page is 768 bits. Recalculated based on 768 bits per page, the check information occupies three minimum programming units starting from bit 256. The final boundary address is 256 plus 768, or 1024 bits, which does not exceed the spare area capacity of 1024 bits, thus eliminating the need for further boundary alignment. The recalculated redundant space of 768 bits is no greater than the preset space threshold of 768 bits, achieving the desired encoding adjustment.

[0093] The data interleaving depth is calculated as the ratio of the target written data to the data length of the second verification information, and the calculation formula is: ; In the formula, The data interleaving depth is dimensionless and ranges from 1 to 64; in this embodiment, it is 21. The information bit length of a single data block, in bits, ranges from 1024 to 8192, and is 4096 bits in this embodiment; The length of the second verification information for a single data block is in bits, ranging from 128 to 2048, and is 192 bits in this embodiment.

[0094] Specifically, the interleaving arrangement is performed on a byte-by-byte basis. First, the logical sequence of the target data stream is organized according to the data interleaving depth, and then it is positioned by physical address mapping: with a data interleaving depth of 21 as the interval, one check byte is inserted after every 21 data bytes, and the successively inserted check bytes are taken from the 1st to the 4th data blocks and rotated in a loop; after 96 check bytes are inserted, a total of 2016 data bytes are interspersed, and the remaining 32 are sequentially appended to the end, thereby forming the target data stream.

[0095] It should be noted that the mapping relationship between logical data stream and physical address is as follows: When the flash memory controller writes, it fills the data bytes in the logical data stream into the main area of ​​the physical page in sequence according to the physical address mapping table, and fills the parity bytes in sequence into the parity space starting from bit 256 in the spare area. That is, the data bytes still fall in the main area, and the parity bytes still fall in the spare area. What is changed by interleaving is the order of the parity bytes of each data block in the parity space of the spare area. Taking this embodiment as an example, a single data block is 4096 bits, which is 512 bytes, and its second parity information is 192 bits, which is 24 bytes; the four data blocks contain a total of 2048 data bytes and 96 parity bytes. After being interleaved as described above, the four physically adjacent parity bytes in the parity space of the spare area belong to four different data blocks.

[0096] For example, Figure 4 This is a diagram illustrating the redundancy space of the verification information. The diagram shows that the first verification information occupies 1024 bits per page. After adjusting the target redundancy, the second verification information occupies 768 bits per page, which meets the preset space threshold.

[0097] The advantage of interleaving lies in the fact that flash memory bit errors often occur in bursts between physically adjacent storage cells. If the parity bytes of the same codeword are stored consecutively in the spare area, a burst error spanning adjacent storage cells will simultaneously destroy the parity bytes of that codeword, rendering it without a basis for verification. By interleaving the parity bytes of different codewords with a fixed step size, the parity bytes destroyed by a single burst error are distributed across different codewords, reducing the number of erroneous bits falling into each codeword, allowing each codeword to still complete error correction and decoding. During reading, the data is decomposed in reverse according to the data interleaving depth, and each parity byte is returned to its corresponding codeword before decoding is performed.

[0098] Finally, the target write data stream is sequentially sent to the write buffer register of the flash memory controller according to the physical page programming timing of the flash memory block. Based on the physical address mapping table, the buffer register data is page-by-page persisted to the memory cell array of the flash memory block, completing the physical layer write. At this point, the target write data and the verification information adaptively determined according to the block-level lifetime status are jointly written to the flash memory block.

[0099] In summary, this invention discloses an adaptive data error correction method for SLC flash memory based on block-level lifetime assessment. It obtains the current erase / write cycle count and historical write speed of the flash memory block in the target single-layer cell flash memory. After wear classification processing and mapping table lookup, the current lifetime stage is determined. The error probability is calculated from the number of historical errors within the current lifetime stage, and the error correction strength is selected accordingly. An initial encoding rule is generated according to the selected error correction strength to encode the target write data, obtaining first verification information. After calculating the redundant space occupied by the first verification information in the flash memory block, the target redundancy is determined and re-encoded to obtain second verification information. The second verification information is merged with the target write data to obtain the target write data stream. This invention achieves synchronous improvement of error correction capability as the flash memory block ages by using block-level measured degradation data to drive the selection of error correction strength and adjusting the encoding redundancy based on the actual physical layout calculation results. This improves the data storage reliability of single-layer cell flash memory throughout its entire lifecycle.

[0100] The second embodiment of the present invention provides an SLC flash memory adaptive data error correction system based on block-level lifetime assessment, comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the SLC flash memory adaptive data error correction method based on block-level lifetime assessment as described above.

[0101] It should be noted that the SLC flash memory adaptive data error correction system based on block-level lifetime assessment provided in this embodiment of the invention is used to execute all the process steps of the SLC flash memory adaptive data error correction method based on block-level lifetime assessment in the above embodiment. The working principles and beneficial effects of the two are one-to-one, so they will not be described again.

[0102] It should be noted that the embodiments of the present invention also provide a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the steps of the above-described SLC flash memory adaptive data error correction method based on block-level lifetime assessment.

[0103] It should be noted that the system embodiments described above are merely illustrative. The system embodiments of the present invention are implemented in the form of a memory, a processor, and a computer program, without functional module division. Those skilled in the art can understand and implement them without creative effort.

[0104] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An adaptive data error correction method for SLC flash memory based on block-level lifetime assessment, characterized in that, include: Obtain the current erase / write cycle count and historical write speed of the flash memory block in the target single-layer cell flash memory; The wear level of the flash memory block is obtained by classifying wear based on the current erase / write cycle count and the historical write speed, and the lifespan stage of the flash memory block is determined by querying a preset mapping table according to the wear level. The number of historical errors of the flash memory block is extracted according to the lifetime stage, the error probability of the flash memory block in the lifetime stage is calculated based on the number of historical errors, and the error correction intensity is determined based on the comparison result of the error probability and the preset probability threshold. An initial encoding rule matching the flash memory block is generated based on the error correction strength, and the target written data is encoded using the initial encoding rule to obtain the first verification information; The redundant space occupied by the first verification information in the flash memory block is calculated. The target redundancy is determined based on the comparison result between the redundant space and the preset space threshold. The target write data is re-encoded according to the target redundancy to obtain the second verification information. The second verification information and the target write data are merged to obtain the target write data stream.

2. The SLC flash memory adaptive data error correction method based on block-level lifetime assessment according to claim 1, characterized in that, The process of obtaining the current erase / write cycle count and historical write speed of the flash memory block in the target single-layer cell flash memory includes: The erase count field in the block-level metadata area maintained by the flash translation layer of the target single-layer cell flash memory is read to obtain the current erase / write cycle number; The cumulative amount of data written and the cumulative writing time of the flash memory block are collected according to a preset statistical period. The historical write speed is calculated based on the cumulative amount of data written and the cumulative write time.

3. The SLC flash memory adaptive data error correction method based on block-level lifetime assessment according to claim 1, characterized in that, The step of classifying the wear level of the flash memory block based on the current erase / write cycle count and the historical write speed, and then determining the lifespan stage of the flash memory block by querying a preset mapping table according to the wear level, includes: A feature vector is constructed based on the current erase / write cycle count and the historical write speed; The feature vector is input into a preset wear classification model for classification processing to obtain the wear level label of the flash memory block, and the wear degree of the flash memory block is determined according to the wear level label; The stage identifier code corresponding to the wear level is extracted by querying the preset mapping table, and the life stage of the flash memory block is determined according to the stage identifier code.

4. The SLC flash memory adaptive data error correction method based on block-level lifetime assessment according to claim 1, characterized in that, The step of extracting the historical error count of the flash memory block based on the lifetime stage, and calculating the error probability of the flash memory block in the lifetime stage based on the historical error count, includes: Extract the number of historical errors corresponding to each error type in the flash memory block during the lifespan stage, and sum the historical error numbers according to a preset error weight to obtain the weighted total number of errors; The initial error frequency is calculated based on the weighted total number of errors and the total number of read / write operations and erase operations of the flash memory block during the lifetime stage. Obtain the historical smoothing frequency corresponding to the previous preset statistical period, and calculate the smoothed error frequency by weighting the initial error frequency and the historical smoothing frequency according to the preset smoothing coefficient. The error probability of the flash memory block during its lifetime is calculated by inputting the smoothed error frequency into a preset probability conversion function.

5. The SLC flash memory adaptive data error correction method based on block-level lifetime assessment according to claim 1, characterized in that, The step of determining the error correction intensity based on the comparison result between the error probability and a preset probability threshold includes: When the error probability is greater than a preset probability threshold, the error correction intensity is determined as the first error correction intensity; When the error probability is not greater than a preset probability threshold, the error correction intensity is determined as the second error correction intensity; The redundancy corresponding to the first error correction intensity is greater than the redundancy corresponding to the second error correction intensity.

6. The SLC flash memory adaptive data error correction method based on block-level lifetime assessment according to claim 1, characterized in that, The step of generating an initial encoding rule matching the flash memory block based on the error correction strength, and encoding the target write data using the initial encoding rule to obtain the first verification information includes: Construct a generation matrix based on the redundancy corresponding to the error correction intensity; The information bit length and check bit length are determined by the generated matrix, and the initial encoding rule is generated based on the information bit length and check bit length. The target data is divided into blocks according to the initial encoding rules to obtain data blocks, and the data blocks are encoded according to the generator matrix to obtain the first verification information.

7. The SLC flash memory adaptive data error correction method based on block-level lifetime assessment according to claim 1, characterized in that, The calculation of the redundant space occupied by the first verification information in the flash memory block includes: The verification bit width specification is extracted based on the first verification information, and the verification bit width specification is matched with the physical page capacity of the flash memory block to obtain the verification information writing start point; The first verification information is divided into verification sector size and boundary address based on the verification information writing start point and the smallest programming unit of the flash memory block; The boundary address is aligned according to the available storage units of the flash memory block to obtain the space occupied by the first verification information after alignment by the minimum programming unit. The redundant space occupied by the first verification information in the flash memory block is calculated based on the occupied space.

8. The SLC flash memory adaptive data error correction method based on block-level lifetime assessment according to claim 1, characterized in that, The process of determining the target redundancy based on the comparison result between the redundancy space and the preset space threshold, re-encoding the target written data according to the target redundancy to obtain the second verification information, and merging the second verification information with the target written data to obtain the target written data stream includes: When the redundancy space is greater than a preset space threshold, the redundancy of the initial encoding rule is reduced to obtain the target redundancy. When the redundancy space is not greater than the preset space threshold, the redundancy of the initial encoding rule is used as the target redundancy. Based on the target redundancy, the row vectors in the parity check matrix corresponding to the generator matrix are removed, and the target generator matrix is ​​re-solved. The target data is re-encoded using the target generation matrix to obtain the second verification information. The data interleaving depth is calculated based on the data length ratio of the target write data and the second verification information. The target write data and the second verification information are then interleaved and arranged according to the data interleaving depth to obtain the target write data stream. The target data stream is written into the flash memory block.

9. An SLC flash memory adaptive data error correction system based on block-level lifetime assessment, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the SLC flash adaptive data error correction method based on block-level lifetime assessment as described in any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the SLC flash memory adaptive data error correction method based on block-level lifetime assessment as described in any one of claims 1 to 8.

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