SLC flash memory data retention dynamic correction method based on temperature-aware aging model

Abstract

This invention relates to the field of dynamic error correction technology for SLC flash memory data retention, and discloses a method and system for dynamic error correction of SLC flash memory data retention based on a temperature-sensing aging model. The method includes acquiring erase / write wear data and ambient temperature data of a single-layer cell flash memory, extracting insulation degradation characteristics and classifying them to obtain the true aging state; locating the target storage block according to the aging state, collecting the error bit rate and read latency, and predicting the expected error amount; when the expected error amount exceeds a safety threshold, performing priority analysis based on the remaining available space to generate a dynamic matching instruction; redundancy allocation of the target block according to the instruction to obtain updated error correction redundancy, and compensating in advance accordingly to improve data retention. This method can achieve accurate dynamic matching between error correction resources and the true aging state of the block.

Description

Technical Field

[0001] This invention relates to the field of dynamic error correction technology for SLC flash memory data retention force, and in particular to a dynamic error correction method for SLC flash memory data retention force based on a temperature-sensing aging model. Background Technology

[0002] Currently, single-cell flash memory, as a non-volatile storage medium carrying critical data in intelligent integrated circuits, is widely used in scenarios with stringent reliability requirements, such as industrial control and automotive electronics. The data retention capability of flash memory depends on the charge retention capacity of the insulating layer; however, repeated erasure and high temperatures accelerate the degradation of the insulating layer, leading to charge leakage. How to dynamically sense the actual aging state of each block and maintain long-term data readability has become an urgent problem to be solved.

[0003] In one existing technology, the SLC flash memory data retention error correction scheme employs a fixed error correction redundancy allocation strategy, uniformly applying a preset strength of error correction coding to all storage blocks and triggering retries or remapping after a read error occurs. From the failure mechanism perspective, insulation layer degradation stems from irreversible physical damage caused by erasure and writing, and the amplification effect of temperature rise on charge escape; these two factors exhibit a non-linear coupling relationship. Different blocks show significantly different aging rates due to variations in the number of erasures and writing cycles and their operating temperature environments. A fixed error correction strength cannot detect this difference, leading to insufficient protection for severely aged blocks and wasted redundancy in healthy blocks. Furthermore, this scheme only intervenes when errors accumulate to a detectable level, lacking the ability to predict error accumulation trends and failing to intervene before data becomes unreadable.

[0004] In summary, existing technologies lack real-time sensing and proactive error correction mechanisms for the coupled aging process of erasure and write wear and environmental temperature, leading to a mismatch in error correction resource allocation in SLC flash memory. Summary of the Invention

[0005] This invention provides a dynamic error correction method and system for SLC flash memory data retention force based on a temperature-sensing aging model, so as to achieve accurate dynamic matching between error correction resources and the actual aging state of blocks.

[0006] In a first aspect, to address the aforementioned technical problems, this invention provides a dynamic error correction method for SLC flash memory data retention force based on a temperature-sensing aging model, comprising: Obtain erase / write wear data and ambient temperature data of storage blocks in a single-layer cell flash memory, and perform multi-dimensional feature extraction on the erase / write wear data and ambient temperature data to obtain insulation degradation characteristics; The true aging state is obtained by classifying the insulation degradation characteristics. Based on the actual aging state, an aging state identifier is extracted. Based on the aging state identifier, the corresponding target storage block is located. The running characteristics of the target storage block are collected to obtain the error bit rate and read latency. Based on the error bit rate and the read latency, a trend prediction is performed to predict the expected error amount. If the expected error amount is greater than the preset error safety threshold, the remaining available space of the target storage block is extracted, and data priority analysis is performed based on the remaining available space and the expected error amount to obtain a dynamic matching instruction; According to the dynamic matching instruction, the target storage block is redundantly allocated to obtain the updated error correction redundancy. The target storage block is then pre-compensated according to the updated error correction redundancy to obtain the compensated target block.

[0007] Secondly, the present invention provides a dynamic error correction system for SLC flash memory data retention force based on a temperature-sensing aging model, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described above.

[0008] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described above.

[0009] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention extracts the wear gradient and temperature drift of the erase and write wear data and the ambient temperature data, constructs a degradation mapping matrix, uses a support vector machine model to extract multidimensional features, obtains insulation degradation features, and uses decision tree classification to determine the true aging state. This solves the problem that fixed error correction strategies cannot distinguish the degree of degradation of insulation layers in different blocks, and realizes accurate identification of temperature and wear coupled aging.

[0010] (2) This invention extracts the current error bit rate and historical read delay time of heavily aged blocks, constructs an aging feature time series, uses a linear regression algorithm to predict the trend, obtains the expected error accumulation value, and generates a dynamic matching instruction in combination with the remaining available space when it exceeds the threshold. This solves the problems of post-event remediation and lack of forward prediction in the prior art, and realizes early warning and dynamic scheduling of error accumulation.

[0011] (3) This invention obtains the physical page wear degree and bit flip frequency by parsing the dynamic matching instruction, calculates the charge leakage rate and generates an error correction coding matrix for redundancy allocation, updates the error correction redundancy, and generates a compensation injection current based on the threshold drift amount for advance compensation. This solves the problem of resource allocation mismatch caused by the inability of fixed error correction redundancy to adapt to the differences in block aging, and realizes dynamic optimization of error correction resources. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the process of a dynamic error correction method for SLC flash memory data retention force based on a temperature-sensing aging model provided by the present invention. Figure 2 This is a schematic diagram showing the distribution of insulation degradation characteristics and actual aging state provided by the present invention; Figure 3 This is a schematic diagram of error bit rate trend prediction provided by the present invention; Figure 4 This is a schematic diagram illustrating the change in error bit rate before and after advance compensation provided by the present invention. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0014] Reference Figure 1 The first embodiment of the present invention provides a dynamic error correction method for SLC flash memory data retention force based on a temperature-sensing aging model, comprising the following steps: S11, acquire erase / write wear data and ambient temperature data of storage blocks in a single-layer cell flash memory, and perform multi-dimensional feature extraction on the erase / write wear data and ambient temperature data to obtain insulation degradation features; S12, classify the state according to the insulation degradation characteristics to obtain the true aging state; S13, extract the aging state identifier based on the actual aging state, locate the corresponding target storage block based on the aging state identifier, collect the running characteristics of the target storage block, and obtain the error bit rate and read latency time. S14, perform trend prediction based on the error bit rate and the read delay time to predict the expected error amount; S15, if the expected error amount is greater than the preset error safety threshold, then extract the remaining available space of the target storage block, perform data priority analysis based on the remaining available space and the expected error amount, and obtain a dynamic matching instruction; S16, according to the dynamic matching instruction, redundancy allocation is performed on the target storage block to obtain the updated error correction redundancy, and the target storage block is pre-compensated according to the updated error correction redundancy to obtain the compensated target block.

[0015] In step S11, erase / write wear data and ambient temperature data of storage blocks in a single-layer cell flash memory are acquired. Multi-dimensional feature extraction is performed on the erase / write wear data and ambient temperature data to obtain insulation degradation features, including: Obtain global erase / write data and global temperature data, and remove abnormal zero values ​​from the global erase / write data to obtain clean wear data; A wear distribution matrix is ​​constructed based on the cleaning wear data and the global temperature data. Working condition analysis is performed based on the wear distribution matrix to generate block status identifiers. Data is extracted based on the block status identifier to obtain erase / write wear data and ambient temperature data. Gradient analysis is performed based on the erase and write wear data and the ambient temperature data to obtain the degradation mapping matrix; Multidimensional feature extraction is performed on the degradation mapping matrix to obtain insulation degradation features.

[0016] It should be noted that the global erase / write data comes from an erase / write counter within each memory block, which automatically increments by one after each erase operation. Global temperature data comes from a temperature sensor inside the flash memory package, which outputs an ambient temperature value in degrees Celsius each sampling period. Due to occasional counter or sensor malfunctions, abnormal zero values ​​may appear in the global erase / write data, which do not conform to physical laws. Under normal operating conditions, the number of erase / write operations increases monotonically and will not return to zero; therefore, it is necessary to remove abnormal zero values ​​from the global erase / write data. The removal process uses a sliding window filter with a window length of 5 sampling periods. Starting from the first sampling point of the original erase / write sequence, it slides forward one sampling point at a time. If two or more zero values ​​appear simultaneously within the window, the zero values ​​in that window are replaced with the arithmetic mean of all non-zero values ​​within the window. If the window contains only zero values, the sampling point is marked as invalid and discarded.

[0017] Next, a wear distribution matrix is ​​constructed based on the cleaning wear data and global temperature data. First, the global temperature data is divided into intervals. Based on the operating temperature range of -40°C to 85°C given in the flash memory datasheet, six intervals are defined in 20°C increments: -40°C to -20°C, -20°C to 0°C, 0°C to 20°C, 20°C to 40°C, 40°C to 60°C, and 60°C to 85°C. The last interval is not perfectly aligned with the 20°C width but covers the entire operating temperature range. For each sampling period, the erase / write increment for each storage block is calculated. The erase / write increment equals the cleaning wear data of the current period minus the cleaning wear data of the previous period. Then, the erase / write increment is accumulated according to the ambient temperature interval corresponding to that sampling period and added to the corresponding position in the wear distribution matrix. The wear distribution matrix is ​​a two-dimensional structure. The row index corresponds to the temperature interval number, the column index corresponds to the storage block number, and the matrix elements represent the cumulative wear increment of that block within a specific temperature interval.

[0018] After construction, operational condition analysis is performed. When the change in any element of the wear distribution matrix between adjacent sampling periods exceeds the increment threshold, the block is determined to be under abnormal high-temperature wear conditions. The increment threshold is determined using an adaptive statistical method. For each storage block, a sliding window of erase / write increments over the past 200 consecutive sampling periods is maintained. The mean and standard deviation of the erase / write increments within this window are calculated, and the mean plus three times the standard deviation is used as the upper limit of normal wear increments for the current block. If the initial statistical samples for the block are less than 200, the default upper limit of 30 times is used. This upper limit is multiplied by a safety factor of 1.5 and rounded to obtain the increment threshold for the current block. Block status is classified into three levels: normal, attention, and high risk. Wear increments exceeding the increment threshold but not exceeding 1.5 times the increment threshold are marked as attention; those exceeding 1.5 times the increment threshold are marked as high risk; and the rest are normal. For blocks in the high-temperature range of 40°C to 60°C, if the change in wear increment between adjacent sampling periods exceeds its current threshold, it is determined to be an abnormal high-temperature wear condition, and the block status is marked as high-risk.

[0019] Subsequently, when extracting data based on block status identifiers, the complete time-series data of the storage blocks corresponding to high-risk identifiers is read first, including erase / write counts and temperature values ​​for each sampling period. If the number of high-risk blocks exceeds 10% of the total number of blocks, the data of blocks with interest identifiers are also read. The extracted erase / write wear data is stored with the block number as the primary key, and the ambient temperature data is aligned one-to-one with the sampling timestamp of the block. Next, gradient analysis is performed based on these two types of data to obtain a degradation mapping matrix. Gradient analysis first calculates the wear gradient between adjacent sampling periods by subtracting the erase / write wear data of the previous sampling period from the current sampling period's erase / write wear data, with the unit being times / period. At the same time, the temperature drift is calculated, which is equal to the ambient temperature data of the current sampling period minus a reference temperature of 25°C. The reference temperature of 25°C comes from the standard test ambient temperature specified in the flash memory datasheet. The wear gradient and temperature drift are combined into a two-dimensional matrix in the order of sampling time, with each row corresponding to a sampling time point. The first column is the wear gradient, and the second column is the temperature drift. This two-dimensional matrix is ​​the degradation mapping matrix.

[0020] It is worth noting that when performing multidimensional feature extraction on the degradation mapping matrix, the matrix was divided into sliding windows of 20 sampling points in chronological order, with two sampling points sliding at a time. Five statistics were calculated for the wear gradient sequence and temperature drift sequence within each window, serving as five components of the insulation degradation characteristics: the arithmetic mean of the wear gradient, the standard deviation of the wear gradient, the arithmetic mean of the temperature drift, the maximum value of the temperature drift, and the correlation coefficient between the wear gradient and the temperature drift. Specifically, the mean wear gradient reflects the average intensity of the erase / write stress, affecting the cumulative dose of charge trapping; the standard deviation of the wear gradient reflects the fluctuation of the erase / write load, relating to the non-uniformity of the degradation process; the mean temperature drift reflects the average level of thermal stress, affecting the thermal generation rate of interface states; the maximum temperature drift reflects the peak thermal stress, related to the sudden increase in stress-induced leakage current; and the correlation coefficient between wear and temperature is used to assess the synergistic acceleration effect of threshold voltage drift. The window length of 20 sampling points is based on the flash memory sampling period of 10ms. The 20 sampling points cover a short-term working condition of 200ms, which can stably estimate statistical features. The sliding step size of 2 sampling points ensures the continuity of the feature sequence.

[0021] In step S12, the insulation degradation characteristics are used to classify the state and obtain the true aging state, including: Information gain is calculated for the insulation degradation characteristics to obtain the information gain value; Based on the information gain value, perform branch path traversal to obtain the leaf node weights; Generate classification status labels based on the weights of the leaf nodes; A classification determination matrix is ​​constructed based on the classification status labels, and the actual aging status of each storage block is extracted from the classification determination matrix.

[0022] It should be noted that before calculating information gain, the insulation degradation features need to be discretized. An equal-frequency binning method is used, arranging the values ​​of each feature in ascending order and dividing them into five equal intervals. Each interval contains an equal number of samples, and the interval separator serves as the dividing point for splitting. For the discretized features, the information gain of each feature is calculated according to the training process of decision tree classification. Information gain equals the entropy of the sample set before splitting minus the weighted sum of the entropies of each subset after splitting according to that feature. Entropy is calculated based on the frequency of different aging state categories in the sample set, which include four categories: normal, mild aging, moderate aging, and severe aging. The sample set comes from a set of storage blocks with labeled actual aging states collected by a flash memory reliability testing platform. This set contains 320 blocks, including 80 normal, 90 mildly aged, 80 moderately aged, and 70 severely aged. The actual aging state labels are determined by long-term data retention testing combined with oxide layer leakage current detection. When calculating information gain, the entropy of all 320 samples at the root node is first calculated. Then, the conditional entropy after splitting with different binning thresholds for each feature is calculated. The smaller the conditional entropy, the greater the information gain. The feature with the largest information gain and the binning threshold are selected as the splitting conditions for the current node.

[0023] It's worth noting that the branch path traversal relies on the already trained decision tree structure. The training process employs a recursive splitting approach. Starting from the root node, the samples are divided into two subsets using the feature with the highest information gain and the corresponding splitting threshold. The left subset contains samples with feature values ​​less than or equal to the splitting threshold, while the right subset contains samples with feature values ​​greater than the splitting threshold. Information gain calculation and splitting operations are repeated for each subset until the stopping conditions are met: the number of samples within a node is less than 5, all samples within a node belong to the same aging state category, or the information gain value of further splits is lower than 0.01. The lower limit of 0.01 information gain is determined based on the purity of the training set labels. Normal splitting information gain is concentrated between 0.05 and 0.3; a value below 0.01 indicates that the split cannot effectively distinguish different aging states. During training, the maximum depth of the decision tree is set to 4 layers. This depth prevents the model from overemphasizing noise patterns specific to the training set.

[0024] After the decision tree is trained, for the insulation degradation features of the target block, the feature values ​​are compared with the split threshold layer by layer starting from the root node. Based on the comparison result, the tree enters the left or right branch until it reaches a leaf node. The leaf node stores the aging state distribution information of all samples that fell into that node during training. The leaf node weight is the proportion of samples in each aging state category within that node. For example, if a leaf node contains 100 samples, of which 70 are severely aged and 30 are moderately aged, then the weight of severely aged samples in that leaf node is 0.7, and the weight of moderately aged samples is 0.3. After training, the features, split thresholds, left child node numbers, right child node numbers, and class weights of each leaf node are stored as lookup table entries. When classifying the target block, only table lookups and numerical comparisons are needed to complete the branch traversal, with a single classification taking less than 0.05 milliseconds.

[0025] Subsequently, classification status labels are generated based on the leaf node weights. When the insulation degradation characteristics of the target block reach a leaf node through the branch path, the weights of each aging status category stored in that leaf node are read, and the aging status category with the highest weight is selected as the classification status label for the target block. For example, if the weight of severe aging (0.7) in the leaf node is greater than that of moderate aging (0.3), then the target block is assigned the classification status label of severe aging. If two categories have the same highest weight within a leaf node, they are selected in descending order of category number, i.e., severe aging takes precedence over moderate aging, moderate aging takes precedence over mild aging, and mild aging takes precedence over normal. Classification status labels are stored using integer encoding: normal is 0, mild aging is 1, moderate aging is 2, and severe aging is 3.

[0026] Then, after classifying the state of a single block, the classification results of different blocks are summarized to form a classification decision matrix. The rows of the classification decision matrix correspond to the block number, and the columns correspond to the aging state category. Each element in a row is the weight value of that block in each aging state category, which is directly taken from the category weights stored in the leaf nodes reached by that block. For each block, the column corresponding to the maximum weight value in that row is found; the aging state category corresponding to that column is the true aging state of that block. The true aging state is defined as the actual aging stage of the target storage block under the current erase / write wear and temperature history. Unlike the degradation classification label, the true aging state is determined by a decision tree combined with multiple dimensional features, resulting in higher state resolution. The classification decision matrix storage structure uses the block number as the primary key, and the row order is fixed as four weight values: normal, lightly aged, moderately aged, and heavily aged. This matrix is ​​stored in a temporary buffer inside the flash memory controller, with a storage overhead of 4 floating-point values ​​per block.

[0027] For example, Figure 2This is a schematic diagram showing the distribution of insulation degradation characteristics and actual aging state. The diagram displays the wear gradient and temperature drift distribution of 320 calibrated storage blocks. Normal, slightly aged, moderately aged, and heavily aged blocks form characteristic regions with natural dispersion and local overlap, reflecting the results of determining the actual aging state through multi-dimensional insulation degradation characteristics.

[0028] In step S13, an aging state identifier is extracted based on the actual aging state, and the corresponding target storage block is located based on the aging state identifier. The target storage block is then subjected to operational feature acquisition to obtain the error bit rate and read latency, including: Based on the actual aging state, a state mapping is performed to obtain an aging state identifier, and the corresponding target storage block is located based on the aging state identifier. Extract the total number of parity bits and the number of flipped bits of the target storage block; The error bit rate is calculated by proportionally dividing the number of flipped bits by the total number of check bits. Extract the delay timestamp of the target storage block and calculate the time difference to obtain the read delay time.

[0029] It should be noted that the mapping table is directly stored in the state buffer inside the flash memory controller. This buffer uses the block number as the primary key, and each block corresponds to a set of aging status codes. After classifying the actual aging status of all target storage blocks, the state buffer is traversed, and blocks with aging status identifiers of 1, 2, or 3 are marked as target storage blocks. Blocks with aging status identifiers of 0 are not included in the subsequent feature acquisition process. The total capacity of the state buffer is the total number of blocks multiplied by 1 byte per block. When locating a target storage block, the aging status identifiers in the state buffer are read one by one according to the block number order. When a non-zero identifier is encountered, the block number is added to the target block number list until all blocks have been traversed. If the target block number list is empty, it indicates that all blocks are currently in a normal aging state, and there is no need to perform error bit rate and read latency acquisition.

[0030] Next, the error check code and the number of flipped bits for the target storage block are extracted. During each read operation of a storage block, the error correction engine inside the flash controller runs simultaneously to verify the raw data read. The error correction engine uses either BCH encoding or LDPC encoding. Each verification generates a set of error check codes, the length of which is fixed by the controller configuration: 96 bits for BCH and 512 bits for LDPC. The error check codes are directly stored in the result register of the error correction engine. After a read operation, the controller writes the error check codes into the error statistics table on the master control unit. The number of flipped bits comes from the total number of bit flips detected during the error correction process. While calculating the check code, the error correction engine counts each bit in each codeword that failed the verification and had its polarity reversed, and writes the count results into the same error statistics table. Each row of the error statistics table corresponds to a storage block and contains at least three columns: error check code, number of flipped bits, and total number of check bits. The total number of parity bits is defined as the sum of the data bits and the additional parity bits in a single error correction codeword. For BCH codes, this is 1024 data bits plus 96 parity bits, totaling 1120 bits. When it is necessary to extract the total parity bits and the number of flipped bits for a target block, the target block number is used as the search condition. The corresponding row is found in the error statistics table, and the total parity bits and the number of flipped bits are read; no further reading is required. If the target block number is not found in the error statistics table, the number of flipped bits for that block is set to 0, and the total parity bits are filled in according to the default value configured by the controller.

[0031] It should be further explained that when calculating the error bit rate, the number of flipped bits in the target storage block is divided by the total number of parity bits in that block, and then the quotient is multiplied by 100% to obtain a value expressed as a percentage. For example, if a target block has 8 flipped bits per codeword and a total of 1120 parity bits, then the error bit rate is 0.71%. When there are multiple target blocks, the error bit rate is calculated separately for each block, without cross-block merging. This ratio calculation is implemented directly in the controller firmware through integer multiplication and division. The multiplication uses the number of flipped bits multiplied by 100,000, then divided by the total number of parity bits, and the result is rounded down to two decimal places to avoid precision loss caused by floating-point operations. The error bit rate is finally stored as a percentage value in a newly added error bit rate column in the error statistics table, with a value range of 0% to 100%. After obtaining the error bit rate, the extraction of read latency continues.

[0032] The delay timestamp comes from the read operation timing module of the flash memory controller. Before each read operation begins, the controller records the system clock count value when the read command is issued as the start timestamp. When the data is returned after the read operation is completed, the controller records the system clock count value triggered by the read completion event as the end timestamp. Both timestamps are based on the controller's master clock cycle, which is fixed at 200MHz, so the time resolution of each timestamp is 5 nanoseconds. The controller writes the start and end timestamps of each read operation into a delay record table. The delay record table is indexed by block number, and each block retains a maximum of 8 timestamp pairs of the most recent read operations. When retrieving the delay timestamp, the start and end timestamps corresponding to the most recent read operation in that block are read from the delay record table. The time difference is calculated by subtracting the start timestamp from the end timestamp to obtain the clock cycle difference, and then multiplying it by 5 nanoseconds to obtain the read delay time in nanoseconds. For example, if the start timestamp is 1234567 and the end timestamp is 1235087, the difference is 520 clock cycles, corresponding to 2600 nanoseconds or 2.6 microseconds. If there is no read record for the block in the delay record table, the read delay time for that block is set to 0 nanoseconds. After the read delay time is calculated, the error bit rate and read delay time are merged and stored in the same running characteristic table. The running characteristic table uses the block number as the primary key, and each row contains two columns: the error bit rate percentage and the read delay time in nanoseconds.

[0033] Finally, the acquisition and calculation of error bit rate and read latency are all completed using the hardware timer and error correction engine inside the flash controller, without relying on additional external measurement equipment. The error statistics table and latency record table are located in the controller's internal random access memory, using a circular buffer structure. When new data is written, the oldest record is overwritten. The circular buffer depth is set to 8 records per block, and this depth is selected based on a balance between the controller's memory capacity and the sampling period. In terms of memory usage, assuming a maximum support of 1024 storage blocks, the error statistics table and latency record table in each block occupy approximately 64 bytes, with a total memory overhead of approximately 64 kilobytes, which can be fully accommodated by the controller's on-chip memory.

[0034] In step S14, trend prediction is performed based on the error bit rate and the read delay time to predict the expected error amount, including: Time alignment is performed on the error bit rate and the read delay time to obtain the aging feature sequence; Logarithmic fitting is performed based on the aging characteristic sequence, and the logarithmic growth rate coefficient and intercept value are extracted. A trend prediction function is constructed based on the logarithmic growth rate coefficient and the intercept value; Trend prediction is performed based on the trend prediction function and the preset prediction period to obtain the expected error amount.

[0035] It should be noted that the delay timestamp and error statistics come from different hardware modules, and there is a slight discrepancy in their recording times. To eliminate this time discrepancy, the error bit rate and read latency need to be realigned using a unified time base. During alignment, the timestamp recorded for the error bit rate is used as the reference. The read latency record closest to this timestamp is searched in the delay record table. If the time difference is no more than 1 millisecond, the alignment is considered successful, and the two are merged into a single aging feature point. This feature point includes three dimensions: error bit rate, read latency, and the corresponding timestamp. If the time difference exceeds 1 millisecond, the delay timestamp is discarded and replaced with the adjacent preceding delay timestamp, ensuring that each error bit rate sampling point has a corresponding read latency value. Multiple sampling points are arranged in ascending chronological order to form an aging feature sequence. The sequence length is at least 5 points; if less than 5 points are available, additional sampling is performed.

[0036] Next, the logarithmic fitting uses the least squares method to calculate the logarithmic bit error rate for each point in the aging feature sequence. ,in This represents the percentage of the error bit rate at that point. This is used to avoid taking the logarithm of zero, thus preventing division by zero or numerical anomalies. The independent variable in the fit is time, in hours, and the dependent variable is the logarithmic error bit rate. The fitting objective is to minimize the sum of squared residuals: ; in The length of the aging feature sequence is given. The read latency is not directly used as the fitting target, but rather as an auxiliary verification metric. The fitting result is considered valid only when the read latency changes in the same direction as the error bit rate. The logarithmic growth rate coefficient is obtained after fitting. and intercept value Logarithmic growth rate coefficient The physical meaning is the exponential growth rate of the error bit rate over time; the intercept value This represents the initial logarithmic error bit rate level.

[0037] It is worth noting that the trend prediction function uses an exponential extrapolation form. The flash memory error bit rate exhibits an exponential growth trend with insulation degradation in the mid-to-late aging stage. After logarithmic transformation, it approximates linear within a short 24-hour window. Therefore, based on the growth rate coefficient obtained from logarithmic fitting, the prediction function is extrapolated as follows: ; in This represents the current percentage of the error bit rate, and 24 represents the prediction period in hours. This prediction period is determined based on the timescale of measurable changes in the error bit rate during flash memory data retention testing. The natural growth rate of the error bit rate in one erase / write cycle of SLC flash memory is approximately 0.02% to 0.05% every 24 hours. Setting the prediction period to 24 hours can accurately capture the growth trend.

[0038] Then, during trend prediction, for each target storage block, the error bit rate corresponding to the last sampling point in its aging feature sequence is taken as the current error bit rate. If the current error bit rate is 0 or missing, it is replaced with... To avoid outliers, the logarithmic growth rate coefficient obtained from the sequence fitting is retrieved and substituted into the trend prediction function for calculation. The current bit error rate is then multiplied by... The error is then compared with the current bit error rate, and the larger value is taken. The resulting expected error is expressed as a percentage. To avoid prediction bias caused by noise at a single sampling point, the validity of the slope feature is checked before prediction. If the slope feature is negative for three consecutive times or its absolute value is less than a certain value, the prediction is considered invalid. If the error rate of the block does not show an increasing trend, the expected error amount is directly assigned to the current error rate without extrapolation. The expected error amount is ultimately recorded as a percentage in a newly added column of the runtime characteristic table.

[0039] The entire trend prediction process is executed online within the flash memory controller's firmware, and all calculations use fixed-point integer arithmetic. The logarithmic growth rate coefficient and intercept values ​​are scaled by a factor of 1000 before storage, and multiplication is performed before division to avoid floating-point overflow. The average time for processing time alignment, logarithmic fitting, and trend prediction for a single target storage block is no more than 0.1 milliseconds. Regarding errors, the relative error of exponential extrapolation is mainly within the range of sampling noise and fitting residuals, with the fitting residuals generally less than 5% of the current bit error rate.

[0040] For example, Figure 3 This is a schematic diagram illustrating the error bit rate trend prediction. The diagram shows that the error bit rate of the target storage block gradually increases over time. The current error bit rate is 0.482%. After logarithmic fitting and 24-hour trend prediction, the expected error rate is 0.603%, exceeding the error safety threshold of 0.55%, thus meeting the conditions for generating dynamic matching instructions.

[0041] In step S15, if the expected error quantity is greater than a preset error safety threshold, the remaining available space of the target storage block is extracted, and data priority analysis is performed based on the remaining available space and the expected error quantity to obtain a dynamic matching instruction, including: If the expected error amount is greater than the preset error safety threshold, then the remaining available space of the target storage block is extracted; Obtain the space fragmentation rate of the target storage block, and calculate the effective space based on the remaining available space and the space fragmentation rate to obtain the available net space. Migration priority is obtained by weighting and scoring based on the available net space and the expected amount of error. The address of the logic block to be processed is extracted according to the migration priority, and the instruction is encapsulated according to the address of the logic block to be processed to obtain the dynamic matching instruction.

[0042] If the expected error amount is not greater than the preset error safety threshold, then the trend prediction for the target storage block continues.

[0043] It should be noted that when the expected error rate exceeds the preset error safety threshold, the remaining available space extraction process for the target storage block is initiated. The preset error safety threshold is 0.55%, derived by working backward from the error correction limit of the error correction engine within the flash memory controller. The BCH error correction code used by the controller uses 1024 bits of raw data plus 96 bits of parity as a codeword. This error correction structure can correct a maximum of 8 error bits, thus the maximum tolerable error bit rate is calculated to be approximately 0.71% after dividing by 8 and converting. In actual use, to avoid false corrections or missed corrections when the error correction engine approaches its limit, a 23% safety margin is reserved, and the error safety threshold is set to 0.55%. This threshold can be adjusted within the range of 0.8 to 1.2 times when the reliability level changes. If the expected error rate is not greater than 0.55%, the data priority analysis is not entered, and the process directly returns to step S14 to continue trend prediction for the target storage block.

[0044] The extraction of remaining available space is performed in the flash memory controller's logical page management table. This table, indexed by block number and page number, records the allocation status of each logical page, including four states: written data, free, invalid, and bad block. During extraction, the block number of the target storage block is first entered into the management table. The number of free physical pages within that block is then counted, and the number of free pages is multiplied by the single-page capacity to obtain the remaining available space. The single-page capacity is 16 kilobytes, and this value is stored fixedly in the controller configuration register. Simultaneously, the fragmentation rate of the target storage block is obtained. The fragmentation rate is defined as the ratio of the number of invalid physical pages within that block to the total number of physical pages in that block. Effective space calculation is performed after obtaining the remaining available space and the fragmentation rate. The calculation process involves multiplying the remaining available space by 1 and subtracting the fragmentation rate; the result is the net available space, also in bytes. This calculation logic deducts the space that cannot be directly written to corresponding invalid pages, ensuring that subsequent migration priority scoring is based on the actual available space.

[0045] It is worth further explaining that before weighting and scoring, the available net space and the expected error rate are normalized separately. The available net space is divided by the total capacity of the storage block to obtain the remaining space occupancy ratio, and the expected error rate is divided by the detected current error bit rate to obtain the relative increase factor. If the error bit rate is 0 or missing, the current error bit rate is taken. To avoid computational overflow, both values ​​are mapped to the range of 0 to 1. The weighting coefficients are set based on the physical contribution of data retention risk: the expected error amount corresponds to a weight of 0.7, and the available net space corresponds to a weight of 0.3, which can be adjusted within the ranges of 0.6 to 0.8 and 0.4 to 0.2. Migration priority is calculated by the weighted sum of two normalized indicators. The closer the expected error amount is to the error safety threshold, the higher the normalized value of this indicator; the smaller the available net space, the higher the normalized value of this indicator. Both together determine the urgency of migrating the block. The calculated migration priority value ranges from 0 to 1; a higher priority value indicates that the block needs to be migrated more quickly. Each time multiple target storage blocks are scored, each block independently calculates its own migration priority and sorts them from largest to smallest.

[0046] After migration priority sorting is completed, the addresses of pending logical blocks that require priority processing are determined from the sorting results. Sorting is performed in a temporary cache, where each cache entry contains the block number, migration priority, current expected error rate, and available net space. When retrieving pending logical block addresses, starting from the top of the sorted list, the corresponding block number is read sequentially, and each block number is mapped to its starting logical block address. The range of logical block addresses is obtained by multiplying the block number by the number of logical pages contained in each block. For example, block number 6 corresponds to the starting logical block address 65536, which is represented in hexadecimal as 0x10000. The retrieval process in each round is determined by the depth of the controller's parallel processing instruction queue, which is fixed at 16 lines. Therefore, a maximum of 16 logical block addresses are retrieved per round. If the number of pending blocks in the sorted list is less than 16, all are retrieved. The retrieved logical block addresses are then enqueued in descending order of migration priority.

[0047] It's worth noting that the process of encapsulating instructions based on the address of the logic block to be processed to obtain dynamically matched instructions is completed within the controller's internal instruction encoding module. Before instruction encapsulation, the data migration granularity for each instruction is determined, set to one logical page, or 16 kilobytes. For each logic block address to be processed, the instruction content includes seven items: source logic block address, target logic block address, number of migrated pages, migration priority, instruction validity period, physical page wear level, and bit flip frequency. The target logic block address is selected from a reserved free block pool during encapsulation. The free block pool is arranged in ascending order of address, and the lowest available address block is selected as the migration target each time. The instruction validity period is set to 2 seconds; instructions not completed within this time are automatically canceled and reassigned by the controller. The dynamically matched instructions are finally written to the instruction queue in a fixed format, with each instruction being 32 bytes long, and are parsed and executed by the controller hardware. When the instruction queue is not empty, the controller executes the migration one by one in descending order of priority, thereby completing the data protection of high-risk blocks.

[0048] In step S16, according to the dynamic matching instruction, redundancy allocation is performed on the target storage block to obtain the updated error correction redundancy, including: The dynamic matching instruction is parsed to obtain the physical page wear rate and bit flip frequency; Leakage is assessed based on the physical page wear rate and the bit flip frequency to obtain the charge leakage rate. Based on the charge leakage rate, a verification and adjustment are performed to generate an error correction coding matrix; Redundancy allocation is performed on the target storage block according to the error correction coding matrix to obtain parity check bits; The redundant page mapping is updated based on the parity check bit to obtain the updated error correction redundancy.

[0049] It should be noted that the dynamic matching instruction includes the physical page wear level and bit flip frequency of the target memory block in the instruction body during generation. The physical page wear level is taken as the ratio of the remaining erase / write cycles per physical page of the memory block to the factory-rated erase / write cycles. The bit flip frequency is taken as the frequency value obtained by dividing the total number of bit flips detected in the most recent read operation of the memory block by the duration of the current read operation and the data bus width. During parsing, these two values ​​are read sequentially according to the fixed field offset in the instruction word, without needing to initiate another low-level access to the target memory block. After parsing, the physical page wear level is recorded as a dimensionless proportional value, and the bit flip frequency is recorded in kHz.

[0050] Next, before the leakage assessment, the physical page wear rate is linearly scaled. The scaling method involves subtracting the remaining erase / write percentage from a value of 1 and then dividing the result by the factory-allowed maximum wear percentage, ensuring the result falls within the 0-1 range. Simultaneously, the bit flip frequency is linearly compressed to an upper limit of 30kHz, also ensuring the result falls within the 0-1 range. After scaling, both values ​​are multiplied by 10 and rounded down to form an integer index from 0 to 9. Simultaneously, the ambient temperature data of the target storage block is mapped to an integer index from 0 to 5 according to the temperature range number in S11. This index combination is then fed into a 10×10×6 leakage rate lookup table. Each entry in the lookup table stores the corresponding average charge leakage rate of the tunneled oxide layer, in units of... The values ​​in this lookup table are the arithmetic mean of the charge leakage rate measured at different temperatures for the corresponding wear level and flip frequency level. If a corresponding entry is missing in the lookup table, the arithmetic mean of the charge leakage rate of the adjacent level is used to fill the gap. The calculated charge leakage rate directly reflects the charge escape velocity per unit area of ​​the tunneling oxide layer under the coupling effect of erase / write wear and bit flip.

[0051] Subsequently, error correction coding is implemented using low-density parity-check codes, based on the charge leakage rate. The values ​​are divided into three intervals: less than or equal to. Classified as a minor leak, greater than and less than or equal to Included in the leakage range, greater than The data is categorized into heavily leaked regions. The corresponding low-density parity-check matrix is ​​selected as the error correction coding matrix based on the leaked region: a parity-check matrix with a code rate of 0.90 is used for lightly leaked regions, 0.82 for medium-leaked regions, and 0.73 for heavily leaked regions. These three code rates correspond to adding 114, 225, and 379 parity bits per 1024 bits of original data, respectively. The boundary value between the two regions is... and Based on statistical calibration of actual flash memory chip samples, at least 500 memory blocks from the same batch were selected. The tunneling oxide leakage current density of each block was measured at five aging stages: factory state, 5000 write cycles, 10000 write cycles, 30000 write cycles, and 50000 write cycles, at a reference temperature of 25°C. The measured leakage rate data were grouped according to aging degree, and the logarithmic mean μ and logarithmic standard deviation σ were calculated for each group. The logarithmic mean of the factory state leakage rate plus 1.5 times the logarithmic standard deviation was used as the boundary between light and medium leakage; the logarithmic mean of the 50000-write-cycle aging state leakage rate minus 0.5 times the logarithmic standard deviation was used as the boundary between medium and heavy leakage.

[0052] It is worth noting that the controller retrieves the original data that has already been migrated and written from the target storage block, uses the selected parity check matrix as the error correction coding matrix, and divides the original data into fixed-length data segments. Each data segment is multiplied modulo-2 by the transpose of the parity check matrix to obtain the set of parity bits corresponding to that data segment. The parity bit sets of all data segments are concatenated in the original data segment order to form a complete parity bit sequence. The modulo-2 multiplication process is performed bit by bit using XOR operations. The time taken to process 1 kilobyte of original data to obtain parity bits is no more than 3 microseconds at a controller frequency of 200MHz. The generated parity bits are temporarily stored in a redundant bit buffer inside the controller. This buffer is divided into regions according to the target storage block number to avoid the parity data of different blocks from overwriting each other.

[0053] Finally, the updated error correction redundancy is obtained by updating the redundant page mapping based on the parity bits. In the redundant page area of ​​the target storage block, unoccupied redundant page addresses that do not conflict with existing parity bits are sequentially searched. The parity bit sequence is divided into 16-kilobyte segments per page and written page by page to the redundant page area. For each redundant page written, a new mapping entry is added to the logical page-to-redundant page address mapping table, recording the physical address of the redundant page in the corresponding row of the target storage block. After writing, the total number of allocated redundant pages in the target storage block is counted, and the ratio of this total number of redundant pages to the total number of data pages in the block is calculated. This ratio is the updated error correction redundancy. The minimum value of the updated error correction redundancy is 0, indicating that no additional redundant pages have been allocated to the block. The maximum value is limited by the reserved redundant page area capacity within the block and cannot exceed 15%. This updated error correction redundancy can be used by the flash memory controller to adjust the initial configuration of the error correction engine when receiving new read requests, ensuring that the decoding process matches the currently allocated number of parity bits.

[0054] In one possible implementation, the target storage block is pre-compensated based on the updated error correction redundancy to obtain a compensated target block, including: Threshold tracking is performed based on the updated error correction redundancy to obtain the threshold drift amount; The level is adjusted according to the threshold drift amount to obtain the read reference level; The compensation offset is calculated based on the difference between the read reference level and the preset level reference, and the current is generated based on the compensation offset to obtain a weak programming pulse; The target storage block is pre-compensated based on the weak programming pulse to obtain the compensated target block.

[0055] It should be noted that the controller internally maintains a threshold tracking mapping table, which contains two columns: the update error correction redundancy level and the threshold drift amount. The levels are divided into five grades, each in 3% increments of redundancy. Redundancy no greater than 3% corresponds to the first grade, 3% to 6% to the second, 6% to 9% to the third, 9% to 12% to the fourth, and 12% to 15% to the fifth. The threshold drift amount for each grade is in millivolts, with values ​​of 10mV, 20mV, 35mV, 50mV, and 70mV respectively. This mapping table was established using a large number of samples obtained from flash memory manufacturers during reliability testing. During testing, error correction coding was performed on single-layer cell flash memory samples from the same batch with different redundancy configurations. A charge pump test was used to measure the threshold voltage drift caused by oxide layer charge trapping. The arithmetic mean of the drift amounts of all samples within the same grade was then entered into the mapping table. When flash memory process nodes are updated or wear characteristics change, the values ​​in the table can be multiplied by an adjustment factor ranging from 0.8 to 1.2. Once the update error correction redundancy of the target storage block falls into a certain level, the corresponding threshold drift amount is directly read from the mapping table.

[0056] Next, the level adjustment process is completed in the reference level generation module of the flash memory controller. This module has an internal reference voltage source, which is initially set to a level reference. This level reference is determined by the initial read voltage recommended in the flash memory datasheet, and its value is 0mV. Before each read operation, the reference level generation module receives the threshold drift from the threshold tracking module and then algebraically adds it to the level reference. Since the programming state threshold voltage of a single-level cell flash memory decreases towards the erase state due to charge leakage, the threshold drift is positive. The read reference level needs to be offset from the reference along the negative voltage direction, that is, the read reference level is equal to the level reference minus the threshold drift. If the level reference is 0mV and the threshold drift is 20mV, the read reference level is -20mV. The generated read reference level is sent to the digital-to-analog converter for voltage output. The resolution of the digital-to-analog converter is set to 2mV per step, and the output range is limited to -100mV to 100mV. If the threshold drift causes the calculated result to exceed this range, it is truncated to the nearest range boundary value, and a level adjustment out-of-bounds event is recorded.

[0057] It is worth noting that the compensation offset is equal to the absolute value of the read reference level minus the preset level reference. This difference directly characterizes the degree to which the memory cell threshold voltage deviates from the original set voltage due to oxide layer charge leakage. The compensation offset is sent to the reference level adjustment module, which determines the compensation strategy based on the compensation offset. The active recovery threshold is set to 30mV by default, with a range of 15mV to 50mV. The calibration process for this threshold is as follows: for sample blocks calibrated by charge pump testing with different threshold voltage drift amounts, data is read under the condition of adjusting only the read reference level without performing weak programming recovery, and the error bit rate under each drift amount is calculated; the maximum allowable drift amount is determined with the read error bit rate not exceeding 50% of the controller's error correction capability limit as a constraint; the arithmetic mean of this maximum drift amount is taken for the same batch of samples, and a margin is retained to obtain 30mV. When the compensation offset is less than the active recovery threshold, only the read reference level is adjusted. That is, the adjusted read reference level is equal to the level reference minus the compensation offset. The adjusted read reference level is output to the word line driver through the digital-to-analog converter and replaces the original level reference as the comparison reference in subsequent read operations.

[0058] When the compensation offset is equal to or greater than the active recovery threshold, in addition to adjusting the read reference level, an active charge recovery operation is triggered simultaneously: the controller applies a weak programming pulse to the corresponding word line of the target memory block. The voltage amplitude of the weak programming pulse is lower than the standard programming voltage. The voltage amplitude of the weak programming pulse is determined based on the ratio of the compensation offset to the reference drift. When the compensation offset is less than the reference drift, the voltage amplitude of the weak programming pulse is equal to the compensation offset divided by the reference drift, then multiplied by the standard programming voltage; when the compensation offset reaches or exceeds the reference drift, the voltage amplitude of the weak programming pulse is the standard programming voltage. The reference drift is 50mV, which is set according to half the voltage window width between the center of the programming state threshold voltage distribution and the center of the erase state threshold voltage distribution in the flash memory datasheet, and is used to represent the maximum acceptable threshold voltage offset. The standard programming voltage is the programming verification voltage specified in the flash memory datasheet. The initial value of the weak programming pulse width is set to 1ms. The calibration process is as follows: apply weak programming pulses of different amplitudes and widths to the sample block, measure the threshold voltage drift caused by each unit pulse width, select the pulse width that makes the threshold voltage drift rate in the range of 0.5mV / ms to 2mV / ms as the initial value, and finally determine 1ms; subsequently, it is adaptively adjusted in the range of 0.1ms to 10ms according to the historical recovery effect.

[0059] After the active recovery operation is completed, a read verification is performed again. If the threshold voltage has recovered to the effective range, the compensation is complete; otherwise, weak programming is repeated until recovery is successful or the preset maximum number of attempts is reached. The maximum number of attempts is set to 3 by default. This value is determined by statistically analyzing the distribution of pulse counts required for successful weak programming recovery through reliability testing. The upper limit is set to the number of pulse counts covering 95% of recoverable samples, while also considering avoiding excessive stress on the oxide layer caused by over-programming. The compensated block is marked as the compensation target block, and the compensation offset, compensation method, and execution time are recorded in its metadata tag. The next time a read operation is performed on this block, the updated read reference level is used directly, thus reducing the read error rate of the compensation target block and extending the data retention time.

[0060] For example, Figure 4 This diagram illustrates the change in error bit rate before and after pre-compensation. The diagram shows that after error correction redundancy allocation, read reference level adjustment, and weak programming pulse processing, the error bit rate of each compensation target block was reduced. The average error bit rate decreased from 0.644% to 0.253%, and the compensation results were all below the error safety threshold.

[0061] In summary, this invention discloses a dynamic error correction method for SLC flash memory data retention based on a temperature-sensing aging model. The method includes acquiring erase / write wear data and ambient temperature data of storage blocks in a single-layer cell flash memory; extracting multi-dimensional features from the erase / write wear data and ambient temperature data to obtain insulation degradation features; classifying the insulation degradation features to obtain the true aging state; extracting aging state identifiers from the true aging state; locating the corresponding target storage block based on the aging state identifiers; collecting operational features from the target storage block to obtain the error bit rate and read latency; performing trend prediction based on the error bit rate and read latency to predict the expected error amount; if the expected error amount is greater than a preset error safety threshold, extracting the remaining available space of the target storage block; performing data priority analysis based on the remaining available space and the expected error amount to obtain a dynamic matching instruction; redundancy allocation to the target storage block based on the dynamic matching instruction to obtain an update error correction redundancy; and pre-compensating the target storage block based on the update error correction redundancy to obtain a compensated target block. This invention extracts degradation characteristics by collecting block wear and temperature data, and combines error trend prediction and dynamic migration redundancy allocation to achieve accurate dynamic matching between error correction resources and the actual aging state of the blocks.

[0062] The second embodiment of the present invention provides a dynamic error correction system for SLC flash memory data retention force based on a temperature-sensing aging model, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described above.

[0063] It should be noted that the SLC flash memory data retention dynamic error correction system based on a temperature-sensing aging model provided in this embodiment of the invention is used to execute all the process steps of the SLC flash memory data retention dynamic error correction method based on a temperature-sensing aging model in the above embodiment. The working principles and beneficial effects of the two are one-to-one, so they will not be described again.

[0064] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided by this invention, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0065] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A dynamic error correction method for SLC flash memory data retention force based on a temperature-sensing aging model, characterized in that, include: Obtain erase / write wear data and ambient temperature data of storage blocks in a single-layer cell flash memory, and perform multi-dimensional feature extraction on the erase / write wear data and ambient temperature data to obtain insulation degradation characteristics; The true aging state is obtained by classifying the insulation degradation characteristics. Based on the actual aging state, an aging state identifier is extracted. Based on the aging state identifier, the corresponding target storage block is located. The running characteristics of the target storage block are collected to obtain the error bit rate and read latency. Based on the error bit rate and the read latency, a trend prediction is performed to predict the expected error amount. If the expected error amount is greater than the preset error safety threshold, the remaining available space of the target storage block is extracted, and data priority analysis is performed based on the remaining available space and the expected error amount to obtain a dynamic matching instruction; According to the dynamic matching instruction, the target storage block is redundantly allocated to obtain the updated error correction redundancy. The target storage block is then pre-compensated according to the updated error correction redundancy to obtain the compensated target block.

2. The dynamic error correction method for SLC flash memory data retention force based on a temperature-sensing aging model according to claim 1, characterized in that, The process involves acquiring erase / write wear data and ambient temperature data for storage blocks in a single-layer cell flash memory, and performing multi-dimensional feature extraction on the erase / write wear data and ambient temperature data to obtain insulation degradation features, including: Obtain global erase / write data and global temperature data, and remove abnormal zero values ​​from the global erase / write data to obtain clean wear data; A wear distribution matrix is ​​constructed based on the cleaning wear data and the global temperature data. Working condition analysis is performed based on the wear distribution matrix to generate block status identifiers. Data is extracted based on the block status identifier to obtain erase / write wear data and ambient temperature data. Gradient analysis is performed based on the erase and write wear data and the ambient temperature data to obtain the degradation mapping matrix; Multidimensional feature extraction is performed on the degradation mapping matrix to obtain insulation degradation features.

3. The dynamic error correction method for SLC flash memory data retention force based on a temperature-sensing aging model according to claim 1, characterized in that, The step of classifying the state based on the insulation degradation characteristics to obtain the true aging state includes: Information gain is calculated for the insulation degradation characteristics to obtain the information gain value; Based on the information gain value, perform branch path traversal to obtain the leaf node weights; Generate classification status labels based on the weights of the leaf nodes; A classification determination matrix is ​​constructed based on the classification status labels, and the actual aging status of each storage block is extracted from the classification determination matrix.

4. The dynamic error correction method for SLC flash memory data retention force based on a temperature-sensing aging model according to claim 1, characterized in that, The step of extracting an aging state identifier based on the actual aging state, locating the corresponding target storage block based on the aging state identifier, and collecting operational characteristics of the target storage block to obtain the error bit rate and read latency includes: Based on the actual aging state, a state mapping is performed to obtain an aging state identifier, and the corresponding target storage block is located based on the aging state identifier. Extract the total number of parity bits and the number of flipped bits of the target storage block; The error bit rate is calculated by proportionally dividing the number of flipped bits by the total number of check bits. Extract the delay timestamp of the target storage block and calculate the time difference to obtain the read delay time.

5. The dynamic error correction method for SLC flash memory data retention force based on a temperature-sensing aging model according to claim 1, characterized in that, The step of predicting the expected error amount based on the error bit rate and the read latency includes: Time alignment is performed on the error bit rate and the read delay time to obtain the aging feature sequence; Logarithmic fitting is performed based on the aging characteristic sequence, and the logarithmic growth rate coefficient and intercept value are extracted. A trend prediction function is constructed based on the logarithmic growth rate coefficient and the intercept value; Trend prediction is performed based on the trend prediction function and the preset prediction period to obtain the expected error amount.

6. The dynamic error correction method for SLC flash memory data retention force based on a temperature-sensing aging model according to claim 1, characterized in that, If the expected error quantity is greater than a preset error safety threshold, then the remaining available space of the target storage block is extracted, and data priority analysis is performed based on the remaining available space and the expected error quantity to obtain a dynamic matching instruction, including: If the expected error amount is greater than the preset error safety threshold, then the remaining available space of the target storage block is extracted; Obtain the space fragmentation rate of the target storage block, and calculate the effective space based on the remaining available space and the space fragmentation rate to obtain the available net space. Migration priority is obtained by weighting and scoring based on the available net space and the expected amount of error. The address of the logic block to be processed is extracted according to the migration priority, and the instruction is encapsulated according to the address of the logic block to be processed to obtain the dynamic matching instruction.

7. The dynamic error correction method for SLC flash memory data retention force based on a temperature-sensing aging model according to claim 1, characterized in that, The step of redundancy allocation of the target storage block according to the dynamic matching instruction to obtain the updated error correction redundancy includes: The dynamic matching instruction is parsed to obtain the physical page wear rate and bit flip frequency; Leakage is assessed based on the physical page wear rate and the bit flip frequency to obtain the charge leakage rate. Based on the charge leakage rate, a verification and adjustment are performed to generate an error correction coding matrix; Redundancy allocation is performed on the target storage block according to the error correction coding matrix to obtain parity check bits; The redundant page mapping is updated based on the parity check bit to obtain the updated error correction redundancy.

8. The dynamic error correction method for SLC flash memory data retention force based on a temperature-sensing aging model according to claim 1, characterized in that, The step of pre-compensating the target storage block based on the updated error correction redundancy to obtain the compensated target block includes: Threshold tracking is performed based on the updated error correction redundancy to obtain the threshold drift amount; The level is adjusted according to the threshold drift amount to obtain the read reference level; The compensation offset is calculated based on the difference between the read reference level and the preset level reference, and the current is generated based on the compensation offset to obtain a weak programming pulse; The target storage block is pre-compensated based on the weak programming pulse to obtain the compensated target block.

9. A dynamic error correction system for SLC flash memory data retention force based on a temperature-sensing aging model, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the method according to any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method described in any one of claims 1 to 8.

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