Test element group structure in semiconductor memory devices

Abstract

A test element group structure in a semiconductor memory device includes a first metal pad, a second metal pad, and a plurality of long active islands. The first metal pad is electrically coupled to a plurality of word lines. The second metal pad is electrically coupled to a plurality of connection lines, wherein the plurality of word lines and the plurality of connection lines are substantially parallel to each other and arranged in an alternating and spaced-apart manner. The plurality of long active islands are respectively electrically coupled to the plurality of connection lines and located between two adjacent ones of the plurality of word lines and the plurality of connection lines. The test element group structure can provide significant advantages in process monitoring, yield improvement, LPST correlation, and reliability enhancement.

Description

Technical Field

[0001] This invention relates to a test element group structure in a semiconductor memory device. Background Technology

[0002] In advanced semiconductor memory manufacturing, maintaining consistency between the word line (WL) and active area (AA) structures has become increasingly important as device dimensions continue to shrink. Process-induced WL-AA imbalances can significantly impact the electrical behavior within memory arrays, particularly under reliability-related test conditions such as Long Parallel Select Test (LPST). When the geometric or electrical relationships between the WL and AA regions become inconsistent, abnormal leakage currents, critical voltage variations, or memory cell operational instability may occur. These issues can directly lead to decreased yields and reliability concerns in mass production. However, traditional wafer acceptance test (WAT) methods typically lack dedicated test element group (TEG) structures to effectively monitor or quantify such WL-AA imbalances. Therefore, there is a growing demand for a newly designed TEG structure that provides accurate electrical monitoring and early process detection capabilities.

[0003] A primary reason for developing the new TEG is that traditional WAT structures are typically optimized for monitoring individual transistor parameters such as critical voltage, gate leakage current, contact resistance, or line resistance. While these parameters are useful for evaluating individual process modules, they are insufficient to identify the complex interactions between WL and AA patterns within highly integrated memory arrays. In actual memory operation, WL-AA imbalances are typically caused by a combination of lithography alignment errors, etching variations, spacer contour deviations, or critical dimension (CD) fluctuations in the active region. Because the affected behavior usually only manifests under array-level operating conditions such as LPST, these process variations may not be observable through conventional parameter testing. Therefore, without a dedicated monitoring structure, engineers may not be able to detect potential process anomalies until significant yield losses have occurred.

[0004] Another important requirement for the new TEG is the ability to more accurately simulate the behavior of real memory arrays. Existing WAT structures are typically simplified transistor patterns and do not fully represent the dense and repetitive layout environment of actual memory cells. However, WL-AA imbalance is highly sensitive to layout-dependent effects, patternloading effects, and interactions between adjacent structures. For example, in dense array regions, slight variations in word line profiles or active region alignment can induce local electric field concentrations or leakage current paths, phenomena that cannot be reproduced in isolated test structures.

[0005] Another key requirement for the new TEG is to improve the efficiency of manufacturing yield learning. In advanced memory manufacturing, identifying the root cause of yield losses related to LPST (Limited-Line Stress Test) typically requires significant engineering investment and lengthy analysis cycles. Without appropriate electrical monitors, process engineers may need to rely heavily on physical failure analysis techniques such as cross-sectional microscopy or defect detection, which are both expensive and time-consuming. A dedicated TEG that directly reflects WL-AA (Waste-Line Stress Assessment) imbalance behavior can significantly reduce troubleshooting time by providing immediate electrical evidence of process instability. This enables faster process adjustments, more accurate excursion management, and improved overall manufacturing efficiency.

[0006] As semiconductor memory technology continues to evolve towards smaller sizes and higher integration densities, traditional WAT structures are no longer sufficient to monitor complex WL-AA interaction effects. Therefore, developing a TEG specifically designed to detect WL-AA imbalances caused by process technology has become increasingly necessary. Summary of the Invention

[0007] This invention proposes an innovative test element group structure in a semiconductor memory device to solve the problems of prior art.

[0008] In some embodiments of the present invention, a test element group structure in a semiconductor memory device includes: a first metal pad electrically coupled to a plurality of word lines; a second metal pad electrically coupled to a plurality of first connection lines, wherein the plurality of word lines and the plurality of first connection lines are parallel to each other and arranged in an alternating and spaced manner; and a plurality of first long active region islands electrically coupled to the plurality of first connection lines and disposed between adjacent ones of the plurality of word lines and the plurality of first connection lines.

[0009] In some embodiments of the present invention, the test element group structure further includes a third metal pad electrically coupled to a plurality of second connection lines, wherein the plurality of character lines are parallel to each other and arranged in an alternating and spaced manner.

[0010] In some embodiments of the present invention, the test element group structure further includes a plurality of second long active region islands, each electrically coupled to the plurality of second connection lines, and disposed between adjacent elements of the plurality of character lines and the plurality of second connection lines.

[0011] In some embodiments of the present invention, the first metal pad, the second metal pad, and the third metal pad have a length direction extending along a first direction.

[0012] In some embodiments of the present invention, the plurality of character lines, the plurality of first connecting lines, and the plurality of second connecting lines have a length direction extending along a second direction, and the second direction is perpendicular to the first direction.

[0013] In some embodiments of the present invention, the first metal pad is electrically coupled to the plurality of character lines through a plurality of contact vias.

[0014] In some embodiments of the present invention, the second metal pad is electrically coupled to the plurality of first connecting lines through a plurality of contact vias.

[0015] In some embodiments of the present invention, the third metal pad is electrically coupled to the plurality of second connecting lines through a plurality of contact vias.

[0016] In some embodiments of the present invention, a test element group structure in a semiconductor memory device includes: a first metal pad electrically coupled to a plurality of word lines; a second metal pad electrically coupled to a plurality of first connection lines, wherein the plurality of word lines and the plurality of first connection lines are parallel to each other and arranged in an alternating and spaced manner; a plurality of first long active region islands electrically coupled to the plurality of first connection lines and disposed between adjacent pairs of the plurality of word lines and the plurality of first connection lines; and a plurality of first short active region islands disposed between adjacent pairs of the plurality of word lines and the plurality of first connection lines, wherein each adjacent pair of first short active region islands is disposed between two adjacent first long active region islands.

[0017] In some embodiments of the present invention, the test element group structure further includes a third metal pad electrically coupled to a plurality of second connection lines, wherein the plurality of character lines are parallel to each other and arranged in an alternating and spaced manner.

[0018] In some embodiments of the present invention, the test element group structure further includes a plurality of second long active region islands, each electrically coupled to the plurality of second connection lines, and disposed between adjacent elements of the plurality of character lines and the plurality of second connection lines.

[0019] In some embodiments of the present invention, the test element group structure further includes a plurality of second short active area islands disposed between adjacent pairs of the plurality of character lines and the plurality of second connection lines, wherein each adjacent pair of second short active area islands is disposed between adjacent two second long active area islands.

[0020] In some embodiments of the present invention, the first metal pad, the second metal pad, and the third metal pad have a length direction extending along a first direction.

[0021] In some embodiments of the present invention, the plurality of character lines, the plurality of first connecting lines, and the plurality of second connecting lines have a length direction extending along a second direction, and the second direction is perpendicular to the first direction.

[0022] In some embodiments of the present invention, the first metal pad is electrically coupled to the plurality of character lines through a plurality of contact vias.

[0023] In some embodiments of the present invention, the second metal pad is electrically coupled to the plurality of first connecting lines through a plurality of contact vias.

[0024] In some embodiments of the present invention, the third metal pad is electrically coupled to the plurality of second connecting lines through a plurality of contact vias.

[0025] In summary, the test element cluster architecture of this application provides a practical and highly sensitive method for electrically monitoring WL-AA imbalance in semiconductor memory devices. By directly comparing parasitic capacitances measured between long active islands and word lines, the architecture accurately detects process-induced asymmetries that cannot be effectively monitored using conventional WAT techniques. As semiconductor memories continue to evolve towards smaller sizes and tighter process margins, this test element cluster architecture offers significant advantages in process monitoring, yield improvement, LPST correlation, and reliability enhancement.

[0026] The above description will be given in detail below with reference to the embodiments, and a further explanation of the technical solution of the present invention will be provided. Attached Figure Description

[0027] To make the above and other objects, features, advantages and embodiments of the present invention more apparent and understandable, the accompanying drawings are described below: Figure 1A plan view illustrating a test element group structure in a semiconductor memory device according to some embodiments of the present invention; and Figure 2 A perspective view is shown illustrating a test element group structure in a semiconductor memory device according to some embodiments of the present invention. Detailed Implementation

[0028] To provide a more detailed and complete description of the invention, reference can be made to the accompanying drawings and the various embodiments described below, in which the same numbers represent the same or similar elements. Furthermore, well-known elements and steps are not described in the embodiments to avoid unnecessarily limiting the invention.

[0029] Please refer to Figure 1 and Figure 2 The diagrams illustrate plan and perspective views of a test element group structure 100 according to certain embodiments of the present invention. At least a portion of the test element group structure 100 is formed in a wide cleavage region of a semiconductor substrate (i.e., a non-product region on the wafer immediately adjacent to a die). A metal pad 101 is electrically coupled to multiple word lines (e.g., word lines WL1, WL2, and WL3). The metal pad 101 has a length direction extending along direction D1. Another metal pad 103 is electrically coupled to multiple connection lines (e.g., connection lines 103a, 103b, and 103c). Yet another metal pad 105 is electrically coupled to multiple connection lines (e.g., connection lines 105a, 105b, and 105c). The plurality of metal pads 103 and 105 also have a length direction extending along direction D1.

[0030] In one or more embodiments of the present invention, the metal pad 101 is electrically coupled to the plurality of character lines (e.g., character lines WL1, WL2, and WL3) through a plurality of contact vias CV101. Each contact via CV101 extends along a direction D3 perpendicular to direction D1 or D2.

[0031] In one or more embodiments of the present invention, the metal pad 103 is electrically coupled to the plurality of connecting lines (e.g., connecting lines 103a, 103b, and 103c) through a plurality of contact vias CV103. Each contact via CV103 extends along a direction D3 perpendicular to direction D1 or D2.

[0032] In one or more embodiments of the present invention, the metal pad 105 is electrically coupled to the plurality of connecting lines (e.g., connecting lines 105a, 105b, and 105c) through a plurality of contact vias CV105. Each contact via CV105 extends along a direction D3 perpendicular to direction D1 or D2.

[0033] In one or more embodiments of the present invention, the plurality of character lines (e.g., character lines WL1, WL2, and WL3) and the plurality of connecting lines (e.g., connecting lines 103a, 103b, and 103c) are generally parallel to each other and arranged in an alternating and spaced manner. Essentially, both the plurality of character lines (e.g., character lines WL1, WL2, and WL3) and the plurality of connecting lines (e.g., connecting lines 103a, 103b, and 103c) have a length direction extending along direction D2, wherein direction D2 is perpendicular to direction D1.

[0034] In one or more embodiments of the present invention, the plurality of character lines (e.g., character lines WL1, WL2, and WL3) and the plurality of connecting lines (e.g., connecting lines 105a, 105b, and 105c) are substantially parallel to each other and arranged in an alternating and spaced manner. Essentially, both the plurality of character lines (e.g., character lines WL1, WL2, and WL3) and the plurality of connecting lines (e.g., connecting lines 105a, 105b, and 105c) have a length direction extending along direction D2, wherein direction D2 is perpendicular to direction D1.

[0035] In one or more embodiments of the present invention, a plurality of long active islands (e.g., long active islands 130a, 130c, or 130e) are electrically coupled to the plurality of connecting lines (e.g., connecting lines 103a, 103b, and 103c), and are located between adjacent characters of the plurality of character lines (e.g., character lines WL1, WL2, and WL3) and the plurality of connecting lines (e.g., connecting lines 103a, 103b, and 103c). The plurality of long active islands (e.g., long active islands 130a, 130c, or 130e) are arranged in a row along direction D1. In one or more embodiments of the present invention, each long active island (e.g., long active island 130a, 130c, or 130e) has a length direction offset relative to direction D1 (refer to...). Figure 1 ).

[0036] In one or more embodiments of the present invention, a plurality of short active area islands (e.g., short active area islands 131a or 131c) are located between adjacent pairs of the plurality of character lines (e.g., character lines WL1, WL2, and WL3) and the plurality of connecting lines (e.g., connecting lines 103a, 103b, and 103c), wherein each adjacent pair of short active area islands (e.g., short active area islands 131a or 131c) is located between adjacent two long active area islands (e.g., long active area islands 130a, 130c, or 130e). The length of each short active area island (e.g., short active area island 131a or 131c) is less than the length of each long active area island (e.g., long active area islands 130a, 130c, or 130e). In one or more embodiments of the present invention, the length of each short active region island (e.g., short active region island 131a or 131c) is less than half the length of each long active region island (e.g., long active region island 130a, 130c or 130e).

[0037] In one or more embodiments of the present invention, a plurality of long active islands (e.g., long active islands 130b, 130d, or 130f) are electrically coupled to the plurality of connecting lines (e.g., 105a, 105b, and 105c), and are located between adjacent characters of the plurality of character lines (e.g., WL1, WL2, and WL3) and the plurality of connecting lines (e.g., 105a, 105b, and 105c). The plurality of long active islands (e.g., 130b, 130d, or 130f) are arranged in a row along direction D1. In one or more embodiments of the present invention, each long active island (e.g., 130b, 130d, or 130f) has a length direction offset relative to direction D1 (see reference). Figure 1 ).

[0038] In one or more embodiments of the present invention, a plurality of short active area islands (e.g., short active area islands 131b or 131d) are located between adjacent pairs of the plurality of character lines (e.g., character lines WL1, WL2, and WL3) and the plurality of connecting lines (e.g., connecting lines 105a, 105b, and 105c), wherein each adjacent pair of short active area islands (e.g., short active area islands 131b or 131d) is located between adjacent two long active area islands (e.g., long active area islands 130b, 130d, or 130f). The length of each short active area island (e.g., short active area island 131b or 131d) is less than the length of each long active area island (e.g., long active area islands 130b, 130d, or 130f). In one or more embodiments of the present invention, the length of each short active region island (e.g., short active region island 131b or 131d) is less than half the length of each long active region island (e.g., long active region island 130b, 130d or 130f).

[0039] In one or more embodiments of the present invention, each long active region island (e.g., long active region island 130a, 130c or 130e) is electrically coupled to a corresponding connection line (e.g., connection line 103a, 103b or 103c) via a columnar capacitor (e.g., columnar capacitor 120a, 120c and 120e) extending along direction D3.

[0040] In one or more embodiments of the present invention, each long active region island (e.g., 130b, 130d or 130f) is electrically coupled to a corresponding connection line (e.g., connection line 105a, 105b or 105c) via a columnar capacitor (e.g., columnar capacitors 120b, 120d and 120f) extending along direction D3.

[0041] Reference Figure 2 The proposed Test Element Group (TEG) structure is specifically designed for electrical monitoring and evaluation of word line-active area (WL-AA) imbalances in semiconductor memory devices. In advanced memory manufacturing processes, minute variations in photolithographic alignment, etching contours, spacer formation, or critical dimensions of the active area can cause asymmetric electrical coupling between word lines and adjacent active areas. While these process variations may appear relatively small from a geometric point of view, they can significantly impact parasitic capacitance distribution, junction leakage current behavior, and the performance of Long Parallel Select Test (LPST). Conventional Wafer Acceptance Test (WAT) structures are typically ineffective at detecting such localized imbalances because they primarily focus on analyzing individual transistor characteristics rather than the array-level interactions between word lines and active areas. Therefore, the TEG structure of this invention provides a more direct and sensitive electrical monitoring mechanism to identify WL-AA imbalance states.

[0042] In the proposed structure, a voltage write test is performed using metal pads 101 and 103 to measure the parasitic capacitance WC1 between the long active islands 130a, 130c, or 130e and the word lines WL1, WL2, or WL3. Additionally, another voltage write test is performed using metal pads 101 and 105 to measure the parasitic capacitance WC2 between the long active islands 130b, 130d, or 130f and the word lines WL1, WL2, or WL3. By comparing the difference between parasitic capacitance WC1 and parasitic capacitance WC2, the proposed TEG structure can quantitatively assess the degree of WL-AA imbalance generated during semiconductor manufacturing processes.

[0043] A key advantage of this TEG structure is its ability to convert subtle variations in physical contours into measurable electrical parameters. In advanced semiconductor memory arrays, WL-AA imbalance is typically associated with overlay shift, active region edge deformation, word line bending, or non-uniform spacer thickness. These physical variations are often difficult to monitor directly using conventional in-line detection methods because dimensional differences may fall below the optical detection limit. However, parasitic capacitance is highly sensitive to variations in spacing between conductive structures and dielectric geometry. Even slight changes in the relative position between word lines and active regions can significantly alter the electric field distribution and coupling capacitance. Therefore, comparing parasitic capacitance WC1 with parasitic capacitance WC2 allows for the electrical detection of process-induced asymmetries with greater sensitivity.

[0044] Another significant improvement offered by this TEG structure is its higher correlation with actual memory array operating conditions. Existing WAT monitoring structures are typically isolated transistor elements or simplified resistor-capacitor patterns, which fail to accurately represent the high-density layout environment of actual memory cells. In contrast, the proposed TEG structure utilizes long active islands and multiple word lines arranged in a memory-like configuration. Therefore, the measured parasitic capacitance behavior more closely reflects the electrical interactions occurring in an actual memory array. This layout similarity is particularly important because WL-AA imbalance is strongly influenced by pattern density effects, neighboring structure interactions, and process load variations. By simulating the geometry of a real memory array, the monitoring data provided by the proposed TEG structure exhibits a stronger correlation with actual LPST behavior and product yield performance.

[0045] Furthermore, the proposed TEG structure improves the detection capability of process excursions during manufacturing. In traditional production processes, LPST failures are typically only discovered after array-level testing, which is relatively late in the process. At this stage, identifying the root cause requires extensive engineering analysis and can lead to significant wafer scrap or yield loss. With this TEG structure, the anomalous capacitance difference between parasitic capacitances WC1 and WC2 can serve as an early warning indicator of process instability. For example, if misalignment causes an active area island on one side to shift closer to the word line, the corresponding parasitic capacitance may increase significantly. By monitoring capacitance imbalance trends at the wafer level, process engineers can identify anomalous process drift earlier and implement corrective measures before severe yield degradation occurs.

[0046] The proposed TEG structure also offers advantages in statistical process control and process optimization. Since parasitic capacitances WC1 and WC2 are directly related to the geometric coupling between word lines and active regions, capacitance differences can serve as quantitative parameters for assessing process uniformity across wafers, batches, or manufacturing cavities. Engineers can establish control limits for acceptable capacitance imbalance ranges and monitor long-term process stability via online WAT measurements. Compared to traditional defect detection methods, electrical capacitance monitoring provides faster feedback and is more sensitive to electrical behavior related to component operation.

[0047] Furthermore, this TEG structure can help improve reliability analysis of advanced semiconductor memory devices. Excessive WL-AA imbalance can lead to increased electric field concentration, anomalous junction leakage current, or parasitic coupling effects, negatively impacting data retention and sensing margin. By accurately characterizing the capacitance difference between the active region islands on opposite sides, the TEG structure can help identify layout regions or process conditions more susceptible to reliability degradation. This information is valuable for lithography margin optimization, etching process windows, spacer contour control, and active region design rules in future technology nodes.

[0048] In the proposed TEG structure, a large number of long active region islands are required to enhance the parasitic capacitance signal generated between the active region (AA) and the word line (WL). Since the capacitance difference associated with WL-AA imbalance is relatively small in advanced semiconductor memory devices, insufficient capacitance can lead to poor measurement sensitivity and unstable electrical monitoring results. By increasing the number of long active region islands and the total effective length, the overall coupling area between the AA structure and the word line can be expanded, thereby significantly improving the detectable parasitic capacitance signal strength.

[0049] Based on current 1C TEG capacitance data, an effective bit count greater than 64K is required to obtain sufficiently distinguishable capacitance characteristics for reliable measurement and process monitoring. A larger effective bit count allows for a proportional increase in accumulated parasitic capacitance, thereby improving the signal-to-noise ratio during capacitance testing. Therefore, the proposed TEG structure can achieve higher electrical detection sensitivity in advanced memory manufacturing processes for subtle WL-AA imbalances caused by process variations, overlay offsets, or etching inhomogeneities.

[0050] In summary, the proposed test element cluster structure provides a practical and highly sensitive method for electrically monitoring WL-AA imbalance in semiconductor memory devices. By directly comparing the parasitic capacitances WC1 and WC2 measured between the long active island and the word line, the structure can accurately detect process-induced asymmetries that cannot be effectively monitored by conventional WAT techniques. As semiconductor memories continue to evolve towards smaller sizes and tighter process margins, this test element cluster structure offers significant advantages in process monitoring, yield improvement, LPST correlation, and reliability enhancement.

[0051] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0052] [Symbol Explanation] 100: Test Component Group Structure 101, 103, 105: Metal solder pads WL1, WL2, WL3: Character lines 103a, 103b, 103c: Connecting wires 105a, 105b, 105c: Connecting wires CV101, CV103, CV105: Contact vias 120a, 120c, 120e, 120b, 120d, 120f: Cylindrical capacitors 130a, 130c, 130e, 130b, 130d, 130f: Long active zone island 131a, 131c, 131b, 131d: Short active region islands D1, D2, D3: Direction WC1, WC2: Parasitic capacitance.

Claims

1. A test element group structure in a semiconductor memory device, characterized in that, Include: The first metal pad is electrically coupled to multiple character lines; The second metal pad is electrically coupled to a plurality of first connection lines, wherein the plurality of character lines are parallel to each other and arranged in an alternating and spaced manner; as well as Multiple first long active area islands are electrically coupled to the multiple first connection lines, and are disposed between the multiple character lines and the multiple first connection lines in an adjacent manner.

2. The test element group structure according to claim 1, characterized in that, It further includes a third metal pad electrically coupled to a plurality of second connection lines, wherein the plurality of character lines are parallel to each other and arranged in an alternating and spaced manner.

3. The test element group structure according to claim 2, characterized in that, It further includes multiple second long active area islands, each electrically coupled to the multiple second connection lines, and disposed between adjacent elements of the multiple character lines and the multiple second connection lines.

4. The test element group structure according to claim 2, characterized in that, The first metal pad, the second metal pad, and the third metal pad have a length direction extending along a first direction.

5. The test element group structure according to claim 4, characterized in that, The plurality of character lines, the plurality of first connecting lines, and the plurality of second connecting lines have a length direction extending along a second direction, and the second direction is perpendicular to the first direction.

6. The test element group structure according to claim 1, characterized in that, The first metal pad is electrically coupled to the multiple character lines through multiple contact vias.

7. The test element group structure according to claim 1, characterized in that, The second metal pad is electrically coupled to the plurality of first connecting lines through a plurality of contact vias.

8. The test element group structure according to claim 2, characterized in that, The third metal pad is electrically coupled to the multiple second connection lines through multiple contact vias.

9. A test element group structure in a semiconductor memory device, characterized in that, Include: The first metal pad is electrically coupled to multiple character lines; The second metal pad is electrically coupled to a plurality of first connection lines, wherein the plurality of character lines are parallel to each other and arranged in an alternating and spaced manner; Multiple first long active area islands are electrically coupled to the multiple first connection lines respectively, and are disposed between the multiple character lines and the multiple first connection lines in an adjacent manner; as well as Multiple first short active area islands are configured between adjacent pairs of the multiple character lines and the multiple first connection lines, wherein each adjacent pair of first short active area islands is configured between two adjacent first long active area islands.

10. The test element group structure according to claim 9, characterized in that, It further includes a third metal pad electrically coupled to a plurality of second connection lines, wherein the plurality of character lines are parallel to each other and arranged in an alternating and spaced manner.

11. The test element group structure according to claim 10, characterized in that, It further includes multiple second long active area islands, each electrically coupled to the multiple second connection lines, and disposed between adjacent elements of the multiple character lines and the multiple second connection lines.

12. The test element group structure according to claim 11, characterized in that, It further includes a plurality of second short active area islands, configured between adjacent pairs of the plurality of character lines and the plurality of second connection lines, wherein each adjacent pair of second short active area islands is configured between adjacent two second long active area islands.

13. The test element group structure according to claim 10, characterized in that, The first metal pad, the second metal pad, and the third metal pad have a length direction extending along a first direction.

14. The test element group structure according to claim 13, characterized in that, The plurality of character lines, the plurality of first connecting lines, and the plurality of second connecting lines have a length direction extending along a second direction, and the second direction is perpendicular to the first direction.

15. The test element group structure according to claim 9, characterized in that, The first metal pad is electrically coupled to the multiple character lines through multiple contact vias.

16. The test element group structure according to claim 9, characterized in that, The second metal pad is electrically coupled to the plurality of first connecting lines through a plurality of contact vias.

17. The test element group structure according to claim 10, characterized in that, The third metal pad is electrically coupled to the multiple second connection lines through multiple contact vias.

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